Methods of forming semiconductor device

Abstract

By depositing conformal sacrificial spacers around vertically adjacent nanostructure channels and then etching the sacrificial spacer layer, a sacrificial spacer layer is formed between the nanostructure channels, remaining solely as a sacrificial spacer between them. Flowable deposition techniques can be used to deposit the sacrificial spacer layer material between nanostructure channels with significant precursor and reactant infiltration. This allows the sacrificial spacer layer between nanostructure channels to achieve high gap-filling performance, thereby preventing, minimizing, and / or otherwise reducing the likelihood of seam formation within the sacrificial spacer layer between nanostructure channels. The seamless nature ensures that the sacrificial spacer layer completely prevents the deposition of work function metal layer material between vertically adjacent nanostructure channels.

Description

Technical Field

[0001] none Prior Technology

[0002] With advancements in semiconductor device manufacturing and the shrinking of technology processing node sizes, transistors may be affected by the short-channel effect (SCE), such as hot carrier degradation, barrier reduction, and quantum confinement. Furthermore, as transistor gate lengths decrease to accommodate smaller technology nodes, source / drain (S / D) electron tunneling increases, which raises the transistor's cutoff current (the current flowing through the transistor channel when the transistor is in the cutoff configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors (such as nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates to overcome the short-channel effect at smaller technology nodes. Nanostructure transistors offer high efficiency compared to other types of transistors, exhibiting reduced SCE and enhanced carrier mobility. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figures 1A to 1C are schematic diagrams illustrating exemplary implementations of the fin boundary customization process described herein. Figure 2 is a schematic diagram of the exemplary dummy gate structure formation process described in this article. Figure 3 is a schematic diagram illustrating an exemplary implementation of the source / drain groove formation process described herein. Figures 4A and 4B are schematic diagrams illustrating exemplary implementations of the internal spacer formation process described herein. Figure 5 is a schematic diagram illustrating an exemplary implementation of the source / drain region formation process described in this paper. Figure 6 is a schematic diagram illustrating an exemplary implementation of the interlayer dielectric layer formation process described herein. Figures 7A to 7K are schematic diagrams illustrating exemplary implementations of the replacement gate process described herein. Figure 8 is a flowchart of an exemplary process related to forming the semiconductor structure described herein. Figure 9 is a flowchart of an exemplary process related to forming the semiconductor structure described herein. Figure 10 is a flowchart of an exemplary process related to forming the semiconductor structure described herein. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] Nanostructured transistors may include gate structures surrounding a plurality of nanostructured channels. Gate structures surrounding nanostructured channels increase the gate structure's control over the conductive paths within the nanostructured channels, increase the drive current of the nanostructured transistor, and / or reduce the short-channel effect (SCE) of the nanostructured transistor, etc. In some cases, semiconductor devices may include p-type metal-oxide-semiconductor (PMOS) and n-type metal-oxide-semiconductor (NMOS) nanostructured transistors. Integrating PMOS and NMOS nanostructured transistors into the same semiconductor device enables the realization of complementary metal-oxide-semiconductor (CMOS) integrated circuits within the semiconductor device. CMOS integrated circuits have many use cases in the semiconductor industry, including microprocessors (e.g., central processing unit (CPU)), graphics processing unit (GPU)), memory devices, digital logic circuits, image sensors (e.g., CMOS image sensors) and / or radio frequency (RF) circuits, etc.

[0008] The threshold voltage (Vt) of a nanostructure transistor is the gate voltage required to selectively turn the transistor on or off. If the threshold voltage is too low (meaning the gate voltage required to start the transistor is too low), the transistor may experience significant current leakage when turned off. Conversely, if the threshold voltage is too high, the transistor's power efficiency may decrease because a higher gate voltage is required to operate it. For both PMOS and NMOS transistors, the type of metal used in the gate structure can directly affect the threshold voltage. Adjusting the gate work function (φm) of the metal to achieve optimal performance in a PMOS transistor may result in a larger bandgap between the gate work function and the conduction band (EC) in an NMOS transistor, leading to a higher threshold voltage (lower power efficiency). Adjusting the gate structure work function to achieve optimal performance of NMOS nanostructure transistors may result in a larger band gap between the gate structure work function and the valence band (EV) of PMOS nanostructure transistors, leading to a higher threshold voltage (lower power efficiency) for PMOS nanostructure transistors.

[0009] In some cases, the work function metal layers of PMOS and NMOS nanostructure transistors can be formed sequentially. For example, the work function metal layer of the PMOS nanostructure transistor can be formed first, followed by the work function metal layer of the NMOS nanostructure transistor. The work function metal layer of the PMOS nanostructure transistor can be formed around the nanostructure channels of both the PMOS and NMOS nanostructure transistors, and then removed from the nanostructure channels of the NMOS nanostructure transistor before forming the work function metal layer. In this way, the work function metal layer of the PMOS nanostructure transistor is only present on the PMOS nanostructure transistor and does not affect the performance of the NMOS nanostructure transistor.

[0010] However, the fabrication process for removing the work function metal layer from PMOS nanostructure transistors is challenging, especially due to the nanoscale of both PMOS and NMOS nanostructure transistors. For example, because the spacing between the nanostructure channels of an NMOS transistor is extremely small, residual material from the work function metal layer of a PMOS nanostructure transistor may remain on the nanostructure channels of the NMOS nanostructure transistor, such as between vertically adjacent nanostructure channels. This residual material can lead to poor performance of the NMOS nanostructure transistor because it may alter the transistor's threshold voltage.

[0011] In some embodiments described herein, sacrificial spacers are formed between vertically adjacent nanostructure channels of the first nanostructure transistor to prevent or reduce the likelihood of material from the work function metal layer of the second nanostructure transistor deposited between the vertically adjacent nanostructure channels. In this way, the sacrificial spacers increase the likelihood of completely removing material from the work function metal layer of the second nanostructure transistor before its formation.

[0012] Sacrificial spacers can be deposited by conformally depositing a sacrificial spacer layer around the nanostructure channels of the first nanostructure channel, followed by etching the sacrificial spacer layer, such that the sacrificial spacer layer remains only between the vertically adjacent nanostructure channels of the first nanostructure transistor. Flow deposition techniques (such as flow chemical vapor deposition (flow CVD or FCVD)) can be used to deposit the material of the sacrificial spacer layer between nanostructure channels with significant precursor and reactant infiltration. This allows the sacrificial spacer layer between nanostructure channels to achieve high gap-filling performance, thereby preventing, minimizing, and / or otherwise reducing the possibility of seam formation in the sacrificial spacer layer between nanostructure channels. The absence of seams in the sacrificial spacer layer ensures that the sacrificial spacer layer completely prevents the deposition of the work function metal layer material of the second nanostructure transistor between the vertically adjacent nanostructure channels of the first nanostructure transistor. Therefore, using the flowable deposition techniques described herein increases the possibility of completely removing the work function metal layer material of the second nanostructure transistor from the first nanostructure transistor before forming the work function metal layer of the second nanostructure transistor.

[0013] Figures 1A through 1C are schematic diagrams illustrating an exemplary embodiment 100 of the fin-bound process described herein. Exemplary embodiment 100 includes examples of forming fin structures and associated shallow trench isolation (STI) regions for a semiconductor device 105 described herein. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors. Exemplary embodiment 100 includes examples of forming fin structures and associated STI regions for the transistors of the semiconductor device 105.

[0014] Figures 1A through 1C illustrate perspective views and cross-sectional views along line AA in the perspective views, respectively. As shown in Figure 1A, the processing of the semiconductor device 105 is performed together with the semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0015] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes vertically alternating layers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 located above the semiconductor substrate 110. The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown in Figure 1A are examples, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of this disclosure.

[0016] The sacrificial nanostructure layer 120 enables the definition of vertical distances between adjacent nanostructure channels formed by the nanostructure channel layer 125 and serves as a berthing layer for the subsequently formed gate structure of the transistor of the semiconductor device 105, the berthing layer being formed around the nanostructure channels. The sacrificial nanostructure layer 120 includes a first material composition, and the nanostructure channel layer 125 includes a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the sacrificial nanostructure layer 120 may include silicon germanium (SiGe), and the nanostructure channel layer 125 may include silicon (Si). This enables the selective etching of the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 depending on the type of etchant used (e.g., the sacrificial nanostructure layer 120 can be etched without etching the nanostructure channel layer 125, and the nanostructure channel layer 125 can be etched without etching the sacrificial nanostructure layer 120).

[0017] One or more types of deposition tools can be used to deposit and / or grow alternating layers of the stack 115 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 110. For example, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be grown by epitaxial growth using deposition tools, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0018] One or more mask layers may be formed on the layer stack 115 (e.g., using one or more deposition tools). The mask layers may include a hard mask (HM) layer 130, a capping layer 135, an oxide layer 140, and / or a nitride layer 145. The mask layers may be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0019] As shown in Figure 1B, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 150 extending over the semiconductor substrate 110. The fin structure 150 may extend in the y-direction within the semiconductor device 105 and may be aligned in the x-direction within the semiconductor device 105. The fin structure 150 includes portions of the layer stack 115 located above and / or on a fin portion 160 above the semiconductor substrate 110. The fin structure 150 may be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on patterns formed in one or more masking layers. One or more masking layers may be patterned using lithography techniques (including dual patterning techniques or multiple patterning techniques). The semiconductor substrate 110 may be etched using etching tools based on patterns using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0020] As further shown in Figure 1B, some fin structures 150 may be formed with different widths for different types of nanostructure transistors. For example, a first subset of fin structures 150a may be formed for p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset of fin structures 150b may be formed for n-type nanostructure transistors (e.g., n-type metal oxide semiconductor (NMOS) nanostructure transistors). As another example, the first subset of fin structures 150a may be formed for nanostructure transistors operating at lower voltages, and the second subset of fin structures 150b may be formed for nanostructure transistors operating at higher voltages.

[0021] As shown in Figure 1C, a pad 165 and an STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. The pad 165 and the STI region 170 may each include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluorosilicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials.

[0022] A deposition tool can be used (e.g., using ALD or another conformal deposition technique) to conformally deposit a liner, and a dielectric layer can be deposited on the liner 165 (e.g., using CVD, PVD, ALD, and / or another suitable deposition technique) such that the dielectric layer completely fills the space between the fin structures 150 and extends above the top of the fin structures 150. A planarization or polishing operation (e.g., chemical mechanical planarization, CMP) can then be performed using a planarization tool to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of the nitride layer 145. The nitride layer 145 serves as a CMP termination layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form an STI region 170 such that the top surface of the STI region 170 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0023] As described above, Figures 1A through 1C are provided as examples. Other examples may differ from those described for Figures 1A through 1C.

[0024] Figure 2 is a schematic diagram of an exemplary embodiment 200 of the dummy gate formation process described herein. Exemplary embodiment 200 includes an example of a dummy gate structure 205 forming a nanostructure transistor of a semiconductor device 105. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the processes described in conjunction with Figures 1A to 1C.

[0025] Figure 2 illustrates a perspective view of a semiconductor device 105, on which a dummy gate structure 205 is formed. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed above a portion of the fin structure 150 and a portion of the STI region 170. The dummy gate structure 205 extends in the x-direction and is arranged in the y-direction such that it is substantially perpendicular to the fin structure 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in subsequent processing stages of the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess, wherein the source / drain regions of the nanostructured transistor are formed in the fin structure 150.

[0026] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 located above and / or on the gate electrode layer 210, a spacer layer 220 located on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 located below the gate electrode layer 210. The gate electrode layer 210 includes polycrystalline silicon (polycrystalline silicon or PO) or other materials. The hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer of silicon dioxide (SiO2) or other materials) and a nitride layer formed above the oxide layer (e.g., a pad nitride layer of silicon nitride such as Si3N4 or other materials). The spacer layer 220 includes silicon carbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiOx, such as SiO2), silicon nitride (e.g., SixNy, such as Si3N4), high dielectric constant (high k) dielectric material (e.g., dielectric material with a dielectric constant greater than about 3.9) and / or other suitable materials.

[0027] The layer of the dummy gate structure 205 can be formed using various semiconductor processing techniques, such as depositing the layer of the dummy gate structure 205, patterning the layer of the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor processing techniques.

[0028] Figure 2 further illustrates the reference sections used in the subsequent figures described herein. Section AA lies in the xz plane (referred to as the y-cut) and spans the fin structure 150 in the source / drain region of semiconductor device 105. Section BB lies in the yz plane perpendicular to section AA (referred to as the x-cut) and spans the dummy gate structure 205 along the underlying fin structure 150. Section CC lies in the xz plane parallel to section AA and perpendicular to section BB, and along the dummy gate structure 205. For clarity, these reference sections will be referenced in subsequent figures. In some figures, for ease of depiction, component symbols for some components or features may be omitted to avoid obscuring other components or features.

[0029] As described above, Figure 2 is provided as an example. Other examples may differ from those described with respect to Figure 2.

[0030] Figure 3 is a schematic diagram of an exemplary embodiment 300 of the source / drain trench formation process described herein. Exemplary embodiment 300 includes an example of a source / drain trench 305 forming a source / drain region for a nanostructured transistor in a semiconductor device 105. Figure 3 is illustrated from multiple perspectives shown in Figure 2, including the perspective of section AA, section BB, and section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 300 are performed after the processes described in conjunction with Figures 1A through 2.

[0031] As shown in sections AA and BB of Figure 3, the source / drain groove 305 is formed through a portion 155 of the fin structure 150 during the etching operation. The source / drain groove 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and may be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes using plasma etching technology, wet chemical etching technology, and / or another type of etching technology.

[0032] The source / drain grooves 305 also extend into a portion of the fin portion 160 of the fin structure 150. This results in the formation of a mesa region 310 in the fin structure 150. The sidewall of the portion of each source / drain groove 305 located below the layer stack 115 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as the base) refers to the region of the fin portion 160 of the fin structure 150 in which a nanostructure channel is defined from the nanostructure channel layer 125. The nanostructure channel 315 extends between adjacent source / drain grooves 305 and is located below the dummy gate structure 205 between adjacent source / drain grooves 305.

[0033] The nanostructure channel 315 includes a silicon-based nanostructure (e.g., a nanosheet or nanowire) and serves as a semiconductor channel for the nanostructure transistor of the semiconductor device 105. In some embodiments, the nanostructure channel 315 may include silicon germanium (SiGe) or another silicon-based material. The nanostructure channel 315 is arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructure channel 315 is vertically aligned or stacked above the semiconductor substrate 110.

[0034] As stated above, Figure 3 is provided as an example. Other examples may differ from those described with respect to Figure 3.

[0035] Figures 4A and 4B are schematic diagrams of an exemplary embodiment 400 of the internal spacer formation process described herein. Exemplary embodiment 400 includes an example of forming internal spacers between the ends of nanostructured channels 315 exposed in a source / drain recess 305. Figures 4A and 4B are illustrated from multiple perspectives shown in Figure 2, including the perspective of section AA, section BB, and section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 400 are performed after the processes described in conjunction with Figures 1A through 3.

[0036] As shown in section BB of Figure 4A, during the etching operation, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain groove 305 are etched laterally (e.g., in the x-direction substantially parallel to the length of the sacrificial nanostructure layer 120), thereby forming a cavity 405 between the ends of the sacrificial nanostructure layer 120 exposed in the source / drain groove 305. Specifically, the ends of the sacrificial nanostructure layer 120 located below the dummy gate structure 205 can be etched laterally via the source / drain groove 305 using an etching tool to form a cavity 405 between the ends of the nanostructure channel 315. The cavity 405 can be formed in an approximately curved shape, an approximately concave shape, an approximately triangular shape, an approximately square shape, or other shapes.

[0037] As shown in sections AA and BB of Figure 4B, an inner spacer (InSP) 410 is formed in the cavity 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The inner spacer 410 is included to reduce parasitic capacitance in the nanostructure transistor and protect the source / drain regions (subsequently formed in the source / drain recess 305) from etching during nanosheet release operations to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The inner spacer 410 includes silicon nitride (SixNy), silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbide nitride (SiOCN), and / or another dielectric material.

[0038] To form the inner spacer 410, a dielectric material layer can be deposited in the cavity 405 along the sidewalls and bottom surface of the source / drain recess 305 using a deposition tool. CVD, PVD, ALD, and / or another deposition technique can be used to deposit the dielectric material layer. Excess material of the dielectric material layer is then removed from the source / drain recess 305 using an etching tool, leaving the remaining portion corresponding to the inner spacer 410 in the cavity 405. In some embodiments, the etching operation may cause the surface of the inner spacer 410 facing the source / drain recess 305 to bend or recess. In some embodiments, the surface of the inner spacer 410 facing the source / drain recess 305 is approximately flat, such that the surface of the inner spacer 410 and the surface of the end of the nanostructure channel 315 are approximately flat and flush.

[0039] As described above, Figures 4A and 4B are provided as examples. Other examples may differ from those described with respect to Figures 4A and 4B.

[0040] Figure 5 is a schematic diagram of an exemplary embodiment 500 of the source / drain trench formation process described herein. Exemplary embodiment 500 includes an example of a source / drain region forming a nanostructure transistor of semiconductor device 105. Figure 5 is illustrated from multiple perspectives shown in Figure 2, including the perspective of section AA, section BB, and section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 500 are performed after the processes described in conjunction with Figures 1A through 4B.

[0041] As shown in cross sections AA and BB of Figure 5, the source / drain groove 305 is filled with one or more layers to form a source / drain region within the source / drain groove 305. For example, a deposition tool can be used to deposit a buffer region 505 at the bottom of the source / drain groove 305, and the deposition tool can deposit a source / drain region 510 on the buffer region 505 in the source / drain groove 305. In some embodiments, a deposition tool can be used to deposit a capping layer 515 on the source / drain region 510 in the source / drain groove 305.

[0042] Buffer region 505 may include silicon (Si), boron-doped silicon (Si:B), or other dopants and / or other materials. Buffer region 505 may be located between source / drain region 510 and mesa region 310, which is adjacent to buffer region 505, to reduce, minimize, and / or prevent dopant migration and / or current leakage from source / drain region 510 to adjacent mesa region 310, which could otherwise lead to short-channel effects in semiconductor device 105. Therefore, buffer region 505 can improve the performance and / or yield of semiconductor device 105.

[0043] Depending on the context, source / drain region 510 may refer individually or collectively to the source or drain. Source / drain regions 510 may be included on opposite sides of the dummy gate structure 205, such that a nanostructure channel 315 beneath the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510. Each source / drain region 510 includes silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge), etc.), n-type materials (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Therefore, the semiconductor device 105 may include a p-type metal-oxide semiconductor (PMOS) nanostructure transistor (including a p-type source / drain region 510), an n-type metal-oxide semiconductor (NMOS) nanostructure transistor (including an n-type source / drain region 510), and / or other types of nanostructure transistors.

[0044] One or more layers of the source / drain region 510 may be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool may epitaxially grow a first layer (referred to as L1) of the source / drain region 510 over a relevant buffer region 505 (referred to as L0), and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 510 over the first layer. The first layer may include lightly doped silicon (e.g., boron (B), phosphorus (P), and / or another dopant) and may serve as a shielding layer to reduce short-channel effects in the semiconductor device 105 and reduce dopant extrusion or migration in the nanostructure channel 315. The second layer may include heavily doped silicon or heavily doped silicon-germanium. A second layer may be included to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0045] The capping layer 515 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or other materials. Prior to contact formation, during semiconductor processing operations of the semiconductor device 105, the capping layer 515 may be included to reduce dopant diffusion and protect the underlying source / drain regions 510. Furthermore, the capping layer 515 may facilitate the formation of metal-semiconductor (e.g., silicate) alloys.

[0046] As stated above, Figure 5 is provided as an example. Other examples may differ from those described for Figure 5.

[0047] Figure 6 is a schematic diagram of an exemplary embodiment 600 of the interlayer dielectric (ILD) formation process described herein. Figure 6 is illustrated from multiple perspectives shown in Figure 2, including the perspective of section AA, section BB, and section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 500 are performed after the processes described in conjunction with Figures 1A through 5.

[0048] As shown in cross-sections AA and BB in Figure 6, a dielectric layer 605 is formed above the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damage to the source / drain region 510 during the gate replacement process and / or to prevent damage to the source / drain region 510 in place of the dummy gate structure 205. The dielectric layer 605 may be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0049] In some embodiments, a contact etch stop layer (CESL) is conformally deposited over the source / drain region 510 (e.g., by means of a deposition tool) prior to the formation of the dielectric layer 605. Alternatively, the capping layer 515 may be a CESL. The dielectric layer 605 is then formed on the CESL. The CESL provides a mechanism to terminate the etching process when forming contacts or vias in the source / drain region 510. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or components. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may include or may be silicon nitride (SixNy), silicon carbonitride (SiCN), carbonitride (CN), silicon oxynitride (SiON), silicon carbide (SiCO), or combinations thereof, etc. The CESL may be deposited using deposition processes such as ALD, CVD, or other deposition techniques.

[0050] As described above, Figure 6 is provided as an example. Other examples may differ from those described with respect to Figure 6.

[0051] Figures 7A through 7K are schematic diagrams of an exemplary embodiment 700 of the replacement gate (RPG) process described herein. Exemplary embodiment 700 includes an example of a replacement gate process in which a high-k / metal gate structure (e.g., a replacement gate structure) of a nanostructured transistor of semiconductor device 105 is used to replace a dummy gate structure 205. Figures 7A through 7K are illustrated from the viewpoint of section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the operations described in conjunction with Figures 1A through 6.

[0052] As shown in sections BB and CC of Figure 7A, the gate replacement process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removal of the dummy gate structure 205 leaves an opening (or groove) between the dielectric layers 605 and provides access to the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 may be removed in one or more etching operations. Such etching operations may include plasma etching, wet chemical etching, and / or another type of etching technique.

[0053] Removing the dummy gate structure 205 exposes the mesa region 310a in the semiconductor device 105 and the stack of nanostructure channels 315a arranged along the z-direction above the mesa region 310a. Removing the dummy gate structure 205 also exposes the mesa region 310b in the semiconductor device 105 and the stack of nanostructure channels 315b arranged along the z-direction above the mesa region 310b. The nanostructure channels 315a and 315b extend in the y-direction of the semiconductor device 105. The nanostructure channels 315a and 315b can be arranged along the x-direction of the semiconductor device 105, such that the nanostructure channels 315a and 315b are side-by-side or laterally adjacent in the semiconductor device 105.

[0054] Expoable terrace surface region 310a and nanostructure channel 315a are prepared to form an n-type gate structure of an NMOS nanostructure transistor of semiconductor device 105 around nanostructure channel 315a. Expoable terrace surface region 310b and nanostructure channel 315b are prepared to form a p-type gate structure of a PMOS nanostructure transistor of semiconductor device 105 around nanostructure channel 315b.

[0055] As further shown in Figure 7A, the gate replacement process includes a nanostructure release operation (e.g., a SiGe release operation). A nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon-germanium layer). This results in openings 705 between nanostructure channels 315a (e.g., the region surrounding nanostructure channels 315a) and between nanostructure channels 315b (e.g., the region surrounding nanostructure channels 315b). The sacrificial nanostructure layer 120 can be removed via the space previously occupied by the dummy gate structure 205. The nanostructure release operation may include performing an etching operation using an etching tool to remove the sacrificial nanostructure layer 120 based on the etch selectivity differences between the material of the sacrificial nanostructure layer 120 and the materials of the nanostructure channels 315a and 315b, and between the material of the sacrificial nanostructure layer 120 and the material of the inner spacer 410. The inner spacer 410 may be used as an etch stop layer in the etching operation to prevent etching of the source / drain regions 510.

[0056] As shown in Figure 7B, the gate replacement operation continues, wherein a gate structure (e.g., a replacement gate structure) is formed in an opening 705 between the source / drain regions 510 of the nanostructured transistor of the semiconductor device 105. Specifically, an n-type gate structure 710a is formed in and around the nanostructured channels 315a of the NMOS nanostructured transistor of the semiconductor device 105. The n-type gate structure 710a occupies the region previously occupied by the sacrificial nanostructure layer 120, such that the n-type gate structure 710a surrounds the nanostructured channel 315a and surrounds the nanostructured channel 315a on at least three sides of the nanostructured channel 315a. In some embodiments, the n-type gate structure 710a completely surrounds the nanostructured channel 315a and surrounds the nanostructured channel 315a on all four sides of the nanostructured channel 315a.

[0057] A p-type gate structure 710b is formed in and around the nanostructure channels 315b of the PMOS nanostructure transistor in the semiconductor device 105. The p-type gate structure 710b occupies the region previously occupied by the sacrificial nanostructure layer 120, such that the p-type gate structure 710b surrounds the nanostructure channel 315b and surrounds the nanostructure channel 315b on at least three sides of the nanostructure channel 315b. In some embodiments, the p-type gate structure 710b completely surrounds the nanostructure channel 315b and surrounds the nanostructure channel 315b on all four sides of the nanostructure channel 315b.

[0058] The steps of forming the n-type gate structure 710a and the p-type gate structure 710b may include the following steps: forming an interface layer 715 around the nanostructure channels 315a and 315b and on the mesa regions 310a and 310b. The interface layer 715 may include a thin layer of dielectric material, such as silicon oxide (SiOx). In some embodiments, the interface layer 715 is deposited using a deposition technique such as ALD or CVD. In some embodiments, the interface layer 715 is formed by oxidation, wherein the surfaces of the nanostructure channels 315a and 315b are oxidized to form the interface layer 715.

[0059] As further shown in Figure 7B, the gate dielectric layer 720 may be formed around the nanostructure channels 315a and 315b (e.g., around the interface layer 715 around the nanostructure channels 315a and 315b) and on the mesa regions 310a and 310b. Deposition tools may be used to deposit the gate dielectric layer 720 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, the gate dielectric layer 720 is a high-k gate dielectric layer comprising one or more high-k materials (e.g., dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO2, dielectric constant of about 3.9). Examples include lanthanum oxide (LaxOy, such as La2O3), hafnium oxide (HfOx, such as HfO2), zirconium oxide (ZrOx, such as ZrO2), and / or aluminum oxide (AlxOy, such as Al2O3). Alternatively and / or silicon dioxide (SiO2) and / or another dielectric material may be used instead of the high-k dielectric material. In some embodiments, the thickness of the gate dielectric layer 720 may be in the range of about 0.5 nanometers to about 3 nanometers. However, other values ​​within this range are within the scope of this disclosure.

[0060] As shown in Figures 7C and 7D, a sacrificial spacer layer 725 is formed on the gate dielectric layer 720, such that the sacrificial spacer layer 725 surrounds the nanostructure channels 315a and 315b. The sacrificial spacer layer 725 is also formed on the mesa regions 310a and 310b. The sacrificial spacer layer 725 is a material layer formed to create sacrificial spacers between vertically adjacent nanostructure channels of nanostructure channel 315a. The sacrificial spacers block or inhibit the deposition of work function metal material of the p-type gate structure 710b between vertically adjacent nanostructure channels of nanostructure channel 315a, which would otherwise be difficult to remove.

[0061] To ensure that the material of the sacrificial spacer layer 725 completely fills the openings 705 between and around the nanostructure channels 315a and 315b, a flowable deposition technique is used to deposit the material of the sacrificial spacer layer 725. The flowable deposition technique may include flowable CVD (FCVD) technology, in which the precursor 730 and reactant 735 flow into the openings 705 and around the nanostructure channels 315a and 315b, and react to form the material of the sacrificial spacer layer 725. This may be referred to as a deposition state or step of the flowable CVD technique. The precursor 730 and reactant 735 can easily flow into the openings 705 between the nanostructure channels 315a and 315b. This allows the material of the sacrificial spacer layer 725 to completely fill the openings 705 better than other deposition techniques (such as ALD). The precursor 730 and reactant 735 react to form a material with high conformal coating and gap-filling properties. This may be referred to as a conversion state or step of the flowable CVD technique.

[0062] In some embodiments, a plurality of cycles of deposition and conversion steps are performed to seamlessly form the sacrificial spacer layer 725. Each cycle may include a deposition step and a conversion step. In some embodiments, two or more cycles are performed using the same process parameters, such as the same deposition flow rate of precursor 730, the same deposition flow rate of reactant 735, the same deposition temperature, the same deposition pressure, the same annealing temperature for the conversion step, and / or another common process parameter. In some embodiments, two or more cycles are performed using different process parameters, such as different deposition flow rates of precursor 730, different deposition flow rates of reactant 735, different deposition temperatures, different deposition pressures, and / or different annealing temperatures for the conversion step, etc.

[0063] To deposit the material of the sacrificial spacer layer 725, a flowable deposition technique can be used to perform the deposition operation, wherein a deposition tool is used to allow the precursor 730 and reactant 735 to flow into the openings 705 between the nanostructure channels 315a and between the nanostructure channels 315b. The semiconductor device 105 can be placed in the processing chamber of the deposition tool (e.g., a flowable CVD tool), and the deposition tool can be used to supply gas streams containing the precursor 730 and reactant 735 to the processing chamber.

[0064] The flow rates of the gas stream containing precursor 730 and the gas stream containing reactant 735 can be selected such that the reaction between precursor 730 and reactant 735 occurs within opening 705 and on the surfaces of nanostructure channels 315a and 315b, rather than prematurely occurring in the processing chamber before reaching the surfaces of nanostructure channels 315a and 315b. For example, the flow rates of the gas stream containing precursor 730 and the gas stream containing reactant 735 can be selected such that the ratio (e.g., by volume) of the dose of precursor 730 to the dose of reactant 735 is in the range of about 1:1.0 to about 1:1.5, such that the reaction between precursor 730 and reactant 735 occurs within opening 705 and on the surfaces of nanostructure channels 315a and 315b. However, other ranges and values ​​of the ratio are within the scope of this disclosure.

[0065] In some embodiments, the pressure in the processing chamber may be maintained in the range of about 0.1 Torr to about 10 Torr to control the deposition rate of the precursor 730 and reactant 735, and to achieve high film uniformity and high conformability of the sacrificial spacer layer 725. However, other values ​​and ranges are also within the scope of this disclosure.

[0066] The pressure and / or temperature in the processing chamber can also be controlled so that the reaction between precursor 730 and reactant 735 occurs in the opening 705 and on the surfaces of nanostructure channels 315a and 315b. For example, annealing can be performed as part of a conversion step to promote the thermal decomposition of precursor 730 and / or to promote the reaction between precursor 730 and reactant 735. In some embodiments, annealing can be performed at a temperature in the range of about 200°C to about 400°C to promote the reaction between precursor 730 and reactant 735. However, other values ​​and ranges of annealing temperature are also within the scope of this disclosure.

[0067] In some embodiments, the material of the sacrificial spacer layer 725 is alumina (AlxOy). In these embodiments, the precursor 730 comprises an alumina precursor, and the reactant 735 comprises an alumina reactant that reacts with the alumina precursor to form the sacrificial spacer layer 725. The reaction between the alumina precursor and the reactant can initially form alumina molecules, each of which has an oxygen atom count in the range of 1 to 2 atoms. The reaction between the alumina precursor and the reactant can initially form alumina molecules, such as alumina (I) (Al2O) and / or alumina (II) (AlO). These alumina molecules can be stably deposited on the nanostructure channels 315a and 315b in the form of alumina (III) (Al2O3).

[0068] Precursor 730 (e.g., an alumina precursor) may include trimethylaluminum (TMA), triethylaluminum (TEA), dimethylethylaluminum (DMEAA), dimethylaluminum hydride (DMAH), tri-tert-butylaluminum (TTBA), triisobutylaluminum (TIBA), trimethylamine aluminum (TMAA), trimethylamine (TEAA), and / or another suitable aluminum-containing organometallic precursor. Reactant 735 may include an oxidant, such as oxygen (O2), ozone (O3), and / or water (H2O). In some embodiments, the oxidant includes an alcohol oxidant, such as tert-butanol ((CH3)3COH), isomers of tert-butanol (e.g., 1-butanol (C4H9OH), isobutanol ((CH3)2CHCH2OH), and but-2-ol (CH3CH(OH)CH2CH3)), and / or another alcohol oxidant.

[0069] In some embodiments, the material of the sacrificial spacer layer 725 is silicon oxide (SiOx, where x ranges from 1 to 2). In these embodiments, the precursor 730 comprises a silicon oxide precursor, and the reactant 735 comprises a silicon oxide reactant that reacts with the silicon oxide precursor to form the sacrificial spacer layer 725. Precursor 730 (e.g., silicon oxide precursor) may include silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H10), methane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylenesilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), hexamethyldisilane ((CH3)6Si2), and / or tris(dimethylamino)silane (TDMAS), etc. Reactant 735 may include oxidizing agents such as oxygen (O2), ozone (O3), and / or water (H2O), etc. In some embodiments, the oxidant includes an alcohol oxidant, such as tert-butanol ((CH3)3COH), isomers of tert-butanol (e.g., 1-butanol (C4H9OH), isobutanol ((CH3)2CHCH2OH) and but-2-ol (CH3CH(OH)CH2CH3)) and / or another alcohol oxidant.

[0070] As shown in Figure 7D, the sacrificial spacer layer 725 continues to grow as material is deposited. The sacrificial spacer layer 725 grows to a sufficient thickness to merge between vertically adjacent nanostructure channels 315a and 315b. The flowable deposition technique results in complete and seamless merging of the sacrificial spacer layer 725 between vertically adjacent nanostructure channels 315a and 315b. In some embodiments, trimming or etching operations may be performed after the deposition of the sacrificial spacer layer 725 to reduce its thickness.

[0071] As shown in Figures 7E and 7F, the sacrificial spacer layer 725 can be removed from the nanostructure channel 315b and the mesa region 310b using the masking layer 740. The masking layer 740 protects the sacrificial spacer layer 725 on the nanostructure channel 315b and the mesa region 310b, so that the sacrificial spacer layer 725 remains on the nanostructure channel 315b and the mesa region 310b.

[0072] As shown in Figure 7E, a mask layer 740 can be deposited on nanostructure channels 315a and 315b and mesa regions 310a and 310b using a deposition tool. The mask layer 740 can then be patterned by removing portions of the mask layer 740 from the nanostructure channels 315b and mesa regions 310b. The mask layer 740 can also be patterned by etching using an etching tool.

[0073] As shown in Figure 7F, the sacrificial spacer layer 725 can then be removed from the nanostructure channel 315b and mesa region 310b using an etching tool, while the masking layer 740 protects the nanostructure channel 315a and mesa region 310a. In some embodiments, a wet etching technique is used to remove the sacrificial spacer layer 725 from the nanostructure channel 315b and mesa region 310b. For example, a basic (or alkaline) wet etchant (e.g., a wet etchant with a pH greater than 7), such as ammonium hydroxide (NH4OH), can be used to isotropically etch the sacrificial spacer layer 725 to remove the sacrificial spacer layer 725 from the nanostructure channel 315b and mesa region 310b, while minimizing or eliminating etching of the gate dielectric layer 720 on the nanostructure channel 315b and mesa region 310b. Ammonium hydroxide wet etchant includes negatively charged ions (e.g., OH ions) that enable the sacrificial spacer layer 725 to be etched isotropically, since the material of the sacrificial spacer layer 725 (e.g., aluminum oxide (Al2O3), etc.) may have a positive surface charge that attracts the negatively charged ions in the ammonium hydroxide wet etchant.

[0074] Subsequently, plasma ashing technology (e.g., using nitrogen (N2) plasma and hydrogen (H2) reaction gas) and / or another type of masking layer removal technology can be used to remove the masking layer 740 from the nanostructure channel 315a and the mesa region 310a.

[0075] As shown in Figure 7G, an etch-back operation can be performed to trim the sacrificial spacer layer 725 on the nanostructure channel 315a and the mesa region 310a. The portions of the sacrificial spacer layer 725 located on the sidewalls of the nanostructure channel 315a and the mesa region 310a can be etched anisotropically, thereby removing these portions. Therefore, the portions of the sacrificial spacer layer 725 located between vertically adjacent nanostructure channels 315a are retained as sacrificial spacers 745. The portions of the sacrificial spacer layer 725 located on the STI region 170 and on the top surface of the topmost nanostructure channel 315a are also removed during the etching operation.

[0076] As shown in Figure 7G, the resulting sacrificial spacer 745 is essentially void-free due to the use of a flowable deposition technique to form the sacrificial spacer layer 725. Therefore, the sacrificial spacer 745 essentially fills the openings 705 between vertically adjacent nanostructure channels 315a.

[0077] In some embodiments, anisotropic etching is performed using a plasma-based etching tool. In these embodiments, anisotropic etching may include plasma-based etching, wherein ions in the plasma are used to etch the sacrificial spacer layer 725 in a highly perpendicular manner.

[0078] In some embodiments, anisotropic etching of the sacrificial spacer layer 725 can be achieved by using an acidic wet etchant comprising positive ions (e.g., a wet etchant with a pH less than 7). Therefore, the wet etchant may differ from the wet etchant used to remove the sacrificial spacer layer 725 from the nanostructure channel 315b and mesa region 310b, and may be used to trim the sacrificial spacer layer 725 on the nanostructure channel 315a and mesa region 310a. For example, a wet etchant comprising hydrogen (H+) ions may be used to trim the sacrificial spacer layer 725 on the nanostructure channel 315a and mesa region 310a. The use of an amphoteric material (such as alumina) for the sacrificial spacer layer 725 allows it to be etched by both alkaline and acidic wet etchants. Examples of acidic wet etchants include hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrobromic acid (HBr), and / or carbon dioxide (CO2) dissolved in water (H2O). In some embodiments, the wet etchant is diluted in water to a concentration ranging from about 0.1 parts per million (ppm) to about 1 × 10⁷ ppm. However, other values ​​and / or ranges are within the scope of this disclosure. An illustrative reaction between the wet etchant and the material of the sacrificial spacer layer 725 may include: Hydrogen ions decompose alumina into aluminum cations and byproducts such as water (H2O). Hydrogen ions can protonate oxygen atoms in alumina, causing solid alumina to decompose into soluble aluminum cations and water molecules.

[0079] As shown in Figure 7H, a p-type work function metal layer 750 is formed on the gate dielectric layer 720 such that the p-type work function metal layer 750 surrounds the nanostructure channel 315b (e.g., on all four sides of the nanostructure channel 315b). The p-type work function metal layer 750 may also be formed on the mesa region 310b. In some embodiments, the p-type work function metal layer 750 surrounding the nanostructure channel 315b is merged between the nanostructure channels 315b. In some embodiments, the p-type work function metal layer 750 surrounding the nanostructure channel 315b is not merged between the nanostructure channels 315b.

[0080] As further shown in Figure 7H, the sacrificial spacer 745 blocks or inhibits the deposition of material of the p-type work function metal layer 750 between vertically adjacent nanostructure channels 315a. As shown above, since the sacrificial spacer layer 725 is formed using a flowable deposition technique, the sacrificial spacer 745 is essentially void-free. In this way, the material of the p-type work function metal layer 750 is deposited only on the sidewalls of the nanostructure channels 315a, the top surface of the topmost nanostructure channel 315a, and the sidewalls of the mesa region 310a.

[0081] Since the p-gate structure 710b is a metallic gate structure, a p-type work function metal layer 750 can be included in the p-gate structure 710b to adjust the work function of the p-gate structure 710b. The p-type work function metal layer 750 can include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals with a work function greater than about 4.7 eV, etc. The p-type work function metal layer 750 can be included to adjust the work function of the PMOS nanostructure transistor, such that the work function is adjusted to be close to the valence band of the material of the nanostructure channel 315b. This enables the achievement of a relatively low threshold voltage for the PMOS nanostructure transistor, while also enabling the achievement of a relatively low current leakage for the PMOS nanostructure transistor.

[0082] The p-type work function metal layer 750 can be deposited using deposition tools, employing PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The p-type work function metal layer 750 can be deposited in one or more deposition operations. In some embodiments, the thickness of the p-type work function metal layer 750 formed is in the range of about 0.5 nanometers to about 20 nanometers. However, other values ​​within this range are within the scope of this disclosure.

[0083] As shown in Figures 7I and 7J, the p-type work function metal layer 750 is removed from the nanostructure channel 315a and the mesa region 310a. If the p-type work function metal layer 750 remains around the nanostructure channel 315a and on the mesa region 310a, the p-type work function metal layer 750 may cause the work function of the n-type gate structure 710a to be too far from the conduction band of the material of the nanostructure channel 315a.

[0084] Therefore, as shown in Figure 7I, a masking layer 755 can be formed on the nanostructure channel 315b and the mesa region 310b. As shown in Figure 7J, the masking layer 755 can be used to remove the p-type work function metal layer 750 from the nanostructure channel 315a and the mesa region 310a, so that the p-type work function metal layer 750 remains on the nanostructure channel 315b and the mesa region 310b.

[0085] A masking layer 755 can be deposited on nanostructure channels 315a and 315b and mesa regions 310a and 310b using a deposition tool. The masking layer 755 can then be patterned by removing a portion of the masking layer 755 from the nanostructure channels 315a and mesa regions 310a. The masking layer 755 can be patterned by etching using an etching tool. The p-type work function metal layer 750 can then be removed from the nanostructure channels 315a and mesa regions 310a using an etching tool, while the masking layer 755 protects the nanostructure channels 315b and mesa regions 310b.

[0086] As further shown in Figure 7J, the sacrificial spacer 745 is also removed from the nanostructure channel 315a and the mesa region 310a. In some embodiments, the sacrificial spacer 745 may be removed after the p-type work function metal layer 750 has been removed from the nanostructure channel 315a and the mesa region 310a. For example, a first etching operation may be performed to remove the p-type work function metal layer 750, and then a second etching operation may be performed to remove the sacrificial spacer 745. In some embodiments, the sacrificial spacer 745 and the p-type work function metal layer 750 are removed together from the nanostructure channel 315a and the mesa region 310a in the same etching operation.

[0087] In some embodiments, a wet etching technique is used to remove the sacrificial spacer 745 from the nanostructure channel 315a and the mesa region 310a. For example, a basic (or alkaline) wet etchant (e.g., a wet etchant with a pH greater than 7), such as ammonium hydroxide (NH4OH), can be used to isotropically etch the sacrificial spacer 745 to remove it from the nanostructure channel 315a and the mesa region 310a while minimizing or eliminating etching of the gate dielectric layer 720 on the nanostructure channel 315a and the mesa region 310a. The ammonium hydroxide wet etchant includes negatively charged ions (e.g., OH ions) that enable isotropic etching of the sacrificial spacer 745 because the material of the sacrificial spacer 745 (e.g., alumina (Al2O3), etc.) may have a positive surface charge that attracts the negatively charged ions in the ammonium hydroxide wet etchant.

[0088] As described above, because the sacrificial spacer layer 725 is formed using a flowable deposition technique, the sacrificial spacer 745 is essentially void-free. This allows the p-type work function metal layer 750 to be completely removed from the sidewalls of the nanostructure channel 315a and the mesa region 310a, as well as the top surface of the topmost nanostructure channel 315a. Therefore, very little or no residual material of the p-type work function metal layer 750 remains on the nanostructure channel 315a and the mesa region 310a, which also allows the sacrificial spacer 745 to be completely removed.

[0089] Subsequently, the masking layer 755 can be removed from the nanostructure channel 315b and the mesa region 310b using plasma ashing technology (e.g., using nitrogen (N2) plasma and hydrogen (H2) reaction gas) and / or another type of masking layer removal technology.

[0090] As shown in Figure 7K, one or more n-type work function metal layers are formed on the gate dielectric layer 720 of the n-type gate structure 710a. After removing the p-type work function metal layer 750 and the sacrificial spacer 745 from the nanostructure channel 315a and the mesa region 310a, one or more n-type work function metal layers can be formed around the nanostructure channel 315a and on the mesa region 310.

[0091] One or more n-type work function metal layers may include an n-type work function metal layer 760. The n-type work function metal layer 760 may include one or more metallic materials that adjust or modify the work function of the n-type gate structure 710a near the conduction band of the material of the nanostructure channel 315a. In some embodiments, the n-type work function metal layer 760 is also formed on the p-type work function metal layer 750 of the p-type gate structure 710b.

[0092] In some embodiments, the n-type work function metal layer 760 comprises titanium aluminum (TiAl). In some embodiments, the n-type work function metal layer 760 comprises titanium aluminum carbon (TiAlC). In some embodiments, the n-type work function metal layer 760 comprises another aluminum-containing metal.

[0093] The n-type work function metal layer 760 is formed such that it surrounds each nanostructure channel 315a. The n-type work function metal layer 760 can also be formed on the exposed portion of the mesa region 310a beneath the nanostructure channel 315a. The n-type work function metal layer 760 can be deposited using deposition tools, employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques.

[0094] In some embodiments, the n-type work function metal layer 760 is formed such that the n-type work function metal layer 760 is merged between vertically adjacent nanostructure channels 315a. The merging region 765 of the n-type work function metal layer 760 is formed in the region previously occupied by the sacrificial spacer 745. In some embodiments, the n-type work function metal layer 760 is formed such that the n-type work function metal layer 760 is not merged between vertically adjacent nanostructure channels 315a.

[0095] As further shown in Figure 7K, a gate electrode layer 770 is formed for an n-type gate structure 710a, and a gate electrode layer 770 is formed for a p-type gate structure 710b. In some embodiments, the same gate electrode layer 770 is formed for both the n-type gate structure 710a and the p-type gate structure 710b. In some embodiments, separate and electrically isolated gate electrode layers 770 are formed for each of the n-type gate structure 710a and the p-type gate structure 710b. The gate electrode layer 770 may be formed on an n-type work function metal layer 760 above the nanostructure channel 315a for the n-type gate structure 710a, and on an n-type work function metal layer 760 above the nanostructure channel 315b for the p-type gate structure 710b.

[0096] The gate electrode layer 770 comprises one or more metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo), etc. In some embodiments, the gate electrode layer 770 comprises a conductive ceramic material, such as titanium nitride (TiN). The gate electrode layer 770 can be deposited using deposition tools, employing CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The gate electrode layer 770 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the gate electrode layer 770 is deposited on the seed layer. In some embodiments, after depositing the gate electrode layer 770, a planarization tool can be used to planarize the gate electrode layer 770.

[0097] As described above, Figures 7A through 7K are provided as examples. Other examples may differ from those described for Figures 7A through 7K.

[0098] Figure 8 is a flowchart of an exemplary process 800 associated with forming the semiconductor structure described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 8.

[0099] As shown in Figure 8, process 800 may include the following steps: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (block 810). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructure channels (e.g., nanostructure channel 315, nanostructure channel 315a) arranged in a direction substantially perpendicular (e.g., the z-direction) to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0100] As further shown in Figure 8, process 800 may include the step of forming a sacrificial spacer layer (block 820) around the nanostructure channels using a flowable deposition technique. For example, one or more semiconductor processing tools may be used to form the sacrificial spacer layer (e.g., sacrificial spacer layer 725) around the nanostructure channels using a flowable deposition technique, as described herein. In some embodiments, the sacrificial spacer layer is merged between vertically adjacent nanostructure channels of the plurality of nanostructure channels.

[0101] As further shown in Figure 8, process 800 may include the following steps: etching the sacrificial spacer layer to remove a first portion (block 830) of the sacrificial spacer layer from the sides of the nanostructure channels. For example, one or more semiconductor processing tools may be used to etch the sacrificial spacer layer to remove the first portion of the sacrificial spacer layer from the sides of the nanostructure channels, as described herein. In some embodiments, a second portion of the sacrificial spacer layer is retained as a sacrificial spacer (e.g., sacrificial spacer 745) between vertically adjacent nanostructure channels.

[0102] As further shown in Figure 8, process 800 may include the step of forming a power function metal layer (block 840) on the nanostructure channels. For example, one or more semiconductor processing tools may be used to form a power function metal layer (e.g., p-type work function metal layer 750) on the nanostructure channels, as described herein. In some embodiments, sacrificial spacers suppress the formation of power function metal layers between vertically adjacent nanostructure channels.

[0103] Process 800 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in combination with those described elsewhere in this document.

[0104] In the first embodiment, the sacrificial spacer layer comprises at least one of alumina (AlxOy) or silicon oxide (SiOx).

[0105] In the second embodiment, either alone or in combination with the first embodiment, the flow deposition technique includes flow chemical vapor deposition.

[0106] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, process 800 includes the following steps: removing the work function metal layer and sacrificial spacers from the nanostructure channels; and after removing the work function metal layer and sacrificial spacers, forming another work function metal layer (e.g., an n-type work function metal layer 760) around the nanostructure channels, wherein the other work function metal layer is formed between vertically adjacent nanostructure channels of the nanostructure channels.

[0107] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the work function metal layer is a p-type work function metal layer, and the other work function metal layer is an n-type work function metal layer.

[0108] Although Figure 8 illustrates an exemplary block of process 800, in some embodiments, process 800 includes more blocks, fewer blocks, different blocks, or blocks with different arrangements than those shown in Figure 8. Alternatively, two or more blocks of process 800 may be executed in parallel.

[0109] Figure 9 is a flowchart of an exemplary process 900 associated with forming the semiconductor structure described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 9.

[0110] As shown in Figure 9, process 900 may include the following steps: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (block 910). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructure channels (e.g., nanostructure channel 315, nanostructure channel 315a) arranged in a direction substantially perpendicular (e.g., the z-direction) to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0111] As further shown in Figure 9, process 900 may include the step of providing a precursor material (block 920) for a sacrificial spacer layer around the nanostructure channels. For example, one or more semiconductor processing tools may be used to provide a precursor material (e.g., precursor 730) for a sacrificial spacer layer (e.g., sacrificial spacer layer 725) around the nanostructure channels, as described herein. In some embodiments, the precursor material for the sacrificial spacer layer flows between vertically adjacent nanostructure channels.

[0112] As further shown in Figure 9, process 900 may include the following steps: providing reactants (block 930) around the nanostructure channels. For example, one or more semiconductor processing tools may be used to provide reactants around the nanostructure channels (e.g., reactant 735), as described herein. In some embodiments, the reactants flow between vertically adjacent nanostructure channels. In some embodiments, precursor materials and reactants react to form a sacrificial spacer layer around the nanostructure channels. In some embodiments, the sacrificial spacer layer merges between vertically adjacent nanostructure channels.

[0113] As further shown in Figure 9, process 900 may include the following steps: etching the sacrificial spacer layer to remove a first portion (block 940) of the sacrificial spacer layer from the sides of the nanostructure channels. For example, one or more semiconductor processing tools may be used to etch the sacrificial spacer layer to remove the first portion of the sacrificial spacer layer from the sides of the nanostructure channels, as described herein. In some embodiments, a second portion of the sacrificial spacer layer is retained as a sacrificial spacer (e.g., sacrificial spacer 745) between vertically adjacent nanostructure channels.

[0114] As further shown in Figure 9, process 900 may include the step of forming a power function metal layer (block 950) on the nanostructure channels. For example, one or more semiconductor processing tools may be used to form a power function metal layer (e.g., p-type work function metal layer 750) on the nanostructure channels, as described herein. In some embodiments, sacrificial spacers suppress the formation of power function metal layers between vertically adjacent nanostructure channels.

[0115] Process 900 may include additional implementations, such as any single implementation or any combination of multiple implementations of one or more other processes described below and / or in conjunction with those described elsewhere in this document.

[0116] In the first embodiment, the precursor material for the sacrificial spacer layer includes an alumina (AlxOy) precursor.

[0117] In the second embodiment, either alone or in combination with the first embodiment, the alumina precursor includes at least one of trimethylaluminum (TMA), triethylaluminum (TEA), dimethylethylaluminum (DMEAA), dimethylaluminum hydride (DMAH), tritert-butylaluminum (TTBA), triisobutylaluminum (TIBA), trimethylamine aluminum (TMAA), and trimethylamine (TEAA).

[0118] In the third embodiment, the reactant includes an oxidizing agent, either alone or in combination with one or more of the first and second embodiments.

[0119] In the fourth embodiment, the oxidant, alone or in combination with one or more of the first to third embodiments, includes at least one of oxygen (O2), ozone (O3), alcohol, or water (H2O).

[0120] In the fifth embodiment, the precursor material for the sacrificial spacer layer includes a silicon oxide (SiOx) precursor, either alone or in combination with one or more of the first to fourth embodiments.

[0121] In the sixth embodiment, the silicon oxide precursor, alone or in combination with one or more of the first to fifth embodiments, includes at least one of silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H10).

[0122] In the seventh embodiment, the silicon oxide precursor, alone or in combination with one or more of the first to sixth embodiments, includes at least one of methane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethoxysilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), hexamethyldisilane ((CH3)6Si2), or tris(dimethylamino)silane (TDMAS).

[0123] In the eighth embodiment, the reactant includes an oxidizing agent, either alone or in combination with one or more of the first to seventh embodiments.

[0124] In the ninth embodiment, the oxidant, alone or in combination with one or more of the first to eighth embodiments, includes at least one of oxygen (O2), ozone (O3), alcohol, or water (H2O).

[0125] In the tenth embodiment, the volume ratio of the precursor material to the reactant is in the range of about 1:1.0 to about 1:1.5, either alone or in combination with one or more of the first to ninth embodiments.

[0126] Although Figure 9 illustrates an exemplary block of process 900, in some embodiments, process 900 includes more blocks, fewer blocks, different blocks, or blocks with different arrangements than those shown in Figure 9. Alternatively, two or more blocks of process 900 may be executed in parallel.

[0127] Figure 10 is a flowchart of an exemplary process 1000 associated with forming the semiconductor structure described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor processing tools) are used to perform one or more process blocks of Figure 10.

[0128] As shown in Figure 10, process 1000 may include the following steps: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (block 1010). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructure channels (e.g., nanostructure channel 315, nanostructure channel 315a) arranged in a direction substantially perpendicular (e.g., z-direction) to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0129] As further shown in Figure 10, process 1000 may include the step of providing a precursor material for a sacrificial spacer layer (block 1020) around the nanostructure channels. For example, a precursor material (e.g., precursor 730) for a sacrificial spacer layer (e.g., sacrificial spacer layer 725) may be deposited around the nanostructure channels using one or more semiconductor processing tools, as described herein. In some embodiments, the precursor material for the sacrificial spacer layer flows between vertically adjacent nanostructure channels.

[0130] As further shown in Figure 10, process 1000 may include the step of depositing reactants (block 1030) around the nanostructure channels. For example, one or more semiconductor processing tools may be used to deposit reactants (e.g., reactant 735) around the nanostructure channels, as described herein. In some embodiments, the reactants flow between vertically adjacent nanostructure channels.

[0131] As further shown in Figure 10, process 1000 may include the following steps: performing an annealing operation to react the precursor material and reactants to form a sacrificial spacer layer (block 1040) around the nanostructure channels. For example, one or more semiconductor processing tools may be used to perform the annealing operation to react the precursor material and reactants to form a sacrificial spacer layer around the nanostructure channels, as described herein. In some embodiments, the sacrificial spacer layer is merged between vertically adjacent nanostructure channels.

[0132] As further shown in Figure 10, process 1000 may include the following steps: etching the sacrificial spacer layer to remove a first portion (block 1050) of the sacrificial spacer layer from the sides of the nanostructure channels. For example, one or more semiconductor processing tools may be used to etch the sacrificial spacer layer to remove the first portion of the sacrificial spacer layer from the sides of the nanostructure channels, as described herein. In some embodiments, a second portion of the sacrificial spacer layer is retained as a sacrificial spacer (e.g., sacrificial spacer 745) between vertically adjacent nanostructure channels.

[0133] As further shown in Figure 10, process 1000 may include the step of forming a power function metal layer (block 1060) on the nanostructure channels. For example, one or more semiconductor processing tools may be used to form a power function metal layer (e.g., p-type work function metal layer 750) on the nanostructure channels, as described herein. In some embodiments, sacrificial spacers suppress the formation of power function metal layers between vertically adjacent nanostructure channels.

[0134] Process 1000 may include additional implementations, such as any single implementation or any combination of multiple implementations of one or more other processes described below and / or in conjunction with those described elsewhere in this document.

[0135] In the first embodiment, the steps of depositing precursor materials, depositing reactants, and performing annealing are performed as the first cycle of a plurality of flowable deposition cycles to form a sacrificial spacer layer.

[0136] In the second embodiment, either alone or in combination with the first embodiment, process 1000 includes the following steps: performing a second cycle of the deposition cycles using at least one of the following: the flow rate of the precursor is different from the flow rate of the precursor in the first cycle, or the flow rate of the reactant is different from the flow rate of the reactant in the first cycle.

[0137] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 1000 includes the following steps: performing a second cycle of the deposition cycles using at least one of the following: the pressure of the deposition precursors and reactants is different from the pressure of the deposition precursors and reactants in the first cycle, or the annealing temperature is different from the annealing temperature of the annealing operation in the first cycle.

[0138] Although Figure 10 illustrates an exemplary block of process 1000, in some embodiments, process 1000 may include more blocks, fewer blocks, different blocks, or blocks with different arrangements than those shown in Figure 10. Alternatively, two or more blocks of process 1000 may be executed in parallel.

[0139] In this manner, sacrificial spacers are formed between vertically adjacent nanostructure channels of the first nanostructure transistor to prevent or reduce the possibility of material deposition from the work function metal layer of the second nanostructure transistor between the vertically adjacent nanostructure channels. The sacrificial spacers can be formed by depositing a conformal sacrificial spacer layer around the nanostructure channels of the first nanostructure channel, followed by etching, such that the sacrificial spacer layer remains only between the vertically adjacent nanostructure channels of the first nanostructure transistor. Flowable deposition techniques can be used to deposit the material of the sacrificial spacer layer between nanostructure channels with significant precursor and reactant infiltration. This allows the sacrificial spacer layer between nanostructure channels to achieve high gap-filling performance, thereby preventing, minimizing, and / or otherwise reducing the possibility of seam formation in the sacrificial spacer layer between nanostructure channels. The absence of seams in the sacrificial spacer layer ensures that the sacrificial spacer layer completely prevents material deposition from the work function metal layer of the second nanostructure transistor between the vertically adjacent nanostructure channels of the first nanostructure transistor. Therefore, the use of the flowable deposition technique described herein can increase the possibility of completely removing the material of the work function metal layer of the second nanostructured transistor from the first nanostructured transistor before forming the work function metal layer of the second nanostructured transistor.

[0140] As described in more detail above, some embodiments of this document provide a method. The method includes the steps of: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a sacrificial spacer layer around the nanostructure channels using a flowable deposition technique, wherein the sacrificial spacer layer is merged between vertically adjacent nanostructure channels; etching the sacrificial spacer layer to remove a first portion of the sacrificial spacer layer from the sides of the nanostructure channels, wherein a second portion of the sacrificial spacer layer remains as a sacrificial spacer between vertically adjacent nanostructure channels; and forming a power function metal layer on the nanostructure channels, wherein the sacrificial spacer prevents the formation of a power function metal layer between vertically adjacent nanostructure channels.

[0141] As described in more detail above, some embodiments described herein provide a method. The method includes the steps of: forming a plurality of nanostructured channels arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; providing a precursor material for a sacrificial spacer layer around the nanostructured channels, wherein the precursor material for the sacrificial spacer layer flows between vertically adjacent nanostructured channels; providing reactants around the nanostructured channels, wherein the reactants flow between vertically adjacent nanostructured channels, wherein the precursor material and the reactants react to form a sacrificial spacer layer around the nanostructured channels, and wherein the sacrificial spacer layer merges between vertically adjacent nanostructured channels; and etching the sacrificial spacer layer to remove a first portion of the sacrificial spacer layer from the sides of the nanostructured channels, wherein a second portion of the sacrificial spacer layer remains as a sacrificial spacer between vertically adjacent nanostructured channels. The method includes the following steps: forming a power function metal layer on the nanostructure channels, wherein sacrificial spacers inhibit the formation of a power function metal layer between vertically adjacent nanostructure channels.

[0142] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of first nanostructure channels arranged along a first direction. The semiconductor device includes a plurality of second nanostructure channels arranged along the first direction, wherein the second nanostructure channels are adjacent to the first nanostructure channels in a second direction substantially perpendicular to the first direction, and wherein the first nanostructure channels and the second nanostructure channels extend upward in a third direction substantially perpendicular to the second direction. The semiconductor device includes a first gate structure surrounding the first nanostructure channels, comprising a first type work function metal layer, wherein portions of the first type work function metal layer between vertically adjacent nanostructure channels of the first nanostructure channels are merged between opposite sides of the vertically adjacent nanostructure channels. The semiconductor device includes a first gate dielectric layer located between the first gate structure and the first nanostructure channels. The semiconductor device includes a second gate structure surrounding each of the second nanostructure channels, comprising a second type work function metal layer different from the first type work function metal layer. The semiconductor device includes a second gate dielectric layer located between the second gate structure and the second nanostructure channels.

[0143] As described in more detail above, some embodiments described herein provide a method. The method includes the steps of: forming a plurality of nanostructured channels arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; depositing a precursor material for a sacrificial spacer layer around the nanostructured channels; the precursor material for the sacrificial spacer layer flowing between vertically adjacent nanostructured channels; depositing reactants around the nanostructured channels; the reactants flowing between vertically adjacent nanostructured channels; performing an annealing operation to react the precursor material and the reactants to form a sacrificial spacer layer around the nanostructured channels; merging the sacrificial spacer layer between vertically adjacent nanostructured channels; and etching the sacrificial spacer layer to remove a first portion of the sacrificial spacer layer from the sides of the nanostructured channels. A second portion of the sacrificial spacer layer remains as a sacrificial spacer between vertically adjacent nanostructured channels. The method includes the following steps: forming a power function metal layer on the nanostructure channels. Sacrificial spacers are used to suppress the formation of power function metal layers between vertically adjacent nanostructure channels.

[0144] The terms "approximately" and "substantially" can mean that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, in accordance with this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0145] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

[0146] 100, 200, 300, 400, 500, 600, 700: Implementation 105: Semiconductor Devices 110: Semiconductor substrate 115: Layer stacking 120: Sacrificial Nanostructure Layer 125: Nanostructured Channel Layer 130: HM layer 135: Covering layer 140: Oxide layer 145: Nitride layer 150: Fin-shaped structure 150a: First fin-shaped structure subset 150b: Second fin-shaped structure subset 155: Part 160: Fin-shaped part 165: Padding 170: STI region 205: Virtual gate structure 210: Gate electrode layer 215: Hard mask layer 220: Spacer layer 225: Gate dielectric layer 305: Source / Drain Groove 310, 310a, 310b: Countertop area 315, 315a, 315b: Nanostructured channels 405: Cavity 410: Internal spacer 505: Buffer Area 510: Source / Drain Region 515: Covering layer 605: Dielectric layer 705: Opening 710a:n-type gate structure 710b: P-type gate structure 715: Interface Layer 720: Gate dielectric layer 725: Sacrificial Interval Layer 730: Precursor 735: Reactants 740, 755: Masking layer 745: Sacrificial Spacer 750: p-type work function metal layer 760: n-type work function metal layer 765: Merging Regions 770: Gate electrode layer 800, 900, 1000: Process Blocks 810, 820, 830, and 840 Blocks 910, 920, 930, and 940 Blocks 950, 1010, and 1020 Blocks 1030, 1040, and 1050 1060: Block AA: Cross section, line BB, CC: Cross-section

[0147] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor device, comprising the steps of: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a sacrificial spacer layer around the nanostructure channels using a flowable deposition technique, wherein the sacrificial spacer layer is incorporated between a plurality of vertically adjacent nanostructure channels; etching the sacrificial spacer layer to remove a plurality of first portions of the sacrificial spacer layer from a plurality of sides of the nanostructure channels, wherein a plurality of second portions of the sacrificial spacer layer remain as a plurality of sacrificial spacers between the vertically adjacent nanostructure channels; and forming a work function metal layer on the nanostructure channels, wherein the sacrificial spacers suppress the formation of the work function metal layer between the vertically adjacent nanostructure channels.

2. The method of claim 1, wherein the sacrificial spacer layer comprises at least one of the following: aluminum oxide (AlxOy) or silicon oxide (SiOx).

3. The method of claim 1, wherein the flowable deposition technique comprises a flowable chemical vapor deposition technique.

4. A method of forming a semiconductor device, comprising the steps of: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; providing a precursor material for a sacrificial spacer layer around the nanostructure channels, wherein the precursor material for the sacrificial spacer layer flows between a plurality of vertically adjacent nanostructure channels; providing a reactant around the nanostructure channels, wherein the reactant flows between the vertically adjacent nanostructure channels, wherein the precursor material and the reactant react to form a sacrificial spacer layer around the nanostructure channels, and wherein the sacrificial spacer layer is incorporated between a plurality of vertically adjacent nanostructure channels; etching the sacrificial spacer layer to remove a plurality of first portions of the sacrificial spacer layer from a plurality of sides of the nanostructure channels. The second portions of the sacrificial spacer layer are retained as sacrificial spacers between the vertically adjacent nanostructure channels of the nanostructure channels; and a work function metal layer is formed on the nanostructure channels, wherein the sacrificial spacers inhibit the formation of the work function metal layer between the vertically adjacent nanostructure channels of the nanostructure channels.

5. The method of claim 4, wherein the precursor material of the sacrificial spacer layer comprises an aluminum oxide (AlxOy) precursor.

6. The method of claim 5, wherein the alumina precursor comprises at least one of the following: trimethylaluminum (TMA), triethylaluminum (TEA), dimethylethylaluminum (DMEAA), dimethylaluminum hydride (DMAH), tritert-butylaluminum (TTBA), triisobutylaluminum (TIBA), trimethylamine aluminum (TMAA), or trimethylamine (TEAA).

7. The method of claim 5, wherein the reactant comprises an oxidizing agent.

8. A method of forming a semiconductor device, comprising the steps of: forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; depositing a precursor material for a sacrificial spacer layer around the nanostructure channels, wherein the precursor material of the sacrificial spacer layer flows between a plurality of vertically adjacent nanostructure channels; depositing a reactant around the nanostructure channels, wherein the reactant flows between the vertically adjacent nanostructure channels; performing an annealing operation to react the precursor material with the reactant to form a sacrificial spacer layer around the nanostructure channels, wherein the sacrificial spacer layer is incorporated between a plurality of vertically adjacent nanostructure channels; etching the sacrificial spacer layer to remove a plurality of first portions of the sacrificial spacer layer from a plurality of sides of the nanostructure channels. The second portions of the sacrificial spacer layer are retained as sacrificial spacers between the vertically adjacent nanostructure channels of the nanostructure channels; and a work function metal layer is formed on the nanostructure channels, wherein the sacrificial spacers inhibit the formation of the work function metal layer between the vertically adjacent nanostructure channels of the nanostructure channels.

9. The method of claim 8, wherein the steps of depositing the precursor material, depositing the reactant, and performing the annealing operation are performed as a first cycle of a plurality of flowable deposition cycles to form the sacrificial spacer layer.

10. The method of claim 9 further comprises the step of: performing a second cycle of the deposition cycles using at least one of the following: a flow rate of the precursor is different from a flow rate of the precursor in the first cycle, or a flow rate of the reactant is different from a flow rate of the reactant in the first cycle.

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