Memory circuit and method for operating the same

Abstract

A memory circuit includes: a memory array including memory cells coupled to word lines; and driver circuitry coupled to the memory cells via the word lines. The driver circuitry includes: a p-type transistor coupled between the word line and a switchable voltage selected from first, second, and third power supply voltages; an inverter having an input for receiving a logically inverted version of a selection signal provided in a first logic state to assert the word line, and an output for providing an intermediate signal; and a first n-type transistor having a gate, a first source / drain, and a second source / drain. The gate is used to receive a control signal switching between the first power supply voltage and a fourth power supply voltage.

Description

Technical Field

[0001] none. Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. As IC dimensions continue to shrink, more devices are integrated into a single chip. This scaling down process typically yields benefits by increasing production efficiency and reducing associated costs. Summary of the Invention

[0003] none. Simple Explanation of the Diagram

[0004] The various embodiments disclosed herein can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 illustrates a block diagram of an exemplary memory device (or circuit) according to some embodiments. Figure 2 illustrates a block diagram of an exemplary memory circuit according to some embodiments. Figure 3 illustrates a circuit diagram of an exemplary memory circuit that may be included in the memory circuit of Figure 1 according to some embodiments. Figures 4 and 5 illustrate exemplary waveforms related to memory circuitry according to some embodiments. Figure 6 illustrates a circuit diagram of an exemplary memory circuit that may be included in the memory circuit of Figure 1 according to some embodiments. Figures 7 and 8 illustrate exemplary waveforms related to memory circuitry according to some embodiments. Figure 9 illustrates a circuit diagram of an exemplary memory circuit that may be included in the memory circuit of Figure 1 according to some embodiments. Figures 10 and 11 illustrate exemplary waveforms related to memory circuitry according to some embodiments. Figure 12 illustrates a circuit diagram of an exemplary memory circuit that may be included in the memory circuit of Figure 1 according to some embodiments. Figures 13 and 14 illustrate exemplary waveforms related to memory circuitry according to some embodiments. Figure 15 illustrates a circuit diagram of an exemplary memory circuit that may be included in the memory circuit of Figure 1 according to some embodiments. Figure 16 illustrates a flowchart of an exemplary method for operating a memory circuit according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, the embodiments disclosed may repeat element symbols and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," "above," "top," and "bottom" may be used herein to describe the relationship between one element or feature and another as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] Typically, word line drivers control the activation of word lines (WL) in memory devices (e.g., resistive switching memory) by providing appropriate voltage levels for read and write operations. During write operations, the word line driver provides a higher voltage to the word line, while during read operations, it provides a lower voltage. In memory devices, the word line voltage during write operations is generally higher than during read operations. Therefore, a high-voltage transistor is used to handle the increased voltage during write operations, and the word line driver switches between these two voltage levels. Typically, a word line driver includes a high-voltage transistor and a voltage switch to select the appropriate power supply based on the operating mode (read or write). However, a significant problem is that the driving capability of the high-voltage transistor is limited, especially at the low voltages during read operations. To achieve high-speed read operations, some word line drivers rely on using larger high-voltage transistors, resulting in an increased area. This area expansion impairs the overall efficiency and density of the memory array, highlighting the need for a more efficient solution.

[0008] This disclosure provides techniques for addressing the aforementioned challenges, such as reducing driver area and power consumption with improved reliability. As disclosed herein, in some embodiments, these techniques include: driver circuitry including a p-type transistor, an n-type transistor, and an inverter. The p-type transistor is coupled between a switchable voltage and a word line. The inverter includes: an input for receiving a logically inverted version of a selection signal; and an output for providing an intermediate signal. Here, a selection signal is provided in a first logic state to assert the word line. The n-type transistor includes a gate, a first source / drain, and a second source / drain. The gate is used to receive a control signal switching between a first supply voltage and a fourth supply voltage, the first source / drain is connected to the output of the inverter, and the second source / drain is connected to the word line. The techniques disclosed herein, including driver circuitry with p-type transistors, n-type transistors, and inverters, effectively address the challenges found in conventional word line drivers. This design enables more efficient switching between read and write voltage levels, while improving driver performance under both high and low voltage conditions, thereby reducing the need for larger high-voltage transistors. This reduces driver size, improves reliability, and lowers power consumption, directly addressing the limitations of traditional designs.

[0009] Figure 1 illustrates a block diagram of an exemplary memory device (or circuit) 100 according to some embodiments. The memory circuit 100 includes a memory controller 105 and a memory array 120. In one embodiment, the memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 further includes: word lines WL0, WL1…WLJ, each extending along one direction (e.g., the X direction); and bit lines BL0, BL1…BLK, each extending along another direction (e.g., the Y direction). The word lines WL and bit lines BL may be conductive metal or conductive rails, respectively. In some embodiments, each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and is operable according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes bit lines BL, BLB, coupled to one or more memory cells 125 arranged along a direction (e.g., the Y direction). Bit lines BL and BLB can receive and / or provide differential signals.

[0010] Each memory cell 125 may include volatile memory cells, non-volatile memory cells, or combinations thereof. In some embodiments, each memory cell 125 includes a resistive random access memory (RRAM) cell. In some embodiments, each memory cell 125 is embodied as a static random access memory (SRAM) cell, etc. However, it should be understood that the memory cell 125 may be implemented as any of a variety of other non-volatile memory cells, such as a magnetoresistive random access memory (MRAM) cell, a phase-change random access memory (PCRAM) cell, an electrically programmable fuse, an antifuse, etc., while still within the scope of the embodiments disclosed herein. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0011] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line (BL) controller 112, word line (WL) controller 114, etc. BL controller 112 and WL controller 114 may be embodied as logic circuitry, analog circuitry, or a combination thereof. In one configuration, WL controller 114 may be circuitry that provides voltage or current to one or more word lines WL of memory array 120. BL controller 112 may be circuitry that provides or senses voltage or current to one or more bit lines BL of memory array 120. BL controller 112 may be coupled to the bit lines BL of memory array 120, while WL controller 114 may be coupled to the word lines WL of memory array 120.

[0012] In some embodiments, the memory controller 105 may include driver circuitry (e.g., a word line controller 114, etc.) coupled to the memory cell 125 via one or more word lines. The driver circuitry may include a first p-type transistor coupled between a switchable voltage and a word line. The switchable voltage is selected from a first power supply voltage, a second power supply voltage, and a third power supply voltage. The driver circuitry may include an inverter having an input for receiving a logically inverted version of a selection signal and an output for providing an intermediate signal. The selection signal is provided in a first logic state to assert the word line. The driver circuitry may include a first n-type transistor having a gate, a first source / drain, and a second source / drain. The gate is used to receive a control signal switching between a first power supply voltage and a fourth power supply voltage. The first source / drain is connected to the output of the inverter, and the second source / drain is connected to the word line.

[0013] In some embodiments, a driver circuit is used to apply a voltage to one or more word lines. The one or more word lines are connected to one or more gates of one or more select transistors of one or more corresponding memory cells. The driver circuit includes a first p-type transistor coupled between a switchable voltage and the word line. The switchable voltage is selected from a first power supply voltage, a second power supply voltage, and a third power supply voltage. The driver circuit includes a first n-type transistor having a gate, a first source / drain terminal connected to the word line, and a second source / drain terminal. The gate is used to receive a control signal switching between a first power supply voltage and a fourth power supply voltage. The driver circuit includes a second p-type transistor and a second n-type transistor. The gates of the second p-type transistor and the second n-type transistor are used to receive a logically inverted version of the select signal and provide the select signal to assert the word line in a first logic state.

[0014] Figure 2 illustrates a block diagram of an exemplary memory circuit 200 according to some embodiments. In some embodiments, memory circuit 200 may be substantially similar to or incorporate features of memory circuit 100. Memory circuit 200 is shown as including driver circuitry 230 (e.g., a word line driver WLDRV) and resistive switching memory cells 225, including resistive switching elements 226 and select transistors 227. It should be understood that the memory circuit 200 in Figure 2 is simplified for illustrative purposes and therefore can be implemented in any of a variety of other configurations while still remaining within the scope of the embodiments disclosed herein.

[0015] Although discussed in more detail below, driver circuitry 230 can control memory cell 225 based on Table 1. Table 1 shows non-limiting examples of bias conditions for memory cell 225. The WL voltage for read operations can be set to the power supply voltage VDD, while the WL voltage for set / reset operations can be set to a voltage higher than the power supply voltage VDD (e.g., VWLSET, VWLRST, etc.). Voltage: WL BL SL Read VDD VBLRD 0 set up VWLSET (>VDD) VBLS 0 Reset VWLRST (>VDD) 0 VSLRST Table 1

[0016] Figure 3 illustrates a circuit diagram of an exemplary memory circuit 300 that may be included in the memory circuit 100 of Figure 1 according to some embodiments. The memory circuit 300 includes a driver circuit 330 and a switching circuit 360. It should be understood that the memory circuit 300 of Figure 3 is simplified for illustrative purposes and therefore can be implemented in any of a variety of other configurations while still remaining within the scope of the embodiments disclosed herein.

[0017] In some embodiments, driver circuitry 330 may be a word line driver circuit (e.g., as shown in Figure 2). Driver circuitry 330 may be coupled to a memory cell (e.g., memory cell 125) via word line WL. Driver circuitry 330 may be used to apply a voltage to word line WL. Word line WL may be connected to the gate terminal of the select transistor of the memory cell (e.g., as shown in Figure 2).

[0018] In some embodiments, as shown in Figure 3, the driver circuit 330 includes: a first p-type transistor 331, a first n-type transistor 332, an inverter 335 (which may include a second n-type transistor 334 and a second p-type transistor 333), a cross-coupled transistor 338, etc. In some embodiments, the first p-type transistor 331 is coupled between a switchable voltage and a word line WL. The switchable voltage may be selected from a first power supply voltage (e.g., VDD), a second power supply voltage (e.g., VWLSET), and a third power supply voltage (e.g., VWLRST). In some embodiments, the inverter 335 includes: an input for receiving a logically inverted version of a selection signal SEL. The inverter 335 may include: an output for providing an intermediate signal VS. The selection signal SEL may be provided in a first logic state to assert the word line WL. In some embodiments, the driver circuit 330 may include a second p-type transistor 333 and a second n-type transistor 334. The gate terminals of the second p-type transistor 333 and the second n-type transistor 334 can be used to receive a logic inverted version of the select signal SEL. In some embodiments, the first n-type transistor 332 includes a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal of the first n-type transistor 332 can be used to receive a control signal CTL that switches between a first supply voltage and a fourth supply voltage (e.g., VDMAX). The first source / drain terminal of the first n-type transistor 332 can be connected to the output terminal of the inverter 335 (or the output terminals of the second p-type transistor 333 and the second n-type transistor 334). The second source / drain terminal of the first n-type transistor 332 can be connected to the word line WL.

[0019] The switching circuit 360 includes a plurality of switches for providing a plurality of corresponding switching signals. In some embodiments, as shown in Figure 3, the switching circuit 360 includes: a switch SW_R for coupling a first power supply voltage (e.g., VDD) to a first p-type transistor 331 of the driver circuit 330; a switch SW_SET for coupling a second power supply voltage (e.g., VWLSET) to the first p-type transistor 331 of the driver circuit 330; and a switch SW_RST for coupling a third power supply voltage (e.g., VWLRST) to the first p-type transistor 331 of the driver circuit 330, etc. In some embodiments, the switch SW_R can be used to couple a fourth power supply voltage (e.g., VDMAX), a second power supply voltage (e.g., VWLSET), a third power supply voltage (e.g., VWLRST), etc., to the gate terminal of a first n-type transistor 332. Switches SW_SET and SW_RST can be used to connect the first power supply voltage (e.g., VDD) to the gate terminal of the first n-type transistor 332.

[0020] In some embodiments, the first p-type transistor 331 and the first n-type transistor 332 can be used to operate at voltages higher than those of the second p-type transistor 333, the second n-type transistor 334, etc. In some embodiments, the second p-type transistor 333 and the second n-type transistor 334 can be used to operate at voltages lower than those of the first p-type transistor 331, the first n-type transistor 332, etc. In some embodiments, the first p-type transistor 331 and the first n-type transistor 332 may each include a gate structure having a first length (e.g., along the X direction) and a first width (e.g., along the Y direction), while the second p-type transistor 333 and the second n-type transistor 334 may each include a gate structure having a second length (e.g., along the X direction) and a second width (e.g., along the Y direction). The first length may be significantly longer than the second length, and the first width may be significantly wider than the second width. In some embodiments, the thickness of the oxide layer and the high-k dielectric layer associated with the first p-type and n-type transistors may be greater than the thickness of the second p-type and n-type transistors. These structural differences enable the first p-type transistor 331 and the first n-type transistor 332 to operate at higher voltages, while the second p-type transistor 333 and the second n-type transistor 334 are used to operate at lower voltages. In some embodiments, the threshold voltages of the first p-type and n-type transistors may be higher than the threshold voltages of the second p-type and n-type transistors, allowing the first transistor to maintain stability and reliability at higher operating voltages, while the second transistor is optimized for performance at lower voltages.

[0021] Switching circuit 360 can provide a control signal CTL that can be configured with various voltages. Driver circuit 330 can be used to receive the control signal CTL and perform various operations (e.g., read, write, etc.) based on the control signal CTL. In some embodiments, when at least one memory cell is selected for writing, the control signal CTL can be configured with a first power supply voltage (e.g., VDD). For example, in response to a memory cell selected for writing, switch SW_R can be turned on and switch SW_SET (and / or switch SW_RST) can be closed to couple the first power supply voltage (e.g., VDD) to the control signal CTL. In some embodiments, when at least one memory cell is selected for reading, the control signal CTL can be configured with a fourth power supply voltage (e.g., VDMAX). For example, in response to a memory cell selected for reading, switch SW_SET (and / or switch SW_RST) can be turned on and switch SW_R can be closed to couple the fourth power supply voltage (e.g., VDMAX) to the control signal CTL. In some embodiments, the fourth power supply voltage (e.g., VDMAX) is higher than the first power supply voltage (e.g., VDD).

[0022] Switching circuit 360 can provide a switchable voltage selectable from a first power supply voltage (e.g., VDD), a second power supply voltage (e.g., VWLSET), and a third power supply voltage (e.g., VWLRST). For example, switching circuit 360 can be used to provide a switchable voltage based on switching operations of switches SW_R, SW_SET, SW_RST, etc. Driver circuit 330 can receive the switchable voltage and perform various operations (e.g., read, write, etc.) based on the switchable voltage. In some embodiments, when at least one memory cell is selected for writing, the switchable voltage can be configured with a second power supply voltage (e.g., VWLSET) or a third power supply voltage (e.g., VWLRST). For example, in response to a memory cell selected for writing, switch SW_R can be turned on, and switch SW_SET or switch SW_RST can be turned off to couple the second power supply voltage (e.g., VWLSET) or the third power supply voltage (e.g., VWLRST) to driver circuit 330. In some embodiments, when at least one memory cell is selected for reading, the switchable voltage can be configured with a first power supply voltage (e.g., VDD). For example, in response to a memory cell selected for reading, switches SW_SET and SW_RST can be turned on, and switch SW_R can be closed to couple a first power supply voltage (e.g., VDD) to driver circuitry 330. In some embodiments, a third power supply voltage (e.g., VWLRST) is higher than a second power supply voltage (e.g., VWLSET), and the second power supply voltage (e.g., VWLSET) is higher than the first power supply voltage (e.g., VDD). In some embodiments, during a read operation, the word line WL can be pulled up by the second p-type transistor 333 and the first p-type transistor 331, and the intermediate signal VS can be set to the power supply voltage VDD via the second p-type transistor 333. During a write operation, the word line WL can be pulled up by the first p-type transistor 331, and the intermediate signal VS can be set to the power supply voltage VDD via the second p-type transistor 333. Since the voltage between the gate terminal (e.g., VDD) and the source / drain terminal (e.g., VDD) is less than the threshold voltage, the first n-type transistor 332 can be substantially turned off, wherein the gate is coupled to the control signal CTL at the supply voltage VDD.

[0023] In some embodiments, during a read operation, the gate of the first n-type transistor 332 may be coupled to a fourth power supply voltage (e.g., VDMAX) that may be higher than the first power supply voltage (e.g., VDD), thereby ensuring drive capability and high-speed pull-up / pull-down operation. During a write operation, the gate of the first n-type transistor 332 may be coupled to the first power supply voltage (e.g., VDD), thereby suppressing the intermediate signal VS (e.g., because the gate of the first n-type transistor 332 is coupled to the first power supply voltage (e.g., VDD), the node of the intermediate signal VS does not exceed the first power supply voltage (e.g., VDD)). Therefore, the memory circuitry disclosed herein allows high-speed operation during read / write operations.

[0024] Table 2 shows non-limiting examples of bias conditions for memory circuit 300. Figures 4 and 5 illustrate exemplary waveforms related to memory circuits (e.g., memory circuits 100, 200, 300, etc.) according to some embodiments. In some embodiments, the waveforms shown in Figure 4 are related to read operations of memory circuit 300, while the waveforms shown in Figure 5 are related to write operations of memory circuit 300. It should be understood that the waveforms shown in Figures 4 and 5 are simplified for illustrative purposes and therefore can be implemented in any of a variety of other forms while still remaining within the scope of the embodiments disclosed herein. WL status operate VWL CTL WL Select WL (For example, SEL = VDD) Read VDD VDMAX VDD set up VWLSET VDD VWLSET Reset VWLRST VDD VWLRST WL not selected (For example, SEL = 0 V) Read VDD VDMAX 0 V set up VWLSET VDD 0 V Reset VWLRST VDD 0 V Table 2

[0025] In response to selecting a memory cell using a selection signal SEL (e.g., a selection signal under the first power supply voltage VDD) (e.g., the WL state is "selected WL"), memory circuitry 300 can be used to perform read operations (e.g., "read") and write operations (e.g., "set", "reset", etc.). During a read operation, switching circuitry 360 can be used to provide a switchable voltage (e.g., VWL) under the first power supply voltage (e.g., VDD) and a control signal CTL under a fourth power supply voltage (e.g., VDMAX), thereby allowing driver circuitry 330 to assert word line WL under the first power supply voltage (e.g., VDD). During a write operation, the switching circuit 360 can be used to provide a switchable voltage (e.g., VWL) at a second supply voltage (e.g., VWLSET) or a third supply voltage (e.g., VWLRST), and to provide a control signal CTL at a first supply voltage (e.g., VDD), thereby allowing the driver circuit 330 to assert the word line WL at the second supply voltage (e.g., VWLSET) or the third supply voltage (e.g., VWLRST).

[0026] In response to a memory cell not being selected (e.g., WL state is "Unselected WL") and the selection signal SEL is 0 V, the memory circuit 300 can be used to prevent the word line WL from being interrupted. In response to a switchable voltage (e.g., VWL) under a first power supply voltage (e.g., VDD), the control signal CTL can be configured with a fourth power supply voltage (e.g., VDMAX), thereby allowing the driver circuit 330 to prevent the word line WL (e.g., 0 V) ​​from being interrupted. In response to a switchable voltage (e.g., VWLSET) under a second power supply voltage (e.g., VWLRST) or a third power supply voltage (e.g., VWLRST), the control signal CTL can be configured with a first power supply voltage (e.g., VDD), thereby allowing the driver circuit 330 to prevent the word line WL (e.g., 0 V) ​​from being interrupted.

[0027] Figure 6 illustrates a circuit diagram of an exemplary memory circuit 600 that may be included in the memory circuit 100 of Figure 1, according to some embodiments. The memory circuit 600 includes a driver circuit 630 and a switching circuit 660. It should be understood that the memory circuit 600 of Figure 6 is simplified for illustrative purposes and therefore can be implemented in any of a variety of other configurations while still remaining within the scope of the embodiments disclosed herein.

[0028] In some embodiments, memory circuit 600 may resemble memory circuit 300 or be integrated with memory circuit 300. For example, in memory circuit 600, a control signal CTL can be used to alternate between a first power supply voltage (e.g., VDD) and a second power supply voltage (e.g., VWLSET), which differs from memory circuit 300. In some embodiments, the control signal CTL can be used to switch between the first power supply voltage (e.g., VDD) and the second power supply voltage (e.g., VWLSET) when the second power supply voltage (e.g., VWLSET) is higher than a third power supply voltage (e.g., VWLRST). In some embodiments, when at least one memory cell is selected for writing, the control signal CTL can be configured with the first power supply voltage (e.g., VDD). For example, in response to a memory cell selected for writing, switch SW_R can be turned on, and switch SW_SET (and / or switch SW_RST) can be closed to couple the first power supply voltage (e.g., VDD) to the control signal CTL. In some embodiments, when at least one memory cell is selected for reading, the control signal CTL can be configured with a second power supply voltage (e.g., VWLSET). For example, in response to a selected memory cell for reading, switch SW_SET (and / or switch SW_RST) can be turned on, and switch SW_R can be closed to couple the second power supply voltage (e.g., VWLSET) to the control signal CTL. In some embodiments, the second power supply voltage (e.g., VWLSET) is higher than the first power supply voltage (e.g., VDD).

[0029] In some embodiments, the gate of the first n-type transistor 632 can be used to receive a control signal CTL that switches between a first supply voltage and a second supply voltage (e.g., VWLSET). In some embodiments, during a read operation, the gate of the first n-type transistor 632 can be coupled to a second supply voltage (e.g., VWLSET) that may be higher than the first supply voltage (e.g., VDD), thereby ensuring drive capability and high-speed pull-up / pull-down operation. During a write operation, the gate of the first n-type transistor 632 can be coupled to the first supply voltage (e.g., VDD), thereby suppressing the intermediate signal VS (e.g., because the gate of the first n-type transistor 632 is coupled to the first supply voltage (e.g., VDD), the node of the intermediate signal VS does not exceed the first supply voltage (e.g., VDD)). Thus, the memory circuitry disclosed herein allows for high-speed operation during read / write operations.

[0030] Table 3 shows non-limiting examples of bias conditions for memory circuit 600. Figures 7 and 8 illustrate exemplary waveforms related to memory circuits (e.g., memory circuits 100, 200, 600, etc.) according to some embodiments. In some embodiments, the waveforms shown in Figure 7 are related to read operations of memory circuit 600, while the waveforms shown in Figure 8 are related to write operations of memory circuit 600. It should be understood that the waveforms shown in Figures 7 and 8 are simplified for illustrative purposes and therefore can be implemented in any of a variety of other forms while still remaining within the scope of the embodiments disclosed herein. WL status operate VWL CTL WL Select WL (For example, SEL = VDD) Read VDD VWLSET VDD set up VWLSET VDD VWLSET Reset VWLRST VDD VWLRST Unrotated WL (For example, SEL = 0 V) Read VDD VWLSET 0 V set up VWLSET VDD 0 V Reset VWLRST VDD 0 V Table 3

[0031] In response to selecting a memory cell using a selection signal SEL (e.g., a selection signal under a first power supply voltage VDD) (e.g., the WL state is "selected WL"), memory circuitry 600 can be used to perform read operations (e.g., "read") and write operations (e.g., "set", "reset", etc.). During a read operation, switching circuitry 660 can be used to provide a switchable voltage (e.g., VWL) under the first power supply voltage (e.g., VDD) and a control signal CTL under a second power supply voltage (e.g., VWLSET), thereby allowing driver circuitry 630 to assert word line WL under the first power supply voltage (e.g., VDD). During a write operation, the switching circuit 660 can be used to provide a switchable voltage (e.g., VWL) at a second supply voltage (e.g., VWLSET) or a third supply voltage (e.g., VWLRST), and to provide a control signal CTL at a first supply voltage (e.g., VDD), thereby allowing the driver circuit 630 to assert the word line WL at the second supply voltage (e.g., VWLSET) or the third supply voltage (e.g., VWLRST).

[0032] In response to a memory cell not being selected (e.g., WL state is "Unselected WL") and the selection signal SEL is 0 V, the memory circuit 600 can be used to prevent the speech character line WL from being interrupted. In response to a switchable voltage (e.g., VWL) under a first power supply voltage (e.g., VDD), the control signal CTL can be configured with a second power supply voltage (e.g., VWLSET), thereby allowing the driver circuit 630 to prevent the speech character line WL (e.g., 0 V) ​​from being interrupted. In response to a switchable voltage (e.g., VWL) under a second power supply voltage (e.g., VWLSET) or a third power supply voltage (e.g., VWLRST), the control signal CTL can be configured with a first power supply voltage (e.g., VDD), thereby allowing the driver circuit 630 to prevent the speech character line WL (e.g., 0 V) ​​from being interrupted.

[0033] Figure 9 illustrates a circuit diagram of an exemplary memory circuit 900 that may be included in the memory circuit 100 of Figure 1, according to some embodiments. The memory circuit 900 includes a driver circuit 930 and a switching circuit 960. It should be understood that the memory circuit 900 in Figure 9 is simplified for illustrative purposes and therefore can be implemented in any of a variety of other configurations while still remaining within the scope of the embodiments disclosed herein.

[0034] In some embodiments, memory circuitry 900 may resemble memory circuitry 300 or incorporate features of memory circuitry 300. For example, in memory circuitry 900, a control signal CTL may be used to alternate between a first power supply voltage (e.g., VDD) and a third power supply voltage (e.g., VWLRST), unlike memory circuitry 300. In some embodiments, the control signal CTL may be used to switch between the first power supply voltage (e.g., VDD) and the third power supply voltage (e.g., VWLRST) when the third power supply voltage (e.g., VWLRST) is higher than the second power supply voltage (e.g., VWLRST). In some embodiments, the control signal CTL may be configured with the first power supply voltage (e.g., VDD) when at least one memory cell is selected for writing. For example, in response to a memory cell selected for writing, switch SW_R may be turned on, and switch SW_SET (and / or switch SW_RST) may be turned off to couple the first power supply voltage (e.g., VDD) to the control signal CTL. In some embodiments, when at least one memory cell is selected for reading, the control signal CTL can be configured with a third power supply voltage (e.g., VWLRST). For example, in response to a selected memory cell for reading, a switch SW_SET (and / or a switch SW_RST) can be turned on, and a switch SW_R can be closed to couple the third power supply voltage (e.g., VWLRST) to the control signal CTL. In some embodiments, the third power supply voltage (e.g., VWLRST) is higher than a first power supply voltage (e.g., VDD).

[0035] In some embodiments, the gate of the first n-type transistor 932 can be used to receive a control signal CTL that switches between a first supply voltage and a third supply voltage (e.g., VWLRST). In some embodiments, during a read operation, the gate of the first n-type transistor 932 can be coupled to a third supply voltage (e.g., VWLRST) that may be higher than the first supply voltage (e.g., VDD), thereby ensuring drive capability and high-speed pull-up / pull-down operation. During a write operation, the gate of the first n-type transistor 932 can be coupled to the first supply voltage (e.g., VDD), thereby suppressing the intermediate signal VS (e.g., because the gate of the first n-type transistor 932 is coupled to the first supply voltage (e.g., VDD), the node of the intermediate signal VS does not exceed the first supply voltage (e.g., VDD)). Thus, the memory circuitry disclosed herein allows for high-speed operation during read / write operations.

[0036] Table 4 shows non-limiting examples of bias conditions for memory circuit 900. Figures 10 and 11 illustrate exemplary waveforms related to memory circuits (e.g., memory circuits 100, 200, 900, etc.) according to some embodiments. In some embodiments, the waveforms shown in Figure 10 are related to read operations of memory circuit 900, while the waveforms shown in Figure 11 are related to write operations of memory circuit 900. It should be understood that the waveforms shown in Figures 10 and 11 are simplified for illustrative purposes and therefore can be implemented in any of a variety of other forms while still remaining within the scope of the embodiments disclosed herein. WL status operate VWL CTL WL Select WL (For example, SEL = VDD) Read VDD VWLRST VDD set up VWLSET VDD VWLSET Reset VWLRST VDD VWLRST WL not selected (For example, SEL = 0 V) Read VDD VWLRST 0 V set up VWLSET VDD 0 V Reset VWLRST VDD 0 V Table 4

[0037] In response to selecting a memory cell using a selection signal SEL (e.g., a selection signal of the first power supply voltage VDD) (e.g., the WL state is "selected WL"), memory circuitry 900 can be used to perform read operations (e.g., "read") and write operations (e.g., "set", "reset", etc.). During a read operation, switching circuitry 960 can be used to provide a switchable voltage (e.g., VWL) at the first power supply voltage (e.g., VDD) and a control signal CTL at the third power supply voltage (e.g., VWLRST), thereby allowing driver circuitry 930 to assert word line WL at the first power supply voltage (e.g., VDD). During a write operation, the switching circuit 960 can be used to provide a switchable voltage (e.g., VWL) at a second supply voltage (e.g., VWLSET) or a third supply voltage (e.g., VWLRST), and to provide a control signal CTL at a first supply voltage (e.g., VDD), thereby allowing the driver circuit 930 to assert the word line WL at the second supply voltage (e.g., VWLSET) or the third supply voltage (e.g., VWLRST).

[0038] In response to a memory cell not being selected (e.g., WL state is "Unselected WL") and the selection signal SEL is 0 V, the memory circuit 900 can be used to prevent the word line WL from being interrupted. In response to a switchable voltage (e.g., VWL) under a first power supply voltage (e.g., VDD), the control signal CTL can be configured with a third power supply voltage (e.g., VWLRST), thereby allowing the driver circuit 930 to prevent the word line WL (e.g., 0 V) ​​from being interrupted. In response to a switchable voltage (e.g., VWLSET) under a second power supply voltage (e.g., VWLSET) or a third power supply voltage (e.g., VWLRST), the control signal CTL can be configured with a first power supply voltage (e.g., VDD), thereby allowing the driver circuit 930 to prevent the word line WL (e.g., 0 V) ​​from being interrupted.

[0039] Figure 12 illustrates a circuit diagram of an exemplary memory circuit 1200 that may be included in the memory circuit 100 of Figure 1 according to some embodiments. It should be understood that the memory circuit 1200 of Figure 12 is simplified for illustrative purposes and therefore can be implemented in any of a variety of other configurations while still remaining within the scope of the embodiments disclosed herein.

[0040] In some embodiments, the memory circuit 1200 may be substantially similar to or incorporate features of memory circuits 100, 200, 300, 600, 900, etc. For example, the memory circuit 1200 includes a driver circuit 1230 and a switching circuit 1260. The driver circuit 1230 includes a first p-type transistor 1231, a first n-type transistor 1232, a second p-type transistor 1233, a second n-type transistor 1234, a cross-coupled transistor 1238, etc. Unlike memory circuits 300, 600, 900, etc., the memory circuit 1200 additionally includes a logic gate 1250.

[0041] In some embodiments, the cross-coupled transistor 1238 may be coupled to the gate of the first p-type transistor 1231. In some embodiments, the logic gate 1250 may be coupled between the select signal SEL and the cross-coupled transistor 1238. For example, as shown, the logic gate 1250 may be coupled to the select signal SEL via a first input and to the read enable signal RDEN_B via a second input, while the logic gate 1250 may provide an output to the cross-coupled transistor 1238. In some embodiments, an inverted version of the read enable signal RDEN_B may be set to logic high during a write operation and to logic low during a read operation. Although shown as an inverted gate, the logic gate 1250 may be or include any logic gate or combination thereof to receive various inputs and perform various logic operations.

[0042] Figures 13 and 14 illustrate exemplary waveforms related to memory circuits (e.g., memory circuits 100, 200, 1200, etc.) according to some embodiments. In some embodiments, the waveforms shown in Figure 13 are related to read operations of memory circuit 1200, while the waveforms shown in Figure 14 are related to write operations of memory circuit 1200. It should be understood that the waveforms shown in Figures 13 and 14 are simplified for illustrative purposes and can therefore be implemented in any of a variety of other forms while still remaining within the scope of the embodiments disclosed herein. As shown in Figure 13, in some embodiments where memory circuit 1200 includes a logic gate 1250, the signal VGH does not switch during a read operation.

[0043] Figure 15 illustrates a circuit diagram of an exemplary memory circuit 1500 that may be included in the memory circuit 100 of Figure 1 according to some embodiments. It should be understood that the memory circuit 1500 of Figure 15 is simplified for illustrative purposes and therefore can be implemented in any of a variety of other configurations while still remaining within the scope of the embodiments disclosed herein.

[0044] In some embodiments, memory circuit 1500 may be substantially similar to or incorporate features of memory circuits 100, 200, 300, 600, 900, 1200, etc. For example, memory circuit 1500 includes driver circuit 1530 and switching circuit 1560. Driver circuit 1530 includes a first p-type transistor 1531, a first n-type transistor 1532, a second p-type transistor 1533, a second n-type transistor 1534, a cross-coupled transistor 1538, etc. Unlike memory circuit 1200, memory circuit 1500 may alternatively include logic gate 1550.

[0045] In some embodiments, gate 1550 can be used to receive a logically inverted version of the select signal SEL and provide an output to cross-coupled transistor 1538. For example, gate 1550 can be used to receive a logically inverted version of the select signal SEL via an inverter through a first input and to receive a read-enable signal RDEN via a second input. Gate 1550 can provide an output to cross-coupled transistor 1538.

[0046] In some embodiments, driver circuitry 1530 may include a third p-type transistor 1570. The third p-type transistor 1570 may include: a first source / drain terminal coupled to the gate terminal of the first p-type transistor 1231; and a second source / drain terminal coupled to the source / drain terminal of the first p-type transistor 1531. In some embodiments, the gate terminal of the third p-type transistor 1570 may be coupled to an inverted version of the read enable signal RDEN_B. Similar to memory circuitry 1200 (e.g., as shown in Figure 13), in some embodiments, signal VGH does not switch with logic gate 1550, third p-type transistor 1570, etc., during read operations. For example, an inverted version of the read enable signal RDEN_B may be set to logic high during write operations and logic low during read operations. The read enable signal RDEN may be set to logic low during write operations and high during read operations. Although shown as a NOT OR gate, the logic gate 1550 may be or include any logic gate or combination thereof to receive various inputs and perform various logic operations.

[0047] As disclosed herein, memory circuitry, including driver circuitry and switching circuitry, is discussed. Although driver circuitry (e.g., driver circuitry 300, 600, 900, etc.) is shown and discussed as including transistors in various ways (e.g., type, arrangement, etc.), in some embodiments, not entirely dependent on this approach, memory circuitry or portions thereof (e.g., switching circuitry) may be used to assert word lines WL at a first supply voltage (e.g., VDD) during read operations and at a second supply voltage (e.g., VWLSET) or a third supply voltage (e.g., VWLRST) during write operations.

[0048] Figure 16 illustrates a flowchart of an exemplary method 1600 for operating memory circuitry according to some embodiments. In some embodiments, method 1600 can be used to operate memory circuitry (e.g., memory circuitry 100, 200, 300, etc.), and therefore, some of the references used above may be repeated in the following discussion of method 1600. It should be noted that method 1600 is merely an example and is not intended to limit the embodiments disclosed herein. Therefore, it should be understood that additional operations may be provided before, during, and after method 1600 of Figure 16, and only a few other operations may be briefly described herein.

[0049] In a brief overview, method 1600 may begin with operation 1610: a switchable voltage is coupled to a word line via a first p-type transistor, the word line being connected to a memory cell. Method 1600 may continue to operation 1620: an operating mode selection voltage level based on the memory cell is applied to the gate of a first n-type transistor having a first source / drain terminal connected to the word line.

[0050] At operation 1610, method 1600 includes the step of coupling a switchable voltage to a word line (e.g., word line WL in Figure 3) via a first p-type transistor (e.g., first p-type transistor 331), the word line being connected to a memory cell (e.g., memory cell 125). The switchable voltage can be selected from a first power supply voltage (e.g., VDD), a second power supply voltage (e.g., VWLSET), and a third power supply voltage (e.g., VWLRST) based on the operating mode of the memory cell.

[0051] In some embodiments, method 1600 includes the step of receiving a selection signal (e.g., selection signal SEL of Figure 3) via an inverter (e.g., inverter 335) including a second p-type transistor (e.g., second p-type transistor 333) and a second n-type transistor (e.g., second n-type transistor 334), the selection signal being configured to assert word lines in a specific logic state. In some embodiments, method 1600 includes the step of providing an intermediate signal (e.g., intermediate signal VS of Figure 3) to a second source / drain terminal of the first n-type transistor based on the selection signal.

[0052] In some embodiments, method 1600 includes the step of configuring a first p-type transistor and a first n-type transistor to operate at a higher voltage (e.g., higher than that of a second p-type transistor 333, a second n-type transistor 334, etc.). In some embodiments, method 1600 includes the step of configuring a second p-type transistor and a second n-type transistor to operate at a lower voltage (e.g., lower than that of a first p-type transistor 331, a first n-type transistor 332, etc.).

[0053] At operation 1620, method 1600 includes the step of: selecting a voltage level based on the operating mode of the memory cell, the voltage level being applied to the gate of a first n-type transistor (e.g., first n-type transistor 332), the first n-type transistor having a first source / drain terminal connected to a word line. The voltage level may be selected to be equal to a first supply voltage or a fourth supply voltage (e.g., VDMAX).

[0054] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes: a memory array including a plurality of memory cells coupled to word lines; and a driver circuit coupled to the memory cells via the word lines. The driver circuit includes: a first p-type transistor coupled between a switchable voltage and a word line, wherein the switchable voltage is selected from a first power supply voltage, a second power supply voltage, and a third power supply voltage; an inverter having an input for receiving a logically inverted version of a selection signal and an output for providing an intermediate signal, wherein the selection signal is provided to assert the word line in a first logic state; and a first n-type transistor having a gate, a first source / drain, and a second source / drain, wherein the gate is used to receive a control signal switching between a first power supply voltage and a fourth power supply voltage, the first source / drain is connected to the output of the inverter, and the second source / drain is connected to the word line.

[0055] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes: a driver circuit for applying a voltage to a word line, wherein the word line is connected to the gate of a selection transistor of a memory cell. The driver circuit includes: a first p-type transistor coupled between a switchable voltage and the word line, wherein the switchable voltage is selected from a first power supply voltage, a second power supply voltage, and a third power supply voltage; a first n-type transistor having a gate, a first source / drain terminal connected to the word line, and a second source / drain terminal, wherein the gate is configured to receive a control signal switching between the first power supply voltage and a fourth power supply voltage; and a second p-type transistor and a second n-type transistor, wherein the gates of the second p-type transistor and the second n-type transistor are configured to receive a logically inverted version of the selection signal, and the selection signal is provided in a first logic state to assert the word line.

[0056] In another embodiment of this disclosure, a method for operating a memory circuit is disclosed. The method includes the steps of: coupling a switchable voltage to a word line via a first p-type transistor, the word line being connected to a memory cell, wherein the switchable voltage is selected based on an operating mode of the memory cell from a first power supply voltage, a second power supply voltage, and a third power supply voltage; and selecting a voltage level based on the operating mode of the memory cell, the voltage level being applied to the gate terminal of a first n-type transistor having a first source / drain terminal connected to the word line, wherein the voltage level is selected to be equal to either the first power supply voltage or a fourth power supply voltage.

[0057] As used herein, the terms “about” and “approximately” generally refer to a given quantity value that can vary depending on the specific technology node associated with the target semiconductor device. Based on a specific technology node, the term “about” can refer to a given quantity value that varies, for example, within 10-30% of that value (e.g., +10%, ±20%, or ±30% of the value).

[0058] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that the embodiments disclosed herein can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of the embodiments disclosed herein.

[0059] 100, 200, 300, 600, 900, 1200, 1500: Memory circuit 105: Memory Controller 112: BL Controller 114: WL Controller 120: Memory Array 125, 225: Memory units 226: Resistive switching element 227: Select Transistor 230, 330, 630, 930, 1230, 1530: Driver circuits 331, 1231, 1531: First p-type transistors 332, 632, 932, 1232, 1532: Type-1 n transistors 333, 1233, 1533: Second p-type transistors 334, 1234, 1534: Type II n transistors 335: Inverter 338, 1538: Cross-coupled transistors 360, 960, 1260, 1560: Switching circuits 1250, 1550: Logic gates 1570: Type 3 p transistor 1600: Method 1610, 1620: Operations BL, BL0~BLK: Bit lines CTL: Control Signal HV: High voltage LV: Low pressure RDEN_B: Read the enable signal SEL: Select Signal SW_R, SW_RST, SW_SET: Switches tr: transistor VDD: First power supply voltage VDMAX: Fourth power supply voltage VGH: Signal VS: Intermediate Signal VWL: Switchable voltage VWLRST: Third power supply voltage VWLSET: Second power supply voltage WL, WL0~WLJ: Character lines

Claims

1. A memory circuit comprising: a memory array including a plurality of memory cells coupled to a word line; and a driver circuit coupled to the memory cells via the word line; wherein the driver circuit includes: a first p-type transistor coupled between a switchable voltage and the word line, wherein the switchable voltage is selected from a first power supply voltage, a second power supply voltage, and a third power supply voltage; a plurality of cross-coupled transistors coupled to a gate of the first p-type transistor, and for providing a signal to the gate of the first p-type transistor; An inverter has an input for receiving a logic-inverted version of a selection signal and an output for providing an intermediate signal, wherein the selection signal is provided in a first logic state to assert the word line; and a first n-type transistor has a gate, a first source / drain, and a second source / drain, wherein the gate is used to receive a control signal switching between a first power supply voltage and a fourth power supply voltage, the first source / drain is connected to the output of the inverter, and the second source / drain is connected to the word line.

2. The memory circuit of claim 1, wherein the inverter includes a second p-type transistor and a second n-type transistor, and wherein the first p-type transistor and the first n-type transistor are configured to operate at a higher voltage, while the second p-type transistor and the second n-type transistor are configured to operate at a lower voltage.

3. The memory circuit as claimed in claim 1, wherein when at least one of the memory cells is selected for writing and when at least one of the memory cells is selected for reading, the control signal is respectively configured at the first power supply voltage and the fourth power supply voltage, wherein the fourth power supply voltage is higher than the first power supply voltage.

4. The memory circuit as claimed in claim 1, wherein when at least one of the memory cells is selected for writing, the switchable voltage is configured at the second or third power supply voltage, and when at least one of the memory cells is selected for reading, the switchable voltage is configured at the first power supply voltage, wherein the third power supply voltage is higher than the second power supply voltage, and the second power supply voltage is higher than the first power supply voltage.

5. The memory circuit as claimed in claim 1, further comprising: a logic gate coupled between the selection signal and the cross-coupled transistors, wherein the logic gate is configured to receive the inverted version of the selection signal and provide an output to the cross-coupled transistors.

6. The memory circuit as claimed in claim 1, further comprising: a third p-type transistor having a first source / drain terminal coupled to the gate terminal of the first p-type transistor and a second source / drain terminal coupled to the source / drain terminal of the first p-type transistor.

7. A memory circuit comprising: a driver circuit for applying a voltage to a word line, wherein the word line is connected to a gate terminal of a select transistor of a memory cell; wherein the driver circuit comprises: a first p-type transistor coupled between a switchable voltage and the word line, wherein the switchable voltage is selected from a first power supply voltage, a second power supply voltage, and a third power supply voltage; a first n-type transistor having a gate terminal, a first source / drain terminal connected to the word line, and a second source / drain terminal, wherein the gate terminal is configured to receive a control signal switching between the first power supply voltage and a fourth power supply voltage; and a second p-type transistor and a second n-type transistor, wherein a plurality of gate terminals of the second p-type transistor and the second n-type transistor are configured to receive a logic inverted version of a select signal and provide the select signal in a first logic state to assert the word line.

8. The memory circuit as claimed in claim 7, wherein the second source / drain terminal of the first n-type transistor is connected to the second p-type transistor and the second n-type transistor, and the second n-type transistor and the second p-type transistor are used to provide an intermediate signal to the second source / drain terminal of the first n-type transistor.

9. A method of operating a memory circuit, comprising the steps of: coupling a switchable voltage to a word line via a first p-type transistor, the word line being connected to a memory cell, wherein the switchable voltage is selected based on an operating mode of the memory cell from a first power supply voltage, a second power supply voltage, and a third power supply voltage; selecting a voltage level based on the operating mode of the memory cell, the voltage level being applied to a gate terminal of a first n-type transistor having a first source / drain terminal connected to the word line, wherein the selected voltage level is equal to the first power supply voltage or a fourth power supply voltage; and selecting the voltage level equal to the fourth power supply voltage when the operating mode is a read mode, wherein the fourth power supply voltage is higher than the first power supply voltage.

10. The method of claim 9 further comprises the steps of: receiving a select signal via an inverter including a second p-type transistor and a second n-type transistor, the select signal being used to assert the word line in a specific logic state; and providing an intermediate signal to a second source / drain terminal of the first n-type transistor based on the select signal, wherein the first p-type transistor and the first n-type transistor are used to operate at a higher voltage, and the second p-type transistor and the second n-type transistor are used to operate at a lower voltage.

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