Semiconductor device and method for forming the same

Abstract

This disclosure provides a semiconductor device and a method for forming the same. The method includes the following steps: providing a substrate having a first conductivity type; forming a device isolation structure defining a plurality of active regions in the substrate; providing a stacked structure on each active region, wherein the stacked structure includes a first stack and first spacers on opposite sidewalls of the first stack; forming a plurality of first lightly doped regions in each active region at opposite sides of the stacked structure, and forming a plurality of second lightly doped regions below the plurality of first lightly doped regions, wherein the first lightly doped regions have a second conductivity type different from the first conductivity type, and the second lightly doped regions have the first conductivity type.

Claims

1. A method of forming a semiconductor device, comprising: A substrate is provided, wherein the substrate has a first conductivity type; a device isolation structure is formed in the substrate to define a plurality of active regions in the substrate; A stacked structure is provided on each of the said active regions, wherein the stacked structure includes a first stack and first spacers on opposite sidewalls of the first stack, the first stack including a gate insulating layer, a high dielectric constant layer, a top cap layer, a sacrificial gate layer and a hard mask layer sequentially stacked on the substrate; and a plurality of first lightly doped regions and a plurality of second lightly doped regions below the plurality of first lightly doped regions are formed in each of the said active regions at opposite sides of the stacked structure, wherein the first lightly doped regions have a second conductivity type different from the first conductivity type, and the second lightly doped regions have the first conductivity type, wherein the first lightly doped regions overlap with the second lightly doped regions, and the side of the first lightly doped region below the first spacer is aligned with the side of the second lightly doped region below the first spacer.

2. The method as described in claim 1, wherein the bottom of the second lightly doped region is formed at a level higher than the bottom of the device isolation structure.

3. The method as described in claim 1, wherein the bottom of the second lightly doped region is at or below the level of the bottom of the device isolation structure.

4. A method of forming a semiconductor device, comprising: A substrate is provided, wherein the substrate has a first conductivity type; a device isolation structure is formed in the substrate to define a plurality of active regions in the substrate; A stacked structure is provided on each of the said active regions, wherein the stacked structure includes a first stack and first spacers on opposite sidewalls of the first stack, the first stack including a gate insulating layer, a high dielectric constant layer, a top cap layer, a sacrificial gate layer and a hard mask layer sequentially stacked on the substrate; and a plurality of first lightly doped regions and a plurality of second lightly doped regions are formed in each of the said active regions at opposite sides of the stacked structure, wherein the first lightly doped regions have a second conductivity type different from the first conductivity type, and the second lightly doped regions have the first conductivity type, wherein the first lightly doped regions include a first portion overlapping with the second lightly doped regions and a second portion not overlapping with the second lightly doped regions.

5. The method as described in claim 4, wherein the bottom of the second lightly doped region is formed at a level higher than, equal to, or lower than the bottom of the device isolation structure.

6. A method of forming a semiconductor device, comprising: A substrate is provided, wherein the substrate has a first conductivity type; a device isolation structure is formed in the substrate to define a plurality of active regions in the substrate; A stacked structure is provided on each of the said active regions, wherein the stacked structure includes a first stack and first spacers on opposite sidewalls of the first stack, the first stack including a gate insulating layer, a high dielectric constant layer, a top cap layer, a sacrificial gate layer and a hard mask layer sequentially stacked on the substrate; and a plurality of first lightly doped regions and a plurality of second lightly doped regions below the plurality of first lightly doped regions are formed in each of the said active regions at opposite sides of the stacked structure, wherein the first lightly doped regions have a second conductivity type different from the first conductivity type, and the second lightly doped regions have the first conductivity type, wherein the second lightly doped regions include a first portion overlapping the first lightly doped regions and a second portion not overlapping the first lightly doped regions and located below the first stack, wherein the bottom of the second lightly doped regions is formed at a level higher than, equal to or lower than the bottom of the device isolation structure.

7. A method of forming a semiconductor device, comprising: A substrate is provided, wherein the substrate has a first conductivity type; a device isolation structure is formed in the substrate to define a plurality of active regions in the substrate; A stacked structure is provided on each of the said active regions, wherein the stacked structure includes a first stack and first spacers on opposite sidewalls of the first stack, the first stack including a gate insulating layer, a high dielectric constant layer, a top cap layer, a sacrificial gate layer, and a hard mask layer sequentially stacked on the substrate; a plurality of first lightly doped regions and a plurality of second lightly doped regions are formed in each of the said active regions at opposite sides of the stacked structure, wherein the first lightly doped regions have a second conductivity type different from the first conductivity type, and the second lightly doped regions have the first conductivity type; second spacers are formed on opposite sidewalls of the stacked structure; source / drain regions are formed in the first lightly doped regions; and silicon layers are formed in the source / drain regions.

8. A semiconductor device, comprising: The substrate has a first conductivity type and includes multiple active regions; A device isolation structure is disposed in the substrate to define a plurality of the active regions; Multiple gate structures are disposed on multiple active regions, each gate structure including a first stack, a first spacer on opposite sidewalls of the first stack, and a second spacer on the first spacer. The first stack includes a gate insulating layer, a high dielectric constant layer, a capping layer, and a gate layer sequentially stacked on the substrate. Multiple first lightly doped regions are disposed in each of the active regions on opposite sides of the first stack and have a second conductivity type different from the first conductivity type. Multiple second lightly doped regions are disposed below the multiple first lightly doped regions and have the first conductivity type. Multiple source / drain regions are disposed in the first lightly doped regions.

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