Semiconductor device and formation method thereof

Abstract

A method of forming a semiconductor device includes the following steps: A first active region and a second active region are formed over a substrate. An isolation feature is formed along a direction over the substrate and between the first active region and the second active region. A first gate structure is formed over the first active region and a second gate structure is formed over the second active region. A gate isolation feature is formed along this direction and disposed between the first gate structure and the second gate structure, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a dielectric constant of less than about 4.

Claims

1. A method of forming a semiconductor device, comprising: forming a first active region and a second active region over a substrate; forming an isolation feature over the substrate along a direction and between the first active region and the second active region; forming a first gate structure over the first active region and forming a second gate structure over the second active region; and forming a gate isolation feature disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes a SiOC with a dielectric constant of less than about 4, wherein forming the gate isolation feature comprises: pulse a first precursor to the substrate; pulse a second precursor to the substrate; and pulse a reactant to the substrate to cleave the first precursor and the second precursor.

2. The method of claim 1, wherein forming the gate isolation feature comprises: forming the gate isolation feature using flowable chemical vapor deposition.

3. The method of claim 1, wherein the second precursor comprises a Si-H group.

4. The method as described in claim 1, wherein the first precursor is a siloxane precursor.

5. A method of forming a semiconductor device, comprising: forming a first active region and a second active region over a substrate; forming an isolation feature over the substrate along a direction and between the first active region and the second active region; forming a first gate structure over the first active region and forming a second gate structure over the second active region; forming a source / drain feature over the substrate; forming a contact etch stop layer (CESL) extending along a sidewall of the first gate structure and a sidewall of the second gate structure; forming an inter-dielectric layer (ILD) over the CESL, wherein the CESL between the ILD layer and the source / drain feature includes a non-linear profile; and forming a gate isolation feature disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes a SiOC with a dielectric constant of less than about 4, wherein forming the gate isolation feature includes: pulse a first precursor onto the substrate; A second precursor is pulsed onto the substrate; and a reactant is pulsed onto the substrate to cleave the first precursor and the second precursor.

6. The method of claim 5, wherein the gate isolation feature has an upper sidewall, a curved intermediate sidewall, and a lower sidewall, and the curved intermediate sidewall is located between the upper sidewall and the lower sidewall.

7. The method as described in claim 6, wherein the curved intermediate sidewall is convex.

8. A semiconductor device comprising: a first channel region and a second channel region extending over a substrate; an isolation feature disposed over the substrate and between the first channel region and the second channel region; a first gate stack disposed over the first channel region and the isolation feature; a second gate stack disposed over the second channel region and the isolation feature; a gate spacer disposed along a sidewall of the first gate stack, wherein the first gate stack includes a gate dielectric layer and a gate electrode above the gate dielectric layer, wherein a bottom surface of the gate spacer is lower than a top surface of the first channel region, wherein a dielectric constant of the gate spacer is less than a dielectric constant of the gate dielectric layer; and a gate isolation feature disposed between the first gate stack and the second gate stack, wherein a middle portion of the gate isolation feature has a first curved sidewall, and a bottom portion of the gate isolation feature has a sloping sidewall, the curvature of the first curved sidewall being greater than the curvature of the sloping sidewall.

9. The semiconductor element as claimed in claim 8, wherein the gate isolation feature includes a second curved sidewall opposite to the first curved sidewall.

10. The semiconductor element as claimed in claim 8, wherein the gate isolation feature is seamless.

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