Enhanced electromigration storage device applied to non-volatile memory

Abstract

This invention relates to an enhanced electromigration storage element for non-volatile memory. During programming, two different voltages are simultaneously applied to the gate terminals of a FinFET or GAA transistor. Furthermore, the threshold voltage of the FinFET or GAA transistor is changed using an electromigration mechanism. Therefore, the storage element can be in a programmed or unprogrammed state. During reading, the same voltage is applied to the gate terminals of the FinFET or GAA transistor, and the storage state of the storage element is determined based on the read current generated by the FinFET or GAA transistor.

Description

[Technical Field]

[0001] The present invention relates to a non-volatile memory, and more particularly to an enhanced electromigration storage element used in non-volatile memory. [Previous Technology]

[0002] As is well known, non-volatile memory (MVM) is widely used in various electronic products, such as SD cards and solid-state drives (SSDs). MVM includes a memory cell array, which is composed of multiple memory cells. Furthermore, each memory cell contains a storage device, such as an antifuse transistor.

[0003] The storage state of an antifuse transistor is determined by the state of its gate dielectric layer. When the gate dielectric layer of the antifuse transistor is intact, the storage element is in the first storage state. Programming the memory cell causes the gate dielectric layer of the antifuse transistor to rupture, then the storage element enters the second storage state. Furthermore, once the gate dielectric layer of the antifuse transistor ruptures, the storage element cannot be returned to the first storage state.

[0004] For example, US Patent 12,289,883 discloses a one-time programming memory cell with a fin field-effect transistor using physically unclonable function technology. The storage element in the one-time programming memory cell is a fin field-effect transistor (hereinafter referred to as FinFET transistor). Please refer to Figures 1A, 1B, and 1C, which illustrate a perspective view, a top view, and a cross-sectional view along the dotted line AB of the FinFET transistor. The FinFET transistor MFIN includes: a gate structure, drain / source contact layers 130 and 140, and fins 112, 114, 116, and 118.

[0005] The gate structure is located on the insulating layer 110. The gate structure covers the middle region of fins 112, 114, 116, and 118. The gate structure includes a gate conductive layer 120 and gate dielectric layers 122, 124, 126, and 128. The gate dielectric layers 122, 124, 126, and 128 respectively cover the middle region and the two lateral surfaces of fins 112, 114, 116, and 118, and the gate conductive layer 120 covers the gate dielectric layers 122, 124, 126, and 128. Furthermore, the drain / source contact layer 130 is electrically contacted on the first lateral region of fins 112, 114, 116, and 118, and the drain / source contact layer 140 is electrically contacted on the second lateral region of fins 112, 114, 116, and 118.

[0006] The gate conductive layer 120 serves as the gate terminal of the FinFET transistor MFIN, the drain / source contact layer 130 serves as the first drain / source terminal of the FinFET transistor MFIN, and the drain / source contact layer 140 serves as the second drain / source terminal of the FinFET transistor MFIN. Of course, the number of fins in the FinFET transistor MFIN is not limited, as long as the number of fins is greater than or equal to 1. Furthermore, the two FinFET transistors can have various connection relationships.

[0007] Please refer to Figure 2, which shows a schematic diagram of two FinFET transistors. Compared to the single FinFET transistor MFIN in Figure 1A, in Figure 2, the drain / source contact layer 130 is electrically contacted on the first side region of fins 112 and 114, and the drain / source contact layer 140 is electrically contacted on the second side region of fins 112 and 114. The drain / source contact layer 156 is electrically contacted on the first side region of fins 116 and 118, and the drain / source contact layer 158 is electrically contacted on the second side region of fins 116 and 118. The drain / source contact layer 130 is not electrically contacted on the drain / source contact layer 156, and the drain / source contact layer 140 is not electrically contacted on the drain / source contact layer 158. Therefore, two FinFET transistors MFIN1 and MFIN2 can be formed. Each FinFET transistor MFIN1 and MFIN2 includes two fins, and the two FinFET transistors MFIN1 and MFIN2 share the gate conductive layer 120.

[0008] US Patent Publication No. 2023 / 0371249A1 discloses an antifuse-type one-time programming memory cell with a gate-all-around transistor. The storage element in the one-time programming memory cell is a gate-all-around transistor (hereinafter referred to as a GAA transistor). Please refer to Figures 3A, 3B, 3C, and 3D, which illustrate a perspective view, a top view, and cross-sectional views along the dashed lines ab and cd of the GAA transistor. The GAA transistor MGAA includes: a gate structure 220, drain / source structures 232 and 236, and a nanowire 230.

[0009] Gate structure 220 is located on insulating layer 210. Gate structure 220 includes two spacers 252 and 246, gate dielectric layer 222 and gate conductive layer 224. Gate dielectric layer 222 surrounds the middle region of nanowire 230, gate conductive layer 224 surrounds gate dielectric layer 222, and gate conductive layer 224 is located on insulating layer 210. Furthermore, the first side region of nanowire 230 is surrounded by spacer 252, and the second side region of nanowire 230 is surrounded by spacer 246, and spacers 252 and 246 are located on semiconductor substrate sub. Moreover, drain / source structure 232 is electrically contacted at the first end of nanowire 230, and drain / source structure 236 is electrically contacted at the second end of nanowire 230.

[0010] The gate conductive layer 224 serves as the gate terminal of the GAA transistor MGAA, the drain / source structure 232 serves as the first drain / source terminal of the GAA transistor MGAA, and the drain / source structure 236 serves as the second drain / source terminal of the GAA transistor MGAA. Of course, the number of nanowires in the GAA transistor is not limited, as long as the number of nanowires is greater than or equal to 1. Furthermore, the two GAA transistors can have various connection relationships.

[0011] Please refer to Figure 4, which shows a schematic diagram of two GAA transistors. Compared to the single GAA transistor MGAA in Figure 3A, in Figure 4, the gate structure further includes a gate dielectric layer 284. A nanowire 290 passes through the gate structure 220, the gate dielectric layer 284 surrounds the middle region of the nanowire 290, and a gate conductive layer 224 surrounds the gate dielectric layer 284. Furthermore, a drain / source structure 292 is electrically contacted at the first end of the nanowire 290, and a drain / source structure 296 is electrically contacted at the second end of the nanowire 290. A drain / source structure 232 is not electrically contacted with a drain / source structure 292, and a drain / source structure 236 is not electrically contacted with a drain / source structure 296. Therefore, two GAA transistors, MGAA1 and MGAA2, can be formed. Each GAA transistor MGAA1 and MGAA2 includes two nanowires, and the two GAA transistors MGAA1 and MGAA2 share a gate conductive layer 224.

[0012] Conventional non-volatile memory cells require a higher operating voltage to change their storage state. For example, when programming a memory cell, the cell receives a programming voltage, such as 8V to 12V, and the resulting programming current is approximately several hundred mA.

[0013] Because the programming voltage is higher than the supply voltage typically received by an IC chip, such as 1.2V, non-volatile memory usually incorporates a charge pump to boost the supply voltage to a higher operating voltage. As is well known, charge pumps occupy a very large layout area on the IC chip. [Summary of the Invention]

[0014] The present invention relates to a storage element of a non-volatile memory, comprising: a first fin field-effect transistor, comprising: a first fin, a gate structure, a first drain / source contact layer and a second drain / source contact layer; wherein, the gate structure comprises: a first gate dielectric layer, a first conductive layer and a second conductive layer; wherein, the first gate dielectric layer covers an upper part of a middle region and two side surfaces of the first fin, the first conductive layer covers the first gate dielectric layer, the second conductive layer covers the first conductive layer, the first drain / source contact layer is electrically contacted to a first side region of the first fin, and the second drain / source contact layer is electrically contacted to a second side region of the first fin; A first conductor is located on a first side of the gate structure and electrically connected to a first side of the second conductive layer; and a second conductor is located on a second side of the gate structure and electrically connected to a second side of the second conductive layer; wherein, during a programming operation, the first conductor receives a first voltage and the second conductor receives a second voltage; wherein a programming current flows from the first conductor through the first conductive layer and the second conductive layer to the second conductor, and the first voltage is greater than the second voltage; wherein, during a reading operation, at least the One of the first and second conductors receives a control voltage, the first drain / source contact layer receives a third voltage, and the second drain / source contact layer receives a fourth voltage, wherein the third voltage is greater than the fourth voltage; wherein a first read current flows from the first drain / source contact layer through a channel region of the first fin field-effect transistor to the second drain / source contact layer, and a storage state of the storage element is determined according to the first read current; wherein the difference between the first voltage and the second voltage is equal to a programming voltage, and the difference between the third voltage and the fourth voltage is equal to a read voltage.

[0015] The present invention relates to a storage element for a non-volatile memory, comprising: a first all-around gate transistor, comprising: a first nanowire, a gate structure, a first drain / source structure and a second drain / source structure, wherein the gate structure comprises: a first gate dielectric layer, a first conductive layer and a second conductive layer; wherein the first gate dielectric layer surrounds a central region of the first nanowire, the first conductive layer surrounds the first gate dielectric layer, the second conductive layer surrounds the first conductive layer, the first drain / source structure is electrically contacted with a first side region of the first nanowire, and the second drain / source structure is electrically contacted with a second side region of the first nanowire; A first conductor is located on a first side of the gate structure and electrically connected to a first side of the second conductive layer; and a second conductor is located on a second side of the gate structure and electrically connected to a second side of the second conductive layer; wherein, during a programming operation, the first conductor receives a first voltage and the second conductor receives a second voltage; wherein a programming current flows from the first conductor through the first conductive layer and the second conductive layer to the second conductor, and the first voltage is different from the second voltage; wherein, during a reading operation, to One of the first and second conductors receives a control voltage, the first drain / source structure receives a third voltage, and the second drain / source structure receives a fourth voltage, wherein the third voltage is greater than the fourth voltage; wherein a first read current flows from the first drain / source structure through a channel region of the first all-around gate transistor to the second drain / source structure, and a storage state of the storage element is determined according to the first read current; wherein the difference between the first voltage and the second voltage is equal to a programming voltage, and the difference between the third voltage and the fourth voltage is equal to a read voltage.

[0016] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings:

Implementation Method

[0018] Electromigration (EM) is a phenomenon in which the movement of electrons within a current-carrying conductor transfers their kinetic energy to metal ions in the conductor, causing the ions to migrate gradually in the opposite direction of the electric field, resulting in atomic diffusion and loss within the conductor. This invention utilizes the mechanism of electromigration to design storage elements for non-volatile memory cells. For example, the storage element can be a FinFET transistor or a gate-all-around transistor (GAA transistor).

[0019] Basically, the threshold voltage of FinFET transistors and GAA transistors is determined by the material and thickness of the work function metal layer. The gate voltage received at the gate terminals of FinFET transistors and GAA transistors is used to control the turn-on and turn-off states of the FinFET transistors and GAA transistors. In other words, those skilled in the art would not simultaneously apply different voltages to the gate terminals of FinFET transistors and GAA transistors.

[0020] This invention utilizes FinFET transistors or GAA transistors as storage elements in memory cells. During programming, two different voltages are simultaneously applied to the gate terminals of the FinFET transistor or GAA transistor. Furthermore, an electromigration mechanism is used to change the threshold voltage of the FinFET transistor or GAA transistor, allowing the storage element to be in a programmed or unprogrammed state. During reading, the same voltage is applied to the gate terminals of the FinFET transistor or GAA transistor, and the storage state of the storage element is determined based on the read current generated by the FinFET transistor or GAA transistor.

[0021] Please refer to Figure 5A, which shows a cross-sectional view of the gate structure of the enhanced electromigration storage element according to the first embodiment of the present invention. Figure 5B is a top view of the enhanced electromigration storage element according to the first embodiment of the present invention. Furthermore, the enhanced electromigration storage element 500 will be simply referred to as storage element 500 below, and the storage element 500 is designed in the memory cell of non-volatile memory.

[0022] The storage element 500 of the first embodiment includes a FinFET transistor MFIN and conductive lines 545 and 547. The FinFET transistor MFIN is located above the semiconductor substrate sub and the insulating layer 510. The FinFET transistor MFIN of the first embodiment has a structure similar to that of the FinFET transistor MFIN in Figure 1C, but has only one fin 512. Of course, the fin 512 of the FinFET transistor MFIN inside the storage element 500 is not limited to only one. The FinFET transistor MFIN includes: a fin 512, a gate structure, and two drain / source contact layers 562 and 566. The gate structure includes: a gate dielectric layer 522 and two conductive layers 532 and 542. The gate dielectric layer 522 covers the middle region and two side surfaces of the fin 512, the conductive layer 532 covers the gate dielectric layer 512, and the conductive layers 542 cover the conductive layer 532. In other words, the gate conductive layer of the FinFET transistor MFIN is composed of conductive layers 532 and 542. Conductive layer 532 is a work function metal layer. For example, the material of conductive layer 532 is titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). Alternatively, the material of conductive layer 542 can be the same as conductive layer 532.

[0023] Furthermore, a conducting line 545 is formed above the first side of the gate structure and is electrically connected to the first side of the conductive layer 542. A conducting line 547 is formed above the second side of the gate structure and is electrically connected to the second side of the conductive layer 542. Basically, contact holes can be formed above both sides of the conductive layer 542, and the conducting lines 545 and 547 can be formed by filling the contact holes with metal. Similarly, a conducting line 561 can also be formed to electrically connect to the source / drain contact layer 562, and a conducting line 565 can be formed to electrically connect to the source / drain contact layer 566.

[0024] This invention utilizes electromigration to perform programming operations. During programming, different voltages are provided to two wires 545 and 547. Therefore, a programming current flows between the two wires 545 and 547. Since electrons in the programming current flow through conductive layers 542 and 532, conductive layer 532 gradually migrates in the opposite direction of the electric field, causing a change in the thickness of conductive layer 532. In other words, this invention utilizes electromigration to create a change in the thickness of the function metal layer, thereby altering the threshold voltage of the FinFET transistor MFIN.

[0025] In addition, during programming, the two drain / source contact layers 562 and 566 of the FinFET transistor MFIN do not need to be provided with any bias voltage. That is, during programming, the two wires 561 and 565 can be floating.

[0026] Please refer to Figure 6A, which illustrates a schematic diagram of programming the storage element of the first embodiment. Before programming, the storage element 500 is in an unprogrammed state. When programming the storage element 500, different voltages are provided to two wires 545 and 547. For example, a programming voltage VPGM is provided to wire 545, and a ground voltage (GND) is provided to wire 547, such that the voltage difference between the two wires 545 and 547 is the programming voltage VPGM. At this time, wire 545 can be regarded as an anode, and wire 547 can be regarded as a cathode, so that the programming current IPGM flows through the conductive layers 532 and 542.

[0027] As shown in Figure 6A, the programming current IPGM (dashed line) flows from conductor 545 through conductive layers 532 and 542 to conductor 547. Generally, electromigration begins at the cathode (i.e., conductor 547). Due to the mechanism of electromigration, metal ions in conductive layers 532 and 542 near the cathode migrate in the opposite direction of the electric field (i.e., to the right). Therefore, after programming, the thickness of conductive layer 532 (shown by the diagonal line on the left) becomes thinner, causing a change in the threshold voltage of the FinFET transistor MFIN, and the storage state of storage element 500 becomes the programmed state. For example, before programming, the threshold voltage of the FinFET transistor MFIN is 0.5V. After programming, the threshold voltage of the FinFET transistor MFIN changes to 0.3V.

[0028] According to a first embodiment of the present invention, when the programming current IPGM is approximately 100 μA or more, the threshold voltage of the FinFET transistor MFIN can be changed by approximately 0.2 to 0.3 V. Since the resistance of the conductive layers 532 and 542 is very low, the programming voltage VPGM is very low. For example, a programming voltage VPGM of approximately 1.5 V to 2.5 V is sufficient for programming. Compared to conventional non-volatile memory which requires a higher programming voltage (e.g., 8 V to 12 V), the storage element 500 of the present invention has the advantages of low programming voltage and low programming current. In other words, a non-volatile memory composed of the storage element 500 of the present invention does not require a very high programming voltage VPGM to complete the programming operation. Furthermore, since a charge pump is not required in the non-volatile memory to provide a high programming voltage VPGM, the overall layout area of ​​the non-volatile memory can be significantly reduced.

[0029] Please refer to Figures 6B and 6C, which illustrate a read operation of the storage element in the first embodiment. For example, in Figure 6B, the storage element 500 is in an unprogrammed state, and the threshold voltage of the FinFET transistor MFIN is 0.5V. In Figure 6C, the storage element 500 is in a programmed state, and the threshold voltage of the FinFET transistor MFIN is 0.3V.

[0030] When reading from storage element 500, the same control voltage VCTRL is provided to the two wires 545 and 547, so no current is generated between wires 545 and 547. Alternatively, different voltages are provided to the two wires 561 and 565. For example, a read voltage VRD is provided to wire 561, and a ground voltage (GND) is provided to wire 565, such that the voltage difference between the two wires 561 and 565 is the read voltage VRD. For example, the read voltage VRD is 1.0V.

[0031] According to the first embodiment of the present invention, during the read operation, the control voltage VCTRL is set to 0.4V and supplied to the wires 545 and 547, so no current is generated between the wires 545 and 547. As shown in Figure 6B, since the control voltage VCTRL is less than the threshold voltage (0.5V) of the FinFET transistor MFIN, the FinFET transistor MFIN is turned off, and the read current IRD between the two wires 561 and 565 is very small, almost zero. In addition, as shown in Figure 6C, since the control voltage VCTRL is greater than the threshold voltage (0.3V) of the FinFET transistor MFIN, the FinFET transistor MFIN is turned on. Therefore, the FinFET transistor MFIN generates a large read current IRD, and the read current IRD flows from the wire 561 through the drain / source contact layer 562, the channel region of the FinFET transistor MFIN, and the drain / source contact layer 566 to the wire 565. Of course, in other embodiments, during the reading operation, the control voltage VCTRL can be provided to one of the wires 545 and 547, while the other of the wires 545 and 547 is floating.

[0032] Furthermore, the storage state of the memory element can be determined using a sensing circuit. For example, a current comparator (not shown) is designed as a sensing circuit in a non-volatile memory. The first input of the current comparator receives the read current IRD, the second input receives the reference current IREF, and the output generates an output signal. When the read current IRD is greater than the reference current IREF, the current comparator outputs a first logic level signal, indicating that the memory element 500 is in a programmed state. Conversely, when the read current IRD is less than the reference current IREF, the current comparator outputs a second logic level signal, indicating that the memory element 500 is in an unprogrammed state. That is, the FinFET transistor MFIN in Figure 6B generates a very small (close to zero) read current IRD, so the memory element 500 is determined to be in an unprogrammed state. While the FinFET transistor MFIN in Figure 6C generates a larger read current IRD, so the memory element 500 is determined to be in a programmed state.

[0033] Of course, in other embodiments, a reference memory cell can also be designed in the non-volatile memory. The reference memory cell includes a reference storage element, the structure of which is similar to that in Figure 5A. The reference storage element can be in an unprogrammed state or a programmed state. During a read operation, the reference storage element receives a control voltage VCTRL and a read voltage VRD, and outputs a reference current IREF.

[0034] Furthermore, the sensing circuit in the non-volatile memory receives the read current IRD and the reference current IREF, and determines the storage state of the storage element based on the difference between the read current IRD and the reference current IREF.

[0035] For example, the reference storage element is in an unprogrammed state. Therefore, when the difference between the read current IRD and the reference current IEF is less than a specific value, the storage element is determined to be in an unprogrammed state. Conversely, when the difference between the read current IRD and the reference current IEF is greater than that specific value, the storage element is determined to be in a programmed state.

[0036] Alternatively, the reference storage element is in a programmed state. Therefore, when the difference between the read current IRD and the reference current IEF is less than a specific value, the storage element is determined to be in a programmed state. Conversely, when the difference between the read current IRD and the reference current IEF is greater than that specific value, the storage element is determined to be in an unprogrammed state.

[0037] Please refer to Figure 7A, which shows a cross-sectional view of the gate structure of the enhanced electromigration storage element according to the second embodiment of the present invention. Figure 7B is a top view of the enhanced electromigration storage element according to the second embodiment of the present invention. The storage element 600 includes two FinFET transistors, MFINA and MFINB, and the storage element 600 is designed in a differential memory cell of non-volatile memory.

[0038] The storage element 600 of the second embodiment includes FinFET transistors MFINA and MFINB, and wires 645 and 647. The FinFET transistors MFINA and MFINB are located above the semiconductor substrate sub and the insulating layer 610. The structures of the FinFET transistors MFINA and MFINB are similar to those of the FinFET transistors MFIN1 and MFIN2 in Figure 2, but the FinFET transistors MFINA and MFINB each have only one fin 612 and 614, respectively. Of course, the fins 612 and 614 of the FinFET transistors MFINA and MFINB inside the storage element 600 are not limited to only one. The FinFET transistor MFINA includes: fin 612, a gate structure, and two drain / source contact layers 662 and 666. The FinFET transistor MFINB includes: fin 614, a gate structure, and two drain / source contact layers 664 and 668. The gate structure includes gate dielectric layers 622 and 624, and conductive layers 632, 634, and 642. Gate dielectric layer 622 covers the upper part of the middle region and the two side surfaces of fin 612, gate dielectric layer 624 covers the upper part of the middle region and the two side surfaces of fin 614, conductive layer 632 covers gate dielectric layer 622, conductive layer 634 covers gate dielectric layer 624, and conductive layer 642 covers conductive layers 632 and 634. In other words, the gate conductive layers of FinFET transistors MFINA and MFINB are composed of conductive layers 632, 634, and 642, and the two FinFET transistors MFINA and MFINB share conductive layer 642. Conductive layers 632 and 634 are work function metal layers. For example, the materials of conductive layers 632 and 634 are titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). Alternatively, the material of conductive layer 642 can be the same as that of conductive layers 632 and 634.

[0039] Furthermore, a wire 645 is formed above the first side of the gate structure and is electrically connected to the first side of the conductive layer 642. A wire 647 is formed above the second side of the gate structure and is electrically connected to the second side of the conductive layer 642. Similarly, a wire 661 may also be formed to be electrically connected to the draw / source contact layer 662, a wire 665 may be formed to be electrically connected to the draw / source contact layer 666, a wire 663 may be formed to be electrically connected to the draw / source contact layer 664, and a wire 667 may be formed to be electrically connected to the draw / source contact layer 668.

[0040] This invention utilizes electromigration to perform programming operations. During programming, different voltages are applied to two wires 645 and 647, generating a programming current between them. As electrons in the programming current flow through conductive layers 632, 634, and 642, conductive layer 632 gradually migrates in the opposite direction of the electric field, causing a change in its thickness. In other words, this invention utilizes electromigration to create a change in the thickness of the functional metal layer, thereby altering the threshold voltage of the FinFET transistor MFINA.

[0041] In addition, during programming, the two drain / source contact layers 662 and 666 of the FinFET transistor MFINA and the two drain / source contact layers 664 and 668 of the FinFET transistor MFINB do not need to provide any bias voltage. That is, the wires 661, 665, 663, and 667 can be floated.

[0042] Please refer to Figure 8A, which illustrates a schematic diagram of programming the storage element of the second embodiment. Before programming, the storage element 600 is in an unprogrammed state. When programming the storage element 600, different voltages are provided to two wires 645 and 647. For example, a programming voltage VPGM is provided to wire 645, and a ground voltage (GND) is provided to wire 647, such that the voltage difference between the two wires 645 and 647 is the programming voltage VPGM. That is, wire 645 can be regarded as an anode, and wire 647 can be regarded as a cathode, so that the programming current IPGM flows through the conductive layers 632, 634, and 642.

[0043] As shown in Figure 8A, the programming current IPGM (dashed line) flows from conductor 645 through conductive layers 632, 634, and 642 to conductor 647. Generally, electromigration begins at the cathode (i.e., conductor 647). Due to the mechanism of electromigration, metal ions in conductive layers 632 and 642 near the cathode migrate in the opposite direction of the electric field (i.e., to the right). Therefore, after programming, the thickness of conductive layer 632 (shown by the diagonal line on the left) thins, causing a change in the threshold voltage of the FinFET transistor MFINA, and the storage state of storage element 600 becomes the programming state. For example, before programming, the threshold voltages of both FinFET transistors MFINA and MFINB are 0.5V. After programming, the threshold voltage of FinFET transistor MFINA changes to 0.3V, while the threshold voltage of FinFET transistor MFINB remains at 0.5V. Of course, in other embodiments, after the programming operation is completed, the thickness of the conductive layer 634 on the left and right sides may also increase, causing the threshold voltage of the FinFET transistor MFINB to change and be greater than 0.5V.

[0044] According to a second embodiment of the present invention, when the programming current IPGM is approximately 100 μA or more, the threshold voltage of the FinFET transistor MFINA can be changed by approximately 0.2 to 0.3 V. Since the resistance of the conductive layers 632, 634, and 642 is very low, the programming voltage VPGM is very low. For example, a programming voltage VPGM of approximately 1.5 V to 2.5 V is sufficient for programming. Compared to conventional non-volatile memory which requires a higher programming voltage (e.g., 8 V to 12 V), the storage element 600 of the present invention has the advantages of low programming voltage and low programming current. In other words, a non-volatile memory composed of the storage element 600 of the present invention does not require a very high programming voltage VPGM to complete the programming operation. Furthermore, since a charge pump is not required in the non-volatile memory to provide a high programming voltage VPGM, the overall layout area of ​​the non-volatile memory can be significantly reduced.

[0045] Please refer to Figures 8B and 8C, which illustrate a reading operation of the storage element in the second embodiment. For example, in Figure 8B, the storage element 600 is in an unprogrammed state, and the threshold voltages of the FinFET transistors MFINA and MFINB are both 0.5V. In Figure 8C, the storage element 600 is in a programmed state, and the threshold voltage of the FinFET transistor MFINA is 0.3V, and the threshold voltage of the FinFET transistor MFINB is 0.5V.

[0046] When reading from storage element 600, the same control voltage VCTRL is provided to the two wires 645 and 647, so no current is generated between wires 645 and 647. Alternatively, different voltages are provided to the two wires 661 and 665, and different voltages are provided to the two wires 663 and 667. For example, a read voltage VRD is provided to wires 661 and 663, and a ground voltage (GND) is provided to wires 665 and 667. Therefore, the voltage difference between the two wires 661 and 665 is the read voltage VRD, and the voltage difference between the two wires 663 and 667 is the read voltage VRD. For example, the read voltage VRD is 1.0V. In other embodiments, during the read operation, at least one of the two wires 645 and 647 may receive the control voltage VCTRL.

[0047] According to the second embodiment of the present invention, during the read operation, the control voltage VCTRL is set to 0.4V and provided to the two wires 645 and 647, so no current is generated between the wires 645 and 647. As shown in Figure 8B, since the control voltage VCTRL is less than the threshold voltage (0.5V) of the FinFET transistors MFINA and MFINB, the FinFET transistors MFINA and MFINB are turned off, the read current IRDA between the two wires 661 and 665 is very small and almost zero, and the read current IRDB between the two wires 663 and 667 is very small and almost zero. In addition, as shown in Figure 8C, since the control voltage VCTRL is greater than the threshold voltage (0.3V) of the FinFET transistor MFINA and less than the threshold voltage (0.5V) of the FinFET transistor MFINB, the FinFET transistor MFINA is turned on and the FinFET transistor MFINB is turned off. Therefore, the FinFET transistor MFINA generates a large read current IRDA, which flows from wire 661 through the drain / source contact layer 662, the channel region of the FinFET transistor MFINA, and the drain / source contact layer 666 to wire 665. Meanwhile, the FinFET transistor MFINB is turned off, and the read current IRDB between the two wires 663 and 667 is very small, almost zero.

[0048] Furthermore, the sensing circuit in the non-volatile memory can receive two read currents, IRDA and IRDB, and determine the storage state of the storage element based on the difference between the two read currents IRDA and IRDB. For example, when the difference between the two read currents IRDA and IRDB is less than a specific value, the storage element is determined to be in an unprogrammed state. When the difference between the two read currents IRDA and IRDB is greater than a specific value, the storage element is determined to be in a programmed state. That is, the FinFET transistors MFINA and MFINB in ​​Figure 8B generate very small (close to zero) read currents IRDA and IRDB, so the storage element 600 will be determined to be in an unprogrammed state. However, the FinFET transistor MFINA in Figure 8C generates a larger read current IRDA, and the FinFET transistor MFINB generates a very small (close to zero) read current IRDB, so the storage element 600 will be determined to be in a programmed state.

[0049] Please refer to Figure 9A, which shows a cross-sectional view of the gate structure of the enhanced electromigration storage element according to the third embodiment of the present invention. Figure 9B is a top view of the enhanced electromigration storage element according to the third embodiment of the present invention. Hereinafter, the enhanced electromigration storage element 700 will be simply referred to as storage element 700, and the storage element 700 is designed in the memory cell of non-volatile memory.

[0050] The storage element 700 of the third embodiment includes a GAA transistor MGAA and two conductive lines 745 and 747. The GAA transistor MGAA is located above the semiconductor substrate sub and the insulating layer 705, and the structure of the GAA transistor MGAA is similar to that of the GAA transistor MGAA1 in Figure 3C. The GAA transistor MGAA has only one nanoline 712. Of course, the nanoline of the GAA transistor MGAA inside the storage element 700 is not limited to only one. The GAA transistor MGAA includes: two drain / source structures 782 and 792, a gate structure, and the nanoline 712. Furthermore, the gate structure of the GAA transistor MGAA includes: spacers 752 and 762, a gate dielectric layer 722, and conductive layers 732 and 742. The gate dielectric layer 722 surrounds the middle region of the nanoline 712, the conductive layer 732 surrounds the gate dielectric layer 722, and the conductive layers 742 surround the conductive layer 732. In other words, the gate conductive layer of the GAA transistor MGAA is composed of conductive layers 732 and 742. Conductive layer 732 is a work function metal layer. For example, the material of conductive layer 732 is titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). Alternatively, the material of conductive layer 742 can be the same as conductive layer 732.

[0051] Furthermore, a wire 745 is formed above the first side of the gate structure and is electrically connected to the first side of the conductive layer 742. A wire 747 is formed above the second side of the gate structure and is electrically connected to the second side of the conductive layer 742. Similarly, a wire 781 may also be formed to be electrically connected to the drain / source structure 782, and a wire 791 may be formed to be electrically connected to the drain / source contact layer 792.

[0052] This invention utilizes electromigration to perform programming operations. During programming, different voltages are applied to two wires 745 and 747, generating a programming current between them. Since electrons in the programming current flow through conductive layers 742 and 732, conductive layer 732 gradually migrates in the opposite direction of the electric field, causing a change in its thickness. In other words, this invention utilizes electromigration to create a change in the thickness of the function metal layer, thereby altering the threshold voltage of the GAA transistor MGAA.

[0053] In addition, during programming, the two drain / source structures 782 and 792 of the GAA transistor MGAA do not need to provide any bias voltage. That is to say, when programming, the wires 781 and 791 can be floated.

[0054] Please refer to Figure 10A, which illustrates a schematic diagram of programming the storage element of the first embodiment. Before programming, the storage element 700 is in an unprogrammed state. When programming the storage element 700, different voltages are provided to two wires 745 and 747. For example, a programming voltage VPGM is provided to wire 745, and a ground voltage (GND) is provided to wire 747. The voltage difference between the two wires 745 and 747 is the programming voltage VPGM. That is, wire 745 can be regarded as an anode, and wire 747 can be regarded as a cathode, so that the programming current IPGM flows through the conductive layers 732 and 742.

[0055] As shown in Figure 10A, the programming current IPGM (dashed line) flows from conductor 745 through conductive layers 732 and 742 to conductor 747. Generally, electromigration begins at the cathode (i.e., conductor 747). Due to the mechanism of electromigration, metal ions in conductive layers 732 and 742 near the cathode migrate in the opposite direction of the electric field (i.e., to the right). Therefore, after programming, the thickness of conductive layer 732 (shown by the diagonal line on the left) thins, causing a change in the threshold voltage of the GAA transistor MGAA, and the storage state of storage element 700 becomes the programming state. For example, before programming, the threshold voltage of the GAA transistor MGAA is 0.5V. After programming, the threshold voltage of the GAA transistor MGAA changes to 0.3V. In other embodiments, the thickness of the right side of conductive layer 732 may also increase after programming.

[0056] According to a third embodiment of the present invention, when the programming current IPGM is approximately 100 μA or more, the threshold voltage of the GAA transistor MGAA can be changed by approximately 0.2 to 0.3 V. Since the resistance of the conductive layers 732 and 742 is very low, the programming voltage VPGM is very low. For example, a programming voltage VPGM of approximately 1.5 V to 2.5 V is sufficient for programming. Compared to conventional non-volatile memory which requires a higher programming voltage (e.g., 8 V to 12 V), the storage element 700 of the present invention has the advantages of low programming voltage and low programming current. In other words, a non-volatile memory composed of the storage element 700 of the present invention does not require a very high programming voltage VPGM to complete the programming operation. Furthermore, since a charge pump is not required in the non-volatile memory to provide a high programming voltage VPGM, the overall layout area of ​​the non-volatile memory can be significantly reduced.

[0057] Please refer to Figures 10B and 10C, which illustrate a reading operation of the storage element in the third embodiment. For example, in Figure 10B, the storage element 700 is in an unprogrammed state, and the threshold voltage of the GAA transistor MGAA is 0.5V. In Figure 10C, the storage element 700 is in a programmed state, and the threshold voltage of the GAA transistor MGAA is 0.3V.

[0058] When reading from the storage element 700, the same control voltage VCTRL is provided to both wires 745 and 747, and no current is generated between the two wires 745 and 747. Furthermore, different voltages are provided to the two wires 781 and 791. For example, a read voltage VRD is provided to wire 781, and a ground voltage (GND) is provided to wire 791. Therefore, the voltage difference between the two wires 781 and 791 is the read voltage VRD. For example, the read voltage VRD is 1.0V. In other embodiments, during the read operation, at least one of the two wires 745 and 747 may receive the control voltage VCTRL.

[0059] According to a third embodiment of the present invention, during the read operation, the control voltage VCTRL is set to 0.4V and supplied to the two wires 745 and 747, so no current is generated between the two wires 745 and 747. As shown in Figure 10B, since the control voltage VCTRL is less than the threshold voltage (0.5V) of the GAA transistor MGAA, the GAA transistor MGAA is turned off, and the read current IRD between the two wires 781 and 791 is very small, almost zero. Furthermore, as shown in Figure 10C, since the control voltage VCTRL is greater than the threshold voltage (0.3V) of the GAA transistor MGAA, the GAA transistor MGAA is turned on. Therefore, the GAA transistor MGAA generates a large read current IRD, which flows from wire 781 through the drain / source structure 782, the channel region of the GAA transistor MGAA, and the drain / source connection structure 792 to wire 791. Similarly, the storage state of the storage element 700 can be determined by the magnitude of the read current IRD.

[0060] Please refer to Figure 11A, which shows a cross-sectional view of the gate structure of the enhanced electromigration storage element according to the fourth embodiment of the present invention. Figure 11B is a top view of the enhanced electromigration storage element according to the fourth embodiment of the present invention. The storage element 800 includes two GAA transistors, MGAAA and MGAAB, and the storage element 800 is designed within a differential memory cell of non-volatile memory.

[0061] The storage element 800 of the fourth embodiment includes GAA transistors MGAAA and MGAAB, and two wires 845 and 847. GAA transistors MGAAA and MGAAB are located above the semiconductor substrate sub and the insulating layer 805. The structures of GAA transistors MGAAA and MGAAB are similar to those of GAA transistors MGAA1 and MGAA2 in Figure 4. Each of the GAA transistors MGAAA and MGAAB contains only one nanowire 812 and 814. However, the number of nanowires in the GAA transistors MGAAA and MGAAB inside the storage element 800 is not limited to only one. The GAA transistor MGAAA includes two drain / source structures 882 and 892, a gate structure, and a nanowire 812. The gate structure of the GAA transistor MGAAA includes spacers 852 and 862, a gate dielectric layer 822, and conductive layers 832 and 842. The GAA transistor MGAAB includes two drain / source structures 884 and 894, a gate structure, and nanowires 814. The gate structure of the GAA transistor MGAAB includes spacers 852 and 862, a gate dielectric layer 824, and conductive layers 834 and 842. Gate dielectric layer 822 surrounds the central region of nanowires 812, gate dielectric layer 824 surrounds the central region of nanowires 814, conductive layer 832 surrounds gate dielectric layer 822, conductive layer 834 surrounds gate dielectric layer 824, and conductive layer 842 surrounds conductive layers 832 and 834. In other words, the gate conductive layer of both GAA transistors MGAAA and MGAAB is composed of conductive layers 832, 834, and 842, and both GAA transistors MGAAA and MGAAB share conductive layer 842. Conductive layers 832 and 834 are work function metal layers. For example, the conductive layers 832 and 834 are made of titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). Alternatively, the conductive layer 842 can be made of the same material as conductive layers 632 and 634.

[0062] Furthermore, a wire 845 is formed above the first side of the gate structure and is electrically connected to the first side of the conductive layer 842. A wire 847 is formed above the second side of the gate structure and is electrically connected to the second side of the conductive layer 842. Similarly, a wire 881 may also be formed to be electrically connected to the drain / source structure 882, a wire 891 may be formed to be electrically connected to the drain / source structure 892, a wire 883 may be formed to be electrically connected to the drain / source structure 884, and a wire 893 may be formed to be electrically connected to the drain / source structure 894.

[0063] This invention utilizes electromigration to perform programming operations. During programming, different voltages are applied to two wires 845 and 847, generating a programming current between them. Because electrons in the programming current flow through conductive layers 832, 834, and 842, conductive layer 832 gradually migrates in the opposite direction of the electric field, causing a change in its thickness. In other words, this invention utilizes electromigration to create a change in the thickness of the function metal layer, thereby altering the threshold voltage of the GAA transistor MGAAA.

[0064] In addition, during programming, the two drain / source structures 882 and 892 of the GAA transistor MGAAA and the two drain / source structures 884 and 894 of the GAA transistor MGAAB do not need to provide any bias voltage. That is, during programming, the wires 881, 883, 891, and 893 can be floated.

[0065] Please refer to Figure 12A, which illustrates a schematic diagram of programming the storage element of the fourth embodiment. Before programming, the storage element 800 is in an unprogrammed state. When programming the storage element 800, different voltages are provided to two wires 845 and 847. For example, a programming voltage VPGM is provided to wire 845, and a ground voltage (GND) is provided to wire 847, such that the voltage difference between the two wires 845 and 847 is the programming voltage VPGM. That is, wire 845 can be regarded as an anode, and wire 847 can be regarded as a cathode, so that the programming current IPGM flows through the conductive layers 832, 834, and 842.

[0066] As shown in Figure 12A, the programming current IPGM (dashed line) flows from conductor 845 through conductive layers 832, 834, and 842 to conductor 847. Generally, electromigration begins at the cathode (i.e., conductor 847). Due to the mechanism of electromigration, metal ions in conductive layers 832 and 842 near the cathode migrate in the opposite direction of the electric field (i.e., to the right). Therefore, after programming, the thickness of conductive layer 832 (shown by the left diagonal line) thins, causing a change in the threshold voltage of the GAA transistor MGAAA, and the storage state of storage element 800 becomes the programming state. For example, before programming, the threshold voltages of both GAA transistors MGAAA and MGAAB are 0.5V. After programming, the threshold voltage of GAA transistor MGAAA changes to 0.3V, while the threshold voltage of GAA transistor MGAAB remains at 0.5V. Of course, in other embodiments, after the programming operation is completed, the thickness of the conductive layer 834 on the left and right sides may also increase, causing the threshold voltage of the GAA transistor MGAAB to change and be greater than 0.5V.

[0067] According to a fourth embodiment of the present invention, when the programming current IPGM is approximately 100 μA or more, the threshold voltage of the GAA transistor MGAAA can be changed by approximately 0.2 to 0.3 V. Since the resistance of the conductive layers 832, 834, and 842 is very low, the programming voltage VPGM is very low. For example, a programming voltage of approximately 1.5 V to 2.5 V VPGM is sufficient for programming. Compared to conventional non-volatile memory which requires a higher programming voltage (e.g., 8 V to 12 V), the storage element 800 of the present invention has the advantages of low programming voltage and low programming current. In other words, a non-volatile memory composed of the storage element 800 of the present invention does not require a very high programming voltage VPGM to complete the programming operation. Furthermore, since a charge pump is not required in the non-volatile memory to provide a high programming voltage VPGM, the overall layout area of ​​the non-volatile memory can be significantly reduced.

[0068] Please refer to Figures 12B and 12C, which illustrate a reading operation of the storage element in the fourth embodiment. For example, in Figure 12B, the storage element 800 is in an unprogrammed state, and the threshold voltages of the GAA transistors MGAAA and MGAAB are both 0.5V. In Figure 12C, the storage element 800 is in a programmed state, and the threshold voltage of the GAA transistor MGAAA is 0.3V, and the threshold voltage of the GAA transistor MGAAB is 0.5V.

[0069] When reading from storage element 800, the same control voltage VCTRL is provided to the two wires 845 and 847, or the control voltage VCTRL is provided to one of the two wires 845 and 847. Alternatively, different voltages are provided to the two wires 881 and 891, and different voltages are provided to the two wires 883 and 893. For example, a read voltage VRD is provided to wires 881 and 883, and a ground voltage (GND) is provided to wires 891 and 893. Therefore, the voltage difference between the two wires 881 and 891 is the read voltage VRD, and the voltage difference between the two wires 883 and 893 is the read voltage VRD. For example, the read voltage VRD is 1.0V.

[0070] According to the fourth embodiment of the present invention, during the read operation, the control voltage VCTRL is set to 0.4V and provided to the two wires 845 and 847. As shown in Figure 12B, since the control voltage VCTRL is less than the threshold voltage (0.5V) of the GAA transistors MGAAA and MGAAB, the GAA transistors MGAAA and MGAAB are turned off. The read current IRDA between the two wires 881 and 891 is very small and almost zero, and the read current IRDB between the two wires 883 and 893 is very small and almost zero. In addition, as shown in Figure 12C, since the control voltage VCTRL is greater than the threshold voltage (0.3V) of the GAA transistor MGAAA and less than the threshold voltage (0.5V) of the GAA transistor MGAAB, the GAA transistor MGAAA is turned on and the GAA transistor MGAAB is turned off. Therefore, the GAA transistor MGAAA generates a large read current IRDA, which flows from wire 881 through drain / source structure 882, the channel region of the GAA transistor MGAAA, and drain / source structure 892 to wire 891. Conversely, the GAA transistor MGAAB is turned off, and the read current IRDB between the two wires 883 and 893 is very small, almost zero. Similarly, the storage state of the storage element 800 can be determined by the magnitudes of the read currents IRDA and IRDB.

[0071] Furthermore, the present invention can modify the structures of storage elements 500, 600, 700, and 800 in the first to fourth embodiments to enhance the electromigration effect, resulting in a greater difference in the threshold voltage of the transistor before and after the programming operation. The modified structure of storage element 500 in the first embodiment is described below. Moreover, the modification method of storage element 500 in the first embodiment can also be applied to storage elements 600, 700, and 800 in the second to fourth embodiments.

[0072] Please refer to Figure 13A, which shows a top view of an enhanced electromigration storage element according to a fifth embodiment of the present invention. Compared to the storage element 500 of the first embodiment, in the storage element 900 of the fifth embodiment, the cross-sectional areas of the contact holes connected to the first and second sides of the conductive layer 542 are different. That is, the cross-sectional area of ​​the contact hole serving as the anode is larger than the cross-sectional area of ​​the contact hole serving as the cathode. For example, assuming that the cross-sectional area of ​​each contact hole is the same, the number of wires designed for the anode is greater than the number of wires designed for the cathode.

[0073] As shown in Figure 13A, two wires 545a and 545b are electrically connected to the first side of the conductive layer 542. During programming, these two wires 545a and 545b act as anodes and receive the programming voltage VPGM. Furthermore, a single wire 547 is electrically connected to the second side of the conductive layer 542. During programming, wire 547 acts as a cathode and receives the ground voltage (GND). Therefore, during programming, the total programming current input from the anode is concentrated at the cathode, making electromigration more likely and resulting in a greater difference in the threshold voltage of the FinFET transistor MFIN before and after programming. Of course, when the storage element 900 performs a read operation, all wires 545a, 545b, and 457 connected to the conductive layer 542 receive the same control voltage VCTRL.

[0074] Similarly, the modification of the storage element 900 in the fifth embodiment can also be applied to the storage elements 600, 700, and 800 in the second to fourth embodiments.

[0075] Please refer to Figure 13B, which shows a top view of an enhanced electromigration storage element according to a sixth embodiment of the present invention. Compared to the storage element 500 of the first embodiment, in the storage element 910 of the sixth embodiment, a heat dissipation metal layer 912 is formed above the first side of the conductive layer 542, and the heat dissipation metal layer 912 contacts the conductive layer 542. In other embodiments, the heat dissipation metal layer 912 may be a metal or an alloy to strengthen grain bonds.

[0076] When the storage element 910 is programmed, the programming current IPGM flows through the conductive layers 542 and 532, causing the FinFET transistor MFIN to heat up. Since the heat dissipation metal layer 912 is located on the first side of the conductive layer 542, it can dissipate the heat energy on the first side of the conductive layer 542 more quickly, increase the heat gradient and thermal stress between the first and second sides of the conductive layer 542, and enhance the electromigration efficiency, which can make the difference in the threshold voltage of the FinFET transistor MFIN before and after the programming operation greater.

[0077] Similarly, the modification of the storage element 910 in the sixth embodiment can also be applied to the storage elements 600, 700, and 800 in the second to fourth embodiments.

[0078] Please refer to Figure 13C, which shows a top view of an enhanced electromigration storage element according to a seventh embodiment of the present invention. Compared to the storage element 500 of the first embodiment, in the storage element 920 of the seventh embodiment, a heating layer 922 is formed above the second side of the conductive layer 542, and the heating layer 922 does not contact the conductive layer 542. For example, the heating layer 922 is a resistive layer. Basically, the heating layer 922 is a lower metal layer of the substrate closer to the connection (i.e., interconnection) between transistors and other components in the electronic circuit layout. For example, the heating layer 922 may be a first metal layer or a second metal layer above the storage element 920.

[0079] When the storage element 910 is programmed, the programming current IPGM flows through the conductive layer 542, the conductive layer 532, and the heating layer 922, causing the FinFET transistor MFIN to heat up. Since the heating layer 922 is located on the second side of the conductive layer 542, it can increase the temperature of the second side of the conductive layer 542, increase the thermal gradient and thermal stress between the first and second sides of the conductive layer 542, thereby enhancing the electromigration efficiency (EM efficiency) and making the difference in the threshold voltage of the FinFET transistor MFIN before and after the programming operation greater.

[0080] Similarly, the modification of the storage element 920 in the seventh embodiment can also be applied to the storage elements 600, 700, and 800 in the second to fourth embodiments.

[0081] Please refer to Figure 13D, which shows a top view of the enhanced electromigration storage element according to the eighth embodiment of the present invention. Compared to the storage element 500 of the first embodiment, in the storage element 930 of the eighth embodiment, the gate structure is an L-shaped gate structure, including a main branch and a sub-branch. The main branch covers the fin 512. The sub-branch extends from a first side of the main branch, and the sub-branch may be parallel to the fin 512, with the main branch and the sub-branch forming a bend. Furthermore, the wire 547a is electrically connected to the conductive layer 542a of the sub-branch. The wire 545 is electrically connected to the conductive layer 542a on the second side of the main branch.

[0082] When the storage element 930 is programmed, the programming current IPGM will cause current crowding when it flows through the turning point of the conductive layer 542a and generate thermal stress, which helps to improve the electromigration efficiency and makes the difference between the threshold voltage of the FinFET transistor MFIN before and after the programming operation greater.

[0083] Similarly, the modification of the storage element 930 in the eighth embodiment can also be applied to the storage elements 600, 700, and 800 in the second to fourth embodiments.

[0084] Please refer to Figure 13E, which shows a top view of an enhanced electromigration storage element according to a ninth embodiment of the present invention. This enhanced electromigration storage element adds a heat sink located at the cathode. Compared to the storage element 500 of the first embodiment, in the storage element 940 of the ninth embodiment, the gate structure is E-shaped (or finger-type). The gate structure includes a main branch, a first sub-branch, and a second sub-branch. The first and second sub-branch extend from the main branch and are located on both sides of the main branch. A portion of the first sub-branch and a portion of the second sub-branch are parallel to the main branch. In addition, the main branch covers the fin 512, and the first and second sub-branch also cover the fin 512. Furthermore, the gate structure includes a conductive layer 542b on the main branch, a conductive layer 542c on the first sub-branch, and a conductive layer 542d on the second sub-branch. Wire 545 is electrically connected to the first side of conductive layer 542b of the main branch, and wire 547b is electrically connected to the second side of conductive layer 542b of the main branch. Additionally, wire 547c is electrically connected to the second side of conductive layer 542c of the first branch, and wire 547d is electrically connected to the second side of conductive layer 542d of the second branch.

[0085] When the storage element 940 is programmed, the programming current IPGM flows through the conductive layer 542b and the conductive layer 532, causing the FinFET transistor MFIN to heat up and generate thermal stress. The two sub-branches of the gate structure can improve heat dissipation capability. Therefore, increasing the heat gradient between the first and second sides of the conductive layer 542b enhances the electromigration efficiency, resulting in a greater difference in the threshold voltage of the FinFET transistor MFIN before and after the programming operation.

[0086] Similarly, the modification of the storage element 940 in the ninth embodiment can also be applied to the storage elements 600, 700, and 800 in the second to fourth embodiments.

[0087] As can be seen from the above description, the present invention proposes an enhanced electromigration storage element for non-volatile memory. During programming, two different voltages are simultaneously applied to the gate terminals of a FinFET transistor or a GAA transistor, and the threshold voltage of the FinFET transistor or GAA transistor is changed using an electromigration mechanism, allowing the storage element to exhibit different storage states. During reading, the same voltage is simultaneously applied to the gate terminals of the FinFET transistor or GAA transistor, and the storage state of the storage element is determined based on the read current generated by the FinFET transistor or GAA transistor.

[0088] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0017] Figures 1A, 1B, and 1C are perspective views, top views, and cross-sectional views along the AB dashed line of a FinFET transistor; Figure 2 is a schematic diagram of two FinFET transistors; Figures 3A, 3B, 3C, and 3D are perspective views, top views, and cross-sectional views along the ab dashed line and the cd dashed line of a GAA transistor; Figure 4 is a schematic diagram of two GAA transistors; Figure 5A is a cross-sectional view of the gate structure of the enhancement-mode electromigration storage element according to the first embodiment of the present invention; Figure 5B is a top view of the enhancement-mode electromigration storage element according to the first embodiment of the present invention; Figure 6A is a schematic diagram of programming the storage element of the first embodiment; Figures 6B and 6C are schematic diagrams of reading the storage element of the first embodiment; Figure 7A is a cross-sectional view of the gate structure of the enhancement-mode electromigration storage element according to the second embodiment of the present invention; Figure 7B is a top view of the enhancement-mode electromigration storage element according to the second embodiment of the present invention. Figure 8A is a schematic diagram of programming the storage element of the second embodiment; Figures 8B and 8C are schematic diagrams of reading the storage element of the second embodiment; Figure 9A is a cross-sectional view of the gate structure of the enhanced electromigration storage element of the third embodiment of the present invention; Figure 9B is a top view of the enhanced electromigration storage element of the third embodiment of the present invention; Figure 10A is a schematic diagram of programming the storage element of the first embodiment; Figures 10B and 10C are schematic diagrams of reading the storage element of the third embodiment; Figure 11A is a cross-sectional view of the gate structure of the enhanced electromigration storage element of the fourth embodiment of the present invention; Figure 11B is a top view of the enhanced electromigration storage element of the fourth embodiment of the present invention; Figure 12A is a schematic diagram of programming the storage element of the fourth embodiment; Figures 12B and 12C are schematic diagrams of reading the storage element of the fourth embodiment; Figure 13A is a top view of the enhanced electromigration storage element of the fifth embodiment of the present invention; Figure 13B is a top view of the enhanced electromigration storage element of the sixth embodiment of the present invention. Figure 13C is a top view of an enhanced electromigration storage element according to a seventh embodiment of the present invention; Figure 13D is a top view of an enhanced electromigration storage element according to an eighth embodiment of the present invention; and Figure 13E is a top view of an enhanced electromigration storage element according to a ninth embodiment of the present invention.

Claims

1. A storage element for non-volatile memory, comprising: A first-fin field-effect transistor includes: a first fin, a gate structure, a first drain / source contact layer, and a second drain / source contact layer; wherein the gate structure includes: a first gate dielectric layer, a first conductive layer, and a second conductive layer; wherein the first gate dielectric layer covers a middle region and two side surfaces of the first fin, the first conductive layer covers the first gate dielectric layer, the second conductive layer covers the first conductive layer, the first drain / source contact layer is electrically contacted to a first side region of the first fin, and the second drain / source contact layer is electrically contacted to a second side region of the first fin, and the first conductive layer is a work function metal layer; a first wire is located on a first side of the gate structure and is electrically connected to a first side of the second conductive layer; and a second wire is located on a second side of the gate structure and is electrically connected to a second side of the second conductive layer. In a programming operation, the first conductor receives a first voltage, and the second conductor receives a second voltage; a programming current flows from the first conductor through the first conductive layer and the second conductive layer to the second conductor, and the first voltage is greater than the second voltage; in a reading operation, at least one of the first conductor and the second conductor receives a control voltage, the first drain / source contact layer receives a third voltage, and the second drain / source contact layer receives a fourth voltage, and the third voltage is greater than the fourth voltage; a first reading current flows from the first drain / source contact layer through a channel region of the first fin field-effect transistor to the second drain / source contact layer, and a storage state of the storage element is determined according to the first reading current; the difference between the first voltage and the second voltage is equal to a programming voltage, and the difference between the third voltage and the fourth voltage is equal to a reading voltage.

2. The storage element as claimed in claim 1, wherein a threshold voltage of the first fin field-effect transistor is determined according to a thickness of the work function metal layer.

3. The storage element as claimed in claim 2, wherein the material of the work function metal layer is titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl).

4. The storage element as claimed in claim 2, wherein during the programming operation, the programming current flows through the first conductive layer; and after the programming operation, the thickness of the first conductive layer changes such that the threshold voltage of the first fin field-effect transistor changes, and the threshold voltage of the first fin field-effect transistor is less than the control voltage.

5. The storage element as claimed in claim 1, wherein the first conductor is electrically connected to the second conductive layer via a first contact hole, the second conductor is electrically in contact with the second conductive layer via a second contact hole, and a cross-sectional area of ​​the first contact hole is larger than a cross-sectional area of ​​the second contact hole.

6. The storage element as claimed in claim 1, further comprising a third conductor formed on the first side of the gate structure, and the third conductor being electrically connected to the first side of the second conductive layer; wherein, During the programming operation, both the first wire and the third wire receive the first voltage.

7. The storage element as claimed in claim 1 further includes a heat dissipation metal layer located above the first side of the second conductive layer, and the heat dissipation metal layer is in contact with the second conductive layer.

8. The storage element as claimed in claim 1 further includes a heating layer located above the second side of the second conductive layer, and the heating layer is not in contact with the second conductive layer.

9. The storage element as claimed in claim 1, wherein the gate structure includes a main branch and a sub-branch; wherein, The main branch covers the first fin and the sub-branch extends from a first side of the main branch; wherein the second wire is electrically connected to the second conductive layer of the sub-branch and the first wire is electrically connected to the second conductive layer on a second side of the main branch.

10. The storage element as claimed in claim 1, wherein the gate structure includes a main branch, a first sub-branch, and a second sub-branch; wherein, The first wire is electrically connected to the second conductive layer on a first side of the main branch, and the second wire is electrically connected to the second conductive layer on a second side of the main branch; wherein the main branch covers the first fin, the first sub-branch and the second sub-branch extend from the second side of the main branch, and both the first sub-branch and the second sub-branch cover the first fin.

11. The storage element as claimed in claim 1, further comprising a second fin field-effect transistor, wherein the second fin field-effect transistor includes: The device comprises a second fin, a gate structure, a third drain / source contact layer, and a fourth drain / source contact layer; wherein the gate structure further comprises a second gate dielectric layer and a third conductive layer; wherein the second gate dielectric layer covers a middle region above and two side surfaces of the second fin, the third conductive layer covers the second gate dielectric layer, the second conductive layer covers the third conductive layer, the third drain / source contact layer is electrically contacted to a first side region of the second fin, and the fourth drain / source contact layer is electrically contacted to a second side region of the second fin; wherein, during the read operation, the third drain / source contact layer receives the third voltage, and the fourth drain / source contact layer receives the fourth voltage; wherein a second read current flows from the third drain / source contact layer through a channel region of the second fin field-effect transistor to the fourth drain / source contact layer, and the storage state of the storage element is determined according to the first read current and the second read current.

12. The storage element as claimed in claim 11, wherein during the programming operation, the programming current flows through the first conductive layer and the third conductive layer; and after the programming operation, the thickness of the first conductive layer and the third conductive layer changes such that the threshold voltages of the first fin field-effect transistor and the second fin field-effect transistor change, wherein the threshold voltage of the first fin field-effect transistor is less than the control voltage, and the threshold voltage of the second fin field-effect transistor is greater than the control voltage.

13. A non-volatile memory storage element, comprising: A first all-around gate transistor includes: a first nanowire, a gate structure, a first drain / source structure, and a second drain / source structure. The gate structure includes: a first gate dielectric layer, a first conductive layer, and a second conductive layer. The first gate dielectric layer surrounds a central region of the first nanowire, the first conductive layer surrounds the first gate dielectric layer, and the second conductive layer surrounds the first conductive layer. The first drain / source structure is electrically contacted on a first side region of the first nanowire, and the second drain / source structure is electrically contacted on a second side region of the first nanowire. The first conductive layer is a work function metal layer. A first wire is located on a first side of the gate structure and electrically connected to a first side of the second conductive layer. A second wire is located on a second side of the gate structure and electrically connected to a second side of the second conductive layer. In a programming operation, the first conductor receives a first voltage, and the second conductor receives a second voltage; a programming current flows from the first conductor through the first conductive layer and the second conductive layer to the second conductor, and the first voltage is greater than the second voltage; in a reading operation, at least one of the first conductor and the second conductor receives a control voltage, the first drain / source structure receives a third voltage, and the second drain / source structure receives a fourth voltage, and the third voltage is greater than the fourth voltage; a first reading current flows from the first drain / source structure through a channel region of the first all-around gate transistor to the second drain / source structure, and a storage state of the storage element is determined according to the first reading current; the difference between the first voltage and the second voltage is equal to a programming voltage, and the difference between the third voltage and the fourth voltage is equal to a reading voltage.

14. The storage element as claimed in claim 13, wherein a threshold voltage of the first all-around gate transistor is determined according to a thickness of the work function metal layer.

15. The storage element as claimed in claim 14, wherein during the programming operation, the programming current flows through the first conductive layer; and after the programming operation, the thickness of the first conductive layer changes such that the threshold voltage of the first all-around gate transistor changes, and the threshold voltage of the first all-around gate transistor is less than the control voltage.

16. The storage element as claimed in claim 13, wherein the first conductor is electrically connected to the second conductive layer via a first contact hole, the second conductor is electrically in contact with the second conductive layer via a second contact hole, and a cross-sectional area of ​​the first contact hole is larger than a cross-sectional area of ​​the second contact hole.

17. The storage element as claimed in claim 13, further comprising a third conductor formed on the first side of the gate structure, and the third conductor being electrically connected to the first side of the second conductive layer; wherein, During the programming operation, both the first wire and the third wire receive the first voltage.

18. The storage element as claimed in claim 13 further includes a heat dissipation metal layer located above the first side of the second conductive layer, and the heat dissipation metal layer is in contact with the second conductive layer.

19. The storage element as claimed in claim 13 further includes a heating layer located above the second side of the second conductive layer, and the heating layer is not in contact with the second conductive layer.

20. The storage element as claimed in claim 13, wherein the gate structure includes a main branch and a sub-branch; wherein, The main branch surrounds the first nanowire and the sub-branch extends from a first side of the main branch; wherein the second wire is electrically connected to the second conductive layer of the sub-branch and the first wire is electrically connected to the second conductive layer on a second side of the main branch.

21. The storage element as claimed in claim 13, wherein the gate structure includes a main branch, a first sub-branch, and a second sub-branch; wherein, The first wire is electrically connected to the second conductive layer on a first side of the main branch, and the second wire is electrically connected to the second conductive layer on a second side of the main branch; wherein the main branch surrounds the first nanowire, the first sub-branch and the second sub-branch extend from the second side of the main branch, and both the first sub-branch and the second sub-branch surround the first nanowire.

22. The storage element as claimed in claim 13 further includes a second all-around gate transistor, wherein the second all-around gate transistor comprises: The device comprises a second nanowire, a gate structure, a third drain / source structure, and a fourth drain / source structure, wherein the gate structure further includes a second gate dielectric layer and a third conductive layer; wherein the second gate dielectric layer surrounds a central region of the second nanowire, the third conductive layer surrounds the second gate dielectric layer, the second conductive layer surrounds the third conductive layer, the third drain / source structure is electrically contacted with a first side region of the second nanowire, and the fourth drain / source structure is electrically contacted with a second side region of the second nanowire; wherein, during the read operation, the third drain / source structure receives the third voltage, and the fourth drain / source structure receives the fourth voltage; wherein a second read current flows from the third drain / source structure through a channel region of the second all-around gate transistor to the fourth drain / source structure, and the storage state of the storage element is determined according to the first read current and the second read current.

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