Camera devices and electronic devices

Abstract

This invention provides a camera device with image processing capabilities and high-speed operation. The camera device includes image processing and other additional functions. In its pixel unit, image data acquired during imaging is binarized, and this binarized data is used for product summation. A memory circuit is provided in the pixel unit to store weighting coefficients used in the product summation operation. Therefore, the operation can be performed without constantly retrieving the weighting coefficients from an external source, reducing power consumption. Furthermore, by stacking the pixel circuit, memory circuit, and product summation circuit, the wiring length between circuits can be shortened, enabling low-power and high-speed operation.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a camera device.

[0002] Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods of operating these devices, or methods of manufacturing these devices.

[0003] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of a semiconductor. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, memory devices, display devices, camera devices, and electronic devices sometimes include semiconductor devices. [Previous Technology]

[0004] The technique of using oxide semiconductor thin films formed on a substrate to form transistors has attracted attention. For example, Patent Document 1 discloses an imaging device that uses a transistor comprising oxide semiconductor with very low off-state current in a pixel circuit structure.

[0005] In addition, Patent Document 2 discloses a technology for giving a camera device a computing function.

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2011-119711 [Patent Document 2] Japanese Patent Application Publication No. 2016-123087 [Summary of the Invention]

[0007] Camera devices installed on mobile devices and the like typically have the ability to capture high-resolution images. There is a need for next-generation camera devices with even more intelligent features.

[0008] Image data (analog data) acquired using a camera device is converted into digital data and extracted externally, and then processed as needed. When this processing can be performed within the camera device, it is possible to link with external devices at a higher speed, and user convenience is improved. In addition, the load and power consumption of peripheral devices can be reduced.

[0009] Furthermore, when assigning functions to a camera device, it is preferable to use components such as stacked circuits. For example, by arranging multiple circuits in a manner that overlaps with the pixel circuit, the area increase can be suppressed, and a high-performance, compact camera device can be formed. In addition, the wiring length between stacked circuits can be shortened, enabling high-speed and low-power operation.

[0010] Therefore, one objective of one embodiment of the present invention is to provide a camera device capable of image processing. Another objective of one embodiment of the present invention is to provide a high-performance, compact camera device. Another objective of one embodiment of the present invention is to provide a camera device capable of high-speed operation. Another objective of one embodiment of the present invention is to provide a low-power camera device. Another objective of one embodiment of the present invention is to provide a highly reliable camera device. Another objective of one embodiment of the present invention is to provide a novel camera device, etc. Another objective of one embodiment of the present invention is to provide a driving method for the above-described camera device. Another objective of one embodiment of the present invention is to provide a novel semiconductor device, etc.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not need to achieve all of the above objectives. Objectives other than those described above are obvious from the description in the specification, drawings, claims, etc., and may be derived from the description.

[0012] One embodiment of the present invention relates to a camera device having image processing function and capable of high-speed operation.

[0013] One embodiment of the present invention is an imaging device comprising a plurality of blocks, the blocks comprising a first layer and a second layer, the first layer having an area overlapping with the second layer, the first layer comprising a plurality of pixel circuits and a plurality of first memory circuits in the blocks, the second layer comprising a plurality of product summation circuits, a plurality of first binarization circuits and a plurality of second binarization circuits, the pixel circuits and the first memory circuits comprising transistors containing metal oxides in the channel forming region.

[0014] Another embodiment of the present invention is a camera device comprising a plurality of blocks, the blocks comprising a first layer, a second layer and a third layer, the first layer being located between the second layer and the third layer or the third layer being located between the first layer and the second layer, the first layer to the third layer having overlapping areas, the first layer comprising a plurality of pixel circuits, the second layer comprising a plurality of product summation circuits, a plurality of first binarization circuits and a plurality of second binarization circuits, the third layer comprising a plurality of first memory circuits, the pixel circuits and the first memory circuits comprising transistors containing metal oxides in the channel forming region.

[0015] The product summation circuit, the first binarization circuit, and the second binarization circuit are preferably transistors containing silicon in the channel forming region.

[0016] The number of pixel circuits and the number of first binarization circuits are the same, and the pixel circuits can be electrically connected to one of the first binarization circuits.

[0017] One of the first binarization circuits can be electrically connected to multiple product summation circuits.

[0018] One of the first memory circuits can be electrically connected to multiple product summation circuits.

[0019] The number of product sum operation circuits and the number of second binarization circuits are the same, and one of the product sum operation circuits can be electrically connected to one of the second binarization circuits.

[0020] The driving circuit for the pixel circuit and the driving circuit for the first memory circuit can be set in the second layer.

[0021] In addition, it may also include a second memory circuit, the input terminals of which can be electrically connected to multiple second binarization circuits, and the output terminals of which can be electrically connected to multiple components in the summation circuit.

[0022] In addition, it may also include a third memory circuit and a third binarization circuit. The third memory circuit may also be electrically connected to multiple product summation circuits via the third binarization circuit.

[0023] The second memory circuit, the third memory circuit, and the third binarization circuit can also be set in the second layer.

[0024] The metal oxide preferably contains In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0025] By employing one embodiment of the present invention, a camera device capable of image processing can be provided. Furthermore, a high-performance, compact camera device can be provided. Furthermore, a camera device capable of high-speed operation can be provided. Furthermore, a low-power camera device can be provided. Furthermore, a highly reliable camera device can be provided. Furthermore, a novel camera device can be provided, etc. Furthermore, a method for operating the above-described camera device can be provided. Furthermore, a novel semiconductor device, etc., can be provided.

Implementation Method

[0027] The embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below. Furthermore, in the structure of the invention described below, the same element symbols are used in different drawings to represent the same parts or parts having the same function, and repeated descriptions are omitted. Additionally, sometimes the shading of the same components is appropriately omitted or changed in different drawings.

[0028] Furthermore, even if a component is represented as a single component on a circuit diagram, it can be constructed using multiple components if there are no functional problems. For example, multiple transistors sometimes used as switches can be connected in series or parallel. In addition, capacitors are sometimes segmented and configured in multiple locations.

[0029] In addition, sometimes a conductor has multiple functions such as wiring, electrodes and terminals, and in this specification, multiple names are sometimes used for the same component. Furthermore, even when components are shown as directly connected in a circuit diagram, sometimes the components are actually connected by one or more conductors, and this structure is also included in the scope of direct connection in this specification.

[0030] Embodiment 1 In this embodiment, a camera device according to an embodiment of the present invention will be described with reference to drawings.

[0031] One embodiment of the present invention is a camera device with additional functions such as image processing. In this camera device, analog data (image data) obtained through imaging is binarized in the pixel unit, and a product summation operation is performed using the binarized data. A memory circuit is provided in the pixel unit to store the weight coefficients (also called weight data or filters) used for the product summation operation. Therefore, the operation can be performed without constantly reading the weight coefficients from an external source, and power consumption can be reduced.

[0032] Furthermore, in a camera device according to one embodiment of the present invention, by stacking pixel circuits, memory circuits, and product calculation circuits, the wiring length between circuits can be shortened, enabling low-power and high-speed operation. Additionally, a high-performance compact camera device can be provided.

[0033] <Camera Device> FIG1 is a perspective view illustrating an embodiment of the camera device of the present invention. The camera device includes layer 10 and layer 20. Layer 10 may also be disposed on layer 20. The camera device includes a pixel section 11 provided with pixel circuits and memory circuits, etc. The pixel section 11 includes components disposed in layer 10 and components disposed in layer 20.

[0034] Pixel circuits and memory circuits can be provided in layer 10. Driving circuits for the circuits included in layer 10, data processing circuits for the data acquired by the circuits included in layer 10, data conversion circuits, and memory circuits can be provided in layer 20. For example, an arithmetic unit 21, row drivers 31 and column drivers 32 for driving the pixel circuits, and row drivers 33 and column drivers 34 for driving the memory circuits can be provided in layer 20. Furthermore, as needed, circuits 35 and 36 with data selection, holding, conversion, and readout functions can also be provided in layer 20.

[0035] The circuits included in layer 10 and layer 20 can be electrically connected using electrodes or wiring in layer 10. Note that some of the circuits described above can be located in layers opposite to those described above or outside the imaging device.

[0036] FIG2A is a diagram illustrating the pixel unit 11 in detail. The pixel unit 11 includes a plurality of squares 12 arranged in a matrix. In addition, each square 12 includes a 3×3 square 13. Furthermore, each square 13 includes a 3×3 pixel 14. In other words, each square 12 includes a 9×9 pixel 14. Each pixel 14 includes a pixel circuit 15 and a memory circuit 16.

[0037] In one embodiment of the present invention, various operations are performed on the premise that the block 13 includes a structure of 3×3 pixels 14, but the number of pixels is not limited to the above-mentioned number, for example, 2×2, 4×4, 5×5, 25×25, etc. can be used. Alternatively, the number of pixels 14 in the horizontal direction and the vertical direction can be different. In addition, adjacent blocks 12 can share a portion of the block 13. In addition, adjacent blocks 13 can share a portion of the pixels 14. Furthermore, the number of blocks 13 included in the block 12 can be appropriately changed.

[0038] The pixel 14 shown in FIG2A is an example of the pixel circuit 15 and the memory circuit 16 arranged in layer 10. However, as shown in FIG2B, the pixel circuit 15 can also be stacked on top of the memory circuit 16. Alternatively, as shown in FIG2C, the memory circuit 16 can also be stacked on top of the pixel circuit 15.

[0039] Figure 3 is a diagram illustrating the components of block 13. Block 13 includes 3×3 pixels 14. Therefore, block 13 includes nine pixel circuits 15 and nine memory circuits 16 in layer 10. In addition, in the area (layer 20) overlapping with the pixel circuits 15 or memory circuits 16, a plurality of binarization circuits 22, a plurality of product summation circuits 23, and a plurality of binarization circuits 24 are provided as an arithmetic unit 21.

[0040] The number of binarization circuits 22 is the same as that of pixel circuits 15, that is, nine binarization circuits 22 are provided. The binarization circuits 22 are provided at positions having regions that overlap with the pixel circuits 15. Figure 4 is a diagram showing the connection relationship between pixel circuits 15 and binarization circuits 22, where one pixel circuit 15 is electrically connected to one binarization circuit 22 having an overlapping region with it.

[0041] The binarization circuit 22 is a circuit that uses a preset threshold to determine and binarize the image data (analog data) obtained by the pixel circuit 15. For example, a comparator can be used.

[0042] Multiple product summation circuits 23 are arranged in a block 13. In this embodiment, an example of six product summation circuits 23 is shown. Note that the number of product summation circuits 23 can be appropriately increased or decreased depending on the purpose. The input terminals of the product summation circuits 23 are electrically connected to the memory circuit 16 and the binarization circuit 22.

[0043] Figure 5 is a diagram showing the connection relationship between the product summation circuit 23, the memory circuit 16, and the binarization circuit 22. To clearly show this connection relationship, nine binarization circuits 22 are extracted and shown.

[0044] Block 13 includes nine memory circuits 16, each of which includes multiple memory cells. A 1-bit weight coefficient can be pre-written into each of these memory cells. Each of the nine memory circuits 16 is electrically connected to each of the six product summation circuits 23. Therefore, a total of 9 bits of weight coefficients can be provided to each of the product summation circuits 23. Since weight coefficients can be provided from one memory circuit 16 to all six product summation circuits 23, this operation can be performed as long as at least one memory circuit 16 is written with a weight coefficient.

[0045] Each of the nine binarization circuits 22 can output image data converted to 1 bit. Each of the nine binarization circuits 22 is electrically connected to each of the six product summation circuits 23. Since image data can be provided from one binarization circuit 22 to the six product summation circuits 23, each product summation circuit 23 is provided with a total of 9 bits of image data.

[0046] Figure 6A is a diagram illustrating the structure and operation of the product summation circuit 23. The product summation circuit 23 may, for example, have a structure including nine multipliers 23a and one adder 23b. Each multiplier 23a is input into the binarization circuit 22 and converted into 1-bit image data (X1 to X9) and 1-bit weight coefficients (W1 to W9) read from the memory circuit 16, performing multiplication and outputting the 1-bit data to the adder 23b. The adder 23b performs addition on the data input from each multiplier 23a and outputs it to the binarization circuit 24. Here, the data output from the adder 23b (product summation circuit 23) will be 0 to 9, therefore 4 bits of data.

[0047] The same number of binarization circuits 24 as the product summation circuit 23 are provided, i.e., six. As shown in Figures 6A, 6B, and 7, one binarization circuit 24 is electrically connected to one product summation circuit 23. As shown in Figures 6A and 6B, the data input to the binarization circuit 24 is 4-bit digital data equivalent to 0 to 9. The binarization circuit 24 outputs 1 when it determines that the input data is 5 or higher, and outputs 0 when it determines that the input data is 4 or lower. In other words, the binarization circuit 24 is a circuit that has the function of converting 4-bit data into 1-bit data.

[0048] As shown in Figure 7, a total of 6 bits of computation data can be output from a block 13. Figure 8 is a diagram illustrating the computation data read from block 12 (block 13[1,1] to block 13[3,3]).

[0049] The six binarization circuits 24 included in block 13 each include a selection transistor 24S for controlling the output. The gates of the six selection transistors 24S are electrically connected to the wiring RSEL (wiring RSEL[0], wiring RSEL[1], wiring RSEL[2]). Blocks 13 arranged in the row direction share the wiring RSEL. In addition, blocks 13 arranged in the column direction share the six output lines OUT (OUT[0] to OUT[5]) that are electrically connected to the six binarization circuits 24.

[0050] A readout circuit 40 is electrically connected to the six output lines OUT. The readout circuit 40 includes switches 40S, 41S and 42S that are electrically connected to the six output lines OUT of each column.

[0051] Switches 40S to 42S include multiple transistors. The gate of the transistor included in switch 40S is electrically connected to the wiring CSEL[0]. The gate of the transistor included in switch 42S is electrically connected to the wiring CSEL[1]. The gate of the transistor included in switch 42S is electrically connected to the wiring CSEL[2].

[0052] The wiring on each output side of switches 40S to 42S is electrically connected to one output line OUT, that is, three wirings are electrically connected to one output line OUT. By adopting this structure, data in blocks 13 can be output.

[0053] The readout circuit 40 can be disposed in layer 20 as a component of circuit 35 or circuit 36 ​​shown in FIG1.

[0054] Figure 9 is a timing diagram illustrating the reading of computational data from block 12 (block 13[1,1] to block 13[3,3]). It is assumed that all computations in each block 13 are completed before time T1 and the binarization circuit 24 maintains the state of the computational data. Furthermore, in the following description, the potential that puts the transistor in the conducting state (high potential) is recorded as "H", and the potential that puts the transistor in the non-conducting state (low potential) is recorded as "L".

[0055] At time T1, the potential of the wiring RSEL[0] is set to “H”. At this time, the selection transistors 24S included in all the binarization circuits 24 of the block 13 configured on the 0th row are turned on, and the operation data is output to the readout circuit 40.

[0056] In addition, at time T1, the potential of the wiring CSEL[0] is set to “H”. At this time, its gate is connected to the switch of wiring CSEL[0] for 40S and the operation data of block 13[1,1] is output to the output line OUT[0] to the output line OUT[5].

[0057] At time T2, the potential of wiring CSEL[0] is set to “L” and the potential of wiring CSEL[1] is set to “H”. At this time, switch 40S becomes non-conducting, and its gate is connected to switch 41S of wiring CSEL[1]. The calculation data of block 13[1,2] is output to output line OUT[0] to output line OUT[5].

[0058] At time T3, the potential of wiring CSEL[1] is set to “L” and the potential of wiring CSEL[2] is set to “H”. At this time, switch 41S becomes non-conducting, and its gate is connected to switch 42S of wiring CSEL[2]. The calculation data of block 13[1,3] is output to output line OUT[0] to output line OUT[5].

[0059] At time T4, set the potential of wiring RSEL[0] to “L” and set the potential of wiring CSEL[2] to “L”, and end the output of the calculation data of block 13 (block 13[1,1] to block 13[1,3]) in row 0.

[0060] From time T4 to time T7, the potential of the wiring RSEL[1] is set to “H”, and the same operation as above is performed, thereby outputting the calculation data of the first row of blocks 13 (blocks 13[2,1] to 13[2,3]).

[0061] In addition, from time T7 to time T10, the potential of the wiring RSEL[2] is set to “H”, and the same operation as above is performed, thereby outputting the calculation data of the second row of blocks 13 (blocks 13[3,1] to 13[3,3]).

[0062] Here, by ending the operation with one clock cycle and performing the reading operation of one block 13 with one clock cycle, a total of ten clock cycles can be used to read one block 12. In addition, by setting the same number of readout circuits 40 as the columns of block 12, the reading of one row of blocks 12 can be performed in parallel.

[0063] <Pixel Circuit> As shown in Figure 10A, the pixel circuit 15 may include a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, and a capacitor 106.

[0064] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source and drain electrodes of the transistor 102. The other of the source and drain electrodes of the transistor 102 is electrically connected to one of the source and drain electrodes of the transistor 103, one electrode of the capacitor 106, and the gate electrode of the transistor 104. One of the source and drain electrodes of the transistor 104 is electrically connected to one of the source and drain electrodes of the transistor 105.

[0065] The other electrode of the photoelectric conversion device 101 is electrically connected to wiring 111. The gate of transistor 102 is electrically connected to wiring 114. The other of the source and drain of transistor 103 is electrically connected to wiring 112. The gate of transistor 103 is electrically connected to wiring 115. The other of the source and drain of transistor 104 is electrically connected to wiring 113. The other of the source and drain of transistor 105 is electrically connected to wiring 117. The gate of transistor 105 is electrically connected to wiring 116.

[0066] Here, the point (wiring) where the other of the source and drain of transistor 102 is electrically connected to one of the source and drain of transistor 103, one electrode of capacitor 106 and gate of transistor 104 is denoted as node N.

[0067] Wiring 111, 112, and 113 can be used as power lines. For example, wiring 111 can be used as a low-potential power line and wiring 112 and 113 can be used as high-potential power lines. Furthermore, wiring 112 and 113 can be electrically connected to each other. Wiring 114, 115, and 116 can be used as signal lines to control the conduction of each transistor. Wiring 117 can be used as wiring to electrically connect pixel circuit 15 and binarization circuit 22.

[0068] A photodiode can be used as the photoelectric conversion device 101. When it is desired to improve the light detection sensitivity in low illumination, a surge photodiode is preferred.

[0069] Transistor 102 may have the function of controlling the potential of node N. Transistor 103 may have the function of initializing the potential of node N. Transistor 104 may have the function of allowing current to flow according to the potential of node N. Transistor 105 may have the function of selecting pixels.

[0070] Alternatively, the connection directions of a pair of electrodes of the photoelectric conversion device 101 can be reversed. In this case, wiring 111 can be used as a high-potential power line and wiring 112 and wiring 113 can be used as low-potential power lines.

[0071] It is preferable to use metal oxide transistors (OS transistors) in the channel forming region as transistors 102 and 103. In addition, OS transistors also have the characteristic of extremely low off-state current. By using OS transistors as transistors 102 and 103, node N can retain charge for a very long period of time. A global shutter mode that performs charge storage operation simultaneously in all pixels can be used without adopting a complex circuit structure and operation mode.

[0072] On the other hand, it is sometimes preferable that the transistor 104 has good amplification characteristics. In addition, it is sometimes preferable that the transistor 105 is a transistor with high mobility that can operate at high speed. Thus, transistors that use silicon in the channel forming region (Si transistors) can be used as transistors 104 and 105.

[0073] Note that, not limited to the above, OS transistors and Si transistors can be used in any combination. Alternatively, OS transistors can be used as all types of transistors. Or, Si transistors can also be used as all types of transistors. Examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (microcrystalline silicon, low-temperature polycrystalline silicon, monocrystalline silicon), etc.

[0074] Alternatively, as shown in FIG10B, a transistor with a back gate (second gate) can also be used. By electrically connecting the back gate to the front gate, the on-state current of the transistor can be increased. Furthermore, by supplying an appropriate constant potential to the back gate, the threshold voltage of the transistor can be controlled. Note that the transistor with a back gate structure can be used in other circuits of this specification. Alternatively, transistors with and without back gates can be combined to form a circuit.

[0075] Alternatively, as shown in FIG10C, a structure can be adopted by adding transistors 107 and 108 to the structure of FIG10A. The gate of transistor 107 is electrically connected to the gate of transistor 104. One of the source and drain of transistor 107 is electrically connected to one of the source and drain of transistor 108. The other of the source and drain of transistor 107 is electrically connected to wiring 113. The gate of transistor 108 is electrically connected to wiring 118. The other of the source and drain of transistor 108 is electrically connected to wiring 119.

[0076] Here, wiring 118 can be used as a signal line to control the conduction of transistor 108. Additionally, wiring 119 can be electrically connected to circuit 60. Circuit 60 is an image readout circuit, such as a CDS circuit (correlated double sampling circuit). Using this structure, image data can be output to wiring 117 and wiring 119. The image data output to wiring 117 is input to binarization circuit 22 and then subjected to a summation operation. The image data output to wiring 119 is read out to the outside via circuit 60. These operations can be performed in parallel. Alternatively, only computation (image processing) or only image data readout can be performed.

[0077] In addition, circuit 60 can be disposed in layer 20 as a component of circuit 35 or circuit 36 ​​shown in FIG1.

[0078] <Memory Circuit> As shown in Figure 2, the memory circuit 16 is disposed in pixel 14. In addition, the memory circuit 16 includes multiple memory cells, each storing 1 bit of data equivalent to a weighting coefficient.

[0079] Figure 11A is a diagram showing the connection relationship of memory cell 150, row driver 33, and column driver 34. Preferably, an OS transistor is used as the transistor constituting memory cell 150. Multiple memory cells 150 are provided as memory circuits 16 in layer 10. Row driver 33 and column driver 34 are driving circuits for memory cells 150 and can be provided in layer 20.

[0080] The memory circuit 16 includes m (m is an integer greater than or equal to 1) memory units 150 in one column and n (n is an integer greater than or equal to 1) memory units in one row, for a total of m×n memory units 150, which are arranged in a matrix.

[0081] Figures 11B and 11C are diagrams illustrating memory cells 150a and 150b that can be used in memory cell 150. Note that, in the following description, bit lines can be connected to column driver 34. Additionally, word lines can be connected to row driver 33. Note that bit lines are also electrically connected to product summing circuitry 23, but this is not shown here.

[0082] As row drivers 33 and column drivers 34, decoders or shift registers can be used, for example. Alternatively, multiple row drivers 33 and multiple column drivers 34 can be configured.

[0083] Figure 11B shows an example of a circuit structure for a gain-cell type (also known as a "2Tr1C type") memory cell 150a, which includes two transistors and a capacitor. The memory cell 150a includes transistors 273 and 272 and a capacitor 274.

[0084] One of the source and drain electrodes of transistor 273 is connected to one electrode of capacitor 274; the other of the source and drain electrodes of transistor 273 is connected to wiring WBL; the gate of transistor 273 is connected to wiring WL; and the back gate of transistor 273 is connected to wiring BGL. The other electrode of capacitor 274 is connected to wiring RL. One of the source and drain electrodes of transistor 272 is connected to wiring RBL; the other of the source and drain electrodes of transistor 272 is connected to wiring SL; and the gate of transistor 272 is connected to one electrode of capacitor 274.

[0085] Wiring WBL is used as the write bit line. Wiring RBL is used as the read bit line. Wiring WL is used as the word line. Wiring RL is used as the wiring to apply a predetermined potential to the other electrode of capacitor 274. During data writing and during data holding, it is preferable to apply a reference potential to wiring RL.

[0086] Wiring BGL is used to apply a potential to the back gate of transistor 273. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor 273 can be increased or decreased.

[0087] Data writing is performed by applying a high-level potential to the wiring WL to turn on the transistor 273, thereby electrically connecting the wiring WBL to one electrode of the capacitor 274. Specifically, when the transistor 273 is in the on state, a potential corresponding to the information to be recorded is applied to the wiring WBL to write that potential to one electrode of the capacitor 274 and the gate of the transistor 272. Then, a low-level potential is applied to the wiring WL to turn the transistor 273 off state, thereby storing the potential of one electrode of the capacitor 274 and the potential of the gate of the transistor 272.

[0088] Data is read out by applying a predetermined potential to wiring RL and wiring SL. Since the current flowing between the source and drain of transistor 272 and the potential of one of the source and drain of transistor 273 are determined by the potential of the gate of transistor 272 and the potential of the other of the source and drain of transistor 273, the potential held by one electrode of capacitor 274 (or the gate of transistor 272) can be read by reading the potential of wiring RBL connected to one of the source and drain of transistor 272. In other words, the information written to the memory cell can be read from the potential held by one electrode of capacitor 274 (or the gate of transistor 272). Alternatively, it can be determined whether information has been written to the memory cell.

[0089] Alternatively, as shown in FIG11C, a structure can be adopted in which the wiring WBL and wiring RBL are combined into a single wiring BIL. In the memory cell 150b shown in FIG11C, the wiring WBL and wiring RBL of the memory cell 150a are combined into a single wiring BIL, and one of the source and drain terminals of transistor 273 and one of the source and drain terminals of transistor 272 are connected to the wiring BIL. That is, the memory cell 150b operates by combining the write bit line and the read bit line into a single wiring BIL.

[0090] Furthermore, the transistors 273 of memory cells 150a and 150b are preferably OS transistors. The memory device using 2Tr1C type memory cells, such as memory cells 150a and 150b, with OS transistors as transistors 273, is called NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

[0091] <Layout> Figures 12A and 12B are examples of a pixel circuit layout (top view) that can be used in one embodiment of the present invention. Figures 12A and 12B are the layout of the pixel circuit shown in Figure 10B. Figure 12A shows a back gate wiring 170, a metal oxide layer 175, and a source-drain wiring 180. Here, the metal oxide layer 175 is the layer where the channel formation region of the OS transistor is disposed.

[0092] To improve the resolution of the camera device, the pixel circuitry needs to be miniaturized. During the miniaturization process, adjacent structures affect each other, so if the structures are randomly arranged, unevenness in wiring width, etc., is amplified. Therefore, as shown in FIG12A, it is preferable to arrange the structures at equal intervals in the horizontal direction (X direction) and the vertical direction (Y direction).

[0093] Figure 12B shows a structure with an additional gate wiring 185 and wiring 190 electrically connected to the gate wiring 185 added to Figure 12A. Thus, by overlapping the components, transistors 102, 103, 104, and 105 as shown in Figure 10B are formed. In addition, a plurality of transistors 109 are formed. Transistors 109 are pseudo-transistors unrelated to circuit operation, but by employing this structure, the uniformity of wiring width, etc., can be improved, and non-uniformity of transistor characteristics can be suppressed.

[0094] By means of an embodiment of the present invention described in this embodiment, a camera device having image processing function and capable of high-speed operation can be provided.

[0095] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0096] Embodiment 2 In this embodiment, a camera device having a structure different from that of Embodiment 1 will be described with reference to the drawings. In the camera device described in Embodiment 1, image data is extracted by performing a product-sum operation once, while in the camera device described in this embodiment, image data is extracted by performing a product-sum operation multiple times.

[0097] The basic structure of pixel 14 and squares (squares 12 and 13) is the same as that of embodiment 1, so detailed description is omitted.

[0098] The camera device, as a component used to extract computational data by performing multiple product sum operations, includes two registers. Figure 13 is a diagram illustrating the connection relationship between block 12 and register 51, one of the two registers (register 51 and register 52). Note that a selection circuit can also be provided between block 13 and register 51 to reduce the number of wires.

[0099] In Figure 13, a simplified version of the block 12 shown in Figure 8 is illustrated, and a total of 6 bits (1 bit × 6) of computational data after the first product sum operation is shown output from each block 13. The total of 6 bits of computational data output from each block 13 is input into and stored in register 51. Here, register 51 is input with a total of 6 bits of computational data output from nine blocks 13, thus storing a total of 54 bits (6 bits × 9) of computational data.

[0100] Next, as shown in FIG14, the total 54 bits of computation data stored in the temporary register 51 are redistributed to each block 13. Each block 13 is provided with six product summation circuits 23, as shown in FIG6A, capable of processing a total of 9 bits of data, and the total 9 bits of computation data are distributed to each product summation circuit 23. In addition, a total of 9 bits of weight coefficients are provided to each product summation circuit 23 from the nine memory circuits 16 included in block 13. Therefore, each product summation circuit 23 can perform a second product summation operation.

[0101] Next, as shown in FIG15A, the 4-bit operation data output by each product sum operation circuit 23 is input to each circuit 25, which is set in the same number as block 13. Here, since there are six product sum operation circuits 23, the total operation data input to the circuit 25 is 24 bits (4 bits × 6).

[0102] Figure 15B is a diagram illustrating circuit 25. Circuit 25 includes an adder circuit 26a and a binarization circuit 26b. Because each of the six product summation circuits 23 inputs 4 bits (equivalent to 0 to 9) of operation data to the adder circuit 26a, the output of the adder circuit 26a is 6 bits (equivalent to 0 to 54) of operation data. The 6 bits of data are input to the binarization circuit 26b. The binarization circuit 26b can convert the input data into 1 bit, outputting 1 when the data is 28 or higher and outputting 0 when the data is 27 or lower. Note that although circuit 25 is located inside block 12 in Figure 15, circuit 25 can also be located outside block 12.

[0103] The 1-bit operation data output by each circuit 25 (a total of 9 bits of data) is input to and stored in the temporary register 52. Here, the total 9 bits of operation data can be read out as needed. Note that a selection circuit can also be set between circuit 25 and temporary register 52 to reduce the number of wires.

[0104] In this embodiment, the operation of repeatedly performing the product summation operation by changing the weight coefficients will be described. After the above operation, the product summation operation circuit 23 included in block 13 retains a total of 54 bits of operation data redistributed from the temporary register 51, and performs the product summation operation again by changing the weight coefficients provided from the memory circuit 16, thereby obtaining different operation data. Furthermore, this operation data is stored in the temporary register 52 in the same way as the operation data obtained in the previous product summation operation. Therefore, a total of 18 bits of operation data is stored in the temporary register 52.

[0105] Figure 16A is a diagram illustrating the readout circuit 41 connected to the output side of the register 52. The output side of the register 52 is provided with six output lines for reading out a total of 6 bits of operational data. The six output lines are electrically connected to the readout circuit 41. The readout circuit 41 includes switches 43S, 44S, and 45S electrically connected to each of the six output lines.

[0106] Switches 43S to 45S include multiple transistors. The gate of the transistor included in switch 43S is electrically connected to the wiring CSEL[0]. The gate of the transistor included in switch 44S is electrically connected to the wiring CSEL[1]. The gate of the transistor included in switch 45S is electrically connected to the wiring CSEL[2].

[0107] The wiring on each output side of switches 43S to 45S is electrically connected to an output line OUT (OUT[0] to OUT[5]), that is, the three wirings are electrically connected to one output line OUT. By adopting this structure, a total of 6 bits of operational data can be output.

[0108] The temporary register 51, the temporary register 52 and the readout circuit 41 can be set in layer 20 as components of circuit 35 or circuit 36 ​​shown in FIG1.

[0109] Figure 16B is a timing diagram illustrating the reading of computation data stored in register 52. It is assumed that all computation data (a total of 18 bits) is stored in register 52 before time T1. Furthermore, in the following description, the potential that puts the transistor in the conducting state (high potential) is recorded as "H", and the potential that puts the transistor in the non-conducting state (low potential) is recorded as "L".

[0110] At time T1, the potential of the wiring CSEL[0] is set to “H”. At this time, its gate is connected to the switch of wiring CSEL[0] for 43S and is turned on. The first total of 6 bits of operation data is output to the output line OUT[0] to the output line OUT[5].

[0111] At time T2, the potential of wiring CSEL[0] is set to “L” and the potential of wiring CSEL[1] is set to “H”. At this time, switch 43S becomes non-conducting, and its gate is connected to switch 44S of wiring CSEL[1]. The second total 6 bits of operation data, which is different from the first data, is output to output line OUT[0] to output line OUT[5].

[0112] At time T3, the potential of wiring CSEL[1] is set to “L” and the potential of wiring CSEL[2] is set to “H”. At this time, switch 44S becomes non-conducting, and its gate is connected to switch 45S of wiring CSEL[2]. The total 6 bits of operation data of the third time, which is different from the data of the first and second times, are output to output line OUT[0] to output line OUT[5].

[0113] Here, the operation of storing a total of 54 bits of computation data in register 51 is performed at the first clock cycle, the operation of storing a total of 9 bits of computation data in register 52 is performed at the second clock cycle, and the operation of storing a total of 9 bits of computation data in register 52 is performed at the third clock cycle. Then, the operation of reading a total of 6 bits of computation data from register 52 at the fourth clock cycle, the operation of reading a total of 6 bits of computation data from the second clock cycle at the fifth clock cycle, and the operation of reading a total of 6 bits of computation data from the third clock cycle at the sixth clock cycle can be completed in six clock cycles.

[0114] The operations of the first to third clock cycles and the fourth to sixth clock cycles can be performed in parallel. In the timing diagram shown in Figure 16B, when time T1 to time T2 corresponds to the fourth clock cycle, time T2 to time T3 corresponds to the fifth clock cycle, and time T3 to time T4 corresponds to the sixth clock cycle, the next total of 18 bits of operation data can be read from time T4 to time T7. Furthermore, the next total of 18 bits of operation data can be read from time T7 to time T10.

[0115] Note that the reading of computation data from block 12 in Implementation 1 and this implementation is equivalent to a step size of 3, omitting pooling processing, but pooling processing can also be performed to further compress the computation data.

[0116] By means of an embodiment of the present invention described in this embodiment, a camera device having image processing function and capable of high-speed operation can be provided.

[0117] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0118] Embodiment 3 In this embodiment, an example of the structure of a camera device according to one embodiment of the present invention will be described.

[0119] <Structural Example> Figure 17A is a diagram showing an example of the pixel structure of a camera device, which can employ a stacked structure of layers 561 and 563.

[0120] Layer 561 includes photoelectric conversion device 101. As shown in FIG18A, photoelectric conversion device 101 may include layers 565a and 565b. Note that, depending on the situation, layers may also be referred to as regions.

[0121] The photoelectric conversion device 101 shown in FIG18A is a pn junction type photodiode. For example, a p-type semiconductor can be used as layer 565a and an n-type semiconductor can be used as layer 565b. Alternatively, an n-type semiconductor can be used as layer 565a and a p-type semiconductor can be used as layer 565b.

[0122] The above-mentioned pn junction type photodiode can typically be formed using single-crystal silicon. Photodiodes using single-crystal silicon as the photoelectric conversion layer have a wider spectroscopic sensitivity characteristics from ultraviolet to near-infrared light, and by combining with the optical conversion layer described later, light of various wavelengths can be detected.

[0123] Furthermore, a compound semiconductor can also be used as the photoelectric conversion layer of the pn-junction type photodiode. For example, gallium-arsenic-phosphorus compound (GaAsP), gallium-phosphorus compound (GaP), indium-gallium-arsenic compound (InGaAs), lead-sulfur compound (PbS), lead-selenium compound (PbSe), indium-arsenic compound (InAs), indium-antimony compound (InSb), mercury-cadmium-tellurium compound (HgCdTe), etc., can be used.

[0124] The compound semiconductor is preferably a compound semiconductor containing Group 13 elements (aluminum, gallium, indium, etc.) and Group 15 elements (nitrogen, phosphorus, arsenic, antimony, etc.) (also known as III-V compound semiconductor) or a compound semiconductor containing Group 12 elements (magnesium, zinc, cadmium, mercury, etc.) and Group 16 elements (oxygen, sulfur, selenium, tellurium, etc.) (also known as II-VI compound semiconductor).

[0125] In compound semiconductors, the band gap can be changed according to the combination of constituent elements and their atomic ratio, thus enabling the formation of photodiodes with sensitivity in various wavelength ranges from ultraviolet to near-infrared light.

[0126] Note that it can generally be defined as follows: the wavelength of ultraviolet light is from about 0.01 μm to about 0.38 μm, the wavelength of visible light is from about 0.38 μm to about 0.75 μm, the wavelength of near-infrared light is from about 0.75 μm to about 2.5 μm, the wavelength of mid-infrared light is from about 2.5 μm to about 4 μm, and the wavelength of far-infrared light is from about 4 μm to about 1000 μm.

[0127] For example, to form a photodiode sensitive to ultraviolet to visible light, GaP or the like can be used as the photoelectric conversion layer. Furthermore, to form a photodiode sensitive to ultraviolet to near-infrared light, silicon or GaAsP or the like can be used as the photoelectric conversion layer. Furthermore, to form a photodiode sensitive to visible to mid-infrared light, InGaAs or the like can be used as the photoelectric conversion layer. Furthermore, to form a photodiode sensitive to near-infrared to mid-infrared light, PbS or InAs or the like can be used as the photoelectric conversion layer. Furthermore, to form a photodiode sensitive to mid-infrared to far-infrared light, PbSe, InSb, or HgCdTe or the like can be used as the photoelectric conversion layer.

[0128] Note that the photodiode using the above-mentioned compound semiconductor may be a pin-junction photodiode rather than a pn-junction photodiode. The pn-junction and pin-junction are not limited to homogeneous junction structures, and heterogeneous junction structures may also be used.

[0129] For example, in the case of a heterojunction, a first compound semiconductor can be used in one layer of the pn junction structure and a second compound semiconductor, different from the first compound semiconductor, can be used in another layer of the pn junction structure. Alternatively, a first compound semiconductor can be used in any one or both layers of the pin junction structure and a second compound semiconductor, different from the first compound semiconductor, can be used in other layers of the pin junction structure. Furthermore, one of the first and second compound semiconductors can also be a monomeric semiconductor such as silicon.

[0130] In addition, different materials can be used to form the photoelectric conversion layer of the photodiode depending on the pixel. By adopting this structure, an imaging device can be formed that includes any two or three types of pixels, such as pixels that detect ultraviolet light, pixels that detect visible light, and pixels that detect infrared light.

[0131] In addition, the photoelectric conversion device 101 in layer 561 can be a stack of layers 566a, 566b, 566c and 566d as shown in FIG18B. The photoelectric conversion device 101 shown in FIG18B is an example of a sudden-amplification photodiode, where layers 566a and 566d are equivalent to electrodes, and layers 566b and 566c are equivalent to photoelectric conversion sections.

[0132] Layer 566a is preferably a low-resistance metal layer, etc. For example, aluminum, titanium, tungsten, tantalum, silver or a stack thereof can be used.

[0133] Layer 566d is preferably a conductive layer with high transmittance to visible light. For example, indium oxide, tin oxide, zinc oxide, indium tin oxide, gallium zinc oxide, indium gallium zinc oxide, or graphene can be used. Alternatively, layer 566d can be omitted.

[0134] Layers 566b and 566c of the photoelectric conversion section may, for example, have a structure of a pn-junction type photodiode in which a selenium-based material is used as the photoelectric conversion layer. Preferably, a selenium-based material, which is a p-type semiconductor, is used as layer 566b, and gallium oxide, which is an n-type semiconductor, is used as layer 566c.

[0135] Photoelectric conversion devices using selenium-based materials exhibit high external quantum efficiency for visible light. These devices can increase the electron amplification relative to the amount of incident light by utilizing burst multiplication. Furthermore, selenium-based materials have a high light absorption coefficient, so photoelectric conversion layers can be fabricated, for example, as thin films; therefore, the use of selenium-based materials is advantageous from a manufacturing point of view. Thin films of selenium-based materials can be formed by methods such as vacuum evaporation or sputtering.

[0136] As a selenium-based material, crystalline selenium (monocrystalline selenium, polycrystalline selenium) and amorphous selenium can be used. These selenium compounds are photosensitive to ultraviolet to visible light. Alternatively, compounds of copper, indium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium (CIGS) can be used. These compounds are photosensitive to ultraviolet to near-infrared light.

[0137] The n-type semiconductor is preferably formed of a material with a wide band gap and transparency to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or oxides of the above substances can be used. In addition, these materials also have the function of a hole injection barrier layer, which can reduce dark current.

[0138] Furthermore, the photoelectric conversion device 101 in layer 561 can be a stack of layers 567a, 567b, 567c, 567d, and 567e, as shown in FIG18C. The photoelectric conversion device 101 shown in FIG18C is an example of an organic photoconductive film, where layer 567a is the lower electrode, layer 567e is the upper electrode with light transmittance, and layers 567b, 567c, and 567d correspond to the photoelectric conversion section.

[0139] Either of layers 567b and 567d in the photoelectric conversion section can be a hole transport layer, and the other can be an electron transport layer. In addition, layer 567c can be a photoelectric conversion layer.

[0140] As a hole transport layer, molybdenum oxide, for example, can be used. As an electron transport layer, fullerenes such as C60 and C70 or their derivatives can be used, for example.

[0141] As a photoelectric conversion layer, a hybrid layer of n-type organic semiconductors and p-type organic semiconductors (bulk heterojunction structure) can be used. There are various types of organic semiconductors, and the material with photosensitive properties to the target wavelength can be selected as the photoelectric conversion layer.

[0142] Layer 563 shown in FIG. 17A can, for example, be a silicon substrate. This silicon substrate includes Si transistors, etc. Using this Si transistor, in addition to forming pixel circuits, circuits driving the pixel circuits, image signal readout circuits, image processing circuits, neural networks, communication circuits, etc., can also be formed. Furthermore, memory circuits such as DRAM (Dynamic Random Access Memory), CPUs (Central Processing Units), MCUs (Micro Controller Units), etc., can also be formed. Note that in this embodiment, the above-mentioned circuits other than the pixel circuits are referred to as functional circuits.

[0143] For example, some or all of the transistors included in the functional circuits (arithmetic unit 21, row driver 31, column driver 32, row driver 33, column driver 34, circuit 35, circuit 36, etc.) provided in layer 20 described in Embodiment 1 may be provided in layer 563.

[0144] Alternatively, layer 563 can also be a stack of multiple layers as shown in FIG17B. FIG17B shows an example of three layers 563a, 563b, and 563c, but it can also be two layers. Alternatively, layer 563 can also be a stack of four or more layers. These layers can be stacked, for example, using a bonding process. By adopting this structure, pixel circuits and functional circuits can be distributed in multiple layers and can be stacked overlappingly, thereby enabling the manufacture of a small and high-performance imaging device.

[0145] In addition, the pixels can also adopt a stacked structure of layers 561, 562 and 563 as shown in FIG17C.

[0146] Layer 562 corresponds to layer 10 described in Embodiment 1 and may include an OS transistor. One or more of the above-described functional circuits may be formed using an OS transistor. Alternatively, one or more functional circuits may be formed using a Si transistor included in layer 563 and an OS transistor included in layer 562. Furthermore, a support substrate such as a glass substrate may be used as layer 563, and pixel circuits and functional circuits may be formed using an OS transistor included in layer 562.

[0147] For example, normally off CPUs (also known as "NoffCPUs (registered trademarks)") can be implemented using OS transistors and Si transistors. NoffCPU refers to an integrated circuit that includes normally off transistors that are in a non-conducting state (also known as a closed state) even when the gate voltage is 0V.

[0148] In the NoffCPU, power supply to circuits that are not in operation can be stopped, putting those circuits into a standby state. In a standby state with power cut off, no power is consumed. Therefore, the NoffCPU can minimize power consumption. Furthermore, even with power cut off, the NoffCPU can retain information necessary for operation, such as settings, for an extended period. When resuming from standby, simply restarting power supply to the circuit is sufficient; rewriting settings is not required. In other words, it can resume from standby at high speed. Thus, the NoffCPU can reduce power consumption without significantly reducing its operating speed.

[0149] Alternatively, layer 562 can also be a stack of multiple layers as shown in FIG17D. FIG17D shows a two-layer structure of layers 562a and 562b, but a stack of three or more layers can be used. These layers can be formed, for example, by being stacked on layer 563. Alternatively, they can be formed by bonding a layer formed on layer 563 with a layer formed on layer 561.

[0150] As semiconductor materials for OS transistors, metal oxides with a bandgap of 2 eV or higher, preferably 2.5 eV or higher, and more preferably 3 eV or higher can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS mentioned later. In CAAC-OS, the atoms constituting the crystal are stable, making it suitable for transistors where reliability is important. CAC-OS exhibits high mobility characteristics, making it suitable for transistors used in high-speed driving.

[0151] Due to the large bandgap in the semiconductor layer of OS transistors, they exhibit extremely low off-state current characteristics, only a few μA / μm (current value per channel width of 1 μm). Unlike Si transistors, OS transistors do not experience impact ionization, sudden collapse, or short-channel effects, thus enabling the formation of circuits with high voltage withstand capability and high reliability. Furthermore, the electrical property inhomogeneities caused by crystallinity non-uniformity in Si transistors are not easily generated in OS transistors.

[0152] As the semiconductor layer in the OS transistor, a film labeled "In-M-Zn oxide" may be used, for example, containing indium, zinc, and M (selected from one or more metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). Typically, In-M-Zn oxide can be formed by sputtering. Alternatively, it can be formed by ALD (atomic layer deposition).

[0153] When forming In-M-Zn type oxides using sputtering, it is preferable that the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn type oxides satisfies In≥M and Zn≥M. Preferred atomic ratios of the metal elements in such sputtering targets are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. Note that the atomic ratio of the semiconductor layer formed may vary within ±40% of the atomic ratio of the metal elements in the sputtering target described above.

[0154] As the semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, an oxide semiconductor with a carrier density of 1×10¹⁷ / cm³ or less, preferably 1×10¹⁵ / cm³ or less, more preferably 1×10¹³ / cm³ or less, further preferably 1×10¹¹ / cm³ or less, and even more preferably less than 1×10¹⁰ / cm³ or more than 1×10⁻⁹ / cm³ can be used as the semiconductor layer. Such an oxide semiconductor is referred to as a high-purity or substantially high-purity oxide semiconductor. This oxide semiconductor has a low defect state density and therefore can be considered an oxide semiconductor with stable characteristics.

[0155] Note that the present invention is not limited to the above description, and materials with appropriate compositions can be used according to the desired semiconductor characteristics and electrical characteristics (field-effect mobility, critical voltage, etc.) of the transistor. In addition, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0156] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which are elements of Group 14, the oxygen vacancies increase, causing the semiconductor layer to become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10¹⁸ atoms / cm³ or less, preferably 2×10¹⁷ atoms / cm³ or less.

[0157] In addition, carriers are sometimes generated when alkali metals and alkaline earth metals bond with oxide semiconductors, thereby increasing the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10¹⁸ atoms / cm³ or less, preferably 2×10¹⁶ atoms / cm³ or less.

[0158] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, increasing the carrier density and making it easier to n-type. As a result, transistors using nitrogen-containing oxide semiconductors tend to have always-on characteristics. Therefore, the nitrogen concentration of the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5 × 10¹⁸ atoms / cm³ or less.

[0159] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, the hydrogen reacts with the oxygen bonded to the metal atoms to form water, thus sometimes forming oxygen vacancies in the oxide semiconductor. When the channel-forming region in the oxide semiconductor contains oxygen vacancies, the transistor tends to have always-on characteristics. Moreover, sometimes defects formed by hydrogen entering oxygen vacancies are used as donors to generate electrons as carriers. In addition, some hydrogen bonds to oxygen bonded to the metal atoms to generate electrons as carriers. Therefore, transistors using oxide semiconductors containing more hydrogen tend to have always-on characteristics.

[0160] Defects formed by hydrogen entering oxygen vacancies are used as donors in oxide semiconductors. However, it is difficult to quantitatively evaluate these defects. Therefore, in oxide semiconductors, evaluation is sometimes based on carrier concentration rather than donor concentration. Consequently, in this specification, etc., carrier concentration, which is assumed to be in a state where no electric field is applied, is sometimes used as a parameter for oxide semiconductors instead of donor concentration. That is to say, the "carrier concentration" described in this specification, etc., may sometimes be referred to as "donor concentration".

[0161] Therefore, it is preferable to minimize the amount of hydrogen in the oxide semiconductor. Specifically, in the oxide semiconductor, the hydrogen concentration, as measured by secondary ion mass spectrometry (SIMS), is less than 1 × 10²⁰ atoms / cm³, more preferably less than 1 × 10¹⁹ atoms / cm³, even more preferably less than 5 × 10¹⁸ atoms / cm³, and further preferably less than 1 × 10¹⁸ atoms / cm³. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical properties can be imparted.

[0162] In addition, the semiconductor layer may also have a non-single-crystal structure. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) with c-axis alignment, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, amorphous structures have the highest defect state density, while CAAC-OS has the lowest defect state density.

[0163] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not have crystalline components. Alternatively, an amorphous oxide film, for example, is a completely amorphous structure and does not have crystalline portions.

[0164] Furthermore, the semiconductor layer may also be a mixture of two or more regions having an amorphous structure, a microcrystalline structure, a polycrystalline structure, a CAAC-OS region, and a single-crystal structure. The mixture may sometimes have, for example, a single-layer structure or a stacked structure including two or more of the aforementioned regions.

[0165] The structure of CAC (Cloud-Aligned Composite)-OS in one embodiment of a non-single-crystal semiconductor layer will be described below.

[0166] CAC-OS refers, for example, to a configuration in which elements contained in an oxide semiconductor are non-uniformly distributed, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed in an oxide semiconductor and the regions containing the metal elements are mixed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately, is also referred to as mosaic or patch.

[0167] The oxide semiconductor preferably contains at least indium. More preferably, it contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0168] For example, CAC-OS in In-Ga-Zn oxide (in particular, In-Ga-Zn oxide can be referred to as CAC-IGZO) refers to a material divided into indium oxide (hereinafter referred to as InOX1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter referred to as InX2ZnY2OZ2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaOX3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as GaX4ZnY4OZ4 (X4, Y4 and Z4 are real numbers greater than 0)) etc., which are mosaic-shaped, and the mosaic-shaped InOX1 or InX2ZnY2OZ2 is uniformly distributed in the film (hereinafter also referred to as cloud-like).

[0169] In other words, CAC-OS is a composite oxide semiconductor composed of regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components. In this specification, for example, when the atomic ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0170] Note that IGZO is a general term and sometimes refers to compounds containing In, Ga, Zn, and O. As typical examples, crystalline compounds can be represented as InGaO3(ZnO)m1 (m1 is a natural number) or In(1+x0)Ga(1-x0)O3(ZnO)m0 (-1≤x0≤1, m0 is an arbitrary number).

[0171] The above-mentioned crystalline compounds have single-crystal, polycrystalline, or CAAC structures. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in an unoriented manner on the ab plane.

[0172] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to a material composition containing In, Ga, Zn, and O, in which nanoparticle-like regions with Ga as the main component are observed in one part, and nanoparticle-like regions with In as the main component are observed in another part, and these regions are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0173] CAC-OS does not contain a stacked structure of two or more films with different compositions. For example, it does not contain a structure consisting of two layers, one of an In-based film and the other of a Ga-based film.

[0174] Note that sometimes it is not possible to observe a clear boundary between regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components.

[0175] When CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium to replace gallium, CAC-OS refers to a composition in which nanoparticle-like regions with the metal element as the main component are observed in one part and nanoparticle-like regions with In as the main component are observed to be irregularly dispersed in a mosaic pattern in another part.

[0176] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gases, and nitrogen gases can be used as the deposition gas. Furthermore, the lower the oxygen gas flow rate ratio in the total flow rate of the deposition gas during film formation, the better; for example, the oxygen gas flow rate ratio is set to 0% or more and less than 30%, preferably 0% or more and less than 10%.

[0177] CAC-OS has the following characteristics: when measured using the out-of-plane method, one of the X-ray diffraction (XRD) methods, with θ / 2θ scanning, no distinct peaks are observed. In other words, according to X-ray diffraction, there is no alignment in the ab plane direction and the c-axis direction in the measurement region.

[0178] Furthermore, in the electron diffraction pattern of CAC-OS obtained by irradiating with an electron beam with a beam diameter of 1 nm (also known as a nano beam), a ring-shaped region of high brightness (ring region) and multiple bright spots within the ring region were observed. Thus, based on the electron diffraction pattern, it can be known that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is not aligned in the planar direction and in the cross-sectional direction.

[0179] In addition, for example, in the CAC-OS of In-Ga-Zn oxide, according to the EDX-mapping image obtained by Energy Dispersive X-ray spectroscopy (EDX), it can be confirmed that there is a mixture of regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components.

[0180] The structure of CAC-OS differs from that of IGZO compounds, where metallic elements are uniformly distributed, and it possesses different properties. In other words, CAC-OS has a mosaic-like structure in which regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components are separated from each other.

[0181] Here, the conductivity of regions with InX2ZnY2OZ2 or InOX1 as the main components is higher than that of regions with GaOX3 or the like. In other words, when carriers flow through regions with InX2ZnY2OZ2 or InOX1 as the main components, they exhibit the conductivity of oxide semiconductors. Therefore, when regions with InX2ZnY2OZ2 or InOX1 as the main components are distributed in a cloud-like pattern in an oxide semiconductor, a high field-efficiency mobility (μ) can be achieved.

[0182] On the other hand, regions with GaOX3 as the main component have higher insulation properties than regions with InX2ZnY2OZ2 or InOX1 as the main component. In other words, when regions with GaOX3 as the main component are distributed in oxide semiconductors, leakage current can be suppressed and good switching operation can be achieved.

[0183] Therefore, when CAC-OS is used in semiconductor devices, high on-state current (Ion) and high field-effect mobility (μ) can be achieved by means of the complementary effect of the insulation caused by GaOX3 and the conductivity caused by InX2ZnY2OZ2 or InOX1.

[0184] In addition, semiconductor components using CAC-OS have high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0185] <Layered Structure 1> Next, the layered structure of the imaging device will be described with reference to the cross-sectional view. Note that the components such as the insulating layer and conductive layer shown below are only examples, and other components may also be included. Alternatively, some of the components shown below may be omitted. In addition, the layered structure shown below can be formed as needed using bonding processes, polishing processes, etc.

[0186] FIG19 is an example of a cross-sectional view of a laminated body including layer 560, layer 561 and layer 563, and having a joint plane between layer 563a and layer 563b constituting layer 563.

[0187] <Layer 563b> Layer 563b may include functional circuitry disposed in silicon substrate 611. Here, transistors 223, 224, and 225 are shown as some of the transistors included in the functional circuitry. Note that transistor 225 is shown as a transistor included in binarization circuit 22.

[0188] Layer 563b is provided with a silicon substrate 611, and insulating layers 612, 613, 614, 616, 617, and 618. Insulating layer 612 serves as a protective film. Insulating layers 613, 614, 616, and 617 serve as interlayer insulating films and planarization films. Insulating layer 618 and conductive layer 619 serve as bonding layers. Conductive layer 619 is electrically connected to the gate of transistor 225.

[0189] As a protective film, silicon nitride film, silicon oxide film, aluminum oxide film, etc., can be used, for example. As an interlayer insulating film and planarization film, inorganic insulating films such as silicon oxide film, and organic insulating films such as acrylic resin, polyimide resin, etc., can be used, for example. As the dielectric layer of the capacitor, silicon nitride film, silicon oxide film, aluminum oxide film, etc., can be used. The bonding layer will be described in detail later.

[0190] As a conductor that can be used for electrical connections between devices, such as wiring, electrodes, and plugs, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy composed of the above metal elements, or an alloy combining the above metal elements may be used. This conductor can be a single layer or multiple layers composed of different materials.

[0191] <Layer 563a> Layer 563a includes components of pixel 14. It may also include components of functional circuitry. Here, transistors 102 and 105, included in pixel circuitry 15, are shown as part of the components of pixel 14. The cross-sectional view shown in FIG19 does not show the electrical connection between the two.

[0192] Layer 563a includes a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638. Additionally, conductive layers 636 and 639 are also provided.

[0193] Insulating layer 631 and conductive layer 639 can be used as bonding layers. Insulating layers 634, 635, and 637 can be used as interlayer insulating films and planarization films. Insulating layer 633 can be used as a protective film. Insulating layer 638 can insulate the silicon substrate 632 from the conductive layer 639. Insulating layer 638 can be formed using the same material as the other insulating layers. Alternatively, insulating layer 638 can be formed using the same material as insulating layer 631.

[0194] The conductive layer 639 is electrically connected to the other of the source and drain electrodes of the transistor 105 and the conductive layer 619. In addition, the conductive layer 636 is electrically connected to the wiring 111 (see Figure 10A).

[0195] The Si transistor shown in FIG19 is a fin-type transistor with a channel forming region in a silicon substrate (silicon substrate 611, 632). FIG20A shows a cross-section in the channel width direction (A1-A2 cross-section of layer 563a in FIG19). Alternatively, the Si transistor can also be a planar transistor as shown in FIG20B.

[0196] Alternatively, as shown in FIG20C, a transistor including a semiconductor layer 545 of a silicon thin film may also be used. For example, the semiconductor layer 545 may be a single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 632.

[0197] <Layer 561> Layer 561 includes a photoelectric conversion device 101. The photoelectric conversion device 101 may be formed on layer 563a. In FIG19, a structure is shown in which the organic photoconductive film shown in FIG18C is used as the photoelectric conversion layer as the photoelectric conversion device 101. Here, layer 567a is the cathode and layer 567e is the anode.

[0198] Layer 561 is provided with insulating layers 651, 652, 653, 654 and conductive layer 655.

[0199] Insulating layers 651, 653, and 654 serve as interlayer insulating films and planarization films. Furthermore, insulating layer 654 is provided to cover the end of photoelectric conversion device 101, thus preventing short circuits between layers 567e and 567a. Insulating layer 652 serves as a component separation layer. Preferably, an organic insulating film or the like is used for the component separation layer.

[0200] Layer 567a, which corresponds to the cathode of photoelectric conversion device 101, is electrically connected to one of the source and drain electrodes of transistor 102 in layer 563a. Layer 567e, which corresponds to the anode of photoelectric conversion device 101, is electrically connected to conductive layer 636 in layer 563a via conductive layer 655.

[0201] <Layer 560> Layer 560 is formed on layer 561. Layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0202] The light-shielding layer 671 can suppress light incident on adjacent pixels. The light-shielding layer 671 can be a metal layer such as aluminum or tungsten. Alternatively, the metal layer can be laminated with a dielectric film that functions as an anti-reflection film.

[0203] When the photoelectric conversion device 101 is sensitive to visible light, color filters can be used as the optical conversion layer 672. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each color filter for each pixel, a color image can be obtained. For example, as shown in the perspective view (including cross-section) of FIG28A, color filter 672R (red), color filter 672G (green), and color filter 672B (blue) can also be assigned to different pixels respectively.

[0204] In addition, in a suitable combination of photoelectric conversion device 101 and optical conversion layer 672, when a wavelength cutoff filter is used as optical conversion layer 672, an imaging device capable of acquiring images in various wavelength regions can be realized.

[0205] For example, when an infrared filter that blocks light with wavelengths lower than visible light is used as the optical conversion layer 672, an infrared imaging device can be obtained. Furthermore, by using a filter that blocks light with wavelengths lower than near-infrared light as the optical conversion layer 672, a far-infrared imaging device can be formed. Additionally, by using an ultraviolet filter that blocks light with wavelengths higher than visible light as the optical conversion layer 672, an ultraviolet imaging device can be formed.

[0206] Furthermore, multiple different optical conversion layers can be configured within a single camera device. For example, as shown in FIG28B, color filter 672R (red), color filter 672G (green), color filter 672B (blue), and infrared filter 672IR can be assigned to different pixels. By employing this structure, visible light images and infrared light images can be acquired simultaneously.

[0207] Alternatively, as shown in Figure 28C, color filters 672R (red), 672G (green), 672B (blue), and 672UV can be assigned to different pixels. By employing this structure, visible light images and ultraviolet light images can be acquired simultaneously.

[0208] Furthermore, by using a scintillator in the optical conversion layer 672, an imaging device for obtaining images that visualize radiation intensity can be formed, such as an X-ray imaging device. When X-rays or other radiation passing through an object are incident on the scintillator, they are converted into visible light or ultraviolet light (fluorescence) due to photoluminescence. Image data is obtained by detecting this light using a photoelectric conversion device 101. In addition, this imaging device can also be used in radiation detectors, etc.

[0209] Scintillators contain substances that absorb the energy of radiation when irradiated with X-rays or gamma rays and emit visible or ultraviolet light. For example, materials in which Gd₂O₂S:Tb, Gd₂O₂S:Pr, Gd₂O₂S:Eu, BaFCl:Eu, NaI, CsI, CaF₂, BaF₂, CeF₃, LiF, LiI, ZnO, etc., are dispersed in resin or ceramics can be used.

[0210] By using infrared or ultraviolet light for imaging, camera devices can be endowed with detection, safety, and sensing functions. For example, by using infrared light for imaging, the following detections can be performed: non-destructive testing of products, selection of agricultural products (such as the function of a saccharimeter), vein recognition, and medical testing. In addition, by using ultraviolet light for imaging, ultraviolet light emitted from light sources or flames can be detected, thereby enabling the management of light sources, heat sources, production equipment, etc.

[0211] A microlens array 673 is disposed on the optical conversion layer 672. Light passing through each lens included in the microlens array 673 passes through the optical conversion layer 672 directly below and illuminates the photoelectric conversion device 101. By disposing of the microlens array 673, the focused light can be incident on the photoelectric conversion device 101, thus enabling efficient photoelectric conversion. The microlens array 673 is preferably formed of a resin or glass, etc., which has high light transmittance to the target wavelength.

[0212] <Adhesion> Next, the adhesion between layer 563b and layer 563a will be explained.

[0213] An insulating layer 618 and a conductive layer 619 are provided in layer 563b. The conductive layer 619 has a region embedded in the insulating layer 618. In addition, the surfaces of the insulating layer 618 and the conductive layer 619 are planarized in a highly consistent manner.

[0214] An insulating layer 631 and a conductive layer 639 are provided in layer 563a. The conductive layer 639 has a region embedded in the insulating layer 631. In addition, the surfaces of the insulating layer 631 and the conductive layer 639 are planarized in a highly consistent manner.

[0215] Here, the main components of conductive layer 619 and conductive layer 639 are preferably the same metallic element. In addition, insulating layer 618 and insulating layer 631 are preferably composed of the same composition.

[0216] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used as conductive layers 619 and 639. From the viewpoint of ease of bonding, Cu, Al, W, or Au is preferred. Furthermore, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, titanium nitride, etc., can be used as insulating layers 618 and 631.

[0217] In other words, preferably, the same metallic material as shown above is used for both conductive layer 619 and conductive layer 639. Furthermore, preferably, the same insulating material as the aforementioned insulating material is used for both insulating layer 618 and insulating layer 631. By adopting the above structure, bonding can be performed with the boundary between layers 563b and 563a as the bonding location.

[0218] Note that conductive layer 619 and conductive layer 639 can also have a multilayer structure with multiple layers, in which case the surface layer (bonding surface) can be made of the same metal material. In addition, insulating layer 618 and insulating layer 631 can also have a multilayer structure with multiple layers, in which case the surface layer (bonding surface) can be made of the same insulating material.

[0219] By performing this bonding, an electrical connection can be obtained between the conductive layer 619 and the conductive layer 639. In addition, the insulating layer 618 and the insulating layer 631 can be connected with sufficient mechanical strength.

[0220] When bonding metal layers, surface activation bonding can be used. In this method, bonding is achieved by removing the oxide film and impurity adsorbed layer on the surface through sputtering or similar processes, resulting in a clean and activated surface contact. Alternatively, diffusion bonding, which uses temperature and pressure to bond the surface, can be used. Both of these methods can achieve atomic-level bonding, thus obtaining excellent electrical and mechanical bonding.

[0221] In addition, when bonding insulating layers, hydrophilic bonding methods can be used. In this method, after obtaining high flatness through polishing, the surfaces that have undergone hydrophilic treatment using oxygen plasma are brought into contact and temporarily bonded. Dehydration is then achieved through heat treatment, thereby performing formal bonding. Hydrophilic bonding also results in atomic-level bonding, thus achieving mechanically superior bonding.

[0222] In the case of bonding layer 563b and layer 563a, since the insulating layer and the metal layer are mixed together at each bonding surface, for example, a combination of surface activation bonding method and hydrophilic bonding method can be used.

[0223] For example, a method can be used where the surface is cleaned after polishing, the surface of the metal layer is treated to prevent oxidation, and then a hydrophilic treatment is performed before bonding. Alternatively, a difficult-to-oxidize metal such as Au can be used as the surface of the metal layer, followed by a hydrophilic treatment. Other bonding methods besides those described above can also be used.

[0224] The above bonding can make the circuit in layer 563b electrically connected to the components of pixel 14 in layer 563a.

[0225] <Deformation example of the stacked structure 1> Figure 21 is a deformation example of the stacked structure shown in Figure 19. The structure of the photoelectric conversion device 101 in layer 561 and part of the structure of layer 563a are different. There is also a joint plane between layer 561 and layer 563a.

[0226] Layer 561 includes photoelectric conversion device 101, insulating layers 661, 662, 664, 665 and conductive layers 685, 686.

[0227] The photoelectric conversion device 101 is a pn-junction photodiode, comprising a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Note that an example of a pn-junction photodiode formed in a silicon substrate is shown here. The photoelectric conversion device 101 is an embedded photodiode that reduces noise by suppressing dark current through a thinner p-type region (a portion of layer 565b) disposed on one side of the surface of layer 565a (the current extraction side).

[0228] Insulating layer 661, conductive layers 685, and 686 are used as bonding layers. Insulating layer 662 is used as an interlayer insulating film and a planarization film. Insulating layer 664 is used as a component release layer.

[0229] A groove for separating pixels is provided in the silicon substrate, and an insulating layer 665 is provided on the top surface of the silicon substrate and in the groove. By providing the insulating layer 665, the inflow of carriers generated in the photoelectric conversion device 101 into adjacent pixels can be suppressed. In addition, the insulating layer 665 also has the function of suppressing the intrusion of stray light. Therefore, color mixing can be suppressed by using the insulating layer 665. Alternatively, an anti-reflection film can be provided between the top surface of the silicon substrate and the insulating layer 665.

[0230] The insulating layer 664 can be formed using the LOCOS (Local Oxidation of Silicon) method. Alternatively, it can be formed using the STI (Shallow Trench Isolation) method, etc. The insulating layer 665 can be, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide resin or acrylic resin. Furthermore, the insulating layer 665 can also have a multilayer structure. Additionally, a space can be provided in a portion of the insulating layer 665. This space can also contain a gas such as air or an inert gas. Furthermore, this space can also be in a depressurized state.

[0231] Layer 565a (n-type region, equivalent to cathode) of photoelectric conversion device 101 is electrically connected to conductive layer 685. Layer 565b (p-type region, equivalent to anode) is electrically connected to conductive layer 686. Conductive layers 685 and 686 have regions embedded in insulating layer 661. In addition, the surfaces of insulating layer 661 and conductive layers 685 and 686 are planarized in a highly consistent manner.

[0232] An insulating layer 638 is formed on the insulating layer 637 in layer 563a. In addition, a conductive layer 683 electrically connected to one of the source and drain electrodes of transistor 102 and a conductive layer 684 electrically connected to conductive layer 636 are formed.

[0233] Insulating layer 638, conductive layers 683, and 684 serve as bonding layers. Conductive layers 683 and 684 have regions embedded in insulating layer 638. In addition, the surfaces of insulating layer 638 and conductive layers 683 and 684 are planarized in a highly consistent manner.

[0234] Here, conductive layers 683, 684, 685, and 686 are the same as the conductive layers 619 and 639 described above. Similarly, insulating layers 638 and 661 are the same as the insulating layers 618 and 631 described above.

[0235] Therefore, by bonding conductive layers 683 and 685, layer 565a (n-type region, equivalent to cathode) of photoelectric conversion device 101 can be electrically connected to one of the source and drain electrodes of transistor 102. Additionally, by bonding conductive layers 684 and 686, layer 565b (p-type region, equivalent to anode) of photoelectric conversion device 101 can be electrically connected to wiring 111 (see Figure 10A). Furthermore, by bonding insulating layers 638 and 661, electrical and mechanical bonding can be achieved between layer 561 and layer 563a.

[0236] Additionally, Figure 22 shows a modified example different from the above, in which the transistor 102 is disposed in layer 561. In this structure, one of the source and drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source and drain of the transistor 102 is used as node N. In this structure, the charge stored in the photoelectric conversion device 101 can be completely transferred, and a low-noise imaging device can be realized.

[0237] Here, the source and drain of the transistor 102 included in layer 561 are electrically connected to the conductive layer 692. Additionally, the gate of the transistor 104 included in layer 563 is electrically connected to the conductive layer 691. Conductive layers 691 and 692 are the same bonding layers as the aforementioned conductive layers 619 and 639.

[0238] <Layered Structure 2> Figure 23 is an example of a cross-sectional view of a laminate including layers 560, 561, 562, and 563 without a bonding plane. A Si transistor is disposed in layer 563. An OS transistor is disposed in layer 562. Note that the structures of layers 563, 561, and 560 are the same as those shown in Figure 19, so their description is omitted.

[0239] <Layer 562> Layer 562 is formed on layer 563. Layer 562 includes an OS transistor. Here, transistor 102 and transistor 105 are shown. The cross-sectional view shown in FIG23 does not show the electrical connection between the two.

[0240] Layer 562 includes insulating layers 621, 622, 623, 624, 625, 626, and 628. Additionally, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to wiring 111 (see Figure 10A).

[0241] Insulating layer 621 serves as a barrier layer. Insulating layers 622, 623, 625, 626, and 628 serve as interlayer insulating films and planarization films. Insulating layer 624 serves as a protective film.

[0242] Preferably, the barrier layer is a film capable of preventing hydrogen diffusion. In Si devices, hydrogen is required to terminate dangling bonds, but hydrogen near the OS transistor becomes one of the causes of carrier generation in the oxide semiconductor layer, thus reducing reliability. Therefore, it is preferable to provide a hydrogen barrier film between the layer forming the Si device and the layer forming the OS transistor.

[0243] As the barrier membrane, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttrium-stabilized zirconium oxide (YSZ) can be used.

[0244] The other of the source and drain terminals of transistor 105 is electrically connected to the gate of transistor 225 via a connector. Conductive layer 627 is electrically connected to wiring 111 (see Figure 10A).

[0245] One of the source and drain electrodes of transistor 102 is electrically connected to the cathode of photoelectric conversion device 101 in layer 561. Conductive layer 627 is electrically connected to the anode of photoelectric conversion device 101 in layer 561.

[0246] FIG24A shows a detailed OS transistor. The OS transistor shown in FIG24A has a self-aligned structure in which an opening is provided to the oxide semiconductor layer by providing an insulating layer on the stack of oxide semiconductor layer and conductive layer to form a source electrode 705 and a drain electrode 706.

[0247] In addition to the channel formation region 708, source region 703, and drain region 704 formed in the oxide semiconductor layer, the OS transistor may also include a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may also be provided in the opening.

[0248] As shown in Figure 24B, the OS transistor can also adopt a self-aligned structure in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.

[0249] Alternatively, as shown in FIG24C, a non-self-aligned top gate transistor with a region where the source electrode 705 or drain electrode 706 overlaps with the gate electrode 701 can be used.

[0250] The OS transistor includes a back gate 735, but may not include one. As shown in the cross-sectional view of the transistor's channel width direction in FIG24D, the back gate 735 may also be electrically connected to the front gate of the opposite transistor. As an example, FIG24D shows a cross-section of B1-B2 of the transistor shown in FIG24A; the same applies to transistors with other structures. Alternatively, a structure capable of supplying a fixed potential to the back gate 735 that is different from that to the front gate may also be used.

[0251] <Deformation example of the stacked structure 2> Figure 25 is a deformation example of the stacked structure shown in Figure 23. The structure of the photoelectric conversion device 101 in layer 561 is different from that of a part of the structure of layer 562. There is a joint plane between layer 561 and layer 562.

[0252] The photoelectric conversion device 101 in layer 561 is a pn junction type photodiode, which has the same structure as shown in Figure 21.

[0253] In layer 562, an insulating layer 648 is formed on the insulating layer 628. In addition, a conductive layer 688 electrically connected to one of the source and drain electrodes of the transistor 102 and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0254] Insulating layer 648, conductive layers 688, and 689 serve as bonding layers. Conductive layers 688 and 689 have regions embedded in insulating layer 648. Furthermore, the surfaces of insulating layer 648 and conductive layers 688 and 689 are planarized in a highly consistent manner.

[0255] Here, conductive layers 688 and 689 are the same as the conductive layers 619 and 639 described above. In addition, insulating layer 648 is the same as the insulating layers 618 and 631 described above.

[0256] Therefore, by bonding conductive layers 688 and 685, layer 565a (n-type region, equivalent to cathode) of photoelectric conversion device 101 can be electrically connected to one of the source and drain electrodes of transistor 102. Furthermore, by bonding conductive layers 689 and 686, layer 565b (p-type region, equivalent to anode) of photoelectric conversion device 101 can be electrically connected to wiring 111 (see Figure 10A). Additionally, by bonding insulating layers 648 and 661, electrical and mechanical bonding can be achieved between layers 561 and 562.

[0257] When multiple Si devices are stacked, multiple polishing and bonding processes are required. Therefore, it has problems such as a large number of processes, the need for special equipment, low yield, and high manufacturing cost. Since OS transistors can be formed by stacking them on a semiconductor substrate on which the devices are formed, the bonding process can be reduced.

[0258] Alternatively, the structure shown in FIG22, in which a transistor 102 is provided in layer 561, can also be used in the above structure.

[0259] Additionally, the memory unit 150 may be disposed in layer 562, for example. FIG26 shows a structure in which transistors 102, 105, etc., of the pixel circuit components and transistors 273, etc., of the memory unit 150 components are disposed on the same surface of layer 562.

[0260] Additionally, Figure 27 shows the structure of transistors 102, 104, 105, etc., which are components of pixel circuits stacked in layer 562 with overlapping regions, and transistors 272, 273, etc., which are components of memory unit 150. By adopting this structure, the circuit area can be reduced, and a high-performance, compact imaging device can be formed. In addition, the wiring length of the electrical connection stacked components can be shortened, thus enabling high-speed and low-power operation.

[0261] Alternatively, the structure shown in FIG22, in which the transistor 102 is disposed in layer 561, can also be used in the structures shown in FIG26 and FIG27. Additionally, the structure of the photoelectric conversion device 101 shown in FIG23 can also be used.

[0262] <Packaging and Module> Figure 29A is a perspective view of the package housing the image sensor chip. The package is a CSP (chip-scale package) and includes a bare image sensor chip 450, a glass cover 440, and an adhesive 430 for bonding them together.

[0263] The electrode pads 425 disposed on the outer side of the pixel array 455 are electrically connected to the back electrode 415 via through electrodes 420. The electrode pads 425 are electrically connected to the circuitry constituting the image sensor via wiring or wires. The bare die 450 may also be a stacked die formed by stacking various functional circuits.

[0264] Figure 29 illustrates a BGA (Ball Grid Array) with a structure in which bumps 410 are formed on the back electrode 415 using solder balls. Note that it is not limited to BGA; LGA (Ground Grid Array) or PGA (Pin Grid Array) can also be used. Alternatively, a package formed by mounting the bare die 450 into a QFN (Quad Flat Package) or QFP (Quad Flat Package) can also be used.

[0265] Additionally, Figure 29B is a perspective view of the top side of a camera module assembled from an image sensor chip and lenses. This camera module, in the structure shown in Figure 29A, includes a lens cover 460 and multiple lenses 470, etc. Furthermore, as needed, an optical filter 480 that absorbs light of a specific wavelength is provided between the lens 470 and the glass cover plate 440. For example, in the case of an image sensor primarily used for visible light imaging, an infrared cut-off filter or the like can be used as the optical filter 480.

[0266] By housing the image sensor chip in the package described above, it can be easily installed on printed circuit boards and other devices, and the image sensor chip can be installed in various semiconductor devices and electronic devices.

[0267] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0268] Embodiment 4 Examples of electronic devices that can use a camera device according to an embodiment of the present invention include display devices, personal computers, image memory devices or image playback devices with storage media, mobile phones, portable game consoles, portable data terminals, e-book readers, shooting devices such as video cameras or digital still cameras, head-mounted displays, navigation systems, audio playback devices (car audio systems, digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. Figures 30A to 30F show specific examples of these electronic devices.

[0269] Figure 30A shows an example of a mobile phone, which includes a housing 981, a display unit 982, operation buttons 983, an external connection interface 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor in the display unit 982. Various operations such as making calls or inputting text can be performed by touching the display unit 982 with a finger or stylus. Furthermore, a camera device and its operating method according to one embodiment of the present invention can also be used in this mobile phone.

[0270] Figure 30B shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Information can be input and output via the touch panel function of the display unit 912. Furthermore, text can be recognized from the image acquired by the camera 919, and the text can be output verbally using the speaker 913. The camera device and its operating method according to one embodiment of the present invention can be used in this portable data terminal.

[0271] Figure 30C shows a surveillance camera, which includes a bracket 951, a camera unit 952, and a protective cover 953, etc. A rotating mechanism is provided in the camera unit 952, allowing it to capture images of the surrounding area by being mounted on the ceiling. The camera device and its operating method according to one embodiment of the present invention can be used in the components of this camera unit for acquiring images. Note that "surveillance camera" is a general term and is not limited to its application. For example, a device having the function of a surveillance camera is called a camera or video camera.

[0272] Figure 30D shows a dashcam, which includes a frame 941, a camera 942, an operation button 943, and a mounting bracket 944. By mounting the dashcam on the windshield or similar surface of a car using the mounting bracket 944, it can record the view ahead while driving. Note that a display panel for displaying the recorded images is provided on the back (not shown). The camera device and its operating method according to one embodiment of the present invention can be used for the camera 942.

[0273] Figure 30E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting part 967, and a lens 965, etc. The imaging device and its operating method according to one embodiment of the present invention can be used in this digital camera.

[0274] Figure 30F shows a watch-type information terminal, which includes a display unit 932, a housing / wristband 933, and a camera 939. The display unit 932 may also include a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and suitable for wearing on the body. A camera device and its operating method according to one embodiment of the present invention can be used in this information terminal.

[0275] Figure 31A shows an example of a mobile drone, which includes a frame 921, arms 922, rotor 923, propeller 924, camera 925, and battery 926, and has autonomous flight and hovering capabilities. The camera device and its operating method according to one embodiment of the present invention can be used for the camera 925.

[0276] Figure 31B is an exterior view of a car showing an example of a moving body. The car 890 includes multiple cameras 891, etc., which can acquire information about the front, rear, left, right, and top of the car 890. The camera device and its operating method according to one embodiment of the present invention can be used for the camera 891. In addition, the car 890 includes various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar. The car 890 analyzes the images of multiple camera directions 892 acquired by the camera 891 to determine the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and can perform autonomous driving. In addition, the camera device and its operating method according to one embodiment of the present invention can be used in systems for navigation, hazard prediction, etc.

[0277] In a camera device according to one embodiment of the present invention, by performing computational processing on the obtained image data such as neural networks, for example, image high resolution, image noise reduction, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration of lensless image sensors, position alignment, text recognition, reduction of reflected glare, etc.

[0278] Note that, above, "car" can be any of the following: internal combustion engine cars, electric cars, hydrogen fuel cell cars, etc. Furthermore, the mobile body is not limited to cars. For example, trams, monorails, ships, and flying objects (helicopters, drones, airplanes, rockets) can also be cited as mobile bodies. The computer of one embodiment of the present invention can be used on these mobile bodies to provide a system utilizing artificial intelligence. [Simplified Explanation of the Diagram]

[0026] [Figure 1] is a diagram illustrating the camera device. [Figures 2A] to [Figure 2C] are diagrams illustrating the pixel section. [Figure 3] is a diagram illustrating the block. [Figure 4] is a diagram illustrating the block. [Figure 5] is a diagram illustrating the block. [Figure 6A] is a diagram illustrating the product summation circuit, and [Figure 6B] is a diagram illustrating the binarization circuit. [Figure 7] is a diagram illustrating the block. [Figure 8] is a diagram illustrating the block and the readout circuit. [Figure 9] is a timing diagram illustrating the operation of the readout circuit. [Figures 10A] to [Figure 10C] are diagrams illustrating the pixel circuit. [Figure 11A] is a diagram illustrating the memory circuit, and [Figures 11B] and [Figure 11C] are diagrams illustrating the memory cell. [Figures 12A] and [Figure 12B] are diagrams illustrating the layout of the pixel circuit. [Figure 13] is a diagram illustrating the operation of reading data from the block. [Figure 14] is a diagram illustrating the operation of allocating data to the block. [Figure 15A] is a diagram illustrating the operation of reading data from the block. [Figure 15B] is a diagram illustrating circuit 25. [Figure 16A] is a diagram illustrating the readout circuit. [Figure 16B] is a timing diagram illustrating the operation of the readout circuit. [Figures 17A] to [Figure 17D] are diagrams illustrating the pixel structure of the imaging device. [Figures 18A] to [Figure 18C] are diagrams illustrating the structure of the photoelectric conversion device. [Figure 19] is a cross-sectional view illustrating the pixel. [Figures 20A] to [Figure 20C] are diagrams illustrating the Si transistor. [Figure 21] is a cross-sectional view illustrating the pixel. [Figure 22] is a cross-sectional view illustrating the pixel. [Figure 23] is a cross-sectional view illustrating the pixel. [Figures 24A] to [Figure 24D] are diagrams illustrating the OS transistor. [Figure 25] is a cross-sectional view illustrating the pixel. [Figure 26] is a cross-sectional view illustrating the pixel. [Figure 27] is a cross-sectional view illustrating the pixel. Figures 28A to 28C are perspective views (cross-sectional views) illustrating pixels. Figure 29A is a diagram illustrating the package housing the camera device, and Figure 29B is a diagram illustrating the module housing the camera device. Figures 30A to 30F are diagrams illustrating the electronic device. Figures 31A and 31B are diagrams illustrating the moving body.

Claims

1. A camera device, comprising: The first layer contains pixel circuitry; The first layer includes a second layer containing a product summation circuit and a binarization circuit. The second layer includes a region overlapping with the third layer. The pixel circuit includes a first transistor and a second transistor. The first layer further includes: a first metal oxide layer containing a channel forming region of the first transistor; a second metal oxide layer containing a channel forming region of the second transistor; a first gate wiring containing a region serving as a gate electrode of the first transistor; and a second gate wiring containing a region serving as a gate electrode of the second transistor. In a top view, each of the first metal oxide layer and the second metal oxide layer extends in a first direction, and in a top view, each of the first gate wiring and the second gate wiring extends in a second direction.

2. The imaging device according to claim 1, wherein the first layer further includes a memory circuit, and wherein the memory circuit includes a transistor and contains a metal oxide in its channel forming region.

3. The imaging device according to claim 1 further includes a third layer, wherein the third layer includes memory circuitry, and wherein the memory circuitry includes a transistor, and wherein a metal oxide is included in its channel forming region.

4. The imaging device according to claim 1, wherein each of the product circuit and the binarization circuit includes a transistor and silicon is included in its channel forming region.

5. The camera device according to claim 1, wherein the pixel circuit is electrically connected to the binarization circuit.

6. The camera device according to claim 1, wherein the product summation circuit is electrically connected to the binarization circuit.

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