Methods for controlling non-volatile memory in the memory system

Abstract

This invention provides a method for controlling non-volatile memory in a memory system. A first memory system stores first data in a first non-volatile memory. A second memory system stores second data in a second non-volatile memory. A host sends first updated data (updated from the first data) to the first memory system and second updated data (updated from the second data) to the second memory system. The first memory system generates first XOR data by performing at least an XOR operation on the first data and the first updated data, and sends it to the second memory system. The second memory system generates second XOR data by performing an XOR operation on the second data, the second updated data, and the first XOR data, and sends it to a third memory system.

Description

Technical Field

[0001] [Related Applications] This application is based on Japanese Patent Application No. 2023-007397 (filed on January 20, 2023) and enjoys priority thereto. This application incorporates the entire contents of the basic application by reference to it.

[0002] The present invention relates to an information processing system including a memory system having non-volatile memory. Prior Technology

[0003] In recent years, memory systems with non-volatile memory and information processing systems with a host and multiple memory systems have become widely used. As one type of such memory system, the solid-state drive (SSD) with NAND flash memory is known. SSDs are used as the main storage in various computing devices.

[0004] To improve the resilience of information processing systems, Redundant Arrays of Independent (Inexpensive) Disks (RAID) are sometimes used. RAID is a technique that uses multiple memory systems to improve the redundancy and access performance of stored data. For example, in RAID-5, the data to be written and the parity (error correcting code: ECC) for that data are distributed across multiple memory systems. Therefore, even if a memory system storing some data fails, the data stored in the failed memory system can be recovered using other data and parity stored in other memory systems.

[0005] When updating data stored in multiple memory systems that constitute a RAID array, or when recovering data stored in a failed memory system and rebuilding the RAID, the load on the host connected to multiple memory systems can sometimes increase. Additionally, in such cases, data transfers to specific memory systems may occur in concentrated bursts. Due to insufficient bandwidth on the bus to the specific memory system, the overall performance of the information processing system may be degraded. Summary of the Invention

[0006] One embodiment provides a method for controlling non-volatile memory in a memory system, which can improve overall performance while reducing the load applied to the host computer.

[0007] According to an embodiment, a method for controlling non-volatile memory in a memory system includes: communicating with a host; communicating with one or more external memory systems; storing first data in the non-volatile memory; receiving a first request from the host and first updated data updated from the first data; receiving first mutually exclusive OR data from the first memory system of one of the one or more external memory systems, wherein the first mutually exclusive OR data is generated in the first memory system by performing a mutually exclusive OR operation on at least second data stored in the first memory system and second updated data updated from the second data; and in response to receiving the first request, generating second mutually exclusive OR data by performing a mutually exclusive OR operation on the first data, the first updated data, and the first mutually exclusive OR data, sending a first response corresponding to the first request to the host, and sending the second mutually exclusive OR data to the second memory system of another of the one or more external memory systems.

[0008] According to an embodiment, the information processing system includes a host and multiple memory systems, each including a controller and non-volatile memory. The controller of a first memory system within the multiple memory systems stores first data in the first non-volatile memory. The controller of a second memory system within the multiple memory systems stores second data in the second non-volatile memory. The first data and the second data constitute part of an error correction code frame. When updating the first data and the second data, the host sends first updated data (updated from the first data) to the first memory system and sends second updated data (updated from the second data) to the second memory system. The controller of the first memory system generates a first mutually exclusive OR data by performing a mutual exclusion OR operation on at least the first data and the first updated data, and sends the first mutually exclusive OR data to the second memory system. The controller of the second memory system generates a second mutually exclusive OR data by performing a mutual exclusion OR operation on the second data, the second updated data, and the first mutually exclusive OR data, and sends the second mutually exclusive OR data to a third memory system within the multiple memory systems. Simple Explanation of the Diagram

[0009] Figure 1 is a block diagram illustrating a structural example of an information processing system in a first embodiment. Figure 2 is a block diagram showing a structural example of the memory system included in the information processing system of the first embodiment. Figure 3 is a diagram illustrating an example of a sequential write operation in an information processing system of the first embodiment. Figure 4 is a diagram illustrating the first update operation in the information processing system of the comparative example. Figure 5 is a diagram illustrating the second update operation in the information processing system of the comparative example. Figure 6 is a diagram illustrating the third update operation in the information processing system of the comparative example. Figure 7 is a diagram illustrating an example of the fourth update operation in the information processing system of the first embodiment. Figure 8 is a sequence diagram illustrating a specific example of the fourth update operation in the information processing system of the first embodiment. Figure 9 is a diagram illustrating a specific example of operation in the first memory system within the information processing system of the first embodiment. Figure 10 is a diagram illustrating an example of the fifth update operation in the information processing system of the first embodiment. Figure 11 is a sequence diagram illustrating a specific example of the fifth update operation in the information processing system of the first embodiment. Figure 12 is a diagram illustrating an example of a first reconstruction operation in an information processing system of the second embodiment. Figure 13 is a sequence diagram illustrating a specific example of the first reconstruction operation in the information processing system of the second embodiment. Figure 14 is a diagram illustrating an example of a second reconstruction operation in an information processing system of a second embodiment. Figure 15 is a sequence diagram illustrating a specific example of a second reconstruction operation in an information processing system of the second embodiment. Figure 16 is a diagram illustrating a specific example of the operation in the first memory system of the information processing system in the second embodiment. Implementation

[0010] The following describes the implementation with reference to the diagram.

[0011] (First Implementation Form) First, the structure of the information processing system 1 in the first embodiment will be described with reference to FIG1. ​​The information processing system 1 includes a host device 2, multiple memory systems 3, and a switch 4.

[0012] Host device 2 can be a storage server that stores large amounts of diverse data across multiple memory systems 3, or it can be a server or a personal computer. Hereinafter, host device 2 will also be referred to as host 2.

[0013] Multiple memory systems 3 are memory systems that constitute a Redundant Array of Independent Disks (RAID). The following example illustrates the case where multiple memory systems 3 constitute RAID-5. Furthermore, Figure 1 shows the case where the multiple memory systems 3 are four memory systems 3-1, 3-2, 3-3, and 3-4; however, the multiple memory systems 3 can be any number of memory systems, such as three or more. Hereinafter, one memory system 3 among the multiple memory systems 3 that is not specifically designated will also be referred to as memory system 3.

[0014] Memory system 3 is a semiconductor storage device configured to write data to and read data from non-volatile memory, such as NAND flash memory. Memory system 3 is also referred to as a storage device. Memory system 3 is implemented, for example, in the form of a solid-state drive (SSD).

[0015] The memory system 3 can be used as storage for the host 2. The memory system 3 can be built into the host 2 or connected to the host 2 via cable or network.

[0016] Switch 4 is a device that connects host 2 and multiple memory systems 3 to each other. Switch 4 includes control circuitry that controls communication between host 2 and multiple memory systems 3.

[0017] The interface used to connect host 2 to multiple memory systems 3 via switch 4 conforms to standards such as PCI Express™ (Peripheral Component Interconnect Express, PCIe™) and NVM Express™ (Non-volatile memory express, NVME™). Hereinafter, switch 4 will also be referred to as PCIe switch 4.

[0018] The following describes the structural examples of the host 2 and the memory system 3. (Example of host 2's structure)

[0019] The host 2 includes, for example, a central processing unit (CPU) 21 and random access memory (RAM) 22.

[0020] CPU 21 is, for example, at least one processor. CPU 21 controls the operation of various components within host 2. Furthermore, CPU 21 controls the communication between host 2 and memory system 3. CPU 21 sends various commands to memory system 3. Commands sent to memory system 3 include, for example, read commands, write commands, XOR commands, and XOR / write commands. An XOR command requests an XOR operation on two or more data. An XOR / write command requests an XOR operation on two or more data and writes the data. Furthermore, a control circuit (interface) can be provided in host 2 to control the communication between host 2 and memory system 3. CPU 21 communicates with memory system 3 through this control circuit.

[0021] RAM 22 is volatile memory. RAM 22 is implemented, for example, as dynamic random access memory (DRAM) or static random access memory (SRAM). The memory area of ​​RAM 22 is allocated, for example, as a buffer area for temporary data storage. The buffer area stores, for example, data to be written to memory system 3 and data read from memory system 3.

[0022] (Example of the structure of memory system 3) Figure 2 is a block diagram showing a structural example of memory system 3.

[0023] The memory system 3 includes, for example, non-volatile memory 5, DRAM 6, and a controller 7.

[0024] Non-volatile memory 5 is, for example, NAND flash memory. Hereinafter, non-volatile memory 5 will be referred to as NAND flash memory 5.

[0025] NAND flash memory 5 includes multiple blocks B0, B1, B2, ..., Bm-1. Each block B0, B1, B2, ..., Bm-1 includes multiple pages P0, ..., Pn-1. The block functions as the smallest unit for data erasure operations. A block is sometimes also called an "erasure block" or a "physical block." Each page P0, ..., Pn-1 includes multiple memory cells connected to a single word line. The page functions as the unit for data write and read operations. Furthermore, a word line can also function as the unit for data write and read operations.

[0026] There is an upper limit to the number of programming / erase cycles (P / E cycles) for each block, called the maximum number of P / E cycles. One P / E cycle for a block includes: a data erasure operation to put all memory cells in the block into an erasure state, and a data write operation (programmed operation) to write data to each page of the block.

[0027] DRAM 6 is volatile memory. In RAMs such as DRAM 6, there are storage areas for firmware (FW), cache areas for logical-physical address translation tables 31, and buffer areas for temporary memory data.

[0028] FW is a program used to control the operation of controller 7. For example, FW loads data from NAND flash memory 5 into DRAM 6.

[0029] The Logical Physical Address Translation Table 31 manages the mapping between logical addresses and physical addresses of NAND flash memory. Logical addresses are used by the host 2 to assign addresses to the memory system 3. For example, a logical block address (LBA) is a logical address.

[0030] The controller 7 functions as a memory controller that controls the NAND flash memory 5.

[0031] The controller 7 can also function as a Flash Translation Layer (FTL), which is configured to perform data management and block management of the NAND flash memory 5. The data management performed by the FTL includes: (1) management of mapping information representing the correspondence between logical addresses and physical addresses of the NAND flash memory 5; and (2) processing to hide the differences between page-based data read / write operations and block-based data erasure operations. Block management includes the management of bad blocks, wear averaging, and garbage collection.

[0032] The controller 7 uses a logical-to-physical address translation table 31 to manage the mapping between logical addresses and physical addresses. The controller 7 uses the logical-to-physical address translation table 31 to manage the mapping between logical addresses and physical addresses in specific management units. The physical address corresponding to a logical address represents the physical memory location within the NAND flash memory 5 where data has been written to that logical address. The controller 7 uses the logical-to-physical address translation table 31 to manage the memory regions of the NAND flash memory 5 into multiple logically divided memory regions. Each of these multiple memory regions corresponds to a multiple logical address. That is, each of the multiple memory regions is determined by a single logical address. The logical-to-physical address translation table 31 can be loaded from the NAND flash memory 5 into the DRAM 6 when the memory system 3 starts up.

[0033] Writing a page of data can only be performed once per P / E cycle. Therefore, controller 7 writes the updated data corresponding to a certain logical address to another physical memory location, instead of the physical memory location where the previous data was stored. Then, controller 7 updates the logical physical address translation table 31 in such a way that the logical address is associated with the other physical memory location, thereby invalidating the previous data. Data referenced from the logical physical address translation table 31 (i.e., data associated with a logical address) is called valid data. Data not associated with any logical address in the logical physical address translation table 31 is called invalid data. Valid data is data that may be read from host 2 in the future. Invalid data is data that is no longer possible to be read from host 2.

[0034] The controller 7 includes, for example, a host interface (host I / F) 11, a NAND interface (NAND I / F) 12, a DRAM interface (DRAM I / F) 13, and a CPU 14. These host I / F 11, NAND I / F 12, DRAM I / F 13, and CPU 14 are connected, for example, via bus 10.

[0035] The host I / F 11 functions as a circuit for receiving various commands and data from the host 2 via the PCIe switch 4. Additionally, the host I / F 11 functions as a circuit for sending responses to commands and data to the host 2 via the PCIe switch 4. Furthermore, the host I / F 11 can also function as a circuit for receiving various commands and data from other memory systems 3 via the PCIe switch 4, and for sending responses to commands to other memory systems 3 via the PCIe switch 4.

[0036] NAND I / F 12 electrically connects the controller 7 to the NAND flash memory 5. NAND I / F 12 corresponds to interface standards such as Toggle DDR (Toggle Double Data Rate) and Open NAND Flash Interface (ONFI).

[0037] NAND I / F 12 functions as a NAND control circuit that controls the NAND flash memory 5. NAND I / F 12 can be connected to multiple memory chips within the NAND flash memory 5 via multiple channels. By driving multiple memory chips in parallel, the access bandwidth to the NAND flash memory 5 can be widened.

[0038] DRAM I / F 13 functions as a DRAM control circuit, which is configured to control access to DRAM 6.

[0039] CPU 14 is a processor configured to control host I / F 11, NAND I / F 12, and DRAM I / F 13. CPU 14 performs various processes by executing a file system (FW) loaded from NAND flash memory 5 into DRAM 6. The FW is a control program that includes a set of commands for causing CPU 14 to perform various processes. CPU 14 can execute command processing, etc., to process various commands from host 2. The operation of CPU 14 is controlled by the FW executed by CPU 14.

[0040] The functions of each part within controller 7 can be implemented by dedicated hardware within controller 7, or by executing software via CPU 14.

[0041] CPU 14 functions, for example, as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144. CPU 14 functions as each of these units, for example, by executing a file system (FW).

[0042] Command receiving unit 141 receives commands sent from host 2 or other memory system 3. Based on the received commands, command receiving unit 141 controls read processing unit 142, XOR processing unit 143, and write processing unit 144. Specifically, command receiving unit 141 instructs read processing unit 142 to read data from NAND flash memory 5. Command receiving unit 141 instructs XOR processing unit 143 to perform XOR operations on two or more data values. Command receiving unit 141 instructs write processing unit 144 to write data to NAND flash memory 5. Command receiving unit 141 sends a response to the command to host 2 or memory system 3 that sent the command. Additionally, command receiving unit 141 can also send commands and data to other memory systems 3.

[0043] The read processing unit 142 reads data from the NAND flash memory 5 according to the instructions given by the command receiving unit 141. The XOR processing unit 143 performs XOR operations on two or more data according to the instructions given by the command receiving unit 141. The write processing unit 144 writes data into the NAND flash memory 5 according to the instructions given by the command receiving unit 141.

[0044] Examples of specific operations performed by the command receiving unit 141, the read processing unit 142, the XOR processing unit 143, and the write processing unit 144 will be described later with reference to FIG9.

[0045] Here, the sequential write operation in information processing system 1 is explained.

[0046] Figure 3 illustrates an example of a sequential write operation in information processing system 1. A sequential write operation is the operation in which host 2 continuously writes data to all four memory systems 3-1, 3-2, 3-3, and 3-4.

[0047] The DRAM 22 memory of host 2 should be written into the user data 51D of memory system 3.

[0048] When the amount of user data 51D to be written to memory system 3 reaches a certain unit, CPU 21 of host 2 generates an error correction code (ECC) for the user data 51D to be written. The specific unit is, for example, equivalent to the total amount of data that can be written in a single data write operation to each of the three memory systems 3. The amount of data that can be written in a single data write operation to one memory system 3 is also called a write unit. ECC is used to correct user data that has been erroneous. ECC is, for example, XOR parity. The following example illustrates the case where ECC is XOR parity. Furthermore, XOR parity will be simply referred to as parity.

[0049] Specifically, CPU 21 acquires user data 511, 512, and 513, which are divided into three write units of user data 51D (i.e., first user data 511, second user data 512, and third user data 513). Then, CPU 21 generates a parity 51P by performing an XOR operation on the three user data 511, 512, and 513. CPU 21 stores the generated parity 51P, for example, in DRAM 22. The three user data 511, 512, and 513 have the same data length as the parity 51P. The three user data 511, 512, and 513, together with the parity 51P, constitute an ECC frame 51E. An ECC frame is a data unit that includes the parity and the user data protected by the parity. That is, the three user data 511, 512, and 513 are protected by the parity 51P. Parity 51P is updated in accordance with updating at least one of the three user data 511, 512, and 513.

[0050] Next, CPU 21 writes the three user data 511, 512, and 513, and the parity 51P to the four memory systems 3-1, 3-2, 3-3, and 3-4 respectively via PCIe switch 4.

[0051] Specifically, for example, CPU 21 sends a write command requesting to write first user data 511 to first memory system 3-1 (1 in Figure 3). CPU 21 sends a write command requesting to write second user data 512 to second memory system 3-2 (2 in Figure 3). CPU 21 sends a write command requesting to write third user data 513 to third memory system 3-3 (3 in Figure 3). CPU 21 sends a write command requesting to write parity 51P to fourth memory system 3-4 (4 in Figure 3). Furthermore, the CPU 21 determines, for example, which of the four memory systems 3-1, 3-2, 3-3, and 3-4 to write the first user data 511, the second user data 512, the third user data 513, and the parity 51P to, according to specific rules. The destination of the writes of the first user data 511, the second user data 512, the third user data 513, and the parity 51P is not limited to the examples described. For example, CPU 21 can also send write commands in the following manner: first user data 511 is written to second memory system 3-2, second user data 512 is written to third memory system 3-3, third user data 513 is written to fourth memory system 3-4, and parity 51P is written to first memory system 3-1.

[0052] In response to receiving a write command from the host 2, the first memory system 3-1 receives the first user data 511 stored in the DRAM 22 of the host 2 via the PCIe switch 4. Then, the first memory system 3-1 writes the first user data 511 into the NAND flash memory 5 within the first memory system 3-1.

[0053] In response to receiving a write command from the host 2, the second memory system 3-2 receives the second user data 512 stored in the DRAM 22 of the host 2 via the PCIe switch 4. Then, the second memory system 3-2 writes the second user data 512 into the NAND flash memory 5 within the second memory system 3-2.

[0054] In response to receiving a write command from host 2, third memory system 3-3 receives third user data 513 stored in DRAM 22 of host 2 via PCIe switch 4. Then, third memory system 3-3 writes the third user data 513 into NAND flash memory 5 within third memory system 3-3.

[0055] In response to receiving a write command from host 2, the fourth memory system 3-4 receives the parity 51P stored in DRAM 22 of host 2 via PCIe switch 4. Then, the fourth memory system 3-4 writes the parity 51P into NAND flash memory 5 within the fourth memory system 3-4.

[0056] Through the sequential write operations described above, in information processing system 1, the first user data 511, the second user data 512, the third user data 513, and the parity 51P constituting an ECC frame 51E are distributed and written to four memory systems 3-1, 3-2, 3-3, and 3-4. Therefore, for example, even if any one of the four memory systems 3-1, 3-2, 3-3, and 3-4 fails, the data stored in the failed memory system 3 can be recovered using the data stored in the other memory systems 3.

[0057] Furthermore, during the sequential write operation, four input / output (I / O) operations are performed between host 2 and memory system 3. These four I / O operations pertain to four write operations from host 2 to memory system 3. The number of I / O operations is a metric related to the bus bandwidth usage determined by the communication between host 2 and memory system 3 via PCIe switch 4. Additionally, the parity 51P is generated using the resources of host 2 (more specifically, CPU 21 and DRAM 22).

[0058] Next, the operation for updating a portion of the user data 51D written to the memory system 3 will be described. The operation for updating a portion of the user data 51D written to the memory system 3 is referred to as an update operation. The update operation includes a random write operation.

[0059] First, the update operation in the comparative example information processing system 1A will be described with reference to Figures 4-6. The comparative example information processing system 1A includes a host 2A, multiple memory systems 3A, and a PCIe switch 4A. The host 2A and the multiple memory systems 3A can communicate with each other via the PCIe switch 4A. The host 2A includes a CPU 21A and a DRAM 22A. The multiple memory systems 3A each include NAND flash memory. The multiple memory systems 3A form a RAID-5 configuration. The multiple memory systems 3A include four memory systems 3-1A, 3-2A, 3-3A, and 3-4A. Here, it is envisioned that, through the same operation as the sequential write operation described with reference to Figure 3, first user data 511, second user data 512, third user data 513, and parity 51P are stored in the four memory systems 3-1A, 3-2A, 3-3A, and 3-4A, respectively.

[0060] Figure 4 illustrates the first update operation in the information processing system 1A of the comparative example. The first update operation is used to update the first user data 511 stored in the first memory system 3-1A to the first updated user data 511-U.

[0061] The DRAM 22A memory of host 2A has the first updated user data 511-U.

[0062] The CPU 21A of the host 2A sends a read command requesting to read the first user data 511 to the first memory system 3-1A (1 in Figure 4).

[0063] In response to a read command from host 2A, first memory system 3-1A reads first user data 511 from NAND flash memory within first memory system 3-1A. Then, first memory system 3-1A sends first user data 511 to host 2A.

[0064] The CPU 21A of host 2A stores the first user data 511 received from the first memory system 3-1A in DRAM 22A. The CPU 21A generates first XOR data 521 by performing an XOR operation between the first user data 511 and the first updated user data 511-U. The first XOR data 521 is stored in DRAM 22A, for example. Then, the CPU 21A sends a write command requesting to write the first updated user data 511-U to the first memory system 3-1A (2 in Figure 4).

[0065] In response to receiving a write command from the host 2A, the first memory system 3-1A receives the first updated user data 511-U stored in the DRAM 22A of the host 2A. Then, the first memory system 3-1A writes the first updated user data 511-U into the NAND flash memory within the first memory system 3-1A.

[0066] Next, the CPU 21A of host 2A sends a read command requesting to read parity 51P to the fourth memory system 3-4A (3 in Figure 4).

[0067] In response to a read command from host 2A, fourth memory system 3-4A reads parity 51P from the NAND flash memory within fourth memory system 3-4A. Then, fourth memory system 3-4A sends parity 51P to host 2A.

[0068] The CPU 21A of host 2A stores the parity 51P received from the fourth memory system 3-4A in DRAM 22A. The CPU 21A generates an updated parity 51P-U by performing an XOR operation between the first XOR data 521 stored in DRAM 22A and the parity 51P. The updated parity 51P-U is the parity that changes in response to an update from the first user data 511 to the first updated user data 511-U. That is, the first updated user data 511-U, the second user data 512, the third user data 513, and the updated parity 51P-U constitute an ECC frame. The CPU 21A sends a write command requesting to write the updated parity 51P-U to the fourth memory system 3-4A (4 in Figure 4).

[0069] In response to receiving a write command from host 2A, the fourth memory system 3-4A receives the updated parity 51P-U stored in DRAM 22A of host 2A. Then, the fourth memory system 3-4A writes the updated parity 51P-U into the NAND flash memory within the fourth memory system 3-4A.

[0070] Through the first update operation described above, in the information processing system 1A, the first user data 511 stored in the first memory system 3-1A is updated to the first updated user data 511-U, and the parity 51P stored in the fourth memory system 3-4A is updated to the updated parity 51P-U.

[0071] In the first update operation, four I / O operations are performed from host 2A to memory system 3A. These four I / O operations include two write I / O operations from host 2A to memory system 3A, and two read-related I / O operations (read I / Os). Additionally, an update parity 51P-U is generated using the resources of host 2A (more specifically, CPU 21A and DRAM 22A).

[0072] Figure 5 illustrates the second update operation in the comparative example information processing system 1A. The second update operation is used to update the first user data 511 stored in the first memory system 3-1A to the first updated user data 511-U while reducing the resources of the host 2A being used.

[0073] The DRAM 22A memory of host 2A has the first updated user data 511-U.

[0074] The CPU 21A of host 2A sends the command (XOR / write command) requesting XOR operation and writing the first updated user data 511-U to the first memory system 3-1A (1 in Figure 5).

[0075] In response to receiving an XOR / write command from host 2A, the first memory system 3-1A receives the first updated user data 511-U from host 2A. Additionally, the first memory system 3-1A reads the first user data 511 from its NAND flash memory. The first memory system 3-1A generates first XOR data 521 by performing an XOR operation between the first user data 511 and the first updated user data 511-U. The first XOR data 521 is stored in the internal buffer 61-1A of the first memory system 3-1A. Then, the first memory system 3-1A writes the first updated user data 511-U into its NAND flash memory.

[0076] Next, CPU 21A of host 2A sends an XOR / write command requesting the XOR operation and updating the parity 51P-U to the fourth memory system 3-4A (2 in Figure 5).

[0077] In response to receiving an XOR / write command from host 2A, the fourth memory system 3-4A receives first XOR data 521 from the first memory system 3-1A. The fourth memory system 3-4A reads parity 51P from its NAND flash memory. The fourth memory system 3-4A generates an updated parity 51P-U by performing an XOR operation between the first XOR data 521 and the parity 51P. Then, the fourth memory system 3-4A writes the updated parity 51P-U into its NAND flash memory.

[0078] Through the second update operation described above, in the information processing system 1A, the first user data 511 stored in the first memory system 3-1A is updated to the first updated user data 511-U, and the parity 51P stored in the fourth memory system 3-4A is updated to the updated parity 51P-U.

[0079] In the second update operation, two I / O operations are performed from host 2A to memory system 3A. These two I / O operations are two write I / O operations from host 2A to memory system 3A. No read I / O operations are generated in the second update operation. Therefore, the number of read I / O operations is reduced in the second update operation compared to the first update operation described with reference to FIG4. Furthermore, the update parity 51P-U is generated using the resources of memory system 3A. Therefore, the load applied to host 2A is reduced in the second update operation. That is, the update operation from host 2A to memory system 3A is offloaded.

[0080] Figure 6 illustrates the third update operation in the comparative example information processing system 1A. The third update operation is used to update the first user data 511 stored in the first memory system 3-1A to first updated user data 511-U, and the third user data 513 stored in the third memory system 3-3A to third updated user data 513-U, while reducing the resources of the host 2A. That is, in the third update operation, the two user data sets 511 and 513 stored in the two memory systems 3-1A and 3-3A respectively are updated.

[0081] The DRAM 22A memory of host 2A has first updated user data 511-U and third updated user data 513-U.

[0082] The CPU 21A of the host 2A sends an XOR / write command (first XOR / write command) requesting an XOR operation and writing the first updated user data 511-U to the first memory system 3-1A (1-1 in Figure 6). In addition, the CPU 21A sends an XOR / write command (second XOR / write command) requesting an XOR operation and writing the third updated user data 513-U to the third memory system 3-3A (1-2 in Figure 6).

[0083] In response to receiving a first XOR / write command from host 2A, the first memory system 3-1A receives first updated user data 511-U from host 2A. The first memory system 3-1A reads the first user data 511 from its NAND flash memory. The first memory system 3-1A generates first XOR data 521 by performing an XOR operation between the first user data 511 and the first updated user data 511-U. The first XOR data 521 is stored in the internal buffer 61-1A of the first memory system 3-1A. Then, the first memory system 3-1A writes the first updated user data 511-U into its NAND flash memory.

[0084] Additionally, in response to receiving a second XOR / write command from host 2A, the third memory system 3-3A receives third updated user data 513-U from host 2A. The third memory system 3-3A reads the third user data 513 from its NAND flash memory. The third memory system 3-3A generates second XOR data 522 by performing an XOR operation between the third user data 513 and the third updated user data 513-U. The second XOR data 522 is stored in the internal buffer 61-3A of the third memory system 3-3A. Then, the third memory system 3-3A writes the third updated user data 513-U into its NAND flash memory.

[0085] Next, CPU 21A of host 2A sends an XOR / write command (third XOR / write command) requesting the XOR operation and the writing of the pre-XOR data 51P-P (described later) to the fourth memory system 3-4A (2-1 in Figure 6). Then, CPU 21A of host 2A sends an XOR / write command (fourth XOR / write command) requesting the XOR operation and the writing of the parity update 51P-U to the fourth memory system 3-4A (2-2 in Figure 6). Host 2A may send the fourth XOR / write command to the fourth memory system 3-4A before receiving a response to the third XOR / write command.

[0086] In response to receiving a third XOR / write command from host 2A, the fourth memory system 3-4A receives first XOR data 521 from the first memory system 3-1A. The fourth memory system 3-4A reads parity 51P from its NAND flash memory. The fourth memory system 3-4A generates prior XOR data 51P-P by performing an XOR operation between the first XOR data 521 and the parity 51P. Then, the fourth memory system 3-4A writes the prior XOR data 51P-P into its NAND flash memory.

[0087] In response to receiving a fourth XOR / write command from host 2A, the fourth memory system 3-4A receives the second XOR data 522 from the third memory system 3-3A. The fourth memory system 3-4A reads the prior XOR data 51P-P from its NAND flash memory. The fourth memory system 3-4A generates an updated parity 51P-U by performing an XOR operation between the prior XOR data 51P-P and the second XOR data 522. Then, the fourth memory system 3-4A writes the updated parity 51P-U into its NAND flash memory.

[0088] Furthermore, if the fourth memory system 3-4A receives a fourth XOR / write command before the third XOR / write command, it generates prior XOR data 51P-P by performing an XOR operation between the second XOR data 522 and the parity 51P. In this case, in response to receiving the third XOR / write command, the fourth memory system 3-4A performs an XOR operation between the prior XOR data 51P-P and the first XOR data 521, thereby generating an updated parity 51P-U.

[0089] Through the above third update operation, in the information processing system 1A, the first user data 511 stored in the first memory system 3-1A is updated to the first updated user data 511-U, the third user data 513 stored in the third memory system 3-3A is updated to the third updated user data 513-U, and the parity 51P stored in the fourth memory system 3-4A is updated to the updated parity 51P-U.

[0090] In the third update operation, similar to the second update operation described with reference to FIG5, the resources of memory system 3A are used to generate the update parity 51P-U. Therefore, in the third update operation, the update operation from host 2A to memory system 3A is unloaded.

[0091] However, in the third update operation, the first XOR data 521 is sent from the first memory system 3-1A to the fourth memory system 3-4A, and the second XOR data 522 is sent from the third memory system 3-3A to the fourth memory system 3-4A. Simultaneously, requests to send the first XOR data 521 and the second XOR data 522 to the fourth memory system 3-4A can be generated. In this case, one of the sending requests must wait until the other sending request is completed. That is, data transmission to the fourth memory system 3-4A storing parity 51P can occur in a concentrated manner. Furthermore, the bus connecting each memory system 3A to the PCIe switch 4A has a smaller bus bandwidth than the bus connecting the host 2 to the PCIe switch 4. Therefore, the bus bandwidth used for transmitting data to the fourth memory system 3-4A is insufficient, potentially reducing the overall performance of the information processing system 1A.

[0092] On the other hand, in the information processing system 1 of the first embodiment, while offloading the update operation from the host 2 to the memory system 3, the centralized transmission of data to the memory system 3 storing the parity 51P is also avoided. Therefore, in the information processing system 1, the overall performance of the information processing system 1 can be improved while reducing the load on the host 2.

[0093] Referring to Figures 7-11, two examples of update operations in information processing system 1 are explained.

[0094] Figure 7 illustrates an example of the fourth update operation in the information processing system 1. The fourth update operation is used to update user data stored in two or more memory systems 3 while reducing the resources of the host 2. Here, an example is shown where the fourth update operation updates the first user data 511 stored in the first memory system 3-1 to the first updated user data 511-U, and updates the third user data 513 stored in the third memory system 3-3 to the third updated user data 513-U. Furthermore, suppose that in the four memory systems 3-1, 3-2, 3-3, and 3-4, the first user data 511, the second user data 512, the third user data 513, and the parity 51P are stored respectively through the sequential write operation described with reference to Figure 3. The first user data 511, the second user data 512, the third user data 513, and the parity 51P constitute an ECC frame 51E.

[0095] The DRAM 22 memory of host 2 has first updated user data 511-U and third updated user data 513-U.

[0096] The CPU 21 of host 2 sends an XOR / write command (first XOR / write command) requesting an XOR operation and writing of the first updated user data 511-U to the first memory system 3-1 (1 in FIG7). The first XOR / write command may include the logical address of the first user data 511.

[0097] In response to receiving a first XOR / write command from host 2, first memory system 3-1 receives first updated user data 511-U from host 2. First memory system 3-1 reads the first user data 511 from NAND flash memory 5 within itself. First memory system 3-1 generates first XOR data 521 by performing an XOR operation between the first user data 511 and the first updated user data 511-U. The first XOR data 521 is stored in an internal buffer 61-1 of first memory system 3-1. For example, a portion of the memory area of ​​DRAM 6 can be allocated as internal buffer 61-1. Internal buffer 61-1 is, for example, a controller memory buffer (CMB) that can be accessed by other memory systems 3 via PCIe switch 4. Because internal buffer 61-1 is used in the storage of the first XOR data 521, the write amplification factor (WAF) does not increase. WAF is the value obtained by dividing the amount of data actually written to NAND flash memory 5 by the amount of data written to NAND flash memory 5 according to the request from host 2. The first memory system 3-1 writes the first updated user data 511-U into NAND flash memory 5 within the first memory system 3-1.

[0098] Next, the CPU 21 of host 2 sends an XOR / write command (second XOR / write command) requesting the XOR operation and the writing of the third updated user data 513-U to the third memory system 3-3 (2 in FIG. 7). The second XOR / write command may include the logical address of the third user data 513 and the identifier (e.g., address) of the internal buffer 61-1 of the first memory system 3-1 (more specifically, the storage location of the first XOR data 521).

[0099] In response to receiving a second XOR / write command from host 2, the third memory system 3-3 receives third updated user data 513-U from host 2 and first XOR data 521 from the first memory system 3-1. Additionally, the third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within itself. The third memory system 3-3 generates third XOR data 523 by performing an XOR operation on the third user data 513, the third updated user data 513-U, and the first XOR data 521. The third XOR data 523 is stored in the internal buffer 61-3 of the third memory system 3-3. Then, the third memory system 3-3 writes the third updated user data 513-U into the NAND flash memory 5 within itself.

[0100] Next, CPU 21 of host 2 sends an XOR / write command (third XOR / write command) requesting the XOR operation and the write of the parity 51P-U to the fourth memory system 3-4 (3 in Figure 7). The third XOR / write command may also include the logical address of parity 51P and the identifier (e.g., address) of the internal buffer 61-3 of the third memory system 3-3 (more specifically, the storage location of the third XOR data 523).

[0101] In response to receiving a third XOR / write command from host 2, the fourth memory system 3-4 receives third XOR data 523 from the third memory system 3-3. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within itself. The fourth memory system 3-4 generates an updated parity 51P-U by performing an XOR operation between the third XOR data 523 and the parity 51P. Then, the fourth memory system 3-4 writes the updated parity 51P-U into the NAND flash memory 5 within itself.

[0102] Through the above fourth update operation, in the information processing system 1, the first user data 511 stored in the first memory system 3-1 is updated to the first updated user data 511-U, the third user data 513 stored in the third memory system 3-3 is updated to the third updated user data 513-U, and the parity 51P stored in the fourth memory system 3-4 is updated to the updated parity 51P-U.

[0103] In the fourth update operation, the resources of memory system 3 are used to generate the update parity 51P-U. Therefore, in the fourth update operation, the update operation from host 2 to memory system 3 is unloaded.

[0104] Furthermore, in the fourth update operation, the first XOR data 521 is sent from the first memory system 3-1 to the third memory system 3-3, and the third XOR data 523 is sent from the third memory system 3-3 to the fourth memory system 3-4. This avoids concentrated data transfers to the fourth memory system 3-4, which stores parity 51P.

[0105] Therefore, in the information processing system 1 that performs the fourth update operation, the overall performance of the information processing system 1 can be improved while reducing the load on the host 2.

[0106] Figure 8 is a sequence diagram illustrating a specific example of the fourth update operation in information processing system 1.

[0107] First, host 2 sends the first XOR / write command and the first update user data 511-U to the first memory system 3-1 (A1). Host 2 can also send the first update user data 511-U to the first memory system 3-1 that has received the first XOR / write command.

[0108] In response to receiving a first XOR / write command and first updated user data 511-U, the first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 (A2). The first memory system 3-1 performs an XOR operation on the first user data 511 and the first updated user data 511-U to generate first XOR data 521 (A3). The first memory system 3-1 writes the first updated user data 511-U into the NAND flash memory 5 within the first memory system 3-1, thus invalidating the first user data 511 (A4). Specifically, the first memory system 3-1 updates the logical physical address translation table 31 so that the logical address corresponding to the first user data 511 is associated with the physical memory location storing the first updated user data 511-U, rather than with the physical memory location storing the first user data 511. In this way, the first user data 511 is invalidated.

[0109] Then, the first memory system 3-1 sends a response to the first XOR / write command to the host 2 (A5). Furthermore, the first memory system 3-1 is not limited to writing the first updated user data 511-U to the NAND flash memory 5; it can also send a response to the first XOR / write command to the host 2 while ensuring that the first updated user data 511-U is not volatile. Specifically, the first memory system 3-1 can, for example, generate the first XOR data 521 and store the first updated user data 511-U in a write buffer (e.g., DRAM 6) with power loss protection (PLP) functionality, and then send a response to the host 2. Therefore, compared to sending a response in response to writing the first updated user data 511-U to the NAND flash memory 5, the first memory system 3-1 can send a response to the host 2 much faster. The PLP function is as follows: when the power supplied from the external power source to the memory system 3 is cut off, it uses the energy of the charge stored in the energy storage device in the memory system 3 to write user data stored in the write buffer and not written to the NAND flash memory 5.

[0110] Next, in response to receiving the reply to the first XOR / write command, host 2 sends the second XOR / write command and the third update user data 513-U to the third memory system 3-3 (A6).

[0111] In response to receiving the second XOR / write command and the third updated user data 513-U, the third memory system 3-3 receives the first XOR data 521 from the first memory system 3-1 (A7). Specifically, the third memory system 3-3 receives, for example, the first XOR data 521 read from and sent from a specific memory region (e.g., internal buffer 61-1) within the first memory system 3-1. The location within the first memory system 3-1 where the first XOR data 521 is stored is, for example, predetermined. The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3 (A8). The third memory system 3-3 performs an XOR operation on the third user data 513, the third updated user data 513-U, and the first XOR data 521 to generate the third XOR data 523 (A9). The third memory system 3-3 writes the third updated user data 513-U into the NAND flash memory 5 within the third memory system 3-3, thereby invalidating the third user data 513 (A10). Then, the third memory system 3-3 sends the response to the second XOR / write command to the host 2 (A11). Furthermore, the third memory system 3-3 can also send the response to the second XOR / write command to the host 2 while ensuring that the third update user data 513-U is non-volatile.

[0112] In response to receiving the reply to the second XOR / write command, host 2 sends the third XOR / write command to the fourth memory system 3-4 (A12).

[0113] In response to receiving the third XOR / write command, the fourth memory system 3-4 receives the third XOR data 523 from the third memory system 3-3 (A13). The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4 (A14). The fourth memory system 3-4 performs an XOR operation between the parity 51P and the third XOR data 523 to generate an updated parity 51P-U (A15). The fourth memory system 3-4 writes the updated parity 51P-U into the NAND flash memory 5 within the fourth memory system 3-4 (A16). Then, the fourth memory system 3-4 sends a response to the third XOR / write command to the host 2 (A17). Alternatively, the fourth memory system 3-4 can also send a response to the third XOR / write command to the host 2 while ensuring that the updated parity 51P-U is not volatile.

[0114] Through the above fourth update operation, the update operation from host 2 to memory system 3 can be unloaded in information processing system 1, and the centralized data transmission to the fourth memory system 3-4 storing parity 51P can be avoided.

[0115] Furthermore, the operation of the first memory system 3-1, the second memory system 3-2, the third memory system 3-3, and the fourth memory system 3-4 is implemented, for example, by a CPU 14, which functions as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144 as described above with reference to FIG2.

[0116] As an example, the operation in the first memory system 3-1 during the fourth update operation will be explained.

[0117] Figure 9 shows an example of a specific operation in the first memory system 3-1 during the fourth update operation.

[0118] Command receiving unit 141 receives a first XOR / write command from host 2 (1) in FIG9. In response to receiving the first XOR / write command, command receiving unit 141 receives first updated user data 511-U from host 2 (2) in FIG9. Based on the first XOR / write command, command receiving unit 141 issues a read instruction to read processing unit 142 to instruct the first user data 511 to be read (3) in FIG9.

[0119] In response to a read instruction, the read processing unit 142 reads the first user data 511 from the NAND flash memory 5 (4 in FIG9). Then, the read processing unit 142 sends the read first user data 511 to the XOR processing unit 143 (5 in FIG9).

[0120] Next, the command receiving unit 141 sends the XOR instruction, which instructs the first user data 511 and the first updated user data 511-U to the XOR processing unit 143 (6 in FIG9).

[0121] In response to an XOR instruction, the XOR processing unit 143 performs an XOR operation on the first user data 511 and the first updated user data 511-U to generate the first XOR data 521. The XOR processing unit 143 stores the generated first XOR data 521 in the internal buffer 61-1 (7 in FIG9).

[0122] Then, the command receiving unit 141 sends the write instruction, which instructs the first updated user data 511-U to be written, and the first updated user data 511-U to the write processing unit 144 (8 in FIG9).

[0123] In response to a write instruction, the write processing unit 144 writes the first updated user data 511-U into the NAND flash memory 5 (9 in FIG. 9). Then, the write processing unit 144 updates the logical physical address translation table 31 by associating the logical address with the physical memory location storing the first user data 511 with the physical memory location storing the first updated user data 511-U (10 in FIG. 9). Thereby, the first user data 511 is invalidated, and the user data corresponding to the logical address is updated to the first updated user data 511-U.

[0124] Then, the command receiving unit 141 sends the response to the first XOR / write command to the host 2 (11 in Figure 9).

[0125] Similarly, the operation of the second memory system 3-2, the third memory system 3-3, and the fourth memory system 3-4 can also be realized by the CPU 14, which functions as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144.

[0126] Figure 10 shows an example of the fifth update operation in the information processing system 1. The fifth update operation is the same as the fourth update operation used to update the first user data 511 stored in the first memory system 3-1 to the first updated user data 511-U, and to update the third user data 513 stored in the third memory system 3-3 to the third updated user data 513-U.

[0127] The DRAM 22 memory of host 2 contains first updated user data 511-U and third updated user data 513-U.

[0128] The CPU 21 of host 2 sends a first XOR / write command requesting an XOR operation and writing of the first updated user data 511-U to the first memory system 3-1 (1-1 in Figure 10). In addition, the CPU 21 of host 2 sends a second XOR / write command requesting an XOR operation and writing of the third updated user data 513-U to the third memory system 3-3 (1-2 in Figure 10).

[0129] In response to receiving a first XOR / write command from host 2, first memory system 3-1 receives first updated user data 511-U from host 2. First memory system 3-1 reads the first user data 511 from its NAND flash memory 5. First memory system 3-1 generates first XOR data 521 by performing an XOR operation between the first user data 511 and the first updated user data 511-U. First XOR data 521 is stored in the internal buffer 61-1 of first memory system 3-1. Then, first memory system 3-1 writes the first updated user data 511-U into its NAND flash memory 5.

[0130] In response to receiving a second XOR / write command from host 2, the third memory system 3-3 receives third updated user data 513-U from host 2. The third memory system 3-3 reads the third user data 513 from its NAND flash memory 5. The third memory system 3-3 generates pre-XOR data 523-P by performing an XOR operation between the third user data 513 and the third updated user data 513-U. The pre-XOR data 523-P is stored in the internal buffer 61-3 of the third memory system 3-3. Then, the third memory system 3-3 writes the third updated user data 513-U into its NAND flash memory 5. The operation performed by the third memory system 3-3 in response to the second XOR / write command is executed, for example, in parallel with the operation performed by the first memory system 3-1 in response to the first XOR / write command.

[0131] Next, the CPU 21 of host 2 sends an XOR command requesting the first XOR data 521 and the prior XOR data 523-P to the third memory system 3-3 (2 in Figure 10).

[0132] In response to receiving an XOR command from host 2, the third memory system 3-3 receives first XOR data 521 from the first memory system 3-1. The third memory system 3-3 generates third XOR data 523 by performing an XOR operation between the first XOR data 521 and the prior XOR data 523-P. The third XOR data 523 is stored in the internal buffer 61-3 of the third memory system 3-3.

[0133] Next, CPU 21 of host 2 sends a third XOR / write command requesting the XOR operation and updating the parity 51P-U to the fourth memory system 3-4 (3 in Figure 10).

[0134] In response to receiving a third XOR / write command from host 2, the fourth memory system 3-4 receives third XOR data 523 from the third memory system 3-3. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within itself. The fourth memory system 3-4 generates an updated parity 51P-U by performing an XOR operation between the third XOR data 523 and the parity 51P. Then, the fourth memory system 3-4 writes the updated parity 51P-U into the NAND flash memory 5 within itself.

[0135] Through the fifth update operation described above, in the information processing system 1, the first user data 511 stored in the first memory system 3-1 is updated to the first updated user data 511-U, the third user data 513 stored in the third memory system 3-3 is updated to the third updated user data 513-U, and the parity 51P stored in the fourth memory system 3-4 is updated to the updated parity 51P-U.

[0136] In the fifth update operation, the resources of memory system 3 are used to generate the update parity 51P-U. Therefore, in the fifth update operation, the update operation from host 2 to memory system 3 is unloaded.

[0137] Furthermore, in the fifth update operation, the first XOR data 521 is sent from the first memory system 3-1 to the third memory system 3-3, and the third XOR data 523 is sent from the third memory system 3-3 to the fourth memory system 3-4. This avoids concentrated data transfers to the fourth memory system 3-4, which stores parity 51P.

[0138] Furthermore, in the fifth update operation, the operation performed by the first memory system 3-1 in response to the first XOR / write command and the operation performed by the third memory system 3-3 in response to the second XOR / write command are executed in parallel. This allows for partial parallelization of the operations performed by the first memory system 3-1 and the operations performed by the third memory system 3-3. Therefore, in the information processing system 1, the time required for the fifth update operation can be shorter than the time required for the fourth update operation.

[0139] Thus, in the information processing system 1 performing the fifth update operation, the overall performance of the information processing system 1 can be improved while reducing the load on the host 2.

[0140] Figure 11 is a sequence diagram showing a specific example of the fifth update operation in information processing system 1.

[0141] First, host 2 sends the first XOR / write command and the first update user data 511-U to the first memory system 3-1 (B1). Host 2 can also send the first update user data 511-U to the first memory system 3-1 that received the first XOR / write command. Additionally, host 2 sends the second XOR / write command and the third update user data 513-U to the third memory system 3-3 (B2). Host 2 can also send the third update user data 513-U to the third memory system 3-3 that received the second XOR / write command.

[0142] In response to receiving the first XOR / write command and the first update user data 511-U, the first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 (B3). The first memory system 3-1 performs an XOR operation on the first user data 511 and the first update user data 511-U to generate the first XOR data 521, and stores it in the internal buffer 61-1 (B4). The first memory system 3-1 writes the first update user data 511-U into the NAND flash memory 5 within the first memory system 3-1, invalidating the first user data 511 (B5). Then, the first memory system 3-1 sends a response to the first XOR / write command to the host 2 (B6).

[0143] In response to receiving the second XOR / write command and the third updated user data 513-U, the third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3 (B7). The third memory system 3-3 performs an XOR operation on the third user data 513 and the third updated user data 513-U to generate pre-XOR data 523-P, and stores it in the internal buffer 61-3 (B8). The third memory system 3-3 writes the third updated user data 513-U into the NAND flash memory 5 within the third memory system 3-3, invalidating the third user data 513 (B9). Then, the third memory system 3-3 sends a response to the second XOR / write command to the host 2 (B10).

[0144] Next, in response to receiving the response to the first XOR / write command and the response to the second XOR / write command, host 2 sends the XOR command to the third memory system 3-3 (B11).

[0145] In response to receiving an XOR command, the third memory system 3-3 receives first XOR data 521 (B12) from the first memory system 3-1. The third memory system 3-3 performs an XOR operation between the first XOR data 521 and the prior XOR data 523-P to generate third XOR data 523, and stores it in the internal buffer 61-3 (B13). Then, the third memory system 3-3 sends a response to the XOR command to the host 2 (B14). The subsequent operations from B15 to B20 are the same as the operations from A12 to A17 of the fourth update operation described with reference to FIG8.

[0146] Through the fifth update operation described above, the update operation from the host 2 to the memory system 3 can be offloaded in the information processing system 1, and the concentrated data transmission to the fourth memory system 3-4 storing parity 51P can be avoided. In addition, by parallelizing a portion of the operations in the first memory system 3-1 and the operations in the third memory system 3-3, the time required for the fifth update operation can be shortened compared to the time required for the fourth update operation.

[0147] (Second Implementation Form) In the information processing system 1 of the first embodiment, when multiple memory systems 3 constitute a RAID, an update operation is performed to update at least a portion of the user data 51D constituting an ECC frame 51E in two or more memory systems 3. In contrast, in the information processing system 1 of the second embodiment, when multiple memory systems 3 constitute a RAID, an operation is performed to recover the data stored in the failed memory system 3 and rebuild the RAID (reconstruction operation).

[0148] The information processing system 1 in the second embodiment has the same structure as the information processing system 1 in the first embodiment. The difference in the second embodiment is that the reconstruction operation is performed in the host computer 2 and the memory system 3. The following mainly describes the differences from the first embodiment.

[0149] Figure 12 illustrates an example of the first rebuild operation in information processing system 1. The first rebuild operation is an operation that restores data stored in the failed memory system 3 and rebuilds the RAID array while reducing the resources of the host 2 being used. Here, the case where the second memory system 3-2 fails is illustrated. The fifth memory system 3-5 is the memory system 3 that was replaced by the failed second memory system 3-2. That is, in information processing system 1, in order to cope with the failure of the second memory system 3-2, a rebuild operation is performed by rebuilding the RAID array using the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0150] In the four memory systems 3-1, 3-2, 3-3, and 3-4, it is set that, through the sequential write operation described with reference to FIG3, first user data 511, second user data 512, third user data 513, and parity 51P are stored respectively. The first user data 511, second user data 512, third user data 513, and parity 51P constitute an ECC frame 51E.

[0151] In the event of a failure in the second memory system 3-2, the host 2 sends an XOR command requesting an XOR operation (the first XOR command) to the first memory system 3-1 (1 in Figure 12). The first XOR command may include the logical address of the first user data 511.

[0152] In response to a first XOR command from host 2, first memory system 3-1 reads first user data 511 from NAND flash memory 5 within first memory system 3-1. First memory system 3-1 generates fourth XOR data 524 by performing an XOR operation between first user data 511 and virtual data 531. Fourth XOR data 524 is stored, for example, in internal buffer 61-1. Virtual data 531 is a data string where all bits are 0. Virtual data 531 has the same data length as first user data 511. Since all bits of the virtual data 531 data string are 0, fourth XOR data 524 is identical to first user data 511. Alternatively, first memory system 3-1 can perform the XOR operation between first user data 511 and virtual data 531 and directly store first user data 511 in internal buffer 61-1.

[0153] Then, host 2 sends the second XOR command to the third memory system 3-3 (2 in Figure 12). The second XOR command may include the logical address of the third user data 513 and the identifier (e.g., address) of the internal buffer 61-1 of the first memory system 3-1 (more specifically, the storage location of the fourth XOR data 524).

[0154] In response to the second XOR command from the host 2, the third memory system 3-3 receives the fourth XOR data 524 from the first memory system 3-1. The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within itself. The third memory system 3-3 generates the fifth XOR data 525 by performing an XOR operation between the third user data 513 and the fourth XOR data 524. The fifth XOR data 525 is stored, for example, in the internal buffer 61-3.

[0155] Next, host 2 sends a third XOR command to the fourth memory system 3-4 (3 in Figure 12). The third XOR command may include the logical address of parity 51P and the identifier (e.g., address) of the internal buffer 61-3 of the third memory system 3-3 (more specifically, the storage location of the fifth XOR data 525).

[0156] In response to the third XOR command from the host 2, the fourth memory system 3-4 receives the fifth XOR data 525 from the third memory system 3-3. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within itself. The fourth memory system 3-4 generates second user data 512 by performing an XOR operation between the parity 51P and the fifth XOR data 525. That is, it restores the second user data 512 stored in the NAND flash memory 5 within the malfunctioning second memory system 3-2. The generated second user data 512 is stored, for example, in the internal buffer 61-4 of the fourth memory system 3-4.

[0157] Then, host 2 sends a write command requesting the writing of second user data 512 to fifth memory system 3-5 (4 in FIG. 12). The write command may include the logical address of second user data 512 and the identifier (e.g., address) of internal buffer 61-4 of fourth memory system 3-4 (more specifically, the storage location of second user data 512).

[0158] In response to receiving a write command from host 2, the fifth memory system 3-5 receives the second user data 512 from the fourth memory system 3-4. Then, the fifth memory system 3-5 writes the second user data 512 into the NAND flash memory 5 within the fifth memory system 3-5.

[0159] Through the first reconstruction operation described above, the second user data 512 stored in the failed second memory system 3-2 can be recovered in information processing system 1 and stored in the fifth memory system 3-5, which was replaced by the second memory system 3-2. Then, by repeating the first reconstruction operation in the same way, all data stored in the second memory system 3-2 (i.e., user data and parity) can be recovered and stored in the fifth memory system 3-5. In this way, RAID can be reconstructed in information processing system 1 using the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0160] In the first reconstruction operation, the resources of memory system 3 are used to restore the second user data 512. Therefore, in the first reconstruction operation, the reconstruction operation from host 2 to memory system 3 is unloaded.

[0161] Alternatively, as another operation for restoring the second user data 512, one could consider retrieving the first user data 511, the third user data 513, and the parity 51P from any one of the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5, performing an XOR operation to restore the second user data 512. However, in this operation, data transmission to the memory system 3 used for restoring the second user data 512 occurs centrally.

[0162] In contrast, during the first reconstruction operation, the fourth XOR data 524 is sent from the first memory system 3-1 to the third memory system 3-3, the fifth XOR data 525 is sent from the third memory system 3-3 to the fourth memory system 3-4, and the second user data 512 is sent from the fourth memory system 3-4 to the fifth memory system 3-5. This avoids the concentrated transmission of data to a single system within the first memory system 3-1, third memory system 3-3, fourth memory system 3-4, and fifth memory system 3-5.

[0163] Therefore, in the information processing system 1 that performs the first reconstruction operation, the overall performance of the information processing system 1 can be improved while reducing the load applied to the host 2.

[0164] Figure 13 is a sequence diagram illustrating a specific example of the first reconstruction operation in information processing system 1.

[0165] First, host 2 sends the first XOR command to the first memory system 3-1 (C1).

[0166] In response to receiving the first XOR command, the first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 (C2). The first memory system 3-1 performs an XOR operation between the first user data 511 and the virtual data 531 to generate a fourth XOR data 524 (= the first user data 511), and stores it in the internal buffer 61-1 (C3). Then, the first memory system 3-1 sends its response to the first XOR command to the host 2 (C4).

[0167] In response to receiving the reply to the first XOR command, host 2 sends the second XOR command to the third memory system 3-3 (C5).

[0168] In response to receiving the second XOR command, the third memory system 3-3 receives the fourth XOR data 524 from the first memory system 3-1 (C6). The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3 (C7). The third memory system 3-3 performs an XOR operation between the third user data 513 and the fourth XOR data 524 to generate the fifth XOR data 525, and stores it in the internal buffer 61-3 (C8). Then, the third memory system 3-3 sends its response to the second XOR command to the host 2 (C9).

[0169] In response to receiving the reply to the second XOR command, host 2 sends the third XOR command to the fourth memory system 3-4 (C10).

[0170] In response to receiving the third XOR command, the fourth memory system 3-4 receives the fifth XOR data 525 from the third memory system 3-3 (C11). The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within itself (C12). The fourth memory system 3-4 performs an XOR operation between the parity 51P and the fifth XOR data 525 to generate the second user data 512, and stores it in the internal buffer 61-4 (C13). Then, the fourth memory system 3-4 sends its response to the third XOR command to the host 2 (C14).

[0171] In response to receiving the reply to the third XOR command, host 2 sends the write command to the fifth memory system 3-5 (C15).

[0172] In response to receiving a write command, the fifth memory system 3-5 receives second user data 512 from the fourth memory system 3-4 (C16). The fifth memory system 3-5 writes the second user data 512 into the NAND flash memory 5 within the fifth memory system 3-5 (C17). Then, the fifth memory system 3-5 sends a response to the write command to the host 2 (C18).

[0173] Through the first reconstruction operation described above, the reconstruction operation from host 2 to memory system 3 can be offloaded in information processing system 1, and centralized data transmission to specific memory system 3 can be avoided.

[0174] Figure 14 illustrates an example of the second reconstruction operation in information processing system 1. The second reconstruction operation is the same as the first reconstruction operation used to rebuild the RAID using the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5 to address the failure of the second memory system 3-2.

[0175] When the host 2 fails in the second memory system 3-2, it sends the first XOR command to the first memory system 3-1 (1 in Figure 14). The first XOR command may further include the identifier of the third memory system 3-3.

[0176] In response to a first XOR command from host 2, first memory system 3-1 reads first user data 511 from NAND flash memory 5 within first memory system 3-1. First memory system 3-1 generates fourth XOR data 524 by performing an XOR operation between the first user data 511 and virtual data 531. Fourth XOR data 524 is stored, for example, in internal buffer 61-1. Then, first memory system 3-1 sends a second XOR command to third memory system 3-3 (2 in Figure 14). The second XOR command may further include an identifier for fourth memory system 3-4.

[0177] In response to a second XOR command from a first memory system 3-1, the third memory system 3-3 receives fourth XOR data 524 from the first memory system 3-1. The third memory system 3-3 reads third user data 513 from the NAND flash memory 5 within the third memory system 3-3. The third memory system 3-3 generates fifth XOR data 525 by performing an XOR operation between the third user data 513 and the fourth XOR data 524. The fifth XOR data 525 is stored, for example, in an internal buffer 61-3. Then, the third memory system 3-3 sends a third XOR command to the fourth memory system 3-4 ((3) in Figure 14). The third XOR command may further include an identifier for the fifth memory system 3-5.

[0178] The fourth memory system 3-4, in response to the third XOR command from the third memory system 3-3, receives the fifth XOR data 525 from the third memory system 3-3. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4. The fourth memory system 3-4 generates the second user data 512 by performing an XOR operation between the parity 51P and the fifth XOR data 525. That is, the second user data 512 stored in the NAND flash memory 5 within the faulty second memory system 3-2 is restored. The generated second user data 512 is stored, for example, in the internal buffer 61-4. Then, the fourth memory system 3-4 sends a write command requesting the writing of the second user data 512 to the fifth memory system 3-5 (4 in Figure 14).

[0179] The fifth memory system 3-5 receives the second user data 512 from the fourth memory system 3-4 in response to a write command. Then, the fifth memory system 3-5 writes the second user data 512 into the NAND flash memory 5 within the fifth memory system 3-5.

[0180] Through the second reconstruction operation described above, the second user data 512 stored in the failed second memory system 3-2 can be recovered in information processing system 1 and stored in the fifth memory system 3-5, which was replaced by the second memory system 3-2. Furthermore, by repeating the second reconstruction operation in the same way, all data stored in the second memory system 3-2 can be recovered and stored in the fifth memory system 3-5. Therefore, in information processing system 1, RAID can be reconstructed using the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0181] Furthermore, in the second reconstruction operation, the resources of memory system 3 are used to restore the second user data 512. In addition, not only data (i.e., the fourth XOR data 524, the fifth XOR data 525, and the second user data 512) are transmitted between memory systems 3, but also commands are transmitted. Therefore, in the second reconstruction operation, host 2 only needs to send the first XOR command to the first memory system 3-1. Thus, in the second reconstruction operation, the reconstruction operation from host 2 to memory system 3 is offloaded.

[0182] Furthermore, in the second reconstruction operation, the fourth XOR data 524 is sent from the first memory system 3-1 to the third memory system 3-3, the fifth XOR data 525 is sent from the third memory system 3-3 to the fourth memory system 3-4, and the second user data 512 is sent from the fourth memory system 3-4 to the fifth memory system 3-5. This avoids data transmission concentrated within a single system among the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0183] Therefore, in the information processing system 1 performing the second reconstruction operation, the overall performance of the information processing system 1 can be improved while reducing the load applied to the host 2.

[0184] Figure 15 is a sequence diagram illustrating a specific example of the second reconstruction operation in information processing system 1.

[0185] First, host 2 sends the first XOR command to the first memory system 3-1 (D1).

[0186] In response to receiving the first XOR command, the first memory system 3-1 reads the first user data 511 (D2) from the NAND flash memory 5 within the first memory system 3-1. The first memory system 3-1 performs an XOR operation on the first user data 511 and the virtual data 531 to generate the fourth XOR data 524, and stores it in the internal buffer 61-1 (D3). Then, the first memory system 3-1 sends the second XOR command and the fourth XOR data 524 to the third memory system 3-3 (D4).

[0187] In response to receiving the second XOR command and the fourth XOR data 524, the third memory system 3-3 reads the third user data 513 (D5) from the NAND flash memory 5 within the third memory system 3-3. The third memory system 3-3 performs an XOR operation on the third user data 513 and the fourth XOR data 524 to generate the fifth XOR data 525, and stores it in the internal buffer 61-3 (D6). Then, the third memory system 3-3 sends the third XOR command and the fifth XOR data 525 to the fourth memory system 3-4 (D7).

[0188] In response to receiving the third XOR command and the fifth XOR data 525, the fourth memory system 3-4 reads the parity 51P (D8) from the NAND flash memory 5 within the fourth memory system 3-4. The fourth memory system 3-4 performs an XOR operation between the parity 51P and the fifth XOR data 525 to generate the second user data 512, and stores it in the internal buffer 61-4 (D9). Then, the fourth memory system 3-4 sends the write command and the second user data 512 to the fifth memory system 3-5 (D10).

[0189] In response to receiving the write command and the second user data 512, the fifth memory system 3-5 writes the second user data 512 into the NAND flash memory 5 (D11) within the fifth memory system 3-5. Then, the fifth memory system 3-5 sends a response to the write command to the fourth memory system 3-4 (D12).

[0190] In response to receiving a response to the write command, the fourth memory system 3-4 sends a response to the third XOR command to the third memory system 3-3 (D13). In response to receiving a response to the third XOR command, the third memory system 3-3 sends a response to the second XOR command to the first memory system 3-1 (D14). In response to receiving a response to the second XOR command, the first memory system 3-1 sends a response to the first XOR command to the host 2 (D15).

[0191] Through the second reconstruction operation described above, the reconstruction operation from host 2 to memory system 3 can be offloaded in information processing system 1, and centralized data transmission to specific memory system 3 can be avoided.

[0192] Furthermore, the operation of each of the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5 is implemented, for example, by a CPU 14 which functions as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144 as described with reference to FIG2.

[0193] As an example, the operation in the first memory system 3-1 during the second reconstruction operation is illustrated.

[0194] Figure 16 shows an example of a specific operation in the first memory system 3-1 when the second reconstruction operation is performed.

[0195] Command receiving unit 141 receives a first XOR command from host 2 (1 in FIG16). Based on the first XOR command, command receiving unit 141 sends a read instruction to read processing unit 142 (2 in FIG16) to instruct the first user data 511 to be read.

[0196] In response to a read instruction, the read processing unit 142 reads the first user data 511 from the NAND flash memory 5 (3 in FIG16). Then, the read processing unit 142 sends the read first user data 511 to the XOR processing unit 143 (4 in FIG16).

[0197] Next, the command receiving unit 141 sends the XOR instruction for the XOR operation of the first user data 511 and the virtual data 531, as well as the virtual data 531, to the XOR processing unit 143 (5 in FIG16).

[0198] In response to the XOR instruction, the XOR processing unit 143 performs an XOR operation on the first user data 511 and the virtual data 531 to generate the fourth XOR data 524. The XOR processing unit 143 stores the generated fourth XOR data 524 in the internal buffer 61-1 (6 in FIG16).

[0199] Next, the command receiving unit 141 sends the second XOR command to the third memory system 3-3 (7 in FIG. 16). Then, the command receiving unit 141 receives the response to the second XOR command from the third memory system 3-3 (8 in FIG. 16). In response to receiving the response to the second XOR command, the command receiving unit 141 sends the response to the first XOR command to the host 2 (9 in FIG. 16).

[0200] Similarly, the operations of the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5 can also be implemented by the CPU 14, which functions as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144.

[0201] As explained above, according to the first and second embodiments, the overall performance can be improved while reducing the load applied to the host 2.

[0202] In the information processing system 1 of the first embodiment, the controller 7 of the first memory system 3-1 stores first user data 511 in the NAND flash memory 5 within the first memory system 3-1. The controller 7 of the third memory system 3-3 stores third user data 513 in the NAND flash memory 5 within the third memory system 3-3. The first user data 511 and the third user data 513 constitute at least a portion of an error correction code frame 51E. When updating the first user data 511 and the third user data 513, the host 2 sends the first updated user data 511-U updated from the first user data 511 to the first memory system 3-1, and sends the third updated user data 513-U updated from the third user data 513 to the third memory system 3-3. The controller 7 of the first memory system 3-1 generates first XOR data 521 by performing an XOR operation on at least the first user data 511 and the first updated user data 511-U, and sends the first XOR data 521 to the third memory system 3-3. The controller 7 of the third memory system 3-3 generates third XOR data 523 by performing XOR operation on third user data 513, third updated user data 513-U, and first XOR data 521, and sends the third XOR data 523 to the fourth memory system 3-4.

[0203] This allows for the offloading of update operations from host 2 to memory system 3, and, for example, avoids concentrated data transfers to the fourth memory system 3-4 storing parity 51P.

[0204] Furthermore, in the information processing system 1 of the second embodiment, the controller 7 of the second memory system 3-2 stores the second user data 512 in the NAND flash memory 5 within the second memory system 3-2. The controller 7 of the third memory system 3-3 stores the third user data 513 in the NAND flash memory 5 within the third memory system 3-3. The controller 7 of the fourth memory system 3-4 stores the parity 51P in the NAND flash memory 5 within the fourth memory system 3-4. The second user data 512, the third user data 513, and the parity 51P constitute at least a portion of an error correction code frame 51E. In the event of a failure in the second memory system 3-2, the controller 7 of the third memory system 3-3 generates a fifth XOR data 525 by performing an XOR operation between the fourth XOR data 524 and the third user data 513, and sends the fifth XOR data 525 to the fourth memory system 3-4. The controller 7 of the fourth memory system 3-4 generates the second user data 512 by performing an XOR operation on the fifth XOR data 525 and the parity 51P, and sends the generated second user data 512 to the fifth memory system 3-5 that was replaced by the second memory system 3-2 that failed.

[0205] In this way, the reconstruction operation from host 2 to memory system 3 can be offloaded in information processing system 1, and centralized data transmission to specific memory systems 3 can be avoided.

[0206] Each of the various functions described in the first and second embodiments can be implemented by a circuit (processing circuit). Examples of processing circuits include a programmable processor, such as a central processing unit (CPU). The processor executes the described functions by executing a computer program (command set) stored in memory. The processor can also be a microprocessor that includes circuitry. Examples of processing circuits also include digital signal processors (DSPs), application-specific integrated circuits (ASICs), microcontrollers, controllers, and other circuit components. Each of the components other than the CPU described in these embodiments can also be implemented by a processing circuit.

[0207] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, with omissions, substitutions, and modifications possible without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents.

[0208] 1. 1A: Information Processing System 2: Host / Host Device 2A: Host 3. 3A: Memory System 3-1, 3-1A: Memory System / First Memory System 3-2, 3-2A: Memory System / Second Memory System 3-3, 3-3A: Memory System / Third Memory System 3-4, 3-4A: Memory System / Fourth Memory System 3-5: The Fifth Memory System 4. 4A: Switch / PCIe Switch 5: Non-volatile memory / NAND flash memory 6, 22, 22A: DRAM 7: Controller 10: Busbar 11: Host I / F 12: NAND I / F 13:DRAM I / F 14, 21, 21A: CPU 31: Logical Physical Address Translation Table 51D: User Data 141: Command Receiving Department 142: Read Processing Unit 143: XOR Processing Department 144: Write Processing Unit 511: User Information / First User Information 512: User Data / Second User Data 513: User Data / Third-Party User Data 51P: Parity 51E: ECC frame / Error Correction Code frame 51P-P, 523-P: Pre-existing XOR data 61-1, 61-1A, 61-3, 61-3A, 61-4: Internal buffers 511-U: First Update of User Data 513-U: Third Update User Data 51P-U: Update parity 521: First XOR Data 522: Second XOR Data 523: Third XOR Data 524: Fourth XOR Data 525: Fifth XOR Data 531: Virtual Data B0, B1, B2, ..., Bm-1: Blocks Pages P0, ..., Pn-1

Claims

1. A method for controlling non-volatile memory in a memory system, comprising performing the following steps using a controller in the memory system: Communicate with the host computer; Communicating with one or more external memory systems; The process involves: storing first data in the non-volatile memory; receiving a first request from the host and first updated data updated from the first data; receiving a first mutually exclusive OR data from the first memory system of one or more external memory systems, wherein the first mutually exclusive OR data is generated in the first memory system by performing a mutually exclusive OR operation on at least second data stored in the first memory system and second updated data updated from the second data; generating a second mutually exclusive OR data in response to receiving the first request by performing a mutually exclusive OR operation on the first data, the first updated data, and the first mutually exclusive OR data; sending a first response corresponding to the first request to the host; and sending the second mutually exclusive OR data to the second memory system of another of the one or more external memory systems.

2. The method as described in request item 1, wherein, The first data and the second data constitute at least a portion of the error correction code frame.

3. The method as described in claim 2, wherein, The parity is stored in the second memory system, and the first data, the second data, and the parity constitute at least a portion of the error correction code frame.

4. The method as described in request item 3, wherein, By performing the parity and the mutual exclusion OR operation of the second mutual exclusion data, an updated parity is generated in the second memory system, and the first updated data, the second updated data, and the updated parity constitute at least a portion of the updated error correction code frame.

5. The method as described in request item 1, wherein, The first memory system includes volatile memory, and the first request specifies the address of a first location of the volatile memory of the first memory system storing the first mutually exclusive or data.

6. The method as described in claim 5, further comprising: Accessing the first location of the volatile memory of the first memory system based on the address specified in the first request, wherein the first mutex or data is received from the first memory system by accessing the first location of the volatile memory of the first memory system.

7. The method as described in claim 1, further comprising: The first updated data is stored in the non-volatile memory; And invalidate the first data.

8. The method as described in request item 7, wherein, The first data is stored in a second location of the non-volatile memory, and the first updated data is stored in a third location of the non-volatile memory. The method further includes: managing a logical-physical address translation table; and updating the logical-physical address translation table when invalidating the first data, such that the logical address of the first data is mapped from the physical address of the second location to the physical address of the third location.

9. The method as described in claim 1, further comprising: Store the second mutex or data in volatile memory; And to send the second mutex or data from the volatile memory to the second memory system.

10. The method of claim 1, wherein each memory system and the one or more external memory systems are solid-state drives containing reverse-type flash memory.

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