Vertical power semiconductor device

Abstract

A vertical power semiconductor device comprises a semiconductor substrate, a semiconductor layer, a Schottky metal and a source contact layer, a first well disposed within the semiconductor layer, a source electrode, and a gate electrode assembly, stacked sequentially. The semiconductor layer has a top surface and a concave surface that defines a recess for housing the gate electrode assembly. The first well has a doped region and a heavily doped region extending from the doped region to the top surface. The source electrode is disposed in the doped region and surrounds the heavily doped region. The gate electrode assembly has a dielectric layer, a gate layer, and an insulating layer. The insulating layer protrudes from the top surface away from the concave surface, and every four adjacent insulating layers define a via on the top surface where a Schottky metal is disposed. The gate layer is annular. Partial contact is maintained between two adjacent gate layers, and partial non-contact is maintained between two adjacent gate layers, with each corresponding four adjacent dielectric layers defining a predetermined region of the semiconductor layer located below the via.

Claims

1. A vertical power semiconductor device, comprising: a semiconductor substrate containing first conductivity type carriers; a semiconductor layer formed on the semiconductor substrate and containing the first conductivity type carriers, the semiconductor layer having a top surface remote from the semiconductor substrate and a plurality of concave surfaces recessed from the top surface toward the semiconductor substrate, each of the concave surfaces defining a pit; a plurality of first wells disposed at intervals within the semiconductor layer and containing second conductivity type carriers opposite to the first conductivity type carriers, each first well including a doped region extending from an interior of the semiconductor layer toward the top surface and a heavily doped region extending from the doped region to the top surface with a doping concentration higher than that of the doped region; a plurality of sources, each disposed in its corresponding doped region and containing the first conductivity type carriers, each source extending from its corresponding doped region to the top surface and surrounding its corresponding heavily doped region; Multiple gate components are respectively disposed in their respective corresponding recesses, and each gate component includes a dielectric layer formed on the recessed surface, a gate layer formed on the dielectric layer and filling the recess, and an insulating layer covering the dielectric layer and the gate layer. The side of the insulating layer away from the recessed surface protrudes from the top surface, so that every four adjacent insulating layers define a via above the top surface; multiple Schottky metals are formed on the top surface of the semiconductor layer, each corresponding to a position in the via; and a source contact layer covers and contacts the sources, the heavily doped regions, the insulating layer, and the Schottky metals; wherein... The gate layers, obtained by projecting an orthographic projection downwards from above the source contact layer, form a first ring surrounding their respective first wells and the source. Some adjacent gate layers are partially in contact, while others are not. A predetermined region of the semiconductor layer is defined by a four-adjacent dielectric layer corresponding to the partially contacting and non-contacting adjacent gate layers. Each predetermined region is located below the respective via. The vertical power semiconductor device also includes a plurality of second wells, each containing a second conductivity type carrier and correspondingly disposed within the respective predetermined region. Each second well extends from the predetermined region to the top surface. Furthermore, the second wells, obtained by projecting an orthographic projection downwards from above the source contact layer, form a second ring surrounding their respective Schottky metals.

2. The vertical power semiconductor device as claimed in claim 1, wherein, The first ring shape is selected from either a ring-shaped regular hexagon or a ring-shaped parallelogram.

3. The vertical power semiconductor device as claimed in claim 2, wherein, The first ring is a regular hexagon, and each gate layer in the regular hexagon has a pair of first parallel sides, a pair of second parallel sides, and a pair of third parallel sides. The first parallel sides of each pair of adjacent gate layers are in complete contact, the second parallel sides of each pair of adjacent gate layers are in partial contact, and the third parallel sides of each pair of adjacent gate layers are not in contact. The four adjacent dielectric layers at the locations corresponding to the partially contacting second parallel sides of the two adjacent gate layers and the non-contacting third parallel sides of the two adjacent gate layers define their respective predetermined regions for setting their respective second wells.

4. The vertical power semiconductor device as claimed in claim 2, wherein, The first ring is a parallelogram, and each gate layer in the parallelogram has a pair of first parallel sides and a pair of second parallel sides. The first parallel sides of each pair of adjacent gate layers are in partial contact, and the second parallel sides of each pair of adjacent gate layers are not in contact. The four adjacent dielectric layers at the locations corresponding to the first parallel sides of the two adjacent gate layers that are in partial contact and the second parallel sides of the two adjacent gate layers that are not in contact define their respective predetermined regions for setting their respective second wells.

5. The vertical power semiconductor device as described in claim 3 or claim 4, wherein, The through holes and the predetermined regions obtained by projecting the orthographic projection downwards from the top of the source contact layer form a parallelogram and have a predetermined area. The second ring is a ring-shaped parallelogram, and each of the second wells forming the ring-shaped parallelogram surrounds the bottom of its corresponding Schottky metal.

6. The vertical power semiconductor device as claimed in claim 5, wherein, The predetermined area is between 0.04 μm² and 32 μm².

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