Semiconductor structure

Abstract

A semiconductor structure is provided, including a substrate, first and second well regions, and first to fifth doped regions. The first well region is formed on the substrate and has a first doping type. The second well region is formed in the first well region and the substrate and has a second doping type. The first and second doped regions are formed in the first well region and each has a first and a second doping type. The third to fifth doped regions are formed in the first well region and have a second doping type. In the stacking direction of the substrate and the first well region, the third to fifth doped regions are located on the second well region, and the first and second doped regions are not located on the second well region.

Claims

1. A semiconductor structure, comprising: One substrate; A first well region is formed on the substrate, wherein the first well region has a first doping type; A second well region is formed in the first well region and the substrate, wherein the second well region has a second doping type; a first doped region and a second doped region are formed in the first well region, wherein the first doped region has the first doping type and the second doped region has the second doping type; and a third doped region, a fourth doped region and a fifth doped region are formed in the first well region, wherein the third doped region, the fourth doped region and the fifth doped region have the second doping type, wherein, in one of the stacking directions of the substrate and the first well region, the third doped region, the fourth doped region and the fifth doped region are located on the second well region, and the first doped region and the second doped region are not located on the second well region.

2. The semiconductor structure as described in claim 1, wherein the second well region comprises: A first sub-well zone and a second sub-well zone are formed within the first well zone; A third sub-well region is formed in the substrate, wherein, in the stacking direction of the substrate and the first well region, the first sub-well region and the second sub-well region are located above the third sub-well region; and the first sub-well region and the second sub-well region are respectively coupled to the third sub-well region.

3. The semiconductor structure as described in claim 2, wherein the third sub-well region is configured as a deep well.

4. The semiconductor structure as claimed in claim 2, wherein the first sub-well region is coupled to the third doped region and the second sub-well region is coupled to the fifth doped region.

5. The semiconductor structure as described in claim 2, wherein: The first sub-well region and the fourth doped region are configured to have a first distance to electrically block the first sub-well region and the fourth doped region; the second sub-well region and the fourth doped region are configured to have a second distance to electrically block the second sub-well region and the fourth doped region; wherein the first distance and the second distance are arranged in a direction of the third doped region, the fourth doped region and the fifth doped region.

6. The semiconductor structure as described in claim 2, further comprising: A sixth doped region is formed between the third and fourth doped regions; And a seventh doped region is formed between the fourth doped region and the fifth doped region, wherein the sixth doped region and the seventh doped region have the first doping type.

7. The semiconductor structure as described in claim 6 further includes: A first barrier protective oxide layer is formed on the third doped region; A second barrier oxide layer is formed on the fifth doped region, wherein the first barrier oxide layer and the second barrier oxide layer are separated from each other; and wherein the first barrier oxide layer at least partially covers the sixth doped region, the second barrier oxide layer at least partially covers the seventh doped region, and the first barrier oxide layer and the second barrier oxide layer are separated from each other.

8. The semiconductor structure as claimed in claim 1, wherein, in a side view, the third doped region, the fourth doped region, and the fifth doped region are separated by the first well region.

9. The semiconductor structure as described in claim 1, further comprising: A first barrier protective oxide layer is formed on the third doped region; A second barrier protective oxide layer is formed on the fifth doped region, wherein the first barrier protective oxide layer and the second barrier protective oxide layer are separated from each other.

10. The semiconductor structure as claimed in claim 9, wherein the first barrier protective oxide layer and the second barrier protective oxide layer each at least partially cover the fourth doped region.

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