Data driving device and data driving system

Abstract

This disclosure provides a data driving device and a data driving system. This disclosure relates to a data driving device, a data processing device, and a system for driving a display device, and more particularly, to a data driving device, a data processing device, and a system for automatically optimizing the configuration of an equalizer in a data driving device in a display device.

Description

[Technical Field]

[0001] This disclosure relates to technology for driving display devices. [Previous Technology]

[0002] Generally, the display panel of a display device is configured as a plurality of pixels arranged in a matrix, and each pixel includes sub-pixels such as R (red), G (green), and B (blue). In addition, each sub-pixel emits light in grayscale corresponding to the image data and displays the image on the display panel.

[0003] Here, the display device may include a data processing device called a "timing controller" and a data driving device called a "source driver," and image data is sent from the data processing device to the data driving device. The image data is transmitted as a digital signal, and the data driving device converts the image data received as a digital signal into an analog voltage and drives each pixel, i.e., the display panel.

[0004] As described above, in order to drive the display panel, the data driving device must receive various types of signals from the data processing device.

[0005] Here, the data driving device may include an equalizer that can enhance signal reception performance by adjusting the signal received from the data processing device.

[0006] The equalizer of the data drive device can adjust the signal in various ways. For example, the equalizer can adjust the amplitude of the signal. Specifically, the equalizer can adjust the amplitude of the signal by multiplying the signal by a predetermined gain.

[0007] Here, if the gain of the equalizer is too small, the amplitude of the signal may be reduced. In this case, inter-symbol interference (ISI) may occur, which may reduce the signal reception performance of the data drive device.

[0008] On the other hand, if the gain of the equalizer is too large, the noise components included in the signal may be amplified, which may reduce the signal receiving performance of the data drive device.

[0009] As mentioned above, if the gain of the equalizer is inappropriate, the signal receiving performance of the data drive device will be degraded. Therefore, it is necessary to always configure the gain appropriately.

[0010] Traditionally, engineers manually determine the configuration value for properly configuring the gain of the equalizer, or a specific configuration value is unilaterally sent from a signal transmitting device (e.g., a data processing device, etc.) and then determined. However, this traditional method may require more effort than is needed to configure the equalizer, or may degrade the accuracy of configuring the equalizer. [Summary of the Invention]

[0011] In this context, in one aspect, the present disclosure provides a technique for configuring an equalizer for an automatically optimized data driving device in a display apparatus.

[0012] To this end, in one aspect, the present disclosure provides a data driving apparatus comprising: a communication circuit including an equalizer and configured to receive a first data signal containing a plurality of EQ (equalizer) configuration information for configuring the equalizer, and then receiving an EQ training signal during a plurality of time intervals, wherein the EQ is an equalizer; and a control circuit configured to evaluate the reception performance of the communication circuit for the EQ training signal in each of the plurality of time intervals by changing the configuration of the equalizer in each time interval according to the respective EQ configuration information, and to select the optimal EQ configuration information based on the evaluation result.

[0013] The first data signal may also include information related to the amount of EQ configuration information, and the control circuit may identify the number of time intervals by means of the information related to the amount of EQ configuration information.

[0014] The communication circuit can receive the first data signal via a low-speed data communication protocol, and can receive the EQ training signal via a high-speed data communication protocol different from the low-speed data communication protocol.

[0015] The EQ training signal may include a training sequence repeated in each time interval, and the training sequence may include an interval signal for distinguishing the time intervals from each other, an EQ clock training signal set at the end of the interval signal, and an EQ test signal set at the end of the EQ clock training signal.

[0016] In the interval signal receiving interval of a training sequence, the communication circuit can initialize the clock trained in the training sequence preceding the training sequence, and in the EQ clock training signal receiving interval of the training sequence, the communication circuit can perform clock training again.

[0017] The first data signal and the EQ training signal may be sent from the data processing device, and when the clock is initialized and clock training is performed again, the voltage level of the lock signal sent from the data driving device to the data processing device may be kept constant.

[0018] The EQ test signal may include a PRBS mode, and the control circuit can calculate the bit error rate for the PRBS mode in each time interval, and can select the EQ configuration information corresponding to the time interval with the minimum bit error rate among the multiple time intervals as the optimal EQ configuration information, wherein PRBS is a pseudo-random binary sequence.

[0019] The EQ test signal may include test data encoded using a DC (direct current) balanced code method, and the control circuit may check whether there are any errors in the test data in each time interval, and may select the EQ configuration information corresponding to the time interval with the smallest number of errors in the test data among the plurality of time intervals as the optimal EQ configuration information.

[0020] When the communication circuit receives the interval signal, the control circuit may change the configuration of the equalizer.

[0021] When a signal with a predetermined voltage level is received during a predetermined time or longer, the communication circuit can initialize the clock and maintain the interval signal at a constant voltage level during the predetermined time.

[0022] In another aspect, this disclosure provides a data driving device, comprising: a communication circuit including an equalizer and configured to receive a first data signal and then receive an EQ training signal, the first data signal including a plurality of EQ configuration information for configuring the equalizer, the EQ training signal including an interval signal having a predetermined voltage level, an EQ clock training signal disposed at the end of the interval signal, and an EQ test signal disposed at the end of the EQ clock training signal, wherein the EQ is the equalizer; and a control circuit configured to divide the reception time of the EQ test signal into a plurality of time intervals when the communication circuit receives the EQ test signal, to evaluate the reception performance of the communication circuit for the EQ training signal in each of the plurality of time intervals by changing the configuration of the equalizer in each of the time intervals according to the respective EQ configuration information, and to select the optimal EQ configuration information based on the evaluation results.

[0023] The first data signal may also include information related to the amount of EQ configuration information, and the control circuit may determine the number of time intervals to match the amount of EQ configuration information.

[0024] Each of the multiple EQ configuration information may include the gain level of the equalizer, and the control circuit may set the gain level of the equalizer differently in each time interval according to each EQ configuration information.

[0025] In another aspect, this disclosure provides a data-driven system, comprising: a data processing apparatus configured to generate a first data signal including a plurality of EQ configuration information, transmit the first data signal, generate an EQ training signal, and transmit the EQ training signal during a plurality of time intervals, wherein the EQ is an equalizer, and the EQ configuration information is configuration information of the equalizer; and a data-driven apparatus including the equalizer and configured to receive the EQ training signal during the plurality of time intervals after receiving the first data signal, evaluate the reception performance for the EQ training signal by changing the configuration of the equalizer in each of the plurality of time intervals according to the respective EQ configuration information, select the optimal EQ configuration information according to the evaluation result, and then configure the equalizer according to the optimal EQ configuration information.

[0026] The data processing device can send a first data signal to the data driving device via a low-speed data communication protocol, and can send the EQ training signal to the data driving device via a high-speed data communication protocol different from the low-speed data communication protocol.

[0027] The data processing device may send a communication signal having a communication frequency corresponding to the high-speed data communication protocol to the data driving device before sending the EQ training signal, and the data driving device may receive the communication signal, train the clock included in the communication signal by changing the configuration value of the oscillator included in the internal circuit at each predetermined time, and determine the optimal configuration value for the communication frequency based on the training result of the clock.

[0028] The configuration value may include any one of the reference current value, reference voltage value and gain of the oscillator.

[0029] The EQ training signal may include a training sequence repeated in each time interval, wherein the training sequence may include an interval signal for distinguishing each time interval from one another, an EQ clock training signal set at the end of the interval signal, and an EQ test signal set at the end of the EQ clock training signal. Moreover, in the interval signal receiving interval of a training sequence, the data driving device may initialize the clock trained in the training sequence preceding the training sequence, and in the EQ clock training signal receiving interval of the training sequence, the data driving device may perform clock training again.

[0030] When a signal with a predetermined voltage level is received during a predetermined time or longer, the data driving device can initialize the clock.

[0031] The data driving device can receive signals with predetermined voltage levels in each time interval for a predetermined time or longer to initialize the clock.

[0032] In another aspect, this disclosure provides a data processing apparatus, including: a control circuit for storing a plurality of EQ (equalizer) configuration information; and a communication circuit configured to generate a first data signal including the plurality of EQ configuration information, transmit the first data signal via a second communication protocol, and, after generating an EQ training signal for an equalizer of a data driving device, transmit an EQ training signal to the data driving device via the first communication protocol, wherein the first communication protocol is different from the second communication protocol.

[0033] The EQ training signal may include a training sequence repeated in each time interval, and the training sequence may include an interval signal for distinguishing each time interval from one another, an EQ clock training signal set at the end of the interval signal, and an EQ test signal set at the end of the EQ clock training signal.

[0034] The EQ training signal may include an interval signal having a predetermined voltage level, an EQ clock training signal set at the end of the interval signal, and an EQ test signal set at the end of the EQ clock training signal.

[0035] As described above, according to this disclosure, since the data driving device can automatically optimize the configuration of the equalizer, the accuracy of the equalizer configuration can be improved and the configuration of the equalizer can be executed efficiently.

Implementation Method

[0042] FIG1 is a diagram showing the configuration of a display device according to an embodiment.

[0043] Referring to FIG1, the display device 100 may include a display panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140, etc.

[0044] Multiple data lines DL and multiple gate lines GL can be arranged on the display panel 110, and multiple pixels can be arranged on the display panel 110. A pixel may include multiple subpixels SP. Here, a subpixel may be R (red), G (green), B (blue), and W (white), etc. A pixel may be configured as an RGB subpixel SP, an RGBG subpixel SP, or an RGBW subpixel SP, etc. In the following description, for ease of description, the case of a pixel including RGB subpixels will be described.

[0045] The data driving device 120, the gate driving device 130, and the data processing device 140 are devices for generating signals for displaying images on the display panel 110.

[0046] The gate drive device 130 can provide a gate drive signal having an on-state voltage or an off-state voltage to the gate line GL. When the gate drive signal with an on-state voltage is provided to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. Conversely, when the gate drive signal with an off-state voltage is provided to the sub-pixel SP, the connection between the sub-pixel SP and the data line DL is released. The gate drive device 130 may be referred to as a "gate driver".

[0047] The data driving device 120 can provide a data voltage Vp to the sub-pixel SP via the data line DL. The data voltage Vp provided to the data line DL can be provided to the sub-pixel SP according to the gate driving signal. The data driving device 120 can be referred to as a "source driver".

[0048] The data driving device 120 may include at least one integrated circuit, which may be connected to the bonding pads of the panel 110 by tape auto-bonding (TAB) or glass flip-chip (COG) type, or may be formed directly on the panel 110. According to an embodiment, the integrated circuit may be formed by integration onto the panel 110. Alternatively, the data driving device 120 may be implemented by thin-film flip-chip (COF) type.

[0049] The data processing device 140 can provide control signals to the gate drive device 130 and the data drive device 120. For example, the data processing device 140 can send a gate control signal GCS for starting scanning to the gate drive device 130. Additionally, the data processing device 140 can output image data to the data drive device 120. Furthermore, the data processing device 140 can send a data control signal for controlling the data drive device 120 to provide a data voltage Vp to each sub-pixel SP. The data processing device 140 can be referred to as a "timing controller".

[0050] Figure 2 is a diagram illustrating the configuration of the system according to an embodiment.

[0051] Referring to FIG2, the system may include at least one data processing device 140 and a plurality of data driving devices 120a, 120b, 120c and 120d.

[0052] The data processing device 140 may be disposed on the first printed circuit board (PCB) PCB1. In addition, the data processing device 140 may be connected to a plurality of data driving devices 120a, 120b, 120c and 120d via the first communication line LN1 and the second communication line LN2.

[0053] The first communication line LN1 and the second communication line LN2 can be guided to a plurality of data driving devices 120a, 120b, 120c and 120d via the first PCB PCB1 and the second PCB PCB2. The first PCB PCB1 and the second PCB PCB2 can be connected by a first film FL1 made of a flexible material, and the first communication line LN1 and the second communication line LN2 can extend from the first PCB PCB1 to the second PCB PCB2 via the first film FL1.

[0054] The data driving devices 120a, 120b, 120c and 120d can each be disposed on the second film FL2 in the form of a chip-on-film (COF). The second film FL2 can be a support substrate made of a flexible material for connecting the second PCB PCB2 to the panel 110, and the first communication line LN1 and the second communication line LN2 can extend through the second film FL2 to each of the data driving devices 120a, 120b, 120c and 120d on the second PCB PCB2.

[0055] The first communication line LN1 can be connected one-to-one with the data processing device 140 and the data driving devices 120a, 120b, 120c and 120d.

[0056] Furthermore, the second communication line LN2 can connect data driving devices 120a, 120b, 120c, and 120d to each other, or it can connect data driving device 120d to data processing device 140 without overlapping with the first communication line LN1 on the panel. For example, the first data driving device 120a can be connected to the second data driving device 120b via the second communication line LN2, and the second data driving device 120b can be connected to the third data driving device 120c via the second communication line LN2. In this case, the second data driving device 120b and the third data driving device 120c can be connected to different second PCBs PCB2. Therefore, the second communication line LN2 disposed therebetween can pass through the second PCB PCB2, the first film FL1, and the first PCB PCB1, thereby connecting the second data driving device 120b and the third data driving device 120c. The third data drive device 120c can be connected to the fourth data drive device 120d via the second communication line LN2, and the fourth data drive device 120d can be connected to the data processing device 140 via the second communication line LN2.

[0057] As described above, the data processing device 140 and the data driving devices 120a, 120b, 120c and 120d can communicate with each other via the first communication line LN1 and the second communication line LN2.

[0058] Here, the data processing device 140 can send image data to the data driving devices 120a, 120b, 120c and 120d via the first communication line LN1.

[0059] In an embodiment, the data driving devices 120a, 120b, 120c and 120d can automatically optimize the configuration of the equalizer using signals sent from the data processing device 140 before receiving image data from the data processing device 140.

[0060] On the other hand, as shown in FIG3, the data processing device 140 may include a data processing control circuit 342, a first data processing communication circuit 344, and a second data processing communication circuit 346.

[0061] In addition, the data driving device 120 may include a data driving control circuit 322, a first data driving communication circuit 324 and a second data driving communication circuit 326.

[0062] The first data processing communication circuit 344 and the first data driving communication circuit 324 can be connected via the first communication line LN1. In addition, the first data processing communication circuit 344 can send the main communication signal MLP to the first data driving communication circuit 324 via the first communication line LN1.

[0063] The second data processing communication circuit 346 and the second data driving communication circuit 326 can be connected via the second communication line LN2. In addition, the second data driving communication circuit 326 can send an auxiliary communication signal ALP to the second data processing communication circuit 346 via the second communication line LN2.

[0064] FIG4 is a diagram showing the configuration of a first data driving communication circuit according to an embodiment.

[0065] Referring to Figure 4, the first data driving communication circuit 324, i.e. the first communication circuit 324 of the data driving device 120, may include an equalizer 410, a clock recovery circuit 420, a byte aligning circuit 430, and a pixel aligning circuit 440.

[0066] The equalizer 410 can be connected to the first communication line LN1 and can control the main communication signal MLP received through the first communication line LN1.

[0067] Specifically, when the signal passes through the first communication line LN1, distortion may occur in the main communication signal MLP. This may lead to attenuation (or pulse dispersion) of the high-frequency components of the main communication signal MLP, as well as inter-symbol interference (ISI). The equalizer 410 can reproduce the high-frequency components in the distorted main communication signal MLP (or remove the pulse dispersion from it), thereby reducing inter-symbol interference.

[0068] The equalizer 410 can send the adjusted main communication signal MLP to the clock recovery circuit 420, the byte alignment circuit 430, and / or the pixel alignment circuit 440, thereby enhancing the receiving performance of the first communication circuit 324.

[0069] The equalizer 410 can adjust the main communication signal MLP according to the configuration.

[0070] For example, equalizer 410 can determine the amplification in the main communication signal MLP based on the configured gain. In other words, the configuration values ​​for configuring equalizer 410 can include the gain level for configuring the gain of equalizer 410.

[0071] The configuration value of equalizer 410 can be stored in data processing device 140.

[0072] In addition, when power is applied to the display device 100, the configuration values ​​of the equalizer 410 can be sent to the first data driving communication circuit 324 of the data driving device 120 via the first data processing communication circuit 344 of the data processing device 140.

[0073] The clock recovery circuit 420 can receive the clock pattern via the main communication signal MLP and perform clock training according to the clock pattern. In this case, the clock training performance of the clock recovery circuit 420 may be affected by the adjustment of the main communication signal MLP by the equalizer 410.

[0074] The byte alignment circuit 430 and the pixel alignment circuit 440 can train link clocks such as symbol clocks and pixel clocks based on link data, and can align image data in units of bytes (e.g., in units of symbols) and pixels based on the link clocks. Here, the link training performance or link recovery performance of the byte alignment circuit 430 and the pixel alignment circuit 440 may also be affected by the equalizer 410's adjustment of the main communication signal MLP.

[0075] As described above, the receiving performance of the first data driving communication circuit 324, the clock training performance of the clock recovery circuit 420, and the link training or link recovery performance of the byte alignment circuit 430 and the pixel alignment circuit 440 may be affected by the configuration of the equalizer 410.

[0076] Here, the main communication signal MLP received by the equalizer 410 via the first communication line LN1 may have distortions that occur therein depending on the characteristics of the first communication line LN1.

[0077] Furthermore, due to the surrounding environment (e.g., temperature rise within the display device 100, static electricity, etc.) and physical deterioration of the first communication line LN1, the characteristics of the first communication line LN1 may change frequently. Therefore, the signal distortion pattern in the main communication signal MLP may also change frequently.

[0078] As described above, if the signal distortion form in the main communication signal MLP changes frequently, the configuration of equalizer 410 must also be changed frequently to conform to the changed signal distortion form.

[0079] In this regard, in the embodiment, the configuration of equalizer 410 can be performed automatically by the following configuration.

[0080] Figures 5 and 6 are diagrams illustrating the signal sequence of the equalizer configuration in the first communication circuit according to an embodiment.

[0081] First, referring to FIG5, when the drive voltage VCC is provided to the data processing device 140 and the data driving device 120, the first data processing communication circuit 344 of the data processing device 140 can send the second protocol signal PS2 to the first data driving communication circuit 324 of the data driving device 120 within a predetermined time (e.g., in the command mode in FIG5).

[0082] After sending the second protocol signal PS2, the first data processing communication circuit 344 can send the first protocol signal PS1. For example, the first data processing communication circuit 344 can send the first protocol signal PS1 in the automatic training mode shown in FIG5.

[0083] Here, the second protocol signal PS2 or the first protocol signal PS1 is a main communication signal MLP transmitted via the first communication line LN1, and can be adjusted between the data processing device 140 and the data driving device 120 based on the second communication protocol and the first communication protocol.

[0084] Furthermore, the communication frequency of the first protocol signal PS1 can be ten times or more than ten times the communication frequency of the second protocol signal PS2. Based on this characteristic, the first protocol signal PS1 can be classified as a high-speed data communication protocol, and the second protocol signal PS2 can be classified as a low-speed data communication protocol.

[0085] Since high-speed data communication may have a higher data loss rate than low-speed data communication, the first data processing communication circuit 344 can send various configuration information of the data driving device 120 required for high-speed data communication to the first data driving communication circuit 324 via the second protocol signal PS2.

[0086] In other words, the data processing device 140 can send various configuration information of the data driving device 120 required for high-speed data communication to the data driving device 120 through low-speed data communication with low data loss rate, so that the data driving device 120 can accurately receive the configuration information.

[0087] In this embodiment, the data processing control circuit 342 of the data processing device 140 can store multiple equalizer (EQ) configuration information and can control the first data processing communication circuit 344. Here, the values ​​of the multiple EQ configuration information can be determined by performing multiple tests on the signal distortion of the frequently changing main communication signal MLP.

[0088] The first data processing communication circuit 344 can generate a second protocol signal PS2, which includes multiple EQ configuration information, under the control of the data processing control circuit 342.

[0089] In addition, the first data processing communication circuit 344 can send a second protocol signal PS2, which includes multiple EQ configuration information, to the first data driving communication circuit 324 in the CFG data interval of FIG5. Hereinafter, the second protocol signal PS2, which includes multiple EQ configuration information, will be referred to as the "first data signal".

[0090] In an embodiment, the plurality of EQ configuration information may include a plurality of gain levels that are different from each other for the equalizer 410. For example, if the plurality of EQ configuration information is first EQ configuration information and second EQ configuration information, the first EQ configuration information may include a first gain level, and the second EQ configuration information may include a second gain level that is different from the first gain level. Each of the plurality of EQ configuration information may also include a tap factor for the equalizer 410.

[0091] On the other hand, the first data drive communication circuit 324, which is connected to the first data processing communication circuit 344 via the first communication line LN1, can receive the first data signal via the second communication protocol. In addition, the data drive control circuit 322 can store multiple EQ configuration information in an auxiliary storage medium (e.g., a temporary register).

[0092] Here, in addition to multiple EQ configuration information, the first data signal may also include information related to the number of EQ configuration information. For example, if there are 8 EQ configuration information, the information related to the number may be "8". In addition, the first data signal may also include preset EQ configuration information, mixing code information, and linear polarity information, etc.

[0093] The data drive control circuit 322 can also store information related to the amount of EQ configuration information in an auxiliary storage medium, and can configure the equalizer 410 to a preset state using the first data signal. Additionally, other circuit components for high-speed data communication can be configured. Here, the preset EQ configuration information may include a preset gain level for the equalizer 410 for high-speed data communication, and the mixing information may include information indicating whether the data is mixed when the data processing device 140 sends data to the data drive device 120. Furthermore, the line polarity information may include information indicating the polarity of the first line in the pixel.

[0094] On the other hand, after the transmission and reception of the first data signal are completed, that is, after the end of the CFG data interval, the first data processing communication circuit 344 can, under the control of the data processing control circuit 342, send a second protocol signal PS2 including a termination message to the first data driving communication circuit 324 during the CFG complete interval. Here, the termination message can be a message indicating the termination of communication of the second protocol signal PS2, and the data driving control circuit 322 can recognize the termination message in the second protocol signal PS2 received from the first data driving communication circuit 324, and terminate the communication according to the second protocol (low-speed data communication protocol).

[0095] On the other hand, in the preamble interval before the CFG data interval, the second protocol signal PS2 may include a low-speed data communication clock signal, and the data driving device 120, i.e. the first data driving communication circuit 324, may use the low-speed data communication clock signal to perform training for the low-speed data communication clock.

[0096] Here, the auxiliary communication signal ALP can be maintained at a low voltage level until clock training for the low-speed data communication clock is completed, and can be changed to a high voltage level when the clock training is completed. In other words, after the drive voltage VCC is supplied, the second data drive communication circuit 326 can maintain the auxiliary communication signal ALP at a low voltage level under the control of the data drive control circuit 322, and can switch the auxiliary communication signal ALP to a high voltage level when clock training for the low-speed data communication clock is completed in the preamble interval. In addition, the first data processing communication circuit 344 can send the first data signal after the auxiliary communication signal ALP changes to a high voltage level. Here, the auxiliary communication signal ALP can be called a "lock signal", and can be sent to the second data processing communication circuit 346 via the second communication line LN2 in FIG2.

[0097] If an internal anomaly exists, or if an unplanned communication error occurs after the auxiliary communication signal ALP is changed to a high voltage level, the data drive control circuit 322 can change the auxiliary communication signal ALP to a low voltage level. For example, if no signal is received in the CFG data interval or the CFG completion interval, or if the clock is corrupted, the data drive device 120 can change the auxiliary communication signal ALP to a low voltage level.

[0098] As described above, after the low-speed data communication between the data processing device 140 and the data driving device 120 terminates, the first data processing communication circuit 344 can generate an EQ training signal as a first protocol signal, and can send the EQ training signal to the first data driving communication circuit 324 via the first communication line LN1. Here, the first data processing communication circuit 344 can send the EQ training signal during multiple time intervals (EQ training intervals).

[0099] In an embodiment, as shown in FIG5, the EQ training signal may include a training sequence repeated for each time interval. Furthermore, the training sequence may be configured as an interval signal H having a predetermined voltage level (e.g., a high voltage level), an EQ clock training signal EQCP located at the end of the interval signal (blank signal), and an EQ test signal EQTP located at the end of the EQ clock training signal EQCP. Here, the interval signal H may be a signal used to distinguish between the time intervals.

[0100] The EQ test signal EQTP can include a pseudo-random binary sequence (PRBS) mode. Here, the PRBS mode can be implemented as PRBS7 mode, PRBS9 mode, and PRBS10 mode, etc.

[0101] The EQ test signal EQTP may include test data encoded by the DC balanced code method. Here, the test data encoded by the DC balanced code method may include multiple code groups having the same number of "0"s and "1"s.

[0102] The first data-driven communication circuit 324 can receive EQ training signals during multiple time intervals. Here, the EQ training signals may be distorted when passing through the first communication line LN1.

[0103] When the first data-driven communication circuit 324 receives an EQ training signal, the data-driven control circuit 322 can change the configuration of the equalizer 410 according to multiple EQ configuration information for each time interval during multiple time intervals. Here, the data-driven control circuit 322 can evaluate the reception performance of the first data-driven communication circuit 324 for the EQ training signal by changing the configuration of the equalizer 410 for each of the multiple time intervals.

[0104] In addition, the best configuration information can be selected from multiple EQ configuration information based on the evaluation results of each time interval.

[0105] For example, if there are N time intervals (where N is a natural number), and if the EQ training signal includes the first training sequence to the Nth training sequence, then the first data-driven communication circuit 324 can receive the first training sequence in the first time interval. In this case, during the interval TEQ_Setup where the first data-driven communication circuit 324 receives the interval signal H of the first training sequence, the data-driven control circuit 322 can use the first EQ configuration information from a plurality of EQ configuration information to configure the equalizer 410.

[0106] Subsequently, the first data-driven communication circuit 324 can perform clock training for testing the equalizer 410 within the interval TEQ_CT of the EQ clock training signal EQCP received from the first training sequence. Here, the clock training can be performed by the clock recovery circuit 420.

[0107] The first data-driven communication circuit 324, which has recovered the clock through clock training, can receive the EQ test signal EQTP by using the equalizer 410 configured with the first EQ configuration information, and can recover the data in the EQ test signal EQTP. Here, data recovery can be performed by the byte alignment circuit 430 and the pixel alignment circuit 440.

[0108] If the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can check whether the PRBS mode included in the recovered data matches the previously stored bit stream during the reception time TEQ_Test of the EQ test signal EQTP, and can identify the bit error rate of the EQ test signal EQTP accordingly.

[0109] If the EQ test signal EQTP includes test data encoded using the DC balanced code method, the data drive control circuit 322 can identify the number of "0"s and "1"s in the code group of the recovered data during the reception time TEQ_Test of the EQ test signal EQTP, and can thereby identify whether there is a data error in the EQ test signal EQTP. Here, the DC balanced code method can be an 8B10B encoding / decoding method.

[0110] The data drive control circuit 322 can evaluate the receiving performance of the first data drive communication circuit 324 for the first EQ configuration information by using the bit error rate of the EQ test signal as described above or information related to whether there are data errors in the EQ test signal.

[0111] After the first training sequence is completed, the first data driving communication circuit 324 can receive the second training sequence during the second time interval.

[0112] When the first data-driven communication circuit 324 receives the interval signal H of the second training sequence, the data-driven control circuit 322 can identify the start of the second time interval and can use the second EQ configuration information from multiple EQ configuration information to configure the equalizer 410. In other words, the equalizer 410 configured as the first EQ configuration information can be changed to be configured as the second EQ configuration information.

[0113] The first data driving communication circuit 324 can initialize the clock recovered in the first training sequence in the interval signal receiving interval of the second training sequence.

[0114] Thereafter, the first data-driven communication circuit 324 and the data-driven control circuit 322 can use the EQ clock training signal and EQ test signal of the second training sequence to perform clock retraining and to evaluate the receiving performance of the first data-driven communication circuit 324.

[0115] As described above, if the clock is initialized by the interval signal H in each training sequence, the clock recovery performance in each training sequence can be equal, so the evaluation of the receiving performance of the first data-driven communication circuit 324 can be performed more accurately.

[0116] On the other hand, when clock initialization and clock retraining are performed by the first data driving communication circuit 324, the lock signal sent from the second data driving communication circuit 326 to the second data processing communication circuit 346 can be maintained at the existing voltage level (e.g., high voltage level).

[0117] Generally, when the first data driving communication circuit 324 initializes the clock, the lock signal changes from a high voltage level to a low voltage level. Here, as described above, if clock initialization and clock retraining are performed for each of the multiple time intervals, the voltage level of the lock signal must also be changed for each time interval. In this case, frequent changes in the voltage level of the lock signal may increase the possibility of errors occurring when transmitting the lock signal. Therefore, in the embodiment, the voltage level of the lock signal can be maintained at an existing voltage level (e.g., a high voltage level), regardless of the clock initialization and clock retraining described above, thereby reducing the possibility of errors occurring when transmitting the lock signal.

[0118] The data-driven control circuit 322 can evaluate the receiving performance of the first data-driven communication circuit 324 for each of the multiple EQ configuration information by repeatedly performing the above process for each of the multiple time intervals.

[0119] In addition, the data drive control circuit 322 can select the EQ configuration information that can achieve the best reception performance from multiple EQ configuration information as the best EQ configuration information, and can complete the configuration of equalizer 410 according to the best EQ configuration information.

[0120] The data-driven control circuit 322 can identify the number of time intervals using previously stored information related to the amount of EQ configuration information. In other words, the data-driven control circuit 322 can identify the number of repetitions of the training sequence included in the EQ training signal using information related to the amount of EQ configuration information.

[0121] For example, if the information related to the number of EQ configuration information is "8", then the data-driven control circuit 322 can identify the number of time intervals, that is, it can identify that the training sequence shown in FIG5 is repeated 8 times. Therefore, the data-driven control circuit 322 can change the configuration of the equalizer 410 for each of the eight time intervals according to the multiple equalizer configuration information, and then can terminate the operation of changing the configuration of the equalizer 410.

[0122] When the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can select the EQ configuration information corresponding to the time interval with the minimum bit error rate from multiple time intervals as the optimal EQ configuration information.

[0123] When the EQ test signal EQTP includes test data encoded by the DC balanced code method, the data drive control circuit 322 can select the EQ configuration information corresponding to the time interval with the fewest errors in the test data from multiple time intervals as the optimal EQ configuration information.

[0124] As described above, when the data driving device 120 completes the configuration of the equalizer 410 according to the optimal EQ configuration information, the data processing control circuit 342 can process the image data and can send the image data to the first data driving communication circuit 324 through the first data processing communication circuit 344.

[0125] In other words, the data processing device 140 and the data driving device 120 can perform communication (display mode) to receive image data.

[0126] Above, the configuration of the training sequence including repeating the EQ training signal in each time interval has been described, that is, the configuration of repeating the interval signal, the EQ training signal and the EQ test signal in each time interval.

[0127] In the following text, the configuration of the EQ training signal, which includes an interval signal, an EQ clock training signal, and an EQ test signal, will be described.

[0128] Referring to FIG6, as described above, after the low-speed data communication between the data processing device 140 and the data driving device 120 terminates, the first data processing communication circuit 344 can generate an EQ training signal as a first protocol signal, and can send the EQ training signal to the first data driving communication circuit 324 via the first communication line LN1. Here, the first data processing communication circuit 344 can send the EQ training signal during multiple time intervals (EQ training intervals).

[0129] In an embodiment, as shown in FIG6, the EQ training signal can be configured as an interval signal H having a predetermined voltage level (e.g., a high voltage level), an EQ clock training signal EQCP set at the end of the interval signal H, and an EQ test signal EQTP set at the end of the EQ clock training signal EQCP.

[0130] In Figure 5, the EQ training signal has a pattern of repeating the interval signal H, the EQ clock training signal EQCP, and the EQ test signal EQTP for each time interval in multiple time intervals. In Figure 6, the EQ training signal can be configured such that the interval signal H lasts for a first time TIDLE, then the EQ clock training signal EQCP lasts for a second time TEQ_CT, and the EQ test signal EQTP lasts for a third time TEQ_T.

[0131] In other words, in the embodiments, instead of repeating the EQ training sequence in each time interval, the EQ training signal may have a pattern that includes an EQ training sequence.

[0132] Here, the third time TEQ_TEST_1 to TEQ_TEST_N can be longer than the first time TIDLE and the second time TEQ_CT.

[0133] In Figure 6, the EQ test signal EQTP can also include a pseudo random binary sequence (PRBS) pattern.

[0134] In addition, the EQ test signal EQTP may include test data encoded by the DC balanced code method.

[0135] On the other hand, when the first data-driven communication circuit 324 receives the EQ training signal, the data-driven control circuit 322 can change the configuration of the equalizer 410 at or after the start of the third time TEQ_T based on multiple EQ configuration information. Here, the data-driven control circuit 322 can store unit time interval information and can determine the third time in advance by multiplying the information related to the number of EQ configuration information by the unit time interval information.

[0136] In addition, the data drive control circuit 322 can subdivide the third time into multiple time intervals.

[0137] For example, if the information related to the quantity of EQ configuration information is "8", and if the unit time interval information is 5ms, then the data drive control circuit 322 can determine the third time as 40ms.

[0138] In addition, the data drive control circuit 322 can subdivide the third time into eight time intervals.

[0139] Subsequently, the data-driven control circuit 322 can change the configuration of the equalizer 410 according to multiple EQ configuration information for each of the multiple time intervals TEQ_TEST_1 to TEQ_TEST_N. Here, the data-driven control circuit 322 can evaluate the reception performance of the first data-driven communication circuit 324 for the EQ training signal by changing the configuration of the equalizer 410 for each time interval.

[0140] In addition, the data drive control circuit 322 can select the best EQ configuration information from multiple EQ configuration information based on the evaluation results for each time interval.

[0141] For example, if the EQ training signal includes a first time TIDLE, a second time TEQ_CT, and a third time TEQ_T, and if the third time is divided into a first time interval TEQ_TEST_1 to an Nth time interval TEQ_TEST_N, then the first data-driven communication circuit 324 can receive the interval signal H during the first time TIDLE. The data-driven control circuit 322 can remain idle during the first time TIDLE.

[0142] Thereafter, the first data-driven communication circuit 324 can receive the EQ clock training signal EQCP during the second time TEQ_CT, and can perform clock training for testing the equalizer 410. Here, the clock training can be performed by the clock recovery circuit 420.

[0143] In addition, the first data driving communication circuit 324 can receive the EQ test signal EQTP during the third time TEQ_T.

[0144] Here, the data drive control circuit 322 can use the first EQ configuration information among multiple EQ configuration information to configure the equalizer 410 at the time when the first time interval TEQ_TEST_1 begins.

[0145] In addition, the first data driving communication circuit 324 can receive the EQ test signal EQTP by the equalizer 410 configured with the first EQ configuration information during the first time interval TEQ_TEST_1, and can recover data based on the EQ test signal EQTP. Here, data recovery can be performed by the byte alignment circuit 430 and the pixel alignment circuit 440.

[0146] When the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can check whether the PRBS mode included in the recovered data for the first time interval TEQ_TEST_1 matches the previously stored bit stream, and can thereby identify the bit error rate of the EQ test signal EQTP received during the first time interval TEQ_TEST_1.

[0147] If the EQ test signal EQTP includes test data encoded using the DC balanced code method, the data drive control circuit 322 can identify the number of "0"s and "1"s in the code group of the recovered data during the first time interval TEQ_TEST_1, and can thereby identify whether there is a data error in the EQ test signal EQTP received during the first time interval TEQ_TEST_1. Here, the DC balanced code method can be an 8B10B encoding / decoding method.

[0148] The data drive control circuit 322 can evaluate the receiving performance of the first data drive communication circuit 324 for the first EQ configuration information by using the bit error rate of the EQ test signal as described above or information related to whether there are data errors in the EQ test signal.

[0149] After the first time interval TEQ_TEST_1, the data drive control circuit 322 can use the second EQ configuration information to configure the equalizer 410 at the beginning of the second time interval TEQ_TEST_2.

[0150] In addition, the first data driving communication circuit 324 can receive the EQ test signal by using the equalizer 410 configured with the second EQ configuration information during the second time interval TEQ_TEST_2, and can recover data based on the EQ test signal EQTP.

[0151] When the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can check whether the PRBS mode included in the recovered data of the second time interval TEQ_TEST_2 matches the previously stored bit stream, and can thereby identify the bit error rate of the EQ test signal EQTP received during the second time interval TEQ_TEST_2.

[0152] If the EQ test signal EQTP includes test data encoded using the DC balanced code method, the data drive control circuit 322 can identify the number of "0" and "1" in the code group of the recovered data during the second time interval TEQ_TEST_2, and can thereby identify whether there is a data error in the EQ test signal EQTP received during the second time interval TEQ_TEST_2.

[0153] The data drive control circuit 322 can evaluate the receiving performance of the first data drive communication circuit 324 for the second EQ configuration information by using the bit error rate of the EQ test signal as described above or information related to whether there are data errors in the EQ test signal.

[0154] The data-driven control circuit 322 can evaluate the receiving performance of the first data-driven communication circuit 324 for each EQ configuration information in the multiple EQ configuration information by repeatedly performing the above processing for each interval subdivided from the third time TEQ_T.

[0155] In addition, the data drive control circuit 322 can select the EQ configuration information that can achieve the best reception performance from multiple EQ configuration information as the best EQ configuration information, and can complete the configuration of the equalizer 410 according to the best EQ configuration information.

[0156] The data driving device 120 (which has configured the equalizer 410 according to the optimal EQ configuration information as described above) can perform communication (display mode) for receiving image data from the data processing device 140.

[0157] As described above, when power is applied to the display device 100, the data driving device 120 can evaluate the reception performance for the EQ training signal by changing the configuration of the equalizer 410 for each time interval according to multiple EQ configuration information, and can configure the equalizer 410 using the EQ configuration information that achieves the best reception performance from among the multiple EQ configuration information. Therefore, when power is applied, the configuration of the equalizer 410 can be automatically optimized according to the signal distortion form of the main communication signal MLP, wherein the signal distortion form of the main communication signal MLP changes according to the characteristics of the first communication line LN1.

[0158] On the other hand, in the embodiment, when the data processing device 140 and the data driving device 120 send and receive the second protocol signal PS2, the communication frequency of the second protocol signal PS2, i.e. the communication frequency of low-speed data communication, can be predetermined.

[0159] In addition, the clock recovery circuit 420, which is an internal circuit of the data drive device 120, can be configured to conform to the communication frequency of the second protocol signal PS2.

[0160] On the other hand, the communication frequency of the first protocol signal PS1, i.e. the communication frequency of high-speed data communication, may not be predetermined.

[0161] Therefore, before sending and receiving the EQ training signal as the first protocol signal PS1, the data processing device 140 and the data driving device 120 can configure their internal circuits to conform to the communication frequency of the first protocol signal PS1 by means of the pre-clock training interval shown in FIG7.

[0162] Specifically, the data processing device 140 may send a first protocol signal PS1, including the training clock pattern TR_CLK, to the data driving device 120 during the pre-clock training interval. Hereinafter, the first protocol signal PS1 sent to the data driving device 120 during the pre-clock training interval will be referred to as the "communication signal".

[0163] The data driving device 120 can subdivide the pre-clock training interval into multiple time intervals (e.g., T1 to Tn in FIG7), and perform training for the training clock pattern TR_CLK included in the communication signal by changing the configuration value of the oscillator (not shown) included in the clock recovery circuit 420 for each subdivided time interval.

[0164] In addition, the data driving device 120 can select the optimal configuration value based on the training result of the training clock pattern TR_CLK, and can use the optimal configuration value to configure the oscillator (not shown). The configuration value of the oscillator (not shown) may include any one of the reference current value, reference voltage value, and gain of the oscillator (not shown).

[0165] Here, the oscillator (not shown) is a circuit whose characteristics change according to the communication frequency, and if any of the reference current, reference voltage and gain of the oscillator (not shown) are changed, the frequency of the oscillation signal output from the oscillator (not shown) may also change.

[0166] This oscillation signal can be used to train the clock pattern TR_CLK.

[0167] Therefore, in the embodiment, the oscillator (not shown) can be configured with the optimal configuration value by means of the above configuration, so that the clock recovery circuit 420 can operate in a manner that conforms to the communication frequency of the first agreement signal PS1.

[0168] The processing of the equalizer 410 in the configuration data drive device 120 will be described below.

[0169] FIG8 is a flowchart illustrating the process for configuring an equalizer in a data driving device according to an embodiment.

[0170] Referring to Figure 8, when the drive voltage VCC is supplied to the data processing device 140 and the data driving device 120, the data driving device 120 can receive a first data signal from the data processing device 140 (S810). This first data signal is a second protocol signal PS2 that includes multiple EQ configuration information. Here, the multiple EQ configuration information may include different gain levels of the equalizer 410, and the first data signal can be transmitted via the first communication line LN1. In addition, the first data signal may also include information related to the number of EQ configuration information.

[0171] The data drive device 120 can store multiple EQ configuration information included in the first data signal (S820).

[0172] Thereafter, the data driving device 120 can receive the EQ training signal as the first protocol signal PS1 from the data processing device 140 (S830). Here, the EQ training signal may include a training sequence repeated in each time interval as shown in FIG5, and the training sequence may be configured as an interval signal H having a predetermined voltage level (e.g., a high voltage level), an EQ clock training signal EQCP set at the end of the interval signal H, and an EQ test signal EQTP set at the end of the EQ clock training signal EQCP.

[0173] Additionally, as shown in FIG6, the EQ training signal can be configured as an interval signal H having a predetermined voltage level (e.g., a high voltage level), an EQ clock training signal EQCP set at the end of the interval signal H, and an EQ test signal EQTP set at the end of the EQ clock training signal EQCP.

[0174] The data driving device 120 can change the configuration of the equalizer 410 according to multiple EQ configuration information for each predetermined time interval, and can evaluate the reception performance of the EQ training signal for each predetermined time interval (S840 and S850). Here, when the EQ training signal includes a training sequence, the data driving device 120 can change the configuration of the equalizer 410 at or after the time when the EQ training signal is first received.

[0175] In addition, when the EQ training signal includes an interval signal H, an EQ clock training signal EQCP and an EQ test signal EQTP, the data driving device 120 can change the configuration of the equalizer 410 at or after the time when the EQ test signal EQTP is received.

[0176] The data driving device 120 may repeat steps S840 and S850 until the reception of the EQ training signal is terminated (S860).

[0177] When the reception of the EQ training signal is terminated, the data driving device 120 can select the best EQ configuration information from multiple EQ configuration information based on the evaluation results for each time interval (S870).

[0178] Thereafter, the data drive device 120 can configure the equalizer (S880) using the optimal EQ configuration information. Accordingly, the data drive device 120 can appropriately cancel the signal distortion of the main communication signal MLP transmitted via the first communication line LN1.

[0179] Cross-reference to related applications

[0180] This application claims priority to Korean Patent Application No. 10-2020-0052575, filed on April 29, 2020, which is incorporated herein by reference. [Simplified Explanation of the Diagram]

[0036] FIG1 is a diagram showing the configuration of a display device according to an embodiment.

[0037] Figures 2 and 3 are diagrams illustrating the configuration of the system according to an embodiment.

[0038] Figure 4 is a diagram showing the configuration of the first data driving communication circuit according to an embodiment.

[0039] Figures 5 and 6 are diagrams illustrating the signal sequence for configuring the equalizer of the first data driving communication circuit according to an embodiment.

[0040] Figure 7 is a diagram illustrating the signal sequence for further configuring the first data driving communication circuit according to an embodiment.

[0041] FIG8 is a flowchart illustrating the process for configuring an equalizer in a data driving device according to an embodiment.

Claims

1. A data driving device, comprising: A communication circuit includes an equalizer and is configured to receive a first data signal containing a plurality of equalizer configuration information for configuring the equalizer, and then receive an equalizer training signal during a plurality of time intervals; and a control circuit is configured to evaluate the reception performance of the communication circuit for the equalizer training signal in each of the plurality of time intervals by changing the configuration of the equalizer according to the respective equalizer configuration information in each time interval, and select one equalizer configuration information from the plurality of equalizer configuration information according to the evaluation result; wherein each equalizer configuration information in the plurality of equalizer configuration information includes a gain level of the equalizer, and the control circuit sets the gain level of the equalizer differently in each time interval according to the respective equalizer configuration information.

2. The data driving device according to claim 1, wherein, The first data signal also includes information related to the quantity of equalizer configuration information, and the control circuit identifies the quantity of the time interval by means of the information related to the quantity of equalizer configuration information.

3. The data driving device according to claim 1, wherein, The communication circuit receives the first data signal via a low-speed data communication protocol and receives the equalizer training signal via a high-speed data communication protocol different from the low-speed data communication protocol.

4. The data driving device according to claim 1, wherein, The equalizer training signal includes a training sequence repeated in each time interval, and the training sequence includes an interval signal for distinguishing the time intervals from each other, an equalizer clock training signal set at the end of the interval signal, and an equalizer test signal set at the end of the equalizer clock training signal.

5. The data driving device according to claim 4, wherein, In the interval signal receiving interval of the training sequence, the communication circuit initializes the clock trained in the training sequence preceding the training sequence, and in the equalizer clock training signal receiving interval of the training sequence, the communication circuit performs clock training again.

6. The data driving device according to claim 5, wherein, The first data signal and the equalizer training signal are sent from the data processing device, and when the clock is initialized and clock training is performed again, the voltage level of the lock signal sent from the data driving device to the data processing device is maintained at a constant level.

7. The data driving device according to claim 4, wherein, The equalizer test signal includes a pseudo-random binary sequence pattern, and the control circuit calculates the bit error rate for the pseudo-random binary sequence pattern in each time interval, and selects the equalizer configuration information corresponding to the time interval with the minimum bit error rate among the multiple time intervals as the optimal equalizer configuration information.

8. The data driving device according to claim 4, wherein, The equalizer test signal includes test data encoded using a DC balanced code method, and the control circuit checks whether there are any errors in the test data in each time interval, and selects the equalizer configuration information corresponding to the time interval with the smallest number of errors in the test data among the plurality of time intervals as the optimal equalizer configuration information.

9. The data driving device according to claim 4, wherein, When the communication circuit receives the interval signal, the control circuit changes the configuration of the equalizer.

10. The data driving device according to claim 4, wherein, When a signal with a predetermined voltage level is received during a predetermined time or longer, the communication circuit initializes the clock and maintains the interval signal at a constant voltage level during the predetermined time.

11. A data driving device, comprising: A communication circuit includes an equalizer and is configured to receive a first data signal and then receive an equalizer training signal. The first data signal includes a plurality of equalizer configuration information for configuring the equalizer. The equalizer training signal includes an interval signal having a predetermined voltage level, an equalizer clock training signal located at the end of the interval signal, and an equalizer test signal located at the end of the equalizer clock training signal. A control circuit is configured to divide the reception time of the equalizer test signal into a plurality of time intervals when the communication circuit receives the equalizer test signal. The control circuit evaluates the reception performance of the communication circuit for the equalizer training signal in each of the plurality of time intervals by changing the configuration of the equalizer in each time interval according to the respective equalizer configuration information, and selects one equalizer configuration information from the plurality of equalizer configuration information based on the evaluation result. The equalizer configuration information includes the gain level of the equalizer, and the control circuit sets the gain level of the equalizer differently in each time interval according to the equalizer configuration information.

12. The data driving device according to claim 11, wherein, The first data signal also includes information relating to the quantity of equalizer configuration information, and wherein the control circuit determines the quantity of the time intervals to match the quantity of equalizer configuration information.

13. A data-driven system, comprising: A data processing apparatus is configured to generate a first data signal including a plurality of equalizer configuration information, transmit the first data signal, generate an equalizer training signal, and transmit the equalizer training signal during a plurality of time intervals, wherein the equalizer configuration information is configuration information of an equalizer; and a data driving apparatus includes the equalizer and is configured to receive the equalizer training signal during the plurality of time intervals after receiving the first data signal, evaluate the reception performance for the equalizer training signal by changing the configuration of the equalizer in each of the plurality of time intervals according to the respective equalizer configuration information, select a selected equalizer configuration information from the plurality of equalizer configuration information according to the evaluation result, and then configure the equalizer according to the selected equalizer configuration information; wherein the equalizer training signal includes a training sequence repeated in each time interval, and the training sequence includes an interval signal for distinguishing the time intervals from each other, an equalizer clock training signal set at the end of the interval signal, and an equalizer test signal set at the end of the equalizer clock training signal. The equalizer configuration information includes the gain level of the equalizer, and the control circuit sets the gain level of the equalizer differently in each time interval according to the equalizer configuration information.

14. The data-driven system according to claim 13, wherein, The data processing device sends the first data signal to the data driving device via a low-speed data communication protocol, and sends the equalizer training signal to the data driving device via a high-speed data communication protocol different from the low-speed data communication protocol.

15. The data-driven system according to claim 14, wherein, Before sending the equalizer training signal, the data processing device sends a communication signal having a communication frequency corresponding to the high-speed data communication protocol to the data driving device, and the data driving device receives the communication signal, trains the clock included in the communication signal by changing the configuration value of the oscillator included in the internal circuit at each predetermined time, and determines the configuration value for the communication frequency based on the training result of the clock.

16. The data-driven system according to claim 15, wherein, The configuration values ​​include any one of the oscillator's reference current value, reference voltage value, and gain.

17. The data-driven system according to claim 13, wherein, The equalizer training signal includes a training sequence repeated in each time interval, wherein the training sequence includes an interval signal for distinguishing the time intervals from each other, an equalizer clock training signal set at the end of the interval signal, and an equalizer test signal set at the end of the equalizer clock training signal. In the interval signal receiving interval of the training sequence, the data driving device initializes the clock trained in the training sequence preceding the training sequence, and in the equalizer clock training signal receiving interval of the training sequence, the data driving device performs clock training again.

18. The data-driven system according to claim 13, wherein, When a signal with a predetermined voltage level is received during a predetermined time or longer, the data driving device initializes the clock.

19. The data-driven system according to claim 18, wherein, The data driving device receives a signal with the predetermined voltage level during the predetermined time or longer in each time interval to initialize the clock.

20. A data driving device, comprising: A communication circuit includes an equalizer and is configured to receive a first data signal containing a plurality of equalizer configuration information for configuring the equalizer, and then receive an equalizer training signal during a plurality of time intervals; and a control circuit configured to evaluate the reception performance of the communication circuit for the equalizer training signal in each of the plurality of time intervals by changing the configuration of the equalizer according to the respective equalizer configuration information in each time interval, and to select one equalizer configuration information from the plurality of equalizer configuration information based on the evaluation result; wherein the first data signal and the equalizer training signal are transmitted from a data processing device, and the voltage level of a lock signal transmitted from the data driving device to the data processing device is maintained constant during clock initialization and clock retraining, wherein each equalizer configuration information in the plurality of equalizer configuration information includes a gain level of the equalizer, and the control circuit sets the gain level of the equalizer differently in each time interval according to the respective equalizer configuration information.

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