Semiconductor device

Abstract

A semiconductor device includes a first semiconductor layer, a second semiconductor layer including an active region, a dielectric layer having a first surface, a trench located in the dielectric layer, and an electrical connector located on the first surface. The active region is connected to the first semiconductor layer, the first semiconductor layer or the active region is located in the trench, and the electrical connector is connected to the second semiconductor layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a group III-V semiconductor diode device for emitting or absorbing light. Prior Technology

[0002] Currently, in the semiconductor field, silicon-based devices have a more mature manufacturing process advantage, while group III-V semiconductor devices possess material properties such as high carrier mobility or special optoelectronic performance. However, due to lattice matching issues, combining group III-V semiconductor devices and silicon-based semiconductor devices into optoelectronic integrated circuits (OEICs) presents many difficulties. With advancements in module chip bonding or die bonding technologies, the electrical signal transmission distance between devices has been reduced to the order of approximately 10² µm, enabling widespread applications in fields such as screen displays, sensing devices, augmented reality (AR), and virtual reality (VR). Summary of the Invention

[0003] The present invention provides a semiconductor device comprising a first semiconductor layer, a second semiconductor layer including an active region, a dielectric layer, a trench, and an electrical connector. The dielectric layer has a first surface; the trench is located in the dielectric layer, the first semiconductor layer or the active region is located in the trench, and the electrical connector is located on the first surface; wherein the active region connects the first semiconductor layer and the second semiconductor layer, and the electrical connector connects the second semiconductor layer.

[0004] The present invention provides a semiconductor device comprising a substrate, a semiconductor element as described above, and a transistor; the substrate includes a first sublayer, the transistor includes a fin, and the first sublayer and the fin are made of the same material. Simple Explanation of the Diagram

[0005] Figures 1A to 1H are cross-sectional views of the manufacturing process of a semiconductor device according to one embodiment of the present invention.

[0006] Figures 1I to 1J are cross-sectional views of a portion of the manufacturing process of a semiconductor device according to one embodiment of the present invention.

[0007] Figures 1K to 1N are cross-sectional views of a portion of the manufacturing process of a semiconductor device according to one embodiment of the present invention.

[0008] Figures 2A to 2H are top views of the manufacturing process flow of the semiconductor device corresponding to Figures 1A to 1H in one embodiment of the present invention.

[0009] Figure 3A is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0010] Figure 3B is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0011] Figure 3C is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0012] Figure 3D is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0013] Figure 4 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0014] Figure 5 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0015] Figure 6 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0016] Figure 7 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0017] Figure 8 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0018] Figure 9 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0019] Figure 10 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0020] Figure 11 is a cross-sectional view of a semiconductor element according to one embodiment of the present invention.

[0021] Figure 12 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0022] Figures 13A to 13D are cross-sectional views of a semiconductor device in one of the process embodiments of the present invention.

[0023] Figure 14 is a perspective view of a semiconductor device according to one embodiment of the present invention. Implementation

[0024] The concept of this invention will be illustrated with embodiments and accompanying drawings. In the drawings or description, similar or identical components will be represented by the same reference numerals. The shape, thickness, or height of elements, components, and devices in the drawings may be enlarged or reduced within reasonable limits. The embodiments listed in this invention are merely illustrative and not intended to limit the scope of the invention. Any obvious modifications or alterations made to this invention do not depart from the spirit and scope of the invention.

[0025] For ease of understanding, each embodiment in the drawings is accompanied by Cartesian coordinates for the X, Y, and Z axes. These Cartesian coordinates are used to illustrate the spatial relative relationships between components in the various embodiments of the present invention. Unless otherwise specified, in each embodiment, "horizontal" means that the component can be located in any positive or negative direction and magnitude of the X or Y axis in the figure; "vertical" means that the component can be located in any positive or negative direction and magnitude of the Z axis in the figure; "up" and "down" refer to the one-dimensional relative relationship between components on the Z axis after multiple components are projected onto the Z axis. The relative relationship on the Z axis can also be obtained by projecting a three-dimensional object. "Up" generally means that an object has a more positive coordinate value on the Z axis than a set basis or reference object; "down" generally means that an object has a more negative coordinate value on the Z axis than a set basis. "Correspondence" or "overlap" generally refers to the overlap of the areas formed by two objects projected onto an XY plane. A series of chemical formulas includes compounds that conform to stoichiometry and those that do not. For example, compounds that conform to stoichiometry have the same total elemental dose as group III elements and the same total elemental dose as group V elements; conversely, compounds that do not conform to stoichiometry have different total elemental doses as group III elements and different total elemental doses as group V elements. For instance, the AlGaAs series of chemical formulas represents compounds containing group III elements aluminum (Al) and / or gallium (Ga), and group V elements arsenic (As). The total elemental dose of group III elements (aluminum and / or gallium) can be the same as or different from the total elemental dose of group V elements (arsenic).

[0026] Figures 1A to 1H are cross-sectional views of the manufacturing process of semiconductor element 10A according to one embodiment of the present invention. Figures 2A to 2H are top views corresponding to Figures 1A to 1H. Semiconductor element 10A may be a light-emitting element (e.g., a light-emitting diode or laser diode), a light-absorbing element (e.g., a photodetector or solar cell), or a non-light-emitting element.

[0027] In the process step shown in Figure 1A, a substrate 1 is provided. The substrate 1 includes a base layer 12 and a first sublayer 14. The base layer 12 has a bottom surface 121 and an upper surface 123 opposite to the bottom surface 121. The base layer 12 is connected to the first sublayer 14 via its upper surface 123. In one embodiment, the substrate 1 may include only the base layer 12 or the first sublayer 14. As shown in Figure 2A, the substrate 1 may have different shapes in its top view depending on design, process, or other practical requirements, such as circular, polygonal, or irregular shapes. In this embodiment, the substrate 1 is quadrilateral.

[0028] As shown in Figure 1B, a dielectric layer 2 is deposited on substrate 1 using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other techniques. More specifically, the dielectric layer 2 is located on the first sublayer 14. Figure 2B, corresponding to Figure 1B, shows that, viewed from above, the first sublayer 14 is completely covered by the dielectric layer 2; that is, the first sublayer 14 and the dielectric layer 2 have the same top-view area. The dielectric layer 2 may selectively undergo a thermal oxidation process to obtain better insulating properties. In another embodiment, as shown in Figure 1A, a thicker first sublayer 14 may be formed, and the first sublayer 14 may be thermally oxidized so that part or all of the first sublayer 14 becomes the dielectric layer 2. For example, the first sublayer 14 may be silicon (Si), and the dielectric layer 2 may be silicon dioxide (SiO2).

[0029] In the process steps shown in Figures 1C and 2C, a plurality of trenches 3 are formed in the dielectric layer 2 by patterning on a first surface S1 away from the substrate layer 12 using nanoimprint lithography (NIL). Each trench 3 has a first opening 322 and exposes a second surface S2 of the first sublayer 14 away from the substrate layer 12. In one embodiment, the second surface S2 of the first sublayer 14 has a (111) crystal plane, and each trench 3 has a trench sidewall 31, and the trench sidewall 31 has a specific crystal plane, such as a {110} planar family surface or a {110} planar family oxidized surface. After analysis by high-resolution transmission electron microscopy (HRTEM), the diffraction pattern of the aforementioned surfaces shows as bright spots on the {110} planar surfaces, and as apertures or arcs on the oxidized {110} planar surfaces. A plurality of trenches 3 in the dielectric layer 2 are projected onto a plane formed by the XY axes to form a first contour P1. This first contour P1 can be regular or irregular, such as a circle, quadrilateral, pentagon, or hexagon. In one embodiment, the quadrilateral can be a rectangle.

[0030] As shown in Figure 1C, a plurality of trenches 3 have a first depth D1, a first width W1, and a first opening 322, the first opening 322 being one end of the trench 3 away from the second surface S2. As shown in Figure 1C, on the Z-axis, the first depth D1 can be 10 nm or more and 500 nm or less, for example, 50 nm, 100 nm, 200 nm, 300 nm, or 400 nm. On the X-axis, the first width W1 can be 10 nm or more and 300 nm or less, for example, 50 nm, 100 nm, 150 nm, or 200 nm. In one embodiment, the ratio of the first depth D1 to the first width W1 can be 0.033 or more and 50 or less, for example, 1, 5, 10, 20, or 40.

[0031] Furthermore, in the process steps shown in Figure 2C, a plurality of trenches 3 can be arranged at intervals along the horizontal direction (X-axis direction) within the dielectric layer 2, and two adjacent trenches 3 have a spacing G on the X-axis. The spacing G can be greater than 0.1 μm and less than 10 µm, for example, 0.5 µm, 1 µm, or 5 µm.

[0032] In the process steps shown in Figures 1D and 2D, a first semiconductor layer 4 is deposited in a plurality of trenches 3 using epitaxial methods such as Metal-Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Hydride Vapor Phase Epitaxy (HVPE) and Aspect Ratio Trapping (ART) technology. In one embodiment, the sidewalls 31 of the trenches 3 have {110} planar family surfaces or {110} planar family oxidized surfaces as described above, which can make the epitaxial growth rate in the vertical direction (Z-axis) significantly higher than the epitaxial growth rate in the horizontal direction (X-axis or Y-axis).

[0033] In the process steps shown in Figures 1E and 2E, an epitaxial lateral overgrowth (ELOG) method is used to deposit a second semiconductor layer 6 on the first semiconductor layer 4, filling a plurality of trenches 3. The second semiconductor layer 6 extends from within the trenches 3 onto the first surface S1 of the dielectric layer 2 and covers the first openings 322 of the plurality of trenches 3. The second semiconductor layer 6 covers a portion of the first surface S1 of the dielectric layer 2 and has gaps T; in other words, the second semiconductor layer 6 is a discontinuous film. In this embodiment, the second semiconductor layer 6 may have a first portion 62 and a second portion 64. The first portion 62 is located within the plurality of trenches 3, and the second portion 64 protrudes from the first opening 322. Projecting the second portion 64 of the second semiconductor layer 6 onto the XY plane reveals a second profile P2 larger than the first profile P1.

[0034] In the process steps shown in Figures 1F and 2F, a doped layer 7 containing a first dopant is deposited on the second semiconductor layer 6. The doped layer 7 is patterned and is not formed at the corresponding position of the first opening 322, so that the doped layer 7 has a gap T' corresponding to the first opening 322, and the gap T' has a width on the X-axis that is approximately equal to the first width W1 of the first opening 322. As shown in Figure 2F, after projecting Figure 1F onto the XY plane, the doped layer 7 forms a doped layer profile 71, and the second semiconductor layer 6, which is not covered by the doped layer 7 corresponding to the first opening 322, can form a third profile P3. The doped layer profile 71 and the third profile P3 can alternate along the X-axis direction. In one embodiment, in order to effectively enable the doped layer 7 to diffuse uniformly into the second semiconductor layer 6, the doped layer 7 can be selectively completely covered on a first side surface 61 of the second semiconductor layer 6.

[0035] As shown in Figure 1G, the doped layer 7 undergoes a thermal processing process to diffuse the first dopant into the second semiconductor layer 6, forming a doped region 8 and an active region 6'. The remaining doped layer 7 can then be removed by etching. In this embodiment, the doped region 8 contains the first dopant from the doped layer 7 and has a first conductivity type, and the dopant concentration of the first dopant is greater than 10¹⁶, for example, 10¹⁷ cm⁻³, 10¹⁸ cm⁻³, 10¹⁹ cm⁻³, or 10²⁰ cm⁻³; the first semiconductor layer 4 contains a second dopant and has a second conductivity type. The second dopant is different from the first dopant, and the first conductivity type (p or n) is different from the second conductivity type (n or p). The second dopant concentration is greater than 10¹⁶, for example, 10¹⁷ cm⁻³, 10¹⁸ cm⁻³, 10¹⁹ cm⁻³, or 10²⁰ cm⁻³. In one embodiment, the first conductivity type is p-type, the second conductivity type is n-type, and the active region 6' is i-type, thus forming a pin diode.

[0036] In the process steps shown in Figure 1H and its corresponding Figure 2H, an electrical connector 9 is formed on the first surface S1 of the dielectric layer 2 by evaporative deposition or sputtering deposition to form a semiconductor device 10A. Referring to Figures 2D and 2H, Figure 2H shows that the electrical connector 9, when projected onto the XY plane, has a fourth contour P4. In one embodiment, the second contour P2, the third contour P3, and the fourth contour P4 can be quadrilaterals, such as rectangles or squares. The first contour P1 has a first area A1, the second contour P2 has a second area A2, the third contour P3 has a third area A3, and the fourth contour P4 has a fourth area A4. In one embodiment, the second area A2, the third area A3, or the fourth area A4 is greater than or equal to the first area A1. In one embodiment, the first area A1 is equal to the third area A3. In this embodiment, the fourth area A4 is greater than the third area A3. In one embodiment, the fourth area A4 is less than or equal to the third area A3.

[0037] In another embodiment, as shown in Figure 1I, the steps shown in Figure 1E can be substituted. Unlike Figure 1E, in this embodiment, the second semiconductor layer 6 is a continuous film. Subsequently, the semiconductor device 10B shown in Figure 1J is completed through the processes shown in Figures 1F-1H, with appropriate additions of photolithography, etching, deposition, and diffusion processes.

[0038] In another embodiment, Figures 1K-1N can replace the steps shown in Figures 1F to 1H. As shown in Figure 1K, the doped layer 7 does not completely cover the second semiconductor layer 6, but the doped layer 7 has a gap T' corresponding to the first opening 322, and a portion of the doped layer 7 correspondingly covers a portion of the first opening 322. In other words, the width of the gap T' of the doped layer 7 is smaller than the first width W1 of the first opening 322'.

[0039] As shown in Figure 1L, a thermal diffusion process is then used to form a doped region 8 and an active region 6' in the second semiconductor layer 6. The remaining doped layer 7 can be removed by etching. The resulting doped region 8 partially covers the active region 6' corresponding to the position of the first opening 322. In this embodiment, by making the width of the gap T' smaller than the first width W1, the doped region 8 can have a U-shaped shape. In other embodiments, the width of the gap T' can be designed to give the doped region 8 different widths and shapes.

[0040] Next, as shown in Figure 1M, a portion of the doped region 8 corresponding to the first opening 322 is removed by dry etching. For example, an inductively coupled plasma (ICP) is used to expose one of the surfaces of the active regions 6' corresponding to the positions of the plurality of trenches 3, forming a recess U. In this embodiment, since a portion of the active regions 6' is covered and another portion is not covered, the semiconductor device can provide adequate protection for the active regions 6' to prevent damage to the active regions 6' from external forces or the environment during application. Finally, as shown in Figure 1N, an electrical connector 9 is formed on the first surface S1 of the dielectric layer 2 to form the semiconductor device 10C.

[0041] Figure 3A shows an embodiment of a semiconductor device 10A manufactured according to the process embodiments shown in Figures 1A to 1H. The semiconductor device 10A has a first epitaxial structure 102, which includes a first semiconductor layer 4 and a second semiconductor layer 6. The second semiconductor layer 6 includes an active region 6' and a doped region 8. The first epitaxial structure 102 is located on a substrate 1 and can be connected to the second surface S2 of a first sublayer 14; the first epitaxial structure 102 is located between dielectric layers 2 and can cover a portion of the first surface S1 of the dielectric layer 2; the first epitaxial structure 102, after being projected onto an XY plane, can be located between a plurality of electrical connectors 9. A plurality of trenches 3 are formed in the dielectric layers 2, and the first epitaxial structure 102 fills the plurality of trenches 3 and connects to the electrical connectors 9. The first semiconductor layer 4 is located on the substrate 1 and can be connected to the second surface S2 of the first sublayer 14, or directly connected to the dielectric layer 2.

[0042] As shown in Figure 3A, and with reference to Figure 2D, the first semiconductor layer 4 fills the trenches 3 in both the X-axis and Y-axis directions, and the first semiconductor layer 4 has the same shape as the trenches 3, such as a rectangle. In one embodiment, the first semiconductor layer 4 does not fill the plurality of trenches 3 in the Z-axis direction; in other words, the first semiconductor layer 4 does not protrude from the first opening 322. The first semiconductor layer 4 has a third surface S3 away from the first sublayer 14, and the third surface S3 is separated from the first surface S1 of the dielectric layer 2 by a distance D2 in the vertical direction (Z-axis). The distance D2 can be greater than 50 nm and less than 200 nm, for example, 50 nm, 100 nm, or 150 nm.

[0043] As shown in Figure 3A, the first portion 62 is located within the trench 3. The second portion 64 of the active region 6' is located on the first portion 62 and extends upward beyond the first surface S1 of the dielectric layer 2. The active region 6' has a fourth surface S4 facing the substrate 1 and a fifth surface S5 opposite to the fourth surface S4. The fourth surface S4 is connected to the third surface S3 of the first semiconductor layer 42 to form a first interface J1, which is located within the trench 3. The active region 6' is connected to the doped region 8 to form a second interface J2. In this embodiment, the second interface J2 is a straight line projected onto an XZ plane and is coplanar with the trench sidewall 31. In another embodiment, in the cross-sectional view, due to process factors, the second interface J2 is not a straight line and has an arc shape. The doped region 8 has a sixth surface S6, which is away from the substrate 1 and in this embodiment, the sixth surface S6 is substantially coplanar with a fifth surface S5 of the active region 6'. The fact that the sixth surface S6 and the fifth surface S5 are approximately coplanar can improve the quality of the subsequent deposited protective layer or the yield of the packaging process.

[0044] As shown in Figure 3A, on the Z-axis, the trench 3 has a first depth D1, and the first semiconductor layer 4 has a first thickness T1 less than the first depth D1. In one embodiment, the first semiconductor layer 4 and the substrate 1 are lattice mismatched. The first sublayer 14 has a first intrinsic lattice constant a1, and the first semiconductor layer 4 has a second intrinsic lattice constant a2. The difference between the first intrinsic lattice constant a1 and the second intrinsic lattice constant a2 is 1% to 15%, and the difference between the first intrinsic lattice constant a1 and the second intrinsic lattice constant a2 can be expressed by the formula: Calculations are performed. The first semiconductor layer 4 can be an InAlGaAs series, AlGaInP series, or InGaSb series material, and the first sublayer 14 can be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). The "intrinsic lattice constant" is defined as the lattice constant a0 of a layer that is substantially free of strain. In this embodiment, the defects formed by the lattice mismatch between the first sublayer 14 and the first semiconductor layer 4 can be reduced by the trench 3, so that the defect density of the first semiconductor layer 4 gradually decreases along a Z-axis direction from the second surface S2 to the first opening 322, thereby giving the second semiconductor layer 6 subsequently grown on the first semiconductor layer 4 better crystallinity. In one embodiment, the first semiconductor layer 4 occupies most of the trench 3, and more specifically, the first thickness T1 is 50%-95% of the first depth D1, thereby enabling the portion of the first semiconductor layer 4 away from the first sublayer 14 to have better crystallinity, which in turn enables the second semiconductor layer 6 grown on the first semiconductor layer 4 to have better crystallinity, thereby improving the light output power.

[0045] In this embodiment, the active region 6' has a second thickness T2, and the first portion has a first portion thickness T21, the second portion 64 has a second portion thickness T22, and T21 + T22 = T2. In one embodiment, the second thickness T2 is less than the first depth D1 or the first thickness T1. On the Z-axis, the doped region 8 has a third thickness T3, and the electrical connector 9 is located on the first surface S1 and has a fourth thickness T4. In this embodiment, the fourth thickness T4 is greater than the third thickness T3, thereby allowing the electrical connector 9 to protrude from the sixth surface S6 of the doped region 8 for subsequent circuit configuration.

[0046] Figure 3B shows a cross-sectional view of a semiconductor device 10D according to an embodiment of this disclosure. The semiconductor device 10D has a structure similar to that of the semiconductor device 10A. In this embodiment, by controlling the orientation growth rate of the epitaxial growth, the active region 6' can extend upwards and protrude beyond the doped region 8. Specifically, the fifth surface S5 of the active region 6' is farther from the second surface S2 of the first sublayer 14 than the sixth surface S6 of the doped region 8, and a portion of the first side surface 61 of the active region 6' of the second semiconductor layer 6 is not connected to the doped region 8. In one embodiment, the second portion thickness T22 is greater than the third thickness T3, and the second portion thickness T22 is less than the fourth thickness T4. In one embodiment, when the semiconductor device 10D is a light-absorbing device, the design of the active region 6' protruding beyond the doped region 8 can increase the light absorption area. The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in previous embodiments and will not be repeated here.

[0047] Figure 3C shows a cross-sectional view of a semiconductor element 10E according to one embodiment of this disclosure. Semiconductor element 10E has a structure similar to that of semiconductor element 10A. The substrate 1 of semiconductor element 10E may further include a second sublayer 16 located on the base layer 12. More specifically, the second sublayer 16 is located between the first sublayer 14 and the base layer 12. The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in previous embodiments and will not be repeated here.

[0048] Figure 3D shows a semiconductor device 10F in one embodiment of this disclosure. Semiconductor device 10F has a structure similar to semiconductor device 10A. In the manufacturing process of semiconductor device 10F, after the process of forming a plurality of trenches 3 in the dielectric layer 2 on the substrate 1 as shown in Figure 1C is completed, an etching technique can be selectively used to form an accommodating space 144 in a first sublayer 14 of the substrate 1. For example, a dry etching process can be applied to the first sublayer 14 first, followed by a wet etching process. The etching solution may contain an acid or alkaline solution such as potassium hydroxide (KOH), hydrofluoric acid (HF), buffered oxide etchant (BOE), or aqua regia to form the first accommodating space 144. The first accommodating space 144 is connected to the trenches 3 of the dielectric layer 2. The first accommodating space 144 has a bottom 144b and a second opening 142 connected to the plurality of trenches 3. The first accommodating space 144 has a width on the X-axis, which increases gradually and then decreases along the Z-axis from the second opening 142 to the bottom 144b.

[0049] In this embodiment, as previously described, defects formed by lattice mismatch between the first sublayer 14 and the first semiconductor layer 4 can be confined within the first accommodating space 144, thereby resulting in a lower defect density for the first semiconductor layer 4 subsequently grown within the trench 3 compared to the first semiconductor layer 4 located within the first accommodating space 144. Furthermore, the lower defect density of the first semiconductor layer 4 within the trench 3 allows for better crystallinity of the second semiconductor layer 6 grown thereon, thus improving luminous efficiency. Moreover, the higher defect density of the first semiconductor layer 4 located within the first accommodating space 144 reduces the electrical impedance between the first semiconductor layer 4 and the first sublayer 14. In an embodiment where the semiconductor element 10F is a light-absorbing element, due to the low impedance between the first semiconductor layer 4 and the first sublayer 14, electrons and holes generated by light absorption in the active region 6' can more easily be transported to the first sublayer 14 and connected in series with the resistance. The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in previous embodiments and will not be repeated here.

[0050] Figure 4 shows a cross-sectional view of a semiconductor element 20 according to one embodiment of this disclosure. The semiconductor element 20 has a structure similar to that of semiconductor element 10A. In this embodiment, the first epitaxial structure 102 is located within a plurality of trenches 3. More specifically, the first semiconductor layer 4 and the second semiconductor layer 6 are both located within a plurality of trenches 3. In the Z-axis direction, the active region 6' of the second semiconductor layer 6 is located between the doped region 8 of the second semiconductor layer 6 and the first semiconductor layer 4, and the second semiconductor layer 6 does not protrude from the first surface S1 of the dielectric layer 2. An electrical connector 9 covers the second semiconductor layer 6 and is connected to the sixth surface S6 of the doped region 8. In this embodiment, the sixth surface S6 is coplanar with the first surface S1 of the dielectric layer 2. In this embodiment, the first thickness T1 of the first semiconductor layer 4, the second thickness T2 of the active region 6', and the third thickness T3 of the doped region 8 are related as T1 ≥ T3 > T2. In this embodiment, the electrical connector 9 covers the first epitaxial structure 102. When the semiconductor element 20 is a light-emitting element, the light emitted by the semiconductor element 20 towards the Z-axis is blocked by the electrical connector 9, and most of the light is emitted through the side (Y-axis direction). Conversely, when the semiconductor element 20 is a light-absorbing element, the light entering the semiconductor element 20 from the outside also enters through the side. The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in the previous embodiments and will not be repeated here.

[0051] Figure 5 shows a cross-sectional view of the semiconductor element 30 in one embodiment of this disclosure. The semiconductor element 30 has a structure similar to that of the semiconductor element 10A. In this embodiment, the second interface J2 connecting the doped region 8 and the active region 6' is coplanar with the first surface S1. In this embodiment, the semiconductor element 30 is a light-emitting element, and the relationship between the first thickness T1 of the first semiconductor layer 4, the second thickness T2 of the active region 6', and the third thickness T3 of the doped region 8 is T1>T2≧T3. In this embodiment, the first depth D1 is equal to the sum of the first thickness T1 and the second thickness T2 (D1=T1+T2). The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in the previous embodiments and will not be repeated here.

[0052] FIG. 6 shows a schematic cross-sectional structure of a semiconductor element 40 in an embodiment of the present disclosure. The semiconductor element 40 has a structure similar to that of the semiconductor element 30. In this embodiment, the doped region 8 of the second semiconductor layer 6 is located on the first surface S1 of the dielectric layer 2. In this embodiment, the active region 6' of the second semiconductor layer 6 includes a first portion 62 and a second portion 64. The first portion 62 is located in the plurality of trenches 3, and the portion where the active region 6' extends and protrudes from the first surface S1 of the dielectric layer 2 forms the second portion 64. The doped region 8 surrounds the second portion 64 in the horizontal direction (X-axis or Y-axis), and in the Z-axis direction, the doped region 8 covers the second portion 64. The second junction J2 formed by the connection of the doped region 8 and the active region 6' is farther from the substrate 1 than the first surface S1 of the dielectric layer 2. In this embodiment, the relationship among the first thickness T1 of the first semiconductor layer 4, the second thickness T2 of the active region 6', and the third thickness T3 of the doped region 8 is T1>T2>T3. Compared with the semiconductor element 30 in FIG. 5, the first depth D1 in this embodiment is less than the sum of the first thickness T1 and the second thickness T2 (D1<T1+T2), making the active region 6' closer to the sixth surface S6 of the doped region 8, whereby the semiconductor element 40 can have better light transmittance. Further, the sum of the third thickness T3 and the first depth D1 is greater than the sum of the first thickness T1 and the second thickness T2 (T3+D1>T1+T2), and the thickness T22 of the second portion is less than the third thickness T3. The positions, relative relationships, material compositions, etc. of other layers or structures in this embodiment can refer to the previous embodiments, and will not be elaborated herein.

[0053] FIG. 7 shows a schematic cross-sectional structure of a semiconductor element 50 in an embodiment of the present disclosure. The semiconductor element 50 has a structure similar to that of the semiconductor element 40. In this embodiment, the first portion 62 of the second semiconductor layer 6 is located in the plurality of trenches 3, and the second portion 64 protrudes from the first surface S1 of the dielectric layer 2. In the Z-axis direction, the second junction J2 formed by the connection of the doped region 8 and the active region 6' is located on the first surface S1 of the dielectric layer 2. In this embodiment, in the X-axis, the trench 3 has a first width W1, and the second portion 64 of the active region 6' in the second semiconductor layer 6 has a second width W2 greater than the first width W1 of the trench 3, and the second portion 64 is connected to the first surface S1. The positions, relative relationships, material compositions, etc. of other layers or structures in this embodiment can refer to the previous embodiments, and will not be elaborated herein.

[0054] Figure 8 shows a cross-sectional view of a semiconductor element 60 according to one embodiment of this disclosure. The semiconductor element 60 has a structure similar to that of the semiconductor element 50. In this embodiment, a first portion 62 is located within a plurality of trenches 3, and a second portion 64 protrudes from the first surface S1 of the dielectric layer 2 and is connected to the first surface S1. In this embodiment, the doped region 8 only surrounds the second portion 64 in the horizontal direction (X-axis or Y-axis), while the doped region 8 does not cover the fifth surface S5 of the second portion 64 in the vertical direction (Z-axis). The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in previous embodiments and will not be repeated here.

[0055] Figure 9 shows a cross-sectional view of a semiconductor element 70 in one embodiment. The semiconductor element 70 has a structure similar to that of the semiconductor element 60. In this embodiment, only the first semiconductor layer 4 is located within the plurality of trenches 3; that is, the first semiconductor layer 4 occupies the plurality of trenches 3, meaning the first depth D1 is equal to the first thickness T1. In the Z-axis direction, the first interface J1 connecting the first semiconductor layer 4 to the active region 6' and the first surface S1 of the dielectric layer 2 are coplanar. The second interface J2 connecting the active region 6' to the doped region 8 is coplanar with the sidewalls 31 of the plurality of trenches. The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in previous embodiments and will not be repeated here.

[0056] Figure 10 shows a cross-sectional view of the semiconductor element 80 in one embodiment of this disclosure. The semiconductor element 80 has a structure similar to that of the semiconductor element 70. In this embodiment, the active region 6' in the second semiconductor layer 6 has a second width W2 on the X-axis that is greater than the first width W1 of the trench 3. In other words, the active region 6' and the doped region 8 of the second semiconductor layer 6 are located on the first surface S1 of the dielectric layer 2, and the active region 6' is connected to the first surface S1 of the dielectric layer 2. The positions, relative relationships, and material compositions of other layers or structures in this embodiment can be referred to in previous embodiments and will not be repeated here.

[0057] Figure 11 shows a cross-sectional view of a semiconductor element 90 according to one embodiment of this disclosure. The semiconductor element 90 has a structure similar to that of semiconductor element 10A. In this embodiment, the plurality of trenches 3 include a first trench 32 and a second trench 34. The first trench 32 has a first width W1, and the second trench 34 has a third width W3, with the first width W1 being greater than the third width W3. During the epitaxial process as shown in Figure 1D, a first epitaxial structure 102 grows from the first trench 32, and a second epitaxial structure 104 grows from the second trench 34. Since the first width W1 of the first trench 32 is greater than the third width W3 of the second trench 34, during the epitaxial process, the amount of reactive gas entering the first trench 32 is greater than the amount entering the second trench 34, resulting in a faster epitaxial growth rate of the first epitaxial structure 102 in the first trench 32 than that of the second epitaxial structure 104 in the second trench 34.

[0058] In one embodiment, the first width W1 is greater than the third width W3. In the Z-axis direction, the first semiconductor layer 4 of the first epitaxial structure 102 has a first thickness T1, and the active region 6' of the first epitaxial structure 102 has a second thickness T2; the first semiconductor layer 4 of the second epitaxial structure 104 has a fifth thickness T5, and the active region 6' of the second epitaxial structure 104 has a sixth thickness T6.

[0059] In the process of growing the first epitaxial structure 102 and the second epitaxial structure 104 in the semiconductor device 90, since the epitaxial growth rate of the first epitaxial structure 102 is faster than that of the second epitaxial structure 104, the first semiconductor layer 4 is deposited first. Therefore, the first thickness T1 of the first semiconductor layer 4 in the first trench 32 is greater than the fifth thickness T5 of the first semiconductor layer 4 in the second trench 34. Subsequently, the active region 6' is grown on the first semiconductor layer 4, and similarly, the thickness of the active region 6' in the first trench 32 is also greater than the thickness of the active region 6' in the second trench 34. Then, a chemical mechanical polishing (CMP) is applied to the first epitaxial structure 102 and the second epitaxial structure 104 so that the first epitaxial structure 102 and the second epitaxial structure 104 have substantially the same thickness as shown in Figure 11. Through the above process, the sixth thickness T6 in Figure 11 will be greater than the second thickness T2.

[0060] In one embodiment, by designing different first widths W1 and second widths W2, a first epitaxial structure 102 and a second epitaxial structure 104 with different compositions can be obtained simultaneously in one epitaxial process. For example, both the first epitaxial structure 102 and the second epitaxial structure 104 are In xGa (1-x)N (0≦x≦1) series. The active region 6' in the first epitaxial structure 102 has In x1Ga (1-x1)N, and the active region 6' in the second epitaxial structure 104 has In x2Ga (1-x2)N, then X1>X2.

[0061] In one embodiment, the active region 6' in the first epitaxial structure 102 emits red light (In x1Ga (1-x1)N) with a peak wavelength between 610 nm and 700 nm, 0.4 ≤ x 1 ≤ 0.85; the active region in the second epitaxial structure 104 emits green light (In x2Ga (1-x2)N) with a peak wavelength between 490 nm and 550 nm, 0.2 ≤ x 2 ≤ 0.34, or blue or dark blue light (In x2Ga (1-x2)N) with a peak wavelength between 400 nm and 490 nm, 0.05 ≤ x 2 ≤ 0.2. In one embodiment, a third epitaxial structure (not shown) may be optionally provided, and as described above, by designing the trench width, epitaxial structures with different compositions can be grown simultaneously. For example, the active region in the first epitaxial structure 102 emits red light, the active region in the second epitaxial structure 104 emits green light, the active region in the third epitaxial structure emits blue light, and the semiconductor element 90 emits white light.

[0062] Besides being different compositions of the same material family, the first epitaxial structure 102 and the second epitaxial structure 104 can also be a combination of different material families. In another embodiment, the first semiconductor layer 4 of the first epitaxial structure 102 can be of the InAlGaAs family, while the first semiconductor layer 4 of the second epitaxial structure 104 can be of the AlGaInP family or the InGaSb family.

[0063] Figure 12 shows a cross-sectional view of a semiconductor device 100 according to one embodiment of the present invention.

[0064] Semiconductor device 100 includes a substrate 1, a fin 320, a dielectric layer 2, a first epitaxial structure 102, an electrical connector 9, a spacer layer 340, and a metal layer 360. The substrate 1 includes a base layer 12, a first sublayer 14, and a second sublayer 16. The fin 320 is located on the second sublayer 16 and is not connected to the first sublayer 14. The fin 320 has sidewalls 3201 and a top surface 3202, and the spacer layer 340 covers the sidewalls 3201 and the top surface 3202. The metal layer 360 covers the spacer layer 340 and a portion of the first sublayer 14. In one embodiment, the metal layer 360 may be connected to the dielectric layer 2. Descriptions of the first epitaxial structure 102 and the electrical connector 9 can be found in the foregoing embodiments and will not be repeated here. The first sublayer 14 and the fin 320 may have the same or different materials. In one embodiment, the first sublayer 14 may be connected to the fin 320 according to circuit design requirements.

[0065] Figures 13A to 13D are cross-sectional views of the manufacturing process of a semiconductor device 100 according to one embodiment of the present invention.

[0066] As shown in Figure 13A, a substrate 1 is provided, comprising a base layer 12, a first thick layer 14', and a second sublayer 16.

[0067] As shown in Figure 13B, the first thick layer 14' of the etched portion forms a protrusion 320' and a platform portion 321'.

[0068] As shown in Figure 13C, a deposited dielectric layer 2 covers the protrusion 320' and the platform portion 321', and selectively applies a chemical mechanical polishing process to expose the protrusion 320'.

[0069] As shown in Figure 13D, the dielectric layer 2 is etched to form a plurality of trenches 3. The platform portion 321' is etched to expose a portion of the second sublayer 16 and to form fins 320 (protrusions 320') and a first sublayer 14. The fins 320 and the first sublayer 14 are separate from each other and not connected.

[0070] As described in Figures 1D to 1H above, the first epitaxial structure 4 and the electrical connector 9 are formed. Next, a spacer layer 340 is deposited to cover the fin 320, and a metal layer 360 is deposited to cover the spacer layer 340 to form the semiconductor device 100 as shown in Figure 12. The fin 320 can serve as a transistor.

[0071] By using the process flow described in the semiconductor device 100 as shown in Figures 13A to 13D, a photodiode array detector and a transistor can be formed simultaneously, thereby eliminating the need for packaging processes such as wire bonding, bonding, and soldering required when integrating semiconductor components and transistors, thus improving process convenience.

[0072] Figure 14 is a perspective view of an embodiment of a semiconductor device 100, and Figure 12 is a cross-sectional view along line A-A' in Figure 14. These figures can be referenced interchangeably during the description. As shown in Figure 14, the semiconductor device 100 includes a first electrode pad 401 and a second electrode pad 402. The first electrode pad 401 is located on the dielectric layer 2 and electrically connected to the first epitaxial structure 4 and the electrical connector 9. The second electrode pad 402 is located on the first sublayer 14 and connected to the fin 320. In one embodiment, the first electrode pad 401 can be subjected to a ground voltage (Vss).

[0073] Figure 14 is a perspective view of a semiconductor device 200 according to one embodiment of the present invention. The cross-sectional view along line A-A' in Figure 14 can be referenced in Figure 12. As shown in Figure 14, the semiconductor device 200 includes a plurality of transistors 300 located on a second sublayer 16. In one embodiment, the plurality of transistors 300 may be FinFETs, and the plurality of transistors 300 may include fins 320. The plurality of transistors 300 may include a source follower transistor Msf, a reset transistor Msrep, and a selection transistor Msel, forming a three-transistor structure or other control circuits for processing carriers such as electrons and holes. In this embodiment, the metal layer 360 is electrically connected to the gate (G) of the source follower transistor Msf and the source / drain (S / D) of the reset transistor Msre. The S / D of the source follower transistor Msf is electrically connected to the S / D of the reset transistor Msre and the S / D of the select transistor Msel. The G of the reset transistor Msre, the G of the select transistor Msel, and the S / D of the select transistor Msel are electrically connected to an external circuit. The external circuit can be used to provide, for example, an operating voltage (VDD), a reset voltage (Vrst), and a ground voltage (Vss). Through the above circuit connection configuration, a horizontal optoelectronic integrated circuit (OEIC) can be formed that can be applied to light-emitting or light-absorbing arrays. In other embodiments, the plurality of transistors 300 can be selectively increased or decreased in number, and the element circuitry can be rearranged to control the light-absorbing or light-emitting semiconductor elements to achieve the desired function.

[0074] The aforementioned substrate 12 and first sublayer 14 may be made of the same or different materials. The substrate 12 and first sublayer 14 may be semiconductor materials. The semiconductor materials may be group IV or group III-V semiconductors, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), germanium-tin (GeSn), silicon carbide (SiC), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAs), gallium arsenide phosphide (AsGaP), or indium phosphide (InP). The first sublayer 14 comprises silicon (Si), germanium (Ge), silicon-germanium (SiGe), or germanium-tin (GeSn). In one embodiment, the substrate 12 comprises silicon material having a (111) crystal plane, or other crystal planes such as (100) may also be selected.

[0075] The material of the second sub-layer 16 can be a semiconductor material or an insulating material as described above. For embodiments where the second sub-layer 16 is selected to be a semiconductor material, the second sub-layer 16 can have a graded chemical composition, such as Si 1-xGe x, In xGa (1-x)N, where 0.1 < x < 1 and the value of x increases as it moves away from the upper surface 123 of the base layer 12 along the Z-axis, to serve as a buffer for the mismatch of the lattice constant between the base layer 12 and the first sub-layer 14. For embodiments where the second sub-layer 16 is selected to be an insulating material, the insulating material can be an oxide, nitride, or halide, etc. Oxides can be, for example, aluminum oxide (Al 2O 3), silicon dioxide (SiO 2), silicon oxynitride (SiO xN y), titanium dioxide (TiO 2), niobium pentoxide (Nb 2O 5), hafnium dioxide (HfO 2), zirconium dioxide (ZrO 2), tantalum pentoxide (Ta 2O 5). Nitrides can be, for example, silicon nitride (SiN x), silicon oxynitride (SiO xN y), titanium nitride (TiN x), tantalum nitride (TaN). Halides can be, for example, magnesium fluoride (MgF ­2). The second sub-layer 16 provides electrical isolation between the base layer 12 and the first sub-layer 14 to reduce the generation of leakage current during operation.

[0076] In one embodiment, the dielectric layer 2 can be selected from the insulating materials as described above, and the material of the dielectric layer 2 is different from that of the first sub-layer 14. For example, if the first sub-layer 14 is germanium (Ge), the dielectric layer 2 can be silicon dioxide or silicon nitride.

[0077] In one embodiment, the first semiconductor layer 4 and the second semiconductor layer 8 can comprise III-V compound semiconductors, such as GaAs, InP, InGaAs, AlGaAs, AlGaInAs, GaP, InGaP, InGaSb, AlInP, AlGaInP, InAlGaAs, GaN, InGaN, AlGaN, AlGaInN, AlAsSb, InGaAsP, InGaAsN, or AlGaAsP.

[0078] In one embodiment, the material of the dopant layer 7 can be (Si), carbon (C), selenium (Se), tellurium (Te), zinc (Zn), magnesium (Mg), beryllium (Be), zinc oxide (ZnO), or magnesium oxide (MgO). The first dopant can be silicon (Si), carbon (C), selenium (Se), tellurium (Te), zinc (Zn), magnesium (Mg), beryllium (Be). The second dopant can be silicon (Si), carbon (C), selenium (Se), tellurium (Te), zinc (Zn), magnesium (Mg), beryllium (Be).

[0079] Electrical connector 9, metal layer 360, first electrode pad 401, and second electrode pad 402 comprise metallic materials or metal oxides. The metallic materials may be, for example, copper (Cu), aluminum (Al), chromium (Cr), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb), cobalt (Co), or alloys thereof. The metal oxides may be, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), or indium zinc oxide (IZO), or combinations of metal oxides thereof.

[0080] The spacer layer 340 contains the aforementioned insulating material, such as alumina (Al₂O₃), niobium pentoxide (Nb₂O₅), hafnium dioxide (HfO₂), or carbon-doped silicon oxide (SiCO).

[0081] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention.

[0082] 1:Substrate 2: Dielectric layer 3: Trench 4: First semiconductor layer 6: Second semiconductor layer 7: Doped layer 8: Doped region 9: Electrical connectors 12: Basal layer 14: First Sub-layer 14': First Thick Layer 16: Second Sublayer 20: Semiconductor components 30: Semiconductor components 31: Trench sidewall 32: First trench 34: Second trench 40: Semiconductor components 50: Semiconductor components 60: Semiconductor components 61: First side surface 62: Part One 64: Part Two 70: Semiconductor components 71: Doped layer profile 80: Semiconductor components 90: Semiconductor components 100: Semiconductor devices 102: First epitaxial structure 104: Second epitaxial structure 121: Bottom surface 123: Upper surface 142: Second opening 144: First Accommodation Space 200: Semiconductor devices 300: Transistor 320: Fins 320': Protrusion 321': Platform Department 322: First Opening 340: Spare layer 360: Metal Layer 401: First electrode pad 402: Second electrode pad 10A: Semiconductor Components 10B: Semiconductor components 10C: Semiconductor components 10D: Semiconductor Components 10E: Semiconductor components 10F: Semiconductor components 144b: Bottom 6': Active Zone A1: First area A2: Second area A3: Third area A4: Fourth area a 1: First essential lattice constant a 2: Second essential lattice constant D1: First Depth D2: Distance G: Spacing J1: First interface J2: Second interface Mrest: Reset Transistor Msel: Select Transistor Msf: Source Follower Transistor P1: First outline P2: Second outline P3: Third outline P4: Fourth Outline S1: First surface S2: Second surface S3: Third Surface S4: Fourth Surface S5: Fifth Surface S6: Sixth Surface T: Gap T': Gap T1: First thickness T2: Second thickness T21: Thickness of the first part T22: Second part thickness T3: Third Thickness T4: Fourth Thickness T5: Fifth Thickness T6: Sixth Thickness U: concave cavity W1: First width W2: Second width W3: Third width

[0083] none

Claims

1. A semiconductor device, comprising: a substrate including a first sublayer, the first sublayer including a receiving space; a dielectric layer located on the first sublayer and having a first surface; a trench located in the dielectric layer and communicating with the receiving space; a first semiconductor layer located in the trench and the receiving space; a second semiconductor layer including an active region connected to the first semiconductor layer; and an electrical connector located on the first surface and connected to the second semiconductor layer; wherein... The accommodating space has a bottom and an opening connected to the groove, and the width of the accommodating space increases and then decreases in a vertical direction from the opening to the bottom.

2. The semiconductor device as described in claim 1, wherein, The substrate further includes a second sublayer, the width of which is smaller than the width of the first sublayer.

3. The semiconductor element as claimed in claim 1 further includes a first junction connecting the first semiconductor layer and the active region, and the first junction is located in the trench.

4. The semiconductor device as described in claim 1, wherein, The second semiconductor layer further includes a doped region and a second junction, the second junction connecting the doped region and the active region, and the second junction being coplanar with the first surface.

5. The semiconductor device as described in claim 1, wherein, The trench has a depth, the first semiconductor layer has a first thickness, the active region has a second thickness, and the sum of the first thickness and the second thickness is greater than the depth.

6. The semiconductor device as described in claim 1, wherein, The active region has a first portion located in the trench and a second portion located on the first surface, and the second portion is connected to the first surface of the dielectric layer.

7. The semiconductor device as described in claim 6, wherein, The second semiconductor layer further includes a doped region that is connected to the first surface of the dielectric layer and the second portion thereof.

8. The semiconductor device as described in claim 7, wherein, The doped region has a third thickness, and the second portion has a fourth thickness, the third thickness being greater than the fourth thickness.

9. The semiconductor device as described in claim 1, wherein, The groove is a plurality of grooves, and the groove further includes a first groove and a second groove. The first groove has a first width, the second groove has a second width, and the first width and the second width are different.

10. A semiconductor device comprising: a semiconductor element as described in claims 1 to 9; and a transistor including a fin, wherein the first sublayer and the fin comprise the same material.

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