Integrated circuit (IC) packages employing front side back-end-of-line (fs-beol) to back side back-end-of-line (bs-beol) stacking for three-dimensional (3D) die stacking, and related fabrication methods

Abstract

Front-side back-end process (FS-BEOL) to back-side back-end process (BS-BEOL) stacking is used for integrated circuit (IC) packaging with three-dimensional (3D) die stacking. To facilitate the provision of additional circuit routing paths for die-to-die interconnects between stacked IC dies in the IC package, the BS-BEOL metallization structure of the first die in the stacked IC package is stacked adjacent to the FS-BEOL metallization structure of the second die in the stacked IC package. Circuit routing paths for die-to-die interconnects between stacked IC dies are provided from the BS-BEOL metallization structure of the first die to the FS-BEOL metallization structure of the second die. Forming shorter circuit routing paths in a BS-BEOL metallization structure that is thinner than the FS-BEOL metallization structure may be more feasible to achieve lower resistance and / or lower capacitance die-to-die interconnects for faster and / or more compatible performance of semiconductor devices in the IC die.

Description

[Technical Field]

[0001] The field of this case relates to integrated circuit (IC) packaging, which includes a die module employing stacked semiconductor dies coupled to a package substrate, the package substrate providing an electrical interface to the semiconductor dies. [Previous Technology]

[0002] Integrated circuits (ICs) are the cornerstone of electronic components. ICs are packaged in IC packages (also known as "semiconductor packages" or "chip packages"). An IC package includes one or more semiconductor dies as ICs, which are mounted on and electrically coupled to a package substrate to provide physical support and electrical interfaces for the semiconductor dies. An IC package may also include three-dimensional (3D) stacked semiconductor dies in a die module coupled to the package substrate. The package substrate may be an embedded trace substrate (ETS), for example, including embedded traces in one or more dielectric layers and vertical interconnects (vias) coupling the traces together to provide electrical interfaces between the semiconductor dies. The package substrate may also be formed as a redistribution layer (RDL). The semiconductor dies are mounted to and electrically connected to the interconnects exposed in the top layer of the package substrate to electrically couple the semiconductor dies to the traces of the package substrate.

[0003] (Various) semiconductor dies and a packaging substrate are encapsulated in a packaging material (such as a molding compound) to form an IC package. The IC package may also include external solder bumps in a ball grid array (BGA) that are electrically coupled to interconnects exposed in the underlying layer of the packaging substrate to electrically couple the solder bumps to electrical traces in the packaging substrate. The solder bumps provide external electrical interfaces to (various) semiconductor dies in the IC package. When the IC package is mounted to a printed circuit board (PCB), the solder bumps are electrically coupled to metal contacts on the PCB to provide electrical interfaces between the traces in the PCB via the packaging substrate in the IC package to the IC chip. [Summary of the Invention]

[0004] The various forms disclosed herein include integrated circuit (IC) packages that stack front-side back-end process (FS-BEOL) to back-side back-end process (BS-BEOL) for three-dimensional (3D) die stacking. Related wafer packaging and methods for manufacturing IC packages are also disclosed. The IC package includes a die module comprising at least two (2) three-dimensional (3D) stacked semiconductor dies (also individually referred to as "IC dies" or "dies"). The FS-BEOL and BS-BEOL metallization structures are metallization structures comprising one or more metal layers including electrical interconnects for routing electrical signals to the semiconductor layers to achieve die interconnects. The FS-BEOL is a metallization structure disposed on the front side of a semiconductor layer adjacent to the IC die. The BS-BEOL is another metallization structure disposed on the back side of a semiconductor layer adjacent to the IC die. The IC die module is also coupled to a metallized structure (e.g., an embedded track substrate (ETS) or redistribution layer (RDL)) that provides external circuitry to the IC die and internal die-to-die routing between IC dies. Circuitry paths via the package substrate can be formed to provide die-to-die interconnects between stacked dies.

[0005] In an exemplary embodiment, to facilitate the provision of primary and / or additional circuit routing paths for die-to-die interconnects between stacked IC dies, a BS-BEOL metallization structure of a first die in the stacked IC package is stacked adjacent to an FS-BEOL metallization structure of a second die in the stacked IC package. A circuit routing path for die-to-die interconnects between stacked IC dies is provided from the BS-BEOL metallization structure of the first die to the FS-BEOL metallization structure of the second die. The BS-BEOL metallization structure is typically thinner than the FS-BEOL metallization structure. Therefore, forming circuit routing structures (e.g., through-silicon vias (TSVs)) in the BS-BEOL metallization structure may be more feasible than in the FS-BEOL metallization structure. Similarly, the thinner BS-BEOL metallization structure from the first die to the second die allows for a shorter circuit routing path for die-to-die interconnects between the first IC die and the second IC die. Shorter circuit paths for die-to-die interconnects enable die-to-die interconnects with lower resistance and / or lower capacitance to achieve faster and / or compatible performance of semiconductor devices in IC chips.

[0006] In another exemplary embodiment, to provide additional circuitry flexibility in the IC package, the IC module may further include an intermediate metallization structure formed between the BS-BEOL metallization structure of the first die and the FS-BEOL metallization structure of the second die. The intermediate metallization structure may include, for example, one or more RDLs. The intermediate metallization structure facilitates the repositioning of die-to-die interconnects between the BS-BEOL metallization structure of the first die and the FS-BEOL metallization structure of the second IC die to achieve greater die-to-die circuitry flexibility and die connection density. The intermediate metallization structure may also facilitate the formation of additional circuitry paths adjacent to stacked IC dies and through the intermediate metallization structure. For example, available blank or gap spaces may exist in the IC package, adjacent to IC dies in the stacked IC dies, and capable of supporting additional circuitry structures to provide additional circuitry paths in the IC package. These additional circuitry structures can be routed through the intermediate metallization structure to facilitate additional die interconnects to dies in the stacked dies.

[0007] In this regard, in one exemplary embodiment, an IC package is provided. The IC package includes a first IC die. The first IC die includes a first FS-BEOL metallization structure. The first IC die also includes a first BS-BEOL metallization structure. The first IC die also includes a first semiconductor layer disposed between the first FS-BEOL metallization structure and the first BS-BEOL metallization structure. The IC package also includes a second IC die. The second IC die includes a second FS-BEOL metallization structure adjacent to the first BS-BEOL metallization structure. The second IC die also includes a second BS-BEOL metallization structure. The second IC die also includes a second semiconductor layer disposed between the second FS-BEOL metallization structure and the second BS-BEOL metallization structure.

[0008] In another exemplary embodiment, a method for manufacturing an IC package is provided. The method includes the steps of: forming a first IC die, wherein forming the first IC die includes: forming a first BS-BEOL metallization structure, forming a first semiconductor layer adjacent to the first BS-BEOL metallization structure, and forming a first FS-BEOL metallization structure adjacent to the first semiconductor layer, such that the first semiconductor layer is disposed between the first BS-BEOL metallization structure and the first FS-BEOL metallization structure. The method also includes the step of: forming a second IC die, wherein forming the second IC die includes: forming a second BS-BEOL metallization structure, forming a second semiconductor layer adjacent to the second BS-BEOL metallization structure, and forming a second FS-BEOL metallization structure adjacent to the second semiconductor layer, such that the second semiconductor layer is disposed between the second BS-BEOL metallization structure and the second FS-BEOL metallization structure.

Implementation Method

[0021] Several exemplary forms of this case are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any form described herein as "exemplary" need not be construed as superior to or better than other forms.

[0022] The various forms disclosed herein include integrated circuit (IC) packages that stack front-side back-end process (FS-BEOL) to back-side back-end process (BS-BEOL) for three-dimensional (3D) die stacking. Related wafer packaging and methods for manufacturing IC packages are also disclosed. The IC package includes a die module comprising at least two (2) three-dimensional (3D) stacked semiconductor dies (also individually referred to as "IC dies" or "dies"). The FS-BEOL and BS-BEOL metallization structures are metallization structures comprising one or more metal layers including electrical interconnects for routing electrical signals to the semiconductor layers to achieve die interconnects. The FS-BEOL is a metallization structure disposed on the front side of a semiconductor layer adjacent to the IC die. The BS-BEOL is another metallization structure disposed on the back side of a semiconductor layer adjacent to the IC die. The IC die module is also coupled to a metallized structure (e.g., an embedded track substrate (ETS) or redistribution layer (RDL)) that provides external circuitry to the IC die and internal die-to-die routing between IC dies. Circuitry paths via the package substrate can be formed to provide die-to-die interconnects between stacked dies.

[0023] In an exemplary embodiment, to facilitate the provision of primary and / or additional circuit routing paths for die-to-die interconnects between stacked IC dies, a BS-BEOL metallization structure of a first die in the stacked IC package is stacked adjacent to an FS-BEOL metallization structure of a second die in the stacked IC package. A circuit routing path for die-to-die interconnects between stacked IC dies is provided from the BS-BEOL metallization structure of the first die to the FS-BEOL metallization structure of the second die. The BS-BEOL metallization structure is typically thinner than the FS-BEOL metallization structure. Therefore, forming circuit routing structures (e.g., through-silicon vias (TSVs)) in the BS-BEOL metallization structure may be more feasible than in the FS-BEOL metallization structure. Similarly, the thinner BS-BEOL metallization structure from the first die to the second die allows for a shorter circuit routing path for die-to-die interconnects between the first IC die and the second IC die. Shorter circuit paths for die-to-die interconnects enable die-to-die interconnects with lower resistance and / or lower capacitance to achieve faster and / or compatible performance of semiconductor devices in IC chips.

[0024] In another exemplary embodiment, to provide additional circuitry flexibility in the IC package, the IC module may further include an intermediate metallization structure formed between the BS-BEOL metallization structure of the first die and the FS-BEOL metallization structure of the second die. The intermediate metallization structure may include, for example, one or more RDLs. The intermediate metallization structure facilitates the repositioning of die-to-die interconnects between the BS-BEOL metallization structure of the first die and the FS-BEOL metallization structure of the second IC die to achieve greater die-to-die circuitry flexibility and die connection density. The intermediate metallization structure may also facilitate the formation of additional circuitry paths adjacent to IC dies in the stacked IC dies and through the intermediate metallization structure. For example, available blank or gap spaces may exist in the IC package, adjacent to IC dies in the stacked IC dies, capable of supporting additional circuitry structures to provide additional circuitry paths in the IC package. These additional circuitry structures can be routed through the intermediate metallization structure to facilitate additional die interconnects to dies in the stacked dies.

[0025] FIG1 is a side view of an exemplary IC package 100 employing a semiconductor die module 102 (also referred to herein as "IC die module 102"). As shown in FIG1, the IC die module 102 includes a plurality of stacked IC dies 104(1)-104(3) in the Z-axis or vertical direction to achieve 3D stacking. The IC die module 102 is disposed in a horizontal plane in the X-axis and Y-axis directions. The IC die module 102 is disposed on a package substrate 106, which is a metallized structure for providing external interconnects to the IC dies 104(1)-104(3). As an example, the package substrate 106 may be a laminate substrate or a redistribution layer (RDL) substrate. The package substrate 106 may also facilitate the provision of die-to-die interconnects between the IC dies 104(1)-104(3). As an example, the package substrate 106 may be an embedded trace substrate (ETS) or formed as a redistribution layer (RDL). The package substrate 106 includes one or more metal interconnect layers 108(1)-108(3) forming interconnect traces for signal routing and vertical interconnect vias (vias) to couple the traces between different layers together. The package substrate 106 also serves as a support structure on which the IC die module 102 may be disposed and supported. Conductive bumps 110 (e.g., solder bumps, ball grid array (BGA)) are formed to make interconnect contacts in the bottom metal interconnect layer 108(3) of the package substrate 106 to provide external electrical interfaces to the IC dies 104(1)-104(3). The package substrate 106 may be mounted to a printed circuit board (PCB) via the external conductive bumps 110 to provide conductive routing paths between the conductive bumps 110 and the IC dies 104(1)-104(3).

[0026] A via 112 is also formed in the IC package 100 to the top metal interconnect layer 108(3) of the package substrate 106 to provide a circuit path through the package substrate 106 to the IC die 104(1)-104(3).

[0027] In the exemplary IC package 100 of FIG1, IC die 104(1) may be a dedicated die, such as an exemplary general-purpose processor. As another example, one of IC dies 104(2) and 104(3) may be a power management IC (PMIC) that controls power management functions to manage power to IC die 104(1). As another example, the other of IC dies 104(2) and 104(3) may be a specific processor, such as a modem or baseband processor. In the IC package 100 of FIG1, die 114 in the form of a dynamic random access memory (DRAM) module 116 is provided and electrically coupled to package substrate 106 via via via 112. DRAM module 116 provides memory accessible to IC die 104(1) via circuitry in metal interconnect layers 108(1)-108(3) in package substrate 106, and package substrate 106 is electrically coupled to DRAM module 116 via via 112. IC die 104(1) is coupled to metal interconnect layers 108(1)-108(3) in package substrate 106 via die interconnect 118. Die-to-die interconnects can be formed between stacked IC dies 104(1)-104(3) and between die interconnects 120(1)-120(3) that are in contact with each other when IC dies 104(1)-104(3) are bonded together.

[0028] Figure 2 is a side view of the IC package 100 in Figure 1. As discussed below, the IC package 100 includes a stack of FS-BEOL metallization structures to BS-BEOL metallization structures to provide a 3D die stack of IC dies 104(1)-104(3) to facilitate improved die-to-die interconnection. In this regard, as shown in Figure 2, the first bottom IC die 104(1) in the IC die module 102 includes an FS-BEOL metallization structure 200 and a BS-BEOL metallization structure 202. The IC die 104(1) includes a semiconductor layer 204 disposed between the FS-BEOL metallization structure 200 and the BS-BEOL metallization structure 202 of the IC die 104(1). The semiconductor layer 204 is the location where active semiconductor elements are formed in the IC die 104(1). For example, the active semiconductor element formed in the semiconductor layer 204 may be a field-effect transistor (FET). For example, the FET can be part of a complementary metal-oxide-semiconductor (CMOS) circuit formed in the semiconductor layer 204 as a positive (P) type FET (PFET) and a negative (N) type FET (NFET). In this example, the FS-BEOL metallization structure 200 of the IC die 104(1) is adjacent to and disposed on the package substrate 106 to provide electrical connection and mechanical support. The FS-BEOL metallization structure 200 is a metallization structure located on the front side FS1 of the IC die 104(1). In this example, the FS-BEOL metallization structure 200 is disposed adjacent to the front side FS1 of the semiconductor layer 204. The FS-BEOL metallization structure 200 includes a metal interconnect layer 206, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) between the conductive bumps 110 and the elements in the semiconductor layer 204 of the IC die 104(1). BEOL is typically the second part of IC manufacturing, in which individual active components formed in semiconductor layer 204 are interconnected to metal lines in metal interconnect layer 206 to provide die connection docking. The FS-BEOL metallization structure 200 disposed on the front side FS1 of semiconductor layer 204 is formed in the front-end process (FEOL) process for IC die 104(1).

[0029] In this example, the FS-BEOL metallization structure 200 includes a die interconnect 208 electrically coupled to the top metal interconnect layer 108(1) of the package substrate 106. The die interconnect 208 is also electrically coupled to an active semiconductor element in the semiconductor layer 204 to provide die interconnect to the IC die 104(1). The die interconnect 208 of the FS-BEOL metallization structure 200 can be electrically coupled to conductive bumps 110 via metal traces in the metal interconnect layers 108(1)-108(3) of the package substrate 106 to facilitate external interconnect to the IC die 104(1). In this regard, the package substrate 106 includes a substrate interconnect 210 electrically coupled to the bottom metal interconnect layer 108(3) and the conductive bumps 110 to form an electrical connection path between the conductive bumps 110 and the metal interconnect layers 108(1)-108(3).

[0030] Referring again to FIG2, the bottom IC die 104(1) in IC die module 102 also includes a BS-BEOL metallization structure 202 on the back side BS1 of IC die 104(1). In this example, the BS-BEOL metallization structure 202 is configured to be adjacent to the back side BS1 of semiconductor layer 204. The BS-BEOL metallization structure 202 is also formed in the FEOL process for IC die 104(1). The BS-BEOL metallization structure 202 includes a metal interconnect layer 212, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) to semiconductor elements in semiconductor layer 204 of IC die 104(1). In this example, the BS-BEOL metallization structure 202 includes a die interconnect 214, which is electrically coupled to an active semiconductor element in the semiconductor layer 204 to provide a die interconnect from the back side BS1 of the IC die 104(1) to the IC die 104(1).

[0031] Note that the IC die 104(1) in the IC package 100 in FIG2 has been flipped so that in this example, the FS-BEOL metallization structure 200 is positioned below the semiconductor layer 204 and adjacent to the front side FS1 of the semiconductor layer 204 in the Z-axis direction. In this example, the BS-BEOL metallization structure 202 is positioned above the semiconductor layer 204 and adjacent to the back side BS1 of the semiconductor layer 204 in the Z-axis direction.

[0032] Continuing to refer to FIG2, the IC die module 102 of IC package 100 includes two other IC dies, namely IC dies 104(2) and 104(3). IC dies 104(2) and 104(3) are stacked on IC die 104(1) in the direction perpendicular to the Z-axis to achieve a 3D stacked arrangement. It is also desirable to provide electrical interfaces to IC dies 104(2) and 104(3). Such electrical interfaces may include external electrical connections via package substrate 106 and conductive bumps 110. Such electrical interfaces may also include die-to-die interconnects with other IC dies 104(1)-104(3) and die-to-die interconnects between other IC dies 104(1)-104(3).

[0033] Accordingly, the second IC die 104(2) of the IC die module 102 in FIG2 includes an FS-BEOL metallization structure 216 and a BS-BEOL metallization structure 218. The IC die 104(2) also includes a semiconductor layer 220 disposed between the FS-BEOL metallization structure 216 and the BS-BEOL metallization structure 218 of the IC die 104(2). The semiconductor layer 220 is the location where active semiconductor elements are formed in the IC die 104(2). In this example, in a stacked arrangement, the FS-BEOL metallization structure 216 of the IC die 104(2) is adjacent to the IC die 104(1) and is disposed on the IC die 104(1). For example, the IC die 104(2) can be bonded to the IC die 104(1) via an adhesive (such as, for example, a thermocompressible adhesive). The FS-BEOL metallization structure 216 is a metallization structure located on the front side FS2 of the IC die 104(2). In this example, the FS-BEOL metallization structure 216 is configured to be adjacent to the front side FS2 of the semiconductor layer 220. The FS-BEOL metallization structure 216 includes a metal interconnect layer 222, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) to semiconductor elements in the semiconductor layer 220 of the IC die 104(2). In this example, the FS-BEOL metallization structure 216 includes a die interconnect 224, which is electrically coupled to a die interconnect 214 in the BS-BEOL metallization structure 202 of the IC die 104(1) to provide a die-to-die interconnect between the IC die 104(1) and the IC die 104(2).

[0034] In this example, the first IC die 104(1) and the second IC die 104(2) are arranged such that the BS-BEOL metallization structure 202 of the first IC die 104(1) is located adjacent to the FS-BEOL metallization structure 216 of the second IC die 104(2) to provide a BS-BEOL metallization structure to FS-BEOL metallization structure stack. The IC dies 104(1) and 204(2) are stacked via the FS-BEOL metallization structure 216 to the BS-BEOL metallization structure 202. This is the opposite of, for example, the IC package 300 in FIG3, which illustrates an alternative arrangement where the FS-BEOL metallization structure 216 of the IC die 104(2) is stacked adjacent to the FS-metallization structure 302 of the bottom IC die 304. Referring back to Figure 2, a circuit path is provided for the die-to-die interconnect between stacked IC dies 104(1) and 104(2), from the BS-BEOL metallization structure 202 of IC die 104(1) to the FS-BEOL metallization structure 216 of the second IC die 104(2). The BS-BEOL metallization structure (including the BS-BEOL metallization structure 202 of the first IC die 104(1)) is typically thinner than the FS-BEOL metallization structure (including the FS-BEOL metallization structure 216 of the second IC die 104(2)) (in the vertical direction of the Z-axis in this example). For example, the thickness of the BS-BEOL metallization structure 202, shown as D1, can be 500 nanometers (nm), while the thickness of the FS-BEOL metallization structure 216, shown as D2, can be between 1500 and 2000 nm. This is because FS-BEOL metallization structures typically include metal interconnect layers that provide interconnections between semiconductor elements within the same semiconductor layer via element contacts located on the front side of that semiconductor layer on the same semiconductor layer of the IC die. Therefore, compared to BS-BEOL metallization structures, FS-BEOL metallization structures may require more metal interconnect layers, resulting in a thicker FS-BEOL metallization structure. Conversely, BS-BEOL metallization structures may require fewer metal interconnect layers, which may only include circuitry for power rails of the semiconductor layer or may not require access to other connections to the semiconductor layer from the front side of the semiconductor layer.

[0035] Therefore, in this example, the circuitry from the thinner BS-BEOL metallization structure 202 of the first IC die 104(1) to the FS-BEOL metallization structure 216 of the second IC die 104(2) allows for a shorter circuit path between the first IC die 104(1) and the second IC die 104(2) for die-to-die interconnects. Providing a shorter circuit path between IC dies 104(1) and 104(2) enables lower resistance and / or lower capacitance in these die-to-die interconnects to achieve faster and / or more compatible performance of the semiconductor elements in the IC dies 104(1) and 104(2). Another advantage of stacking the FS-BEOL metallization structure 216 adjacent to the second IC die 104(2) with the BS-BEOL metallization structure 202 of the first IC die 104(1) to provide die-to-die interconnects therebetween could be a manufacturing consideration. It may be more feasible to form circuitry structures (e.g., TSVs) in a thinner metallization structure (such as the BS-BEOL metallization structure 202) compared to a thicker metallization structure (such as the FS-BEOL metallization structure 216). For example, it may be easier to form dense TSV structures in the BS-BEOL metallization structure 202 because the aspect ratio is limited to 1:10. Thus, for example, if the thickness of the BS-BEOL metallization structure is 500 nm, a 50 nm diameter TSV circuitry structure may be possible. This situation could allow for the formation of a higher density of circuitry structures, for example, in the BS-BEOL metallization structure 202 of the first IC die 104(1), to support a higher density of die interconnects to the IC die 104(1). With technological advancements, more and more semiconductor devices are being manufactured within a given die area in IC chips.

[0036] Referring again to FIG2, the IC die 104(2) in the IC die module 102 also includes a BS-BEOL metallization structure 218 on the back side BS2 of the IC die 104(2). In this example, the BS-BEOL metallization structure 218 is configured to be adjacent to the back side BS2 of the semiconductor layer 220. The BS-BEOL metallization structure 218 is also formed in the FEOL process for the IC die 104(2). The BS-BEOL metallization structure 218 includes a metal interconnect layer 226, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) to the semiconductor elements in the semiconductor layer 220 of the IC die 104(2). In this example, the BS-BEOL metallization structure 218 also includes a die interconnect 228 electrically coupled to an active semiconductor element in the semiconductor layer 220 and another metallization structure 230 to provide a die interconnect from the back side BS2 of the IC die 104(2) to the IC die 104(2). For example, as shown in FIG1, the metallization structure 230 may facilitate the electrical coupling of another IC die (such as DRAM module 116) to IC die module 102 and provide electrical interconnects to IC dies 104(1)-104(3). The metallization structure 230 may be a package substrate, such as, for example, an ETS or RDL. The metallization structure 230 includes one or more metal interconnect layers 232(1)-232(2), which include metal traces configured to route electrical signals. Therefore, in order to provide a die interconnect between the metallization structure 230 and the IC die 104(2), the metallization structure 230 can be bonded to the IC die module 102 to connect the metal interconnects in the metal interconnect layers 232(1)-232(2) to the die interconnect 228 of the second IC die 104(2).

[0037] Continuing to refer to FIG2, the second IC die 104(2) of the IC die module 102 in FIG2 includes an FS-BEOL metallization structure 216 and a BS-BEOL metallization structure 218. The IC die 104(2) also includes a semiconductor layer 220 disposed between the FS-BEOL metallization structure 216 and the BS-BEOL metallization structure 218 of the IC die 104(2). The semiconductor layer 220 is the location where active semiconductor elements are formed in the IC die 104(2). In this example, in a stacked arrangement, the FS-BEOL metallization structure 216 of the IC die 104(2) is adjacent to the IC die 104(1) and is disposed on the IC die 104(1). For example, the IC die 104(2) can be bonded to the IC die 104(1) via an adhesive (such as, for example, a thermocompressible adhesive). The FS-BEOL metallization structure 216 is a metallization structure located on the front side FS2 of the IC die 104(2). In this example, the FS-BEOL metallization structure 216 is configured to be adjacent to the front side FS2 of the semiconductor layer 220. The FS-BEOL metallization structure 216 includes a metal interconnect layer 222, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) to semiconductor elements in the semiconductor layer 220 of the IC die 104(2). In this example, the FS-BEOL metallization structure 216 includes a die interconnect 224, which is electrically coupled to a die interconnect 214 in the BS-BEOL metallization structure 202 of the IC die 104(1) to provide a die-to-die interconnect between the IC die 104(1) and the IC die 104(2).

[0038] In this example, the first IC die 104(1) and the second IC die 104(2) are arranged such that the BS-BEOL metallization structure 202 of the first IC die 104(1) is located adjacent to the FS-BEOL metallization structure 216 of the second IC die 104(2) to provide a stack of FS-BEOL metallization structure 216 to BS-BEOL metallization structure 202. A circuit path is provided from the BS-BEOL metallization structure 202 of the first IC die 104(1) to the FS-BEOL metallization structure 216 of the second IC die 104(2) for die-to-die interconnection between the stacked IC dies 104(1) and 104(2). BS-BEOL metallization structures (BS-BEOL metallization structure 202 including the first IC die 104(1)) are typically thinner than FS-BEOL metallization structures (FS-BEOL metallization structure 216 including the second IC die 104(2)) (in the vertical direction of the Z-axis in this example). For example, the thickness of BS-BEOL metallization structure 202, shown as D1, can be 500 nm, while the thickness of FS-BEOL metallization structure 216, shown as D2, can be between 1500 and 2000 nm. This is because FS-BEOL metallization structures typically include metal interconnect layers that provide interconnections between semiconductor elements in the semiconductor layer via element contacts located on the front side of the same semiconductor layer on their IC die. Therefore, more metal interconnect layers may be required in FS-BEOL metallization structures compared to BS-BEOL metallization structures, resulting in thicker FS-BEOL metallization structures. For example, fewer metal interconnect layers may be required in a BS-BEOL metallization structure. These fewer metal interconnect layers may only include, for example, circuitry for power rails of the semiconductor layer, or may not require access to other connections to the semiconductor layer from the front side of the semiconductor layer.

[0039] Therefore, in this example, the circuitry from the thinner BS-BEOL metallization structure 202 of the first IC die 104(1) to the FS-BEOL metallization structure 216 of the second IC die 104(2) allows for a shorter circuit path between the first IC die 104(1) and the second IC die 104(2) for die-to-die interconnects. Providing a shorter circuit path between IC dies 104(1) and 104(2) enables lower resistance and / or lower capacitance in these die-to-die interconnects to achieve faster and / or more compatible performance of the semiconductor elements in the IC dies 104(1) and 104(2). Another advantage of stacking the FS-BEOL metallization structure 216 adjacent to the second IC die 104(2) with the BS-BEOL metallization structure 202 of the first IC die 104(1) to provide die-to-die interconnects therebetween can be for manufacturing considerations. For example, it may be more feasible to form circuitry structures (e.g., TSVs) in a thinner metallization structure (such as the BS-BEOL metallization structure 202) compared to a thicker metallization structure (such as the FS-BEOL metallization structure 216). This situation may allow for the formation of a higher density of circuitry structures, for example, in the BS-BEOL metallization structure 202 of the first IC die 104(1), to support a higher density of die interconnects to the IC die 104(1). With technological advancements, more and more semiconductor devices are being fabricated in IC dies for a given die area.

[0040] Referring again to FIG2, the IC die 104(2) in the IC die module 102 also includes a BS-BEOL metallization structure 218 on the back side BS2 of the IC die 104(2). In this example, the BS-BEOL metallization structure 218 is configured to be adjacent to the back side BS2 of the semiconductor layer 220. The BS-BEOL metallization structure 218 is also formed in the FEOL process for the IC die 104(2). The BS-BEOL metallization structure 218 includes a metal interconnect layer 226, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) to the semiconductor elements in the semiconductor layer 220 of the IC die 104(2). In this example, the BS-BEOL metallization structure 218 also includes a die interconnect 228 electrically coupled to an active semiconductor element in semiconductor layer 204 and another metallization structure 230 to provide a die interconnect from the back side BS2 of IC die 104(2) to IC die 104(2). For example, as shown in FIG2, the metallization structure 230 may facilitate the electrical coupling of another IC die (such as DRAM module 116) to IC die module 102 and provide electrical interconnects to IC dies 104(1)-104(3). The metallization structure 230 may be a package substrate, such as, for example, an ETS or RDL. The metallization structure 230 includes one or more metal interconnect layers 232(1)-232(2), which include metal traces configured to route electrical signals. Therefore, in order to provide a die interconnect between the metallization structure 230 and the IC die 104(2), the metallization structure 230 can be bonded to the IC die module 102 to connect the metal interconnects in the metal interconnect layers 232(1)-232(2) of the metallization structure 230 to the die interconnect 228 of the second IC die 104(2).

[0041] Continuing to refer to FIG2, the third IC die 104(3) of the IC die module 102 in FIG2 includes an FS-BEOL metallization structure 234 and a BS-BEOL metallization structure 236. The IC die 104(3) also includes a semiconductor layer 238 disposed between the FS-BEOL metallization structure 234 and the BS-BEOL metallization structure 236 of the IC die 104(3). The semiconductor layer 238 is the location in the IC die 104(3) where active semiconductor elements are formed. In this example, in a stacked arrangement, the FS-BEOL metallization structure 234 of the IC die 104(3) is adjacent to the IC die 104(1) and is disposed on the IC die 104(1). For example, the IC die 104(3) can be bonded to the IC die 104(1) via an adhesive (such as, for example, a thermocompressible adhesive). The FS-BEOL metallization structure 234 is a metallization structure located on the front side FS2 of the IC die 104(3). In this example, the FS-BEOL metallization structure 234 is configured to be adjacent to the front side FS2 of the semiconductor layer 238. The FS-BEOL metallization structure 234 includes a metal interconnect layer 240, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) to semiconductor elements in the semiconductor layer 238 of the IC die 104(3). In this example, the FS-BEOL metallization structure 234 includes a die interconnect 242, which is electrically coupled to a die interconnect 214 in the BS-BEOL metallization structure 202 of the IC die 104(1) to provide a die-to-die interconnect between the IC die 104(1) and the IC die 104(3).

[0042] In this example, the first IC die 104(1) and the third IC die 104(3) are arranged such that the BS-BEOL metallization structure 202 of the first IC die 104(1) is located adjacent to the FS-BEOL metallization structure 234 of the third IC die 104(3) to provide a stack of FS-BEOL metallization structure 234 to BS-BEOL metallization structure 202. A circuit path is provided from the BS-BEOL metallization structure 202 of IC die 104(1) to the FS-BEOL metallization structure 234 of the third IC die 104(3) for die-to-die interconnection between the stacked IC dies 104(1) and 104(3). In this example, the BS-BEOL metallization structure (including the BS-BEOL metallization structure 202 of the first IC grain 104(1)) is also thinner than the FS-BEOL metallization structure 234 of the third IC grain 104(3) (in the vertical direction of the Z-axis in this example). For example, the thickness of the BS-BEOL metallization structure 202, shown as D1, can be 500 nm, while the thickness of the FS-BEOL metallization structure 234, also shown as D2 in this example, can be between 1500 and 2000 nm.

[0043] Therefore, in this example, the circuit from the thinner BS-BEOL metallization structure 202 of the first IC die 104(1) to the FS-BEOL metallization structure 234 of the third IC die 104(3) allows for a shorter circuit path between the first IC die 104(1) and the third IC die 104(3) for die-to-die interconnects. Providing a shorter circuit path between IC dies 104(1) and 104(3) can provide lower resistance and / or lower capacitance for these die-to-die interconnects to achieve faster and / or more compatible performance of the semiconductor elements in the IC dies 104(1) and 104(3). Another advantage of stacking the FS-BEOL metallization structure 234 of the third IC die 104(1) with the BS-BEOL metallization structure 202 of the first IC die 104(1) to provide die-to-die interconnects therebetween can be for manufacturing considerations. For example, it may be more feasible to form circuitry structures (e.g., TSVs) in a thinner metallization structure (such as the BS-BEOL metallization structure 202) compared to a thicker metallization structure (such as the FS-BEOL metallization structure 234). This situation may allow for the formation of a higher density of circuitry structures, for example, in the BS-BEOL metallization structure 202 of the first IC die 104(1), to support a higher density of die interconnects to the IC die 104(1). With technological advancements, more and more semiconductor devices are being fabricated in IC dies for a given die area.

[0044] Referring again to FIG2, the IC die 104(3) in the IC die module 102 also includes a BS-BEOL metallization structure 236 on the back side BS2 of the IC die 104(3). In this example, the BS-BEOL metallization structure 236 is configured to be adjacent to the back side BS2 of the semiconductor layer 238. The BS-BEOL metallization structure 236 is also formed in the FEOL process for the IC die 104(3). The BS-BEOL metallization structure 236 includes a metal interconnect layer 244, which includes metal lines for carrying electrical signals (e.g., input / output (I / O) signals, power signals) to the semiconductor elements in the semiconductor layer 238 of the IC die 104(3). In this example, the BS-BEOL metallization structure 236 also includes a die interconnect 246, which is electrically coupled to an active semiconductor element in the semiconductor layer 238 and a metallization structure 230 to provide a die interconnect from the back side BS2 of the IC die 104(3) to the IC die 104(3). Therefore, in order to provide a die interconnect between the metallization structure 230 and the IC die 104(3), the metallization structure 230 can be bonded to the IC die module 102 to connect the metal interconnects in the metal interconnect layers 232(1)-232(2) of the metallization structure 230 to the die interconnect 246 of the third IC die 104(3).

[0045] Similarly, it should be noted that the die-to-die interconnects between IC dies 104(1)-104(3) in IC package 100 can also be provided via package substrate 106 and / or metallization structure 230. These die-to-die interconnects can be provided via interconnects other than the interconnects between the FS-BEOL metallization structures 216, 234 of the second and / or third IC dies 104(2), 204(3) and the BS-BEOL metallization structure 202 of the first IC die 104(1). For example, as shown in IC package 100 in FIG1, vias 112 can be provided adjacent to IC dies 104(1)-104(3) in IC die module 102. The vias 112 can be interconnected to metal lines in the metal interconnect layers 232(1), 108(1) of metallization structure 230 and / or metal interconnect layers 232(1), 108(1) of package substrate 106. In this manner, electrical signal routing between the metallization structure 230 and / or the package substrate 106 can be provided. The circuitry provided between the metallization structure 230 and / or the package substrate 106 is provided by allowing the die-to-die interconnect between the first IC die 104(1) and the second and / or third IC dies 104(2), 104(3) via the FS-BEOL metallization structure 200 of the first IC die 104(1) via the BS-BEOL metallization structures 218, 236 of the second and / or third IC dies 104(2), 104(3). The circuitry to the first IC die 104(1) is routed via the package substrate 106 to the metal interconnect layer 108(1) and to the die interconnect 208 of the first IC die 104(1). As shown in Figure 2, the circuit to the second and / or third IC chips 104(2), 104(3) is routed via the metallization structure 230 to the metal interconnect layer 232(1) and to the chip interconnects 228, 246 to the second and / or third IC chips 104(2), 104(3).

[0046] Note that the terms "top" and "bottom" are relative terms when the metallization structures in Figure 2 are oriented in the Z-axis or vertical direction. However, it should also be noted that the IC package 100 can also be oriented in a manner that is rotated 180 degrees from the orientation shown in Figure 2, where a metallization structure indicated as being above or on top of another metallization structure will be below that other metallization structure. Therefore, the terms "top" and "bottom" are relative terms and do not imply a strict limitation on the orientation of one metallization structure relative to another metallization structure.

[0047] FIG4 is a flowchart illustrating an exemplary process 400 for manufacturing an IC package (including but not limited to IC package 100 in FIG1 and FIG2) that uses FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking of IC die modules. The process 400 in FIG4 will be described with reference to the exemplary IC package 100 in FIG1 and FIG2.

[0048] Accordingly, process 400 includes forming a first IC die 104(1) (block 402 in FIG. 4). The first IC die 104(1) is formed by forming a first BS-BEOL metallization structure 202 (block 404 in FIG. 4). The first IC die 104(1) is also formed by forming a first semiconductor layer 204 adjacent to the first BS-BEOL metallization structure 202 (block 406 in FIG. 4). The first IC die 104(1) is also formed by forming an FS-BEOL metallization structure 200 adjacent to the first semiconductor layer 204, wherein the first semiconductor layer 204 is disposed between the first BS-BEOL metallization structure 202 and the first FS-BEOL metallization structure 200 (block 408 in FIG. 4). Process 400 also includes forming second IC dies 104(2) and 104(3) (block 410 in FIG. 4). The second IC dies 104(2) and 104(3) are formed by forming second BS-BEOL metallization structures 218 and 236 (block 412 in FIG4). The second IC dies 104(2) and 104(3) are also formed by forming second semiconductor layers 220 and 238 adjacent to the second BS-BEOL metallization structures 218 and 236 (block 414 in FIG4). The second IC dies 104(2) and 104(3) are also formed by forming second FS-BEOL metallization structures 216 and 234 adjacent to the second semiconductor layers 220 and 238, wherein the second semiconductor layers 220 and 238 are disposed between the second BS-BEOL metallization structures 218 and 236 and the second FS-BEOL metallization structures 216 and 234 (block 416 in FIG4).

[0049] Figures 5A-5C are flowcharts illustrating an exemplary manufacturing process 500 for manufacturing IC dies supporting a stack from FS-BEOL metallization structure to BS-BEOL metallization structure. Figures 6A-6F illustrate exemplary manufacturing stages of the IC dies according to the manufacturing process 500 in Figures 5A-5C. The manufacturing process 500 for manufacturing IC dies in Figures 5A-5C can be used to manufacture any of the IC dies 104(1)-104(3) in the IC package 100 of Figures 1 and 2, for example. The manufacturing process 500 in Figures 5A-5C will be described below using the IC die 104(1) in the IC package 100 as an example in conjunction with the manufacturing stages in Figures 6A-6F.

[0050] As shown in the exemplary manufacturing stage 600A in FIG. 6A, process 500 includes forming a first BS-BEOL metallization structure 202 on a substrate 602 such that a first surface 604 of the first BS-BEOL metallization structure 202 is disposed adjacent to a first surface 606 of the substrate (block 502 in FIG. 5A). As an example, in an RDL process, the first BS-BEOL metallization structure 202 may be formed as an RDL layer. The substrate 602 provides a support structure for forming the first BS-BEOL metallization structure 202 and / or provides insulation as a dielectric layer. The substrate 602 has a height H1 in the Z-axis direction, as shown in FIG. 5A. The substrate 602 may be, for example, a dielectric material. As shown in exemplary manufacturing stage 600B in FIG. 6B, the next step in process 500 is to form a carrier wafer 608 (block 504 in FIG. 5A) on the second surface 610 of the first BS-BEOL metallization structure 202, which is opposite to the first surface 604 of the first BS-BEOL metallization structure 202. The carrier wafer 608 is used to provide handles for the first BS-BEOL metallization structure 202 and the substrate 602 for further processing. As shown in exemplary manufacturing stage 600C in FIG. 6C, the next step in process 500 is to thin the substrate 602 (block 506 in FIG. 5A). In exemplary manufacturing stage 600C of FIG. 6C, the height of the substrate 602 is thinned in the Z-axis direction to a height H2, which is a reduced height compared to the height H1 of the substrate 602 in manufacturing stages 600A and 600B of FIG. 6A and 6B.

[0051] As shown in the exemplary manufacturing stage 600D in FIG. 6D, the next step in process 500 is to form a first semiconductor layer 204 (block 508 in FIG. 5B) on a thinned second surface 612 of the substrate 602 opposite to a first surface 606 of the substrate 602. An active semiconductor element, such as a FET, may then be formed in the first semiconductor layer 204. Contacts are also formed to contact the active semiconductor element formed in the first semiconductor layer 204. A first FS-BEOL metallization structure 200 is also formed adjacent to the first semiconductor layer 204 and on the first semiconductor layer 204 to form a first IC die 104 (1). As previously discussed, the first FS-BEOL metallization structure 200 provides electrical signal routing between the metal lines in the first FS-BEOL metallization structure 200 and the active semiconductor element formed in the first semiconductor layer 204. As shown in the exemplary manufacturing stage 600E in FIG. 6E, the next step in process 500 may be to form conductive bumps 110 (such as solder bumps) that make die interconnect contacts with the first FS-BEOL metallization structure 200, as shown in FIG. 6E (block 510 in FIG. 5). Alternatively, a package substrate (such as package substrate 106 in FIG. 1 and FIG. 2) may be formed on the first FS-BEOL metallization structure 200 to provide additional support and electrical signal routing.

[0052] As shown in the exemplary manufacturing stage 600F in FIG. 6F, the next step in process 500 is to remove the carrier wafer 608 from the second surface 610 of the first BS-BEOL metallization structure 202 and stack the second FS-BEOL metallization structures 216, 234 (block 512 in FIG. 5C) of the second IC dies 104(2), 104(3) on the first BS-BEOL metallization structure 202 of the first IC die 104(1). The second IC dies 104(2), 104(3) can be manufactured by the same manufacturing process for manufacturing the first IC die 104(1) as described above with reference to manufacturing stages 600A-600E in FIG. 5A-5B and FIG. 6A-6E.

[0053] As shown in the IC package 100 in Figures 1 and 2, the FS-BEOL metallization structures 216 and 234 of the second and third IC dies 104(2) and 104(3) are directly mounted to the BS-BEOL metallization structure 202 of the first IC die 104(1). This requires that the die interconnects 224 and 242 of the FS-BEOL metallization structures 216 and 234 of the second and third IC dies 104(2) and 104(3) be aligned with the die interconnects 214 of the BS-BEOL metallization structure 202 of the first IC die 104(1). This may be difficult to achieve in the manufacturing process, and / or the risk of misalignment of the non-die interconnects 214, 224, 242 may be difficult to achieve. Misalignment of the die interconnects 214, 224, 242 can increase the resistance of the die-to-die interconnects achieved via the FS-BEOL metallization structures 216, 234 and the BS-BEOL metallization structure 202. It may be more desirable to provide greater flexibility in providing interconnect patterns between the die interconnects 214, 224, 242 of the FS-BEOL metallization structures 216, 234 and the BS-BEOL metallization structure 202.

[0054] Accordingly, FIG7 is a side view of another exemplary IC package 700 employing IC die modules 702 utilizing IC dies 104(1)-104(3) in IC package 100 of FIG1 and FIG2. Common elements between IC package 700 in FIG7 and IC package 100 in FIG1 and FIG2 are illustrated with the same element reference numerals in FIG1 and FIG2 and will not be described again. However, as shown in FIG7, IC package 700 includes an intermediate metallization structure 704 disposed between the BS-BEOL metallization structure 202 of the first IC die 104(1) and the FS-BEOL metallization structures 216, 234 of the second and third IC dies 104(2), 104(3) to facilitate more flexible die-to-die interconnection between the first IC die 104(1) and the second and third IC dies 104(2), 104(3). As an example, the intermediate metallization structure 704 may be formed by RDL.

[0055] Referring to FIG7, the intermediate metallization structure 704 includes one or more intermediate metal interconnect layers 706(1), 706(2), each of which includes one or more intermediate interconnects 708(1), 708(2). At least one of the first die interconnects 214 of the first BS-BEOL metallization structure 202 of the first IC die 104(1) is coupled to at least one of the intermediate interconnects 708(1) of the bottom intermediate metal interconnect layer 706(1). In addition, at least one of the second and / or third die interconnects 224, 236 of the second and / or third FS-BEOL metallization structures 216, 234 of the second and / or third IC dies 104(2), 104(3) is coupled to at least one of the intermediate interconnects 708(2) of the top intermediate metal interconnect layer 706(2). Intermediate metal interconnect layers 706(1) and 706(2) provide electrical connections and routing between them to provide desired electrical signal routing between the first BS-BEOL metallization structure 202 of the first IC die 104(1) and the second and / or third FS-BEOL metallization structures 216 and 234 of the second and / or third IC dies 104(2) and 104(3) to provide desired die-to-die interconnects.

[0056] Also as shown in FIG7, as a result of bonding IC dies 104(2), 104(3) to IC die 104(1), a gap space 710 for use in circuit routing is provided in the IC package 700 between adjacent IC dies 104(2), 104(3) in the X-axis direction. In the case of providing an intermediate metallization structure 704, this allows additional circuit routing paths to be formed between IC dies 104(2), 104(3) down to the intermediate metallization structure 704 to achieve additional electrical signal routing capability. For example, one or more vias 712 can be formed in the gap space 710, which are coupled between the additional metallization structure 230 and the intermediate metallization structure 704 to provide additional electrical signal routing to the first IC die 104(1). The electrical signal route from the intermediate metallization structure 704 can then be routed to one or both of the other IC dies 104(2), 104(3) via the additional metallization structure 230. The electrical signal route from the intermediate metallization structure 704 via the additional metallization structure 230 can also be routed to the package substrate 106 via the via 112, as shown in FIG8.

[0057] Thus, via the IC package 700 in FIG7, at least three (3) electrical signal routing paths for die interconnection are provided. One electrical signal routing path is used for die-to-die interconnection between the BS-BEOL metallization structure 202 of IC die 104 (1) and the FS-BEOL metallization structures 216, 234 of IC dies 104 (2), 104 (3) via the intermediate metallization structure 704. Another electrical signal routing path is between the intermediate metallization structure 704 and the additional metallization structure 230, which can then be routed via the BS-BEOL metallization structures 218, 236 of the second and third IC dies 104 (2), 104 (3). Another electrical signal routing path exists between the additional metallization structure 230 and the package substrate 106, which provides an electrical signal routing from the BS-BEOL metallization structures 218, 236 of the second and third IC dies 104(2), 104(3) via the additional metallization structure 230 and the package substrate 106 to the FS-BEOL metallization structure 200 of the first IC die 104(1). It should also be noted that if an additional IC die (such as the DRAM module 116 shown in FIG. 8) is mounted to the additional metallization structure 230, an electrical signal routing can be provided from the intermediate metallization structure 704 via the gap space 710 and via the additional metallization structure 230 to that additional IC die.

[0058] Figures 9A-9E are flowcharts illustrating an exemplary process 900 for manufacturing an IC package employing an IC die module stacked using FS-BEOL metallization structures to provide 3D die stacking, wherein the IC die module also includes an intermediate metallization layer disposed between the FS-BEOL and BS-BEOL metallization structures to facilitate die-to-die interconnection. For example, process 900 in Figures 9A-9E can be used to manufacture the IC package 700 in Figures 7 and 8. Figures 10A-10M illustrate exemplary manufacturing stages during the manufacture of the IC package according to process 900 in Figures 9A-9E. Process 900 in Figures 9A-9E will be discussed below in conjunction with the manufacturing stages in Figures 10A-10M and with reference to the components of the IC package 700 in Figures 7 and 8 as examples.

[0059] Accordingly, as shown in the exemplary manufacturing stage 1000A in FIG10A, the step in manufacturing process 900 for forming an IC package using an FS-BEOL metallization structure to a BS-BEOL metallization structure stack to provide a 3D die stack is to cut the manufactured IC dies, as shown in the first IC die 104(1). The first IC die 104(1) is attached to a carrier wafer 1002 to support the first IC die 104(1) in further manufacturing steps (block 902 in FIG9A). Through-holes 112(1) are also formed to form circuit paths that are not directly die-to-die interconnects as desired (block 902 in FIG9A). As shown in exemplary manufacturing stage 1000B in FIG10B, another step in manufacturing process 900 is to apply molding compound 1004 to the IC die 104(1) mounted on carrier wafer 1002 and around via 112(1) to isolate the IC die 104(1) and via 112(1) (block 904 in FIG9A). As shown in exemplary manufacturing stage 1000C in FIG10C, another step in manufacturing process 900 is to remove carrier wafer 1002 (block 906 in FIG9A). Steps 902-906 prepare the first IC die 104(1) for stacking with other IC dies in later manufacturing steps discussed hereafter.

[0060] As shown in the exemplary manufacturing stage 1000D in FIG10D, another step in manufacturing process 900 is to prepare second and third IC dies 104(2), 104(3). The second and third IC dies 104(2), 104(3) are attached to carrier wafer 1006 to support the second and third IC dies 104(2), 104(3) in further manufacturing steps (block 908 in FIG9B). Through-hole 112(2) is also formed to form a circuit path that is not a direct die-to-die interconnect as desired (block 908 in FIG9A). As shown in the exemplary manufacturing stage 1000E in FIG10E, another step in the manufacturing process 900 is to apply molding compound 1008 on IC dies 104(2), 104(3) mounted on carrier wafer 1006 and around via 112(1) to isolate IC dies 104(2), 104(3) and via 112(2) (block 910 in FIG9B).

[0061] As shown in the exemplary manufacturing stage 1000F in FIG10F, another step in manufacturing process 900 is to remove (e.g., grind away) molding compound 1008 to expose the top surface 1010(2) of via 112(2) (block 912 in FIG9C). Via 112(2) is also ground away to provide the top surface 1010(2) (block 912 in FIG9C). This allows via 112(2) to be connected to via 112(1) formed together with the first IC die 104(1) in FIG10C when IC dies 104(1)-104(3) are stacked in later manufacturing steps to form IC package 700. As shown in the exemplary manufacturing stage 1000G in FIG10G, another step in manufacturing process 900 is to form an intermediate metallization structure 704 (block 914 in FIG9C) on the FS-BEOL metallization structures 216, 234 of IC dies 104(2), 104(3). In this example, the intermediate metallization structure 704 is formed such that the intermediate interconnect 708(2) of the intermediate metal interconnect layer 706(2) is formed to contact the die interconnects 224, 242 of IC dies 104(2), 104(3), as discussed above. As an example, the intermediate metallization structure 704 may be formed as an RDL.

[0062] As shown in the exemplary manufacturing stage 1000H in FIG10H, another step in the manufacturing process 900 is to bond the BS-BEOL metallization structure 202 of the IC die 104(1) to the intermediate metallization structure 704 (block 916 in FIG9D), which is part of the IC package 700. The die interconnect 214 of the IC die 104(1) is positioned to contact the intermediate interconnect 708(1) of the intermediate metal interconnect layer 706(1) of the intermediate metallization structure 704, as discussed above. The IC die 104(1) can be bonded to the intermediate metallization structure 704 using thermocompression bonding to form a thermocompression bond between the two. As a result of bonding the IC die 104(1) to the intermediate metallization structure 704, vias 112(1) and 112(2) are also bonded together. As shown in exemplary manufacturing stage 1000I in FIG. 10I, another step in manufacturing process 900 is to remove (e.g., grind away) molding compound 1004 to expose the top surface 1010(1) of via 112(1) (block 918 in FIG. 9D). As shown in exemplary manufacturing stage 1000J in FIG. 10J, another step in manufacturing process 900 is to form a package substrate 106 (block 920 in FIG. 9D) on the FS-BEOL metallization structure 200 of IC die 104(1). For example, the package substrate 106 may be formed as an RDL.

[0063] As shown in the exemplary manufacturing stage 1000K in FIG10K, another step in manufacturing process 900 is to form conductive bumps 110 and attach them to the substrate interconnects 210 of the package substrate 106 (block 922 in FIG9E). As shown in the exemplary manufacturing stage 1000L in FIG10L, another step in manufacturing process 900 is to decouple the carrier wafer 1006 from the IC package 700 (block 924 in FIG9E). As shown in the exemplary manufacturing stage 1000M in FIG10M, another step in manufacturing process 900 is to bond the additional IC die 230 / DRAM module 116 to the IC package 700 and couple it to the via 112 (2) to form a conductive connection to the package substrate 106 (block 926 in FIG9E).

[0064] Note that the terms "top" and "bottom" are relative terms when oriented in the Z-axis or vertical direction. However, it should also be noted that any of the IC packages disclosed herein may also be oriented by rotating 180 degrees from the orientation shown, wherein the metallization indicated as being above or on top of another metallization will be below that other metallization. Therefore, the terms "top" and "bottom" are relative terms and do not imply a strict limitation on the orientation of one metallization relative to another metallization.

[0065] IC packages that utilize FS-BEOL metallization structures to stack BS-BEOL metallization structures to provide 3D die stacking IC die modules (including, but not limited to, IC packages in Figures 1, 2, 7 and 8 and manufactured according to the processes in Figures 5A-6F and 9A-10M) can be provided in or integrated into any processor-based device. Examples not limited to these include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, automotive components, avionics systems, drones, and multi-rotor aircraft.

[0066] Accordingly, FIG11 illustrates an example of a processor-based system 1100 including circuitry that can be provided in an IC package 1102 (including, but not limited to, IC packages in FIG1, 2, 7 and 8 and manufactured according to the processes in FIG5A-6F and FIG9A-10M) employing an IC die module using an FS-BEOL metallization structure to a BS-BEOL metallization structure stack to provide 3D die stacking. In this example, the processor-based system 1100 may be formed as an IC 1104 in the IC package 1102 and as a system-on-a-chip (SoC) 1106. The processor-based system 1100 includes a CPU 1108, which includes one or more processors 1110, which may also be referred to as CPU cores or processor cores. The CPU 1108 may have cache memory 1112 coupled to the CPU 1108 for fast access to temporarily stored data. CPU 1108 is coupled to system bus 1114 and can be coupled to master and slave devices included in processor-based system 1100. As is well known, CPU 1108 communicates with these other devices by exchanging address, control, and data information on system bus 1114. For example, CPU 1108 can communicate bus transaction requests to memory controller 1116, which is an instance of a slave device. Although not shown in FIG11, multiple system buses 1114 may be provided, each forming a different texture.

[0067] Other master and slave devices may be connected to system bus 1114. As illustrated in FIG11, as an example, such devices may include a memory system 1120 comprising a memory controller 1116 and (various) memory arrays 1118, one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128. Each of the memory system 1120, the one or more input devices 1122, the one or more output devices 1124, the one or more network interface devices 1126, and the one or more display controllers 1128 may be provided in the same or different IC packages 1102. The (various) input devices 1122 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (various) output devices 1124 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (All) Network interface device 1126 may be any device configured to allow data exchange to and from network 1130. Network 1130 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. (All) Network interface device 1126 may be configured to support any type of communication protocol desired.

[0068] The CPU 1108 may also be configured to access the display controllers 1128 via the system bus 1114 to control information sent to one or more displays 1132. The display controllers 1128 send information to be displayed to the displays 1132 via one or more video processors 1134, which process the information to be displayed into a format suitable for the displays 1132. As an example, the display controllers 1128 and the video processors 1134 may be included as ICs in the same or different IC packages 1102, and in the same or different IC packages 1102 containing the CPU 1108. The displays 1132 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0069] FIG12 illustrates an exemplary wireless communication device 1200 including radio frequency (RF) components formed from one or more ICs 1202, wherein any of the ICs 1202 may be included in an IC package 1203 (including, but not limited to, IC packages of any type disclosed herein, manufactured according to the processes in FIG5A-6F and FIG9A-10M, and using the FS-BEOL metallization structure to provide a 3D die stack) employing an IC die module with an FS-BEOL metallization structure to a BS-BEOL metallization structure stack. As an example, the wireless communication device 1200 may include or be disposed in any of the above-described devices. As shown in FIG12, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include memory for storing data and code. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 supporting bidirectional communication. Generally, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0070] The transmitter 1208 or receiver 1210 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted in multiple stages between the RF and the baseband frequency; for example, for receiver 1210, it is converted from RF to intermediate frequency (IF) in one stage, and then from IF to the baseband frequency in another stage. In a direct conversion architecture, the signal is converted between the RF and the baseband frequency in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 1200 in Figure 12, the transmitter 1208 and receiver 1210 are implemented using a direct conversion architecture.

[0071] In the transmission path, the data processor 1206 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1208. In the exemplary wireless communication device 1200, the data processor 1206 includes digital-to-analog converters (DACs) 1212(1) and 1212(2) to convert the digital signals generated by the data processor 1206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0072] Within transmitter 1208, low-pass filters 1214(1) and 1214(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1216(1) and 1216(2) amplify the signals from low-pass filters 1214(1) and 1214(2), respectively, and provide I and Q baseband signals. Upconverter 1218 upconverts the I and Q baseband signals via mixers 1220(1) and 1220(2) using the I and Q TX LO signals from the transmit (TX) local oscillator (LO) signal generator 1222 to provide upconverted signal 1224. Filter 1226 filters upconverted signal 1224 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1228 amplifies the up-converted signal 1224 from filter 1226 to obtain the desired output power level and provide a transmitted RF signal. This transmitted RF signal is routed through duplexer or switch 1230 and transmitted via antenna 1232.

[0073] In the receiving path, antenna 1232 receives signals transmitted from the base station and provides a received RF signal, which is routed through duplexer or switch 1230 and provided to low noise amplifier (LNA) 1234. Duplexer or switch 1230 is designed to operate with specific receive (RX) and -TX duplexer frequencies separated, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Down-conversion mixers 1238(1) and 1238(2) mix the output of filter 1236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q fundamental frequency signals are amplified by AMPs 1242(1) and 1242(2) and further filtered by low-pass filters 1244(1) and 1244(2) to obtain I and Q analog input signals, which are provided to data processor 1206. In this example, data processor 1206 includes analog-to-digital converters (ADCs) 1246(1) and 1246(2) to convert the analog input signals into digital signals to be further processed by data processor 1206.

[0074] In the wireless communication device 1200 of FIG12, the TX LO signal generator 1222 generates I and Q TX LO signals for up-conversion, while the RX LO signal generator 1240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1248 receives timing information from the data processor 1206 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1222. Similarly, the RX PLL circuit 1250 receives timing information from the data processor 1206 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1240.

[0075] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described herein in conjunction with the various forms disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As examples, the master and slave devices described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative elements, blocks, modules, circuits, and steps have been generally described above in their functional form. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as deviating from the scope of this work.

[0076] The various illustrative logic blocks, modules, and circuits described herein can be implemented or executed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, individual gate or transistor logic, individual hardware elements, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternatives, it may be any known processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors coordinated with a DSP core, or any other such configuration).

[0077] The various forms disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. Exemplary storage media are coupled to a processor so that the processor can read and write information from / to the storage media. In alternatives, the storage media can be integrated into the processor. The processor and storage media can reside in an ASIC. The ASIC can reside in a remote station. In alternatives, the processor and storage media can reside as separate components in a remote station, base station, or server.

[0078] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than those illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowchart. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the foregoing description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0079] The prior description of this invention is provided so that anyone skilled in the art can make or use it. Various modifications to this invention will be apparent to those skilled in the art, and the universal principles defined herein can be applied to other variations. Therefore, this invention is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0080] Each implementation example is described in the following numbered embodiments: 1. An integrated circuit (IC) package, comprising: a first IC die, including: a first front-side (FS)-back-side (BEOL) (FS-BEOL) metallization structure; a first back-side (BS)-BEOL (BS-BEOL) metallization structure; and a first semiconductor layer disposed between the first FS-BEOL metallization structure and the first BS-BEOL metallization structure; and a second IC die, including: a second FS-BEOL metallization structure adjacent to the first BS-BEOL metallization structure; a second BS-BEOL metallization structure; and a second semiconductor layer disposed between the second FS-BEOL metallization structure and the second BS-BEOL metallization structure. 2. The IC package of embodiment 1, further comprising an IC package; the first FS-BEOL metallization structure of the first IC die being adjacent to a package substrate. 3. The IC package of either embodiment 1 or 2, wherein the second IC die is disposed above the first IC die in a vertical direction. 4. An IC package of any of embodiments 1 to 3, wherein: the first BS-BEOL metallization structure of the first IC die includes a first metal interconnect layer, the first metal interconnect layer including one or more first die interconnects electrically coupled to the first semiconductor layer; the second FS-BEOL metallization structure of the second IC die includes a second metal interconnect layer, the second metal interconnect layer including one or more second die interconnects electrically coupled to the second semiconductor layer; and at least one of the one or more first die interconnects is coupled to at least one of the one or more second die interconnects. 5. An IC package of embodiment 4, wherein the first FS-BEOL metallization structure of the first IC die includes a third metal interconnect layer, the third metal interconnect layer including one or more third die interconnects electrically coupled to the first semiconductor layer. 6. An IC package of any of embodiments 4 to 5, further comprising: a package substrate including one or more substrate interconnects; the first FS-BEOL metallization structure of the first IC die adjacent to the package substrate; at least one of the one or more substrate interconnects electrically coupled to at least one of the one or more first die interconnects; and further comprising one or more conductive bumps electrically coupled to the one or more substrate interconnects. 7. An IC package of any of embodiments 1 to 6, wherein the first FS-BEOL metallization structure of the first IC die includes a third metal interconnect layer, the third metal interconnect layer including one or more third die interconnects electrically coupled to the first semiconductor layer.8. An IC package of form 4, wherein: the first BS-BEOL metallization structure of the first IC die further includes one or more first vertical interconnects (vias) electrically coupled to the one or more first die interconnects and the first semiconductor interconnect; and the second FS-BEOL metallization structure of the second IC die further includes one or more second vias electrically coupled to the one or more second die interconnects and the second semiconductor layer. 9. An IC package of any of forms 1 to 8, further including an intermediate metallization structure disposed between the first BS-BEOL metallization structure of the first IC die and the second FS-BEOL metallization structure of the second IC die. 10. An IC package as described in Example 9, wherein: the first BS-BEOL metallization structure of the first IC die includes a first metal interconnect layer, the first metal interconnect layer including one or more first die interconnects electrically coupled to the first semiconductor layer; the second FS-BEOL metallization structure of the second IC die includes a second metal interconnect layer, the second metal interconnect layer including one or more second die interconnects electrically coupled to the second semiconductor layer; the intermediate metallization structure includes at least one intermediate metal interconnect layer, the at least one intermediate metal interconnect layer including one or more intermediate interconnects; at least one of the one or more first die interconnects is coupled to at least one of the one or more intermediate interconnects; and at least one of the one or more second die interconnects is coupled to at least one of the one or more intermediate interconnects to electrically couple the at least one of the one or more second die interconnects to the at least one of the one or more second die interconnects. 11. An IC package of form 10, wherein the first FS-BEOL metallization structure of the first IC die includes a third metal interconnect layer, the third metal interconnect layer including one or more third die interconnects electrically coupled to the first semiconductor layer. 12. An IC package of any of forms 9 to 11, further comprising: a third IC die, including: a third FS-BEOL metallization structure adjacent to the first BS-BEOL metallization structure; a third BS-BEOL metallization structure; and a third semiconductor layer disposed between the third FS-BEOL metallization structure and the third BS-BEOL metallization structure; the third IC die being configured to be adjacent to the second IC die in the lateral direction and separated from the second IC die by a gap distance to form a void region between the second IC die and the third IC die; and the intermediate metallization structure including at least one intermediate metallization layer, the at least one intermediate metallization layer including one or more intermediate interconnects. 13. The IC package of form 12 further includes a through-hole disposed in the gap region and electrically coupled to at least one of the one or more intermediate interconnects in the intermediate metallization structure.14. The IC package of embodiment 13, further comprising a fourth IC die, the fourth IC die including a fourth semiconductor layer, the fourth IC die being disposed adjacent to the second IC die; the via electrically coupled to the fourth semiconductor layer. 15. The IC package of any of embodiments 12 to 13, wherein: the first BS-BEOL metallization structure of the first IC die includes a first metal interconnect layer, the first metal interconnect layer including one or more first die interconnects electrically coupled to the first semiconductor layer; and at least one of the one or more first die interconnects is coupled to at least one of the one or more intermediate interconnects. 16. The IC package of any of embodiments 10 to 11, wherein the intermediate metallization structure includes one or more redistribution layers (RDLs). 17. An IC package as described in any of 1 to 16, wherein the IC package is integrated into a device selected from the group consisting of: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, automotive components, avionics systems, unmanned aerial vehicles, and multi-rotor aircraft. 18. A method of manufacturing an integrated circuit (IC) package, comprising the steps of: forming a first IC die, comprising: forming a first back-side (BS)-back-end process (BEOL) (BS-BEOL) metallization structure; forming a first semiconductor layer adjacent to the first BS-BEOL metallization structure; and forming a first front-side (FS)-BEOL (FS-BEOL) metallization structure adjacent to the first semiconductor layer, wherein the first semiconductor layer is disposed between the first BS-BEOL metallization structure and the first FS-BEOL metallization structure; and forming a second IC die, comprising: forming a second BS-BEOL metallization structure; forming a second semiconductor layer adjacent to the second BS-BEOL metallization structure; and forming a second FS-BEOL metallization structure adjacent to the second semiconductor layer, wherein the second semiconductor layer is disposed between the second BS-BEOL metallization structure and the second FS-BEOL metallization structure. 19. The method of embodiment 18, further comprising the step of: bonding the second IC die to the first IC die.20. The method of embodiment 19, further comprising the steps of: forming an intermediate metallization structure adjacent to the second FS-BEOL metallization structure of the second IC die; and coupling at least one intermediate interconnect of one or more intermediate interconnects in the intermediate metal interconnect layer of the intermediate metallization structure to at least one first die interconnect of one or more first die interconnects in the first FS-BEOL metallization structure of the first IC die. 21. The method of embodiment 20, further comprising the steps of: coupling at least one via to the at least one intermediate interconnect of the one or more intermediate interconnects; and removing molding compound from the first IC die to expose the top surface of the at least one via. 22. The method of any one of embodiments 20 to 21, further comprising the steps of: forming a package substrate adjacent to the first FS-BEOL metallization structure of the first IC die; and electrically coupling at least one first substrate interconnect of one or more first substrate interconnects in the first metal interconnect layer of the first FS-BEOL metallization structure of the first IC die coupled to the first semiconductor layer to the package substrate. 23. The method of any of embodiments 18 to 22, wherein forming the first CI die comprises: forming the first BS-BEOL metallization structure on a substrate such that a first surface of the first BS-BEOL metallization structure is disposed adjacent to a first surface of the substrate; and further comprises the steps of: forming a carrier wafer on a second surface of the first BS-BEOL metallization structure opposite to the first surface of the first BS-BEOL metallization structure; forming the first semiconductor layer on the second surface of the substrate opposite to the first surface of the substrate; forming the first FS-BEOL metallization structure adjacent to the first semiconductor layer; and removing the carrier wafer from the first BS-BEOL metallization structure. 24. The method of embodiment 23, further comprising the step of: thinning before forming the first semiconductor layer on the second surface of the substrate opposite to the first surface of the substrate. 25. The method of any of embodiments 23 to 24, further comprising the step of: forming one or more conductive bumps adjacent to the first FS-BEOL metallization structure, the one or more conductive bumps being coupled to one or more first substrate interconnects in the first metal interconnect layer of the first BS-FEOL metallization structure. 26. The method of any of embodiments 21 to 22, further comprising the step of: coupling a third IC die to the at least one via. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a side view of an exemplary integrated circuit (IC) package employing a front-side (FS)-back-side process (BEOL) (FS-BEOL) metallization structure to a back-side (BS)-BEOL (BS-BEOL) metallization structure stacked for three-dimensional (3D) die stacking to facilitate die-to-die interconnection of a semiconductor die ("IC die") module.

[0010] Figure 2 is a side view of the IC package in Figure 1, with additional details shown;

[0011] Figure 3 is a side view of another exemplary IC package that uses FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking for IC die module;

[0012] Figure 4 is a flowchart illustrating an exemplary process for manufacturing an IC package (including but not limited to the IC packages in Figures 1 and 2) that uses FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking of IC die modules.

[0013] Figures 5A-5C are flowcharts illustrating another exemplary process for manufacturing IC dies that facilitates the stacking of FS-BEOL metallization structures to BS-BEOL metallization structures in IC packages to provide 3D die stacking.

[0014] Figures 6A-6F illustrate exemplary manufacturing stages for the processes in Figures 5A-5C;

[0015] Figure 7 is a side view of another exemplary IC package that uses FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking, wherein the IC die module also includes an intermediate metallization layer disposed between the FS-BEOL and BS-BEOL metallization structures to facilitate die-to-die interconnection.

[0016] Figure 8 is a side view of another exemplary IC package employing an IC die module that utilizes FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking, wherein the IC die module also includes an intermediate metallization layer disposed between the FS-BEOL and BS-BEOL metallization structures to facilitate die-to-die interconnection and a blank space interconnection between adjacent IC dies;

[0017] Figures 9A-9E are flowcharts illustrating another exemplary process for manufacturing an IC package (including but not limited to the IC package in Figures 7 and 8) that uses FS-BEOL metallization structure to BS-BEOL metallization structure to provide 3D die stacking, wherein the IC die module also includes an intermediate metallization layer disposed between the FS-BEOL and BS-BEOL metallization structures to facilitate die-to-die interconnection;

[0018] Figures 10A-10M illustrate exemplary manufacturing stages during IC packaging of an IC die module that utilizes FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking, according to the process in Figures 9A-9E.

[0019] FIG11 is a block diagram of an exemplary processor-based system that can be provided in one or more IC packages (including, but not limited to, IC packages in FIG1, FIG2, FIG7 and FIG8 and according to the manufacturing processes in FIG5A-FIG and FIG9A-FIG10M) employing FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking; and

[0020] FIG12 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components provided in one or more IC packages (including, but not limited to, IC packages in FIG1, FIG2, FIG7 and FIG8 and manufactured according to the manufacturing processes in FIG5A-FIG and FIG9A-FIG 10M) that employ FS-BEOL metallization structure to BS-BEOL metallization structure stacking to provide 3D die stacking. [Biomaterial Storage]

[0082] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An integrated circuit (IC) package, comprising: A first IC die includes: a first front-side (FS)-back-side (BEOL) metallization structure configured to provide an electrical path for a signal to a first semiconductor layer; a first back-side (BS)-BEOL metallization structure configured to provide an electrical path for a signal to the first semiconductor layer; and a first semiconductor layer disposed between the first FS-BEOL metallization structure and the first BS-BEOL metallization structure; and a second IC die includes: a second FS-BEOL metallization structure configured to provide an electrical path for a signal to a second semiconductor layer, the second FS-BEOL metallization structure being adjacent to the first BS-BEOL metallization structure; A second BS-BEOL metallization structure configured to provide an electrical path for a signal to the second semiconductor layer; and a second semiconductor layer disposed between the second FS-BEOL metallization structure and the second BS-BEOL metallization structure, wherein the first BS-BEOL metallization structure is thinner than the second FS-BEOL metallization structure; and an intermediate metallization structure disposed between the first BS-BEOL metallization structure of the first IC die and the second FS-BEOL metallization structure of the second IC die.

2. The IC package of claim 1 further includes an IC package; the first FS-BEOL metallization structure of the first IC die is adjacent to a package substrate.

3. The IC package of claim 1, wherein the second IC die is positioned above the first IC die in a vertical direction.

4. As in request item 1, the IC package includes: The first BS-BEOL metallization structure of the first IC die includes a first metal interconnect layer, the first metal interconnect layer including one or more first die interconnects electrically coupled to the first semiconductor layer; the second FS-BEOL metallization structure of the second IC die includes a second metal interconnect layer, the second metal interconnect layer including one or more second die interconnects electrically coupled to the second semiconductor layer; and at least one of the one or more first die interconnects is coupled to at least one of the one or more second die interconnects.

5. The IC package of claim 4, wherein the first FS-BEOL metallization structure of the first IC die includes a third metal interconnect layer, the third metal interconnect layer including one or more third die interconnects electrically coupled to the first semiconductor layer.

6. The IC package as described in claim 5 further includes: A packaged substrate comprising one or more interconnected substrates; The first FS-BEOL metallization structure of the first IC die is adjacent to the packaging substrate; At least one of the one or more substrate interconnects is electrically coupled to at least one of the one or more first die interconnects; and further includes one or more conductive bumps electrically coupled to the one or more substrate interconnects.

7. The IC package of claim 1, wherein the first FS-BEOL metallization structure of the first IC die includes a third metal interconnect layer, the third metal interconnect layer including one or more third die interconnects electrically coupled to the first semiconductor layer.

8. As in request item 4, the IC package includes: The first BS-BEOL metallization structure of the first IC die further includes one or more first vertical interconnects (vias) electrically coupled to one or more first die interconnects and the first semiconductor layer; and the second FS-BEOL metallization structure of the second IC die further includes one or more second vias electrically coupled to one or more second die interconnects and the second semiconductor layer.

9. As in request item 1, the IC package includes: The first BS-BEOL metallization structure of the first IC die includes a first metal interconnect layer, the first metal interconnect layer including one or more first die interconnects electrically coupled to the first semiconductor layer; the second FS-BEOL metallization structure of the second IC die includes a second metal interconnect layer, the second metal interconnect layer including one or more second die interconnects electrically coupled to the second semiconductor layer; the intermediate metallization structure includes at least one intermediate metal interconnect layer, the at least one intermediate metal interconnect layer including one or more intermediate interconnects; at least one of the one or more first die interconnects is coupled to at least one of the one or more intermediate interconnects; and at least one of the one or more second die interconnects is coupled to at least one of the one or more intermediate interconnects to electrically couple the at least one of the one or more second die interconnects to the at least one of the one or more second die interconnects.

10. The IC package of claim 9, wherein the first FS-BEOL metallization structure of the first IC die includes a third metal interconnect layer, the third metal interconnect layer including one or more third die interconnects electrically coupled to the first semiconductor layer.

11. The IC package as described in claim 1, further includes: A third IC die includes: a third FS-BEOL metallization structure adjacent to the first BS-BEOL metallization structure; a third BS-BEOL metallization structure; and a third semiconductor layer disposed between the third FS-BEOL metallization structure and the third BS-BEOL metallization structure; the third IC die is configured to be adjacent to the second IC die in a lateral direction and separated from the second IC die by a gap distance to form a void region between the second IC die and the third IC die; and the intermediate metallization structure includes at least one intermediate metallization layer, the at least one intermediate metallization layer including one or more intermediate interconnects.

12. The IC package of claim 11 further includes a through-hole disposed in the void region and electrically coupled to at least one of the one or more intermediate interconnects in the intermediate metallization structure.

13. The IC package of claim 12 further includes a fourth IC die, the fourth IC die including a fourth semiconductor layer, the fourth IC die being configured adjacent to the second IC die; the via is electrically coupled to the fourth semiconductor layer.

14. As in request item 11, the IC package includes: The first BS-BEOL metallization structure of the first IC die includes a first metal interconnect layer, the first metal interconnect layer including one or more first die interconnects electrically coupled to the first semiconductor layer; and at least one of the one or more first die interconnects coupled to at least one of the one or more intermediate interconnects.

15. The IC package of claim 1, wherein the intermediate metallization structure includes one or more redistribution layers (RDLs).

16. The IC package of claim 1, wherein the IC package is integrated into a device selected from the group consisting of: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smartphone, a SIP phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, an in-vehicle component, an avionics system, a drone, and a multi-rotor aircraft.

17. A method of manufacturing an integrated circuit (IC) package, comprising the steps of: forming a first IC die, comprising the steps of: forming a first back-side (BS)-back-end process (BEOL) (BS-BEOL) metallization structure, the first BS-BEOL metallization structure being configured to provide an electrical path for a signal to a first semiconductor layer; forming a first semiconductor layer adjacent to the first BS-BEOL metallization structure; and forming a first front-side (FS)-BEOL (FS-BEOL) metallization structure adjacent to the first semiconductor layer, the first FS-BEOL metallization structure being configured to provide an electrical path for a signal to the first semiconductor layer, wherein the first semiconductor layer is disposed between the first BS-BEOL metallization structure and the first FS-BEOL metallization structure; and forming a second IC die, comprising the steps of: forming a second BS-BEOL metallization structure, the second BS-BEOL metallization structure being configured to provide an electrical path for a signal to a second semiconductor layer; The second semiconductor layer is formed adjacent to the second BS-BEOL metallization structure; and a second FS-BEOL metallization structure is formed adjacent to the second semiconductor layer, the second FS-BEOL metallization structure being configured to provide an electrical path for a signal to the second semiconductor layer, wherein the second semiconductor layer is disposed between the second BS-BEOL metallization structure and the second FS-BEOL metallization structure, wherein the first BS-BEOL metallization structure is thinner than the second FS-BEOL metallization structure; an intermediate metallization structure is formed adjacent to the second FS-BEOL metallization structure of the second IC die; and at least one intermediate interconnect of one or more intermediate interconnects in an intermediate metal interconnect layer of the intermediate metallization structure is coupled to at least one first die interconnect of one or more first die interconnects in the first FS-BEOL metallization structure of the first IC die.

18. The method of claim 17 further includes the step of bonding the second IC die to the first IC die.

19. The method of claim 17 further includes the steps of: coupling at least one via to at least one intermediate interconnect in one or more intermediate interconnects; and removing a molding compound on the first IC die to expose a top surface of the at least one via.

20. The method of claim 17 further includes the steps of: forming a package substrate from the first FS-BEOL metallization structure adjacent to the first IC die; and electrically coupling at least one of one or more first substrate interconnects in a first metal interconnect layer of the first FS-BEOL metallization structure of the first IC die coupled to the first semiconductor layer to the package substrate.

21. The method of claim 17, wherein the step of forming the first IC die comprises the following steps: forming the first BS-BEOL metallization structure on a substrate such that a first surface of the first BS-BEOL metallization structure is disposed adjacent to a first surface of the substrate; and further comprises the following steps: forming a carrier wafer on a second surface of the first BS-BEOL metallization structure opposite to the first surface of the first BS-BEOL metallization structure; forming the first semiconductor layer on a second surface of the substrate opposite to the first surface of the substrate; forming the first FS-BEOL metallization structure adjacent to the first semiconductor layer; and removing the carrier wafer from the first BS-BEOL metallization structure.

22. The method of claim 21 further includes the step of: thinning before forming the first semiconductor layer on the second surface of the substrate opposite to the first surface of the substrate.

23. The method of claim 21 further includes the step of: forming one or more conductive bumps adjacent to the first FS-BEOL metallization structure, the one or more conductive bumps being coupled to one or more first substrate interconnects in a first metal interconnect layer of the first BS-BEOL metallization structure.

24. The method of claim 19 further includes the step of coupling a third IC die to the at least one via.

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