Image sensor and electronic device including the same

Abstract

An electronic device includes: an image sensor for generating image data; and an image processor for processing the image data. The image sensor includes a pixel array comprising pixels repeatedly arranged along column and row directions. Each pixel in a first column of the pixel array includes a sub-pixel, each sub-pixel being connected to one of a first transmission metal line, a second transmission metal line, and a third transmission metal line. In response to signals applied to the first to third transmission metal lines respectively, at least a portion of the charge integrated at the sub-pixel of the pixel belonging to the first column diffuses to a corresponding floating diffusion region.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an image sensor and an electronic device including the image sensor, and more particularly, to an image sensor supporting an autofocus function and an electronic device including the image sensor. [Cross-reference to related applications]

[0002] This application claims priority based on 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0014244, filed with the Korean Intellectual Property Office on February 1, 2021, the entire disclosure of which is incorporated herein by reference.

Background Art

[0003] An image sensor may be installed in various types of electronic devices. For example, an electronic device including an image sensor may be implemented using one of various types of electronic devices (such as a smartphone, a tablet personal computer (PC), a laptop PC, and a wearable device).

[0004] An image sensor obtains image information about an external object by converting light reflected from the external object into an electrical signal. An electronic device including an image sensor may display an image on a display panel using the obtained image information.

[0005] An autofocus (AF) function may be used to improve the image quality of an external object. To perform the autofocus function more quickly, an image sensor supporting phase detection autofocus (PDAF) may be used.

Summary of the Invention

[0006] Embodiments of the present disclosure provide an image sensor capable of supporting phase detection autofocus and improving its autofocus performance, and an electronic device including the image sensor.

[0007] According to an embodiment, an electronic device may include: an image sensor that generates image data; and an image processor that processes the image data. The image sensor may include a pixel array including pixels repetitively arranged along a column direction and a row direction. Each of the pixels belonging to a first column among the columns of the pixel array may include sub-pixels, each of the sub-pixels being connected to one of a first transmission metal line, a second transmission metal line, and a third transmission metal line. In response to signals respectively applied to the first transmission metal line to the third transmission metal line, at least a part of the charge integrated at the sub-pixels of the pixels belonging to the first column among the pixels may diffuse to corresponding floating diffusion regions.

[0008] According to an embodiment, an image sensor may include a pixel array. The pixel array may include a first pixel group including pixels that generate image data. A first column of the first pixel group may include: a first pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of a first transfer gate signal and a second transfer gate signal; and a second pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the second transfer gate signal and a third transfer gate signal.

[0009] According to an embodiment, an image sensor may include a pixel array. The pixel array may include a first pixel group including a first unit pixel group, a second unit pixel group, a third unit pixel group, and a fourth unit pixel group. The first pixel group may include: a first pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of a first transfer gate signal and a second transfer gate signal; and a second pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the first transfer gate signal and the second transfer gate signal and a third transfer gate signal.

Embodiments

[0011] Embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the same reference numerals always refer to the same elements, and thus additional description may be omitted to avoid redundancy.

[0012] It should be understood that the terms “first”, “second”, “third”, etc. are used herein to distinguish each element, and the elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0013] Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein are intended to include the plural forms as well.

[0014] It should be understood that when an element is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element, the element can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element, or there may be intervening elements. Other phrases used to describe the relationship between elements should be interpreted in a similar manner.

[0015] In this document, when two or more elements or values are described as being substantially the same or approximately equal to each other, it should be understood that the elements or values are equal to each other, the elements or values are equal to each other within measurement error, or if not equal in measurement, then close enough in value to be equal in function, as would be understood by one of ordinary skill in the art. For example, the term "about" as used herein includes the stated value and means within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations as would be understood by one of ordinary skill in the art. In addition, it should be understood that although a parameter may be described herein as having "about" a certain value, according to an embodiment, the parameter can be an exact certain value or an approximate certain value within the measurement error as would be understood by one of ordinary skill in the art.

[0016] As is conventional in the art of this disclosure, embodiments are described in terms of functional blocks, units, and / or modules and are illustrated in the drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.), which can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. In the case where a block, unit, and / or module is implemented by a microprocessor or the like, software (such as microcode) can be used to program the block, unit, and / or module to perform the various functions discussed herein, and the block, unit, and / or module can be driven by firmware and / or software as needed. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (such as one or more programmed microprocessors and associated circuitry) for performing other functions.

[0017] FIG. 1 is a block diagram of an electronic device 1000 according to an embodiment of the present disclosure. Referring to FIG. 1, the electronic device 1000 may include an image sensor 100 and an image processor 10. The image sensor 100 may operate in response to a control command provided from the image processor 10. The image sensor 100 may convert light from an object into an electrical signal and transmit the electrical signal as image data to the image processor 10.

[0018] The image sensor 100 may include a pixel array 110, a column driver 120, a correlated double sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, and a timing controller 160. The pixel array 110 may include a plurality of pixels PIX arranged in a column direction and a row direction. Each of the pixels PIX may include a photoelectric element (e.g., a photodiode) that receives light and generates electric charges based on the received light.

[0019] In some embodiments, at least a portion of the plurality of pixels PIX may include two or more photodiodes. The image sensor 100 may provide autofocus based on a phase difference of electrical signals generated from the two or more photodiodes included in at least the portion of the plurality of pixels PIX. That is, the image sensor 100 may provide phase detection autofocus.

[0020] Each of the plurality of pixels PIX may further include a circuit for generating an electrical signal from the electric charges generated by the photodiode. The circuit included in each of the plurality of pixels PIX and the operation of the circuit will be further described in detail below.

[0021] The pixel array 110 may be controlled by a sensor driving signal transmitted from the column driver 120. The sensor driving signal may include, for example, a selection signal SEL, a reset signal RG, and a transfer gate signal TG. A plurality of electrical signals sensed by corresponding pixels in response to the sensor driving signal may be transferred as an output signal OUT to the CDS 130. The arrangement of the pixels PIX in the pixel array 110 will be further described in detail below.

[0022] The column driver 120 can select one of multiple columns of the pixel array 110 under the control of the timing controller 160. The column driver 120 generates a selection signal SEL for the purpose of selecting one or more of the multiple columns. The column driver 120 can sequentially enable (or activate) the reset signal RG and the transfer gate signal TG for the pixels corresponding to the selected column. In this way, the output signal OUT associated with the illuminance generated by the pixels of the selected column can be sequentially provided to the CDS 130.

[0023] The CDS 130 can be connected to the pixels included in the column selected by the selection signal SEL via the row lines. The CDS 130 can detect the pixel voltages respectively generated by the pixels by performing correlated double sampling. For example, the CDS 130 can sample and hold the pixel voltages generated by each pixel. The CDS 130 can perform correlated double sampling on the level of specific noise and the level of the pixel voltages output from each pixel, and can output a voltage (i.e., the level difference) corresponding to the result of the correlated double sampling. In this way, the CDS 130 can detect the reset voltage when the reset signal RG is enabled and the pixel voltages corresponding to the charges integrated in the photodiodes of each pixel PIX.

[0024] The ADC 140 can convert the reset voltage and the pixel voltage detected by the CDS 130 into digital signals. For example, the ADC 140 can convert the pixel voltage detected by the CDS 130 into a pixel signal. The pixel signal (i.e., the digital signal) converted by the ADC 140 can be provided to the output buffer 150.

[0025] The output buffer 150 can store the digital signals converted by the ADC 140. The output buffer 150 can transmit the digital signals stored in the output buffer 150 as image data to the image processor 10 under the control of the timing controller 160.

[0026] The timing controller 160 can control the pixel array 110, the column driver 120, the CDS 130, the ADC 140, and the output buffer 150. The timing controller 160 can generate control signals (such as (for example) clock signals and timing control signals) for the operation of the pixel array 110, the column driver 120, the CDS 130, the ADC 140, and the output buffer 150. In response to a request received from the image processor 10, the timing controller 160 can generate control signals and can provide the control signals to any other components of the image sensor 100.

[0027] The image processor 10 can process the image data received from the output buffer 150. For example, the image processor 10 can calculate the phase difference between two pixels from the image data. The image processor 10 can perform autofocus processing based on the calculated phase difference. The image processor 10 can correct the image data of the pixel for which the pixel voltage is not detected based on the image data associated with the pixel adjacent to the pixel for which the pixel voltage is not detected. The image data processed by the image processor 10 can be stored in a storage device or can be output to a display device.

[0028] FIG. 2 shows a part of the pixel array 110 shown in FIG. 1 according to an embodiment of the present disclosure.

[0029] Referring to FIGS. 1 and 2, the pixel array 110 shown in FIG. 1 may include a first pixel group PIXGR1 repeatedly arranged in the column direction (e.g., the X-axis direction) and the row direction (e.g., the Y-axis direction).

[0030] The first pixel group PIXGR1 may include pixels PIX1, PIX2, PIX3, and PIX4. Color filters may be provided over the pixels PIX1, PIX2, PIX3, and PIX4. In the embodiment shown in FIG. 2, a first unit color filter array including four color filters may be provided over the first pixel group PIXGR1. The first unit color filter array may include a blue (B) color filter, a green (G) color filter, a red (R) color filter, and a green (G) color filter arranged in clockwise order from the upper left end of the first unit color filter array. The first unit color filter array may be repeatedly arranged along the X-axis and the Y-axis.

[0031] The pixels PIX1, PIX2, PIX3, and PIX4 may correspond to the color filters of the first unit color filter array. In the embodiment shown in FIG. 2, the pixel PIX1 may correspond to the blue (B) color filter, the pixels PIX2 and PIX3 may correspond to the green (G) color filter, and the pixel PIX4 may correspond to the red (R) color filter. In this way, the pixel PIX1 can output information corresponding to the amount of blue (B) light in the form of current or voltage, the pixels PIX2 and PIX3 can output information corresponding to the amount of green (G) light in the form of current or voltage, and the pixel PIX4 can output information corresponding to the amount of red (R) light in the form of current or voltage.

[0032] FIG. 3 shows the first pixel group PIXGR1 shown in FIG. 2 according to an embodiment of the present disclosure in more detail.

[0033] Referring to FIGS. 1 to 3, the pixels PIX1, PIX2, PIX3, and PIX4 of the first pixel group PIXGR1 may respectively include sub-pixel pairs. For example, pixel PIX1 may include sub-pixels PIX1L and PIX1R, pixel PIX2 may include sub-pixels PIX2L and PIX2R, pixel PIX3 may include sub-pixels PIX3L and PIX3R, and pixel PIX4 may include sub-pixels PIX4L and PIX4R. Each of the sub-pixels PIX1L, PIX1R, PIX2L, PIX2R, PIX3L, PIX3R, PIX4L, and PIX4R may include a photoelectric conversion element.

[0034] Two sub-pixels included in a pixel may receive different transfer gate signals. In the embodiment shown in FIG. 3, the sub-pixel PIX1L included in pixel PIX1 may receive the transfer gate signal TGL, and the sub-pixel PIX1R included in pixel PIX1 may receive the transfer gate signal TGR. When the transfer gate signal TGL is enabled, the pixel voltage corresponding to the sub-pixel PIX1L can be detected by the CDS 130. Then, when the transfer gate signal TGR is enabled, the pixel voltage corresponding to the sub-pixel PIX1R can be detected by the CDS 130.

[0035] When the transfer gate signals TGL and TGR are sequentially enabled, the pixel voltages corresponding to the sub-pixels receiving the transfer gate signal TGL and the pixel voltages corresponding to the sub-pixels receiving the transfer gate signal TGR can be sequentially detected. The detected pixel voltages can be sequentially converted into pixel signals to be transmitted to the image processor 10.

[0036] The image processor 10 can calculate the phase difference based on the phase information of the pixel signal corresponding to the transfer gate signal TGL and the phase information of the pixel signal corresponding to the transfer gate signal TGR. The image processor 10 can calculate the distance between the image sensor 100 and the object based on the calculation result. The image processor 10 can generate a control signal for adjusting the distance between the image sensor 100 and the object based on the calculated distance. For example, the image processor 10 can generate a control signal for moving the lens position of the image sensor 100. In this way, the distance between the image sensor 100 and the object can be adjusted.

[0037] FIG. 4 is a circuit diagram of the pixel PIX1 shown in FIG. 2 according to an embodiment of the present disclosure.

[0038] Referring to FIGS. 1 to 4, pixel PIX1 may include photodiodes PD1L and PD1R, transfer transistors T1L and T1R, a floating diffusion region FD1 (or floating diffusion node), a reset transistor R1, a source follower transistor SF1, and a select transistor SE1.

[0039] Each of photodiodes PD1L and PD1R may generate electrons (or charges) corresponding to light incident on image sensor 100 and integrate the electrons (or charges). In some embodiments, each of photodiodes PD1L and PD1R may also be implemented using one of photoelectric conversion elements (such as, for example, a phototransistor, a photogate, and a pinned photodiode, or a combination thereof). In the embodiment shown in FIG. 4, photodiode PD1L may correspond to sub-pixel PIX1L, and photodiode PD1R may correspond to sub-pixel PIX1R.

[0040] A first end of transfer transistor T1L and a first end of T1R may be respectively connected to photodiodes PD1L and PD1R, and a second end of transfer transistor T1L and a second end of T1R may be commonly connected to floating diffusion region FD1. In response to transfer gate signals TGL and TGR, transfer transistors T1L and T1R may transfer electrons integrated by photodiodes PD1L and PD1R to floating diffusion region FD1. Transfer gate signals TGL and TGR may be included in transfer gate signal TG shown in FIG. 1.

[0041] Floating diffusion region FD1 may integrate and store electrons provided from transfer transistors T1L and T1R. The capacitance of floating diffusion region FD1 may be referred to as "CFD1". The voltage level of floating diffusion region FD1 may be determined based on capacitance CFD1 and the amount of electrons provided from transfer transistors T1L and T1R.

[0042] In the embodiment shown in FIG. 4, floating diffusion region FD1 is shared by two photodiodes PD1L and PD1R. However, the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, three or more photodiodes may share one floating diffusion region FD1.

[0043] The reset transistor R1 can reset the floating diffusion region FD1. For example, the reset transistor R1 can electrically connect the floating diffusion region FD1 to the power supply voltage VDD based on the reset signal RG1. The reset transistor R1 can remove or discharge the electrons stored at the floating diffusion region FD1 by driving the floating diffusion region FD1 with the power supply voltage VDD in response to the reset signal RG1. The reset signal RG1 can be included in the reset signal RG shown in FIG. 1.

[0044] The source follower transistor SF1 can be connected between the power supply voltage VDD and the selection transistor SE1. The gate terminal of the source follower transistor SF1 can be connected to the floating diffusion region FD1. The source follower transistor SF1 can output an output signal to the selection transistor SE1 based on the voltage level of the floating diffusion region FD1. The source follower transistor SF1 can be a source follower buffer amplifier.

[0045] The selection transistor SE1 can be connected between the source follower transistor SF1 and the output line. The selection transistor SE1 can output the output signal OUT1 to the row line CL1 based on the selection signal SEL1. The selection signal SEL1 can be included in the selection signal SEL shown in FIG. 1. The output signal OUT1 can be included in the output signal OUT shown in FIG. 1. An example is shown in which the above transistors are n-type metal-oxide semiconductor (NMOS) transistors. However, the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the transistors can be implemented as p-type metal-oxide semiconductor (PMOS) transistors or a combination of PMOS transistors and NMOS transistors.

[0046] In the embodiment shown in FIG. 4, to provide an autofocus function, a pixel voltage is detected from a corresponding photodiode connected to a floating diffusion region. For example, to obtain the pixel voltage corresponding to sub-pixel PIX1L and the pixel voltage corresponding to sub-pixel PIX1R separately, first, the reset signal RG1 can be enabled and the floating diffusion region FD1 can be reset. Next, the transfer gate signal TGL can be enabled, and the charge stored in the photodiode PD1L can be integrated at the floating diffusion region FD1. Then, the select signal SEL1 can be enabled, and the pixel voltage corresponding to the photodiode PD1L can be output as the output signal OUT1 via the row line CL1. Next, the reset signal RG1 can be enabled again so that the floating diffusion region FD1 is reset. As in the description given with reference to the photodiode PD1L, the pixel voltage corresponding to the photodiode PD1R can be output as the output signal OUT1 via the row line CL1. Therefore, the pixel voltage can be detected from multiple pixels PIX multiple times, which results in an increase in the time and power consumption for autofocus processing and reading.

[0047] In some embodiments of the present disclosure, different from the above solution, when the floating diffusion region is reset once, the pixel voltages corresponding to multiple photodiodes connected to the floating diffusion region can be detected separately. For example, after the floating diffusion region FD1 is reset, first, the first pixel voltage corresponding to the charge integrated at the photodiode PD1L can be detected, and then the second pixel voltage corresponding to the sum of the charge integrated at the photodiode PD1L and the charge integrated at the photodiode PD1R can be detected. The image processor 10 can use the first pixel voltage and the second pixel voltage to calculate the phase difference. In this case, first, the third pixel voltage corresponding to the charge integrated at the photodiode PD1R can be calculated from the first pixel voltage and the second pixel voltage, and then the phase difference can be calculated based on the first pixel voltage and the third pixel voltage.

[0048] FIG. 5 is a flowchart showing an operation method of the image sensor 100 shown in FIG. 1 according to an embodiment of the present disclosure. FIGS. 6A to 6C show in more detail the pixel groups PIXGR1A, PIXGR2A, PIXGR1B, PIXGR2B, PIXGR1C, and PIXGR2C repeatedly arranged in the pixel array 110 according to some embodiments of the present disclosure. The embodiments shown in FIGS. 6A to 6C will be described in detail below with reference to FIGS. 1 to 5.

[0049] Similar to the first pixel group PIXGR1 shown in FIG. 2, the first unit color filter array including green (G), red (R), green (G), and blue (B) color filters arranged in clockwise order from its upper left end can be located on each of pixel groups PIXGR1A, PIXGR2A, PIXGR1B, PIXGR2B, PIXGR1C, and PIXGR2C. The pixel array 110 shown in FIG. 1 can include pixel groups PIXGR1A and PIXGR2A / PIXGR1B and PIXGR2B / PIXGR1C and PIXGR2C repeatedly arranged in the column direction and the row direction.

[0050] Different from the embodiments shown in FIGS. 3 and 4, in the embodiments shown in FIGS. 6A to 6C, at least a part of the columns of the pixel array 110 can be connected to three transmission metal lines associated with transfer gate signals TGL, TGR, TGAL, and TGAR. For example, the sub-pixels PIX1LA, PIX1RA, PIX2LA, PIX2RA, PIX5LA, PIX5RA, PIX6LA, and PIX6RA arranged in the first column can be connected to one of the three transmission metal lines corresponding to transfer gate signals TGL, TGR, and TGAL respectively. Each transmission metal line can be named based on the transfer gate signal emitted on the line. For example, the transmission metal line emitting transfer gate signal TGL on it can be called the TGL transmission metal line, the transmission metal line emitting transfer gate signal TGR on it can be called the TGR transmission metal line, and the transmission metal line emitting transfer gate signal TGAL on it can be called the TGAL transmission metal line. According to an embodiment, multiple different transmission metal lines can be used to emit the same transfer gate signal. Therefore, some embodiments can include a first TGL transmission metal line, a second TGL transmission metal line, a first TGR transmission metal line, a second TGR transmission metal line, etc. The sub-pixels PIX3LA, PIX3RA, PIX4LA, PIX4RA, PIX7LA, PIX7RA, PIX8LA, and PIX8RA arranged in the second column can be connected to one of the three transmission metal lines corresponding to transfer gate signals TGL, TGR, and TGAR respectively.

[0051] In the embodiment shown in FIG. 6A, pixel group PIXGR1A and pixel group PIXGR2A may be disposed adjacent to each other. Pixel group PIXGR2A may be disposed on one side of pixel group PIXGR1A in a first direction (e.g., the x-axis direction). Each of pixel group PIXGR1A and pixel group PIXGR2A may include four pixels, and each of the four pixels may include two sub-pixels. For example, pixel group PIXGR1A may include pixels PIX1A, PIX2A, PIX3A, and PIX4A, and pixel group PIXGR2A may include pixels PIX5A, PIX6A, PIX7A, and PIX8A. Each of pixels PIX1A, PIX2A, PIX3A, PIX4A, PIX5A, PIX6A, PIX7A, and PIX8A may include two sub-pixels (e.g., pixel PIX1A may include sub-pixels PIX1LA and PIX1RA).

[0052] The two sub-pixels included in one pixel may share a floating diffusion region. The floating diffusion region may be connected to a row line via a selection block. The selection block may include components such as reset transistor R1, source follower transistor SF1, or selection transistor SE1 shown in FIG. 4, for example. For example, sub-pixel PIX1LA and sub-pixel PIX1RA included in pixel PIX1A may share a floating diffusion region FD1. The floating diffusion region FD1 may be connected to row line CL1 via selection block SL1. In response to the operations of selection block SL1 and selection block SL3, a pixel voltage corresponding to the charge at the photodiode of one of the pixels (e.g., pixel PIX1A and pixel PIX3A) stored in shared row line CL1 may be output as output signal OUT1.

[0053] Floating diffusion regions FD2, FD3, FD4, FD5, FD6, FD7, and FD8 may be implemented and operate similarly to floating diffusion region FD1. Selection blocks SL2, SL3, SL4, SL5, SL6, SL7, and SL8 may be implemented and operate similarly to selection block SL1. Row lines CL2, CL3, and CL4 may be implemented and operate similarly to row line CL1. Output signals OUT2, OUT3, and OUT4 may be output similarly to output signal OUT1.

[0054] Among the sub-pixels PIX1LA, PIX1RA, PIX2LA, PIX2RA, PIX5LA, PIX5RA, PIX6LA, and PIX6RA disposed in the first column, the sub-pixels PIX1LA, PIX5LA, and PIX6LA may include transfer transistors T1LA, T5LA, and T6LA that respectively receive a transfer gate signal TGL. The sub-pixels PIX1RA, PIX2RA, PIX5RA, and PIX6RA may include transfer transistors T1RA, T2RA, T5RA, and T6RA that respectively receive a transfer gate signal TGR. The sub-pixel PIX2LA may include a transfer transistor T2LA that receives a transfer gate signal TGAL different from the transfer gate signals TGR and TGL.

[0055] Among the sub-pixels PIX3LA, PIX3RA, PIX4LA, PIX4RA, PIX7LA, PIX7RA, PIX8LA, and PIX8RA disposed in the second column, the sub-pixels PIX3LA, PIX4LA, PIX7LA, and PIX8LA may include transfer transistors T3LA, T4LA, T7LA, and T8LA that respectively receive a transfer gate signal TGL. The sub-pixels PIX3RA, PIX4RA, and PIX8RA may include transfer transistors T3RA, T4RA, and T8RA that respectively receive a transfer gate signal TGR. The sub-pixel PIX7RA may include a transfer transistor T7RA that receives a transfer gate signal TGAR different from the transfer gate signals TGR and TGL.

[0056] In some embodiments of the present disclosure, when performing a read operation, the transfer gate signals (e.g., the transfer gate signal TGL and the transfer gate signal TGAL / TGAR) may be enabled first, and then the remaining transfer gate signals (e.g., the transfer gate signal TGR and the transfer gate signal TGAR) may be enabled.

[0057] In some embodiments of the present disclosure, when performing a read operation, the detection operation may be performed only once for each column by enabling only some of the transfer gate signals (e.g., the transfer gate signal TGR and the transfer gate signal TGL) simultaneously. The image processor 10 may perform autofocus processing by calculating a phase difference based on a part of the detected pixel voltages and may perform image processing based on the remaining pixel voltages.

[0058] Referring to FIG. 5, the image sensor 100 can perform operation S100, operation S200, operations S310 to S330, and operations S410 to S430. In operation S100, the image sensor 100 can receive a capture request (or command) from the image processor 10. For example, the image processor 10 can request the image processor 10 to generate image data in response to a request from the user.

[0059] In operation S200, the image sensor 100 can determine whether the autofocus mode is the first mode or the second mode. The image sensor 100 can operate in one of the first mode or the second mode based on a request from the image processor 10. The image sensor 100 can perform one of a first read operation or a second read operation on each frame generated by the pixel array 110 based on the determined mode.

[0060] When the autofocus mode is determined to be the first mode, the image sensor 100 can perform operations S310 to S330. In operation S310, the image sensor 100 can select a column. For example, in response to a control signal generated by the timing controller 160, the column driver 120 of the image sensor 100 can select a column to be read out from among the columns of the pixel array 110.

[0061] In operation S320, the image sensor 100 can perform a first read operation on the selected column. In the first read operation, the image sensor 100 can first enable the reset signal RG to reset the floating diffusion regions included in the selected column. Subsequently, the reset signal RG can be disabled, and only the transfer gate signal TGL and the transfer gate signal TGAL or TGAR can be enabled first. In this way, the pixel voltage can be detected from the correlated sub-pixels. Next, the transfer gate signal TGL and the transfer gate signal TGAL or TGAR can be disabled, and the transfer gate signal TGR and TGAR can be enabled (or in some embodiments, only the transfer gate signal TGR can be enabled). In this way, the correlated pixel voltage can be detected.

[0062] For example, in the embodiment shown in FIG. 6A, when the image sensor 100 selects the first column and performs a first read operation on the first column, all the floating diffusion regions FD1, FD2, FD5, and FD6 in the first column can be reset, and the transfer gate signals TGL and TGAL can be enabled first. In this way, the pixel voltages corresponding to the sub-pixels PIX1LA, PIX2LA, PIX5LA, and PIX6LA can be detected from the first column. Subsequently, when the transfer gate signal TGR is enabled, the pixel voltages corresponding to the sub-pixels PIX1RA, PIX2RA, PIX5RA, and PIX6RA can be detected from the first column. The image processor 10 can perform autofocus processing based on the pixel voltages detected from the first column.

[0063] In operation S330, the image sensor 100 can determine whether the column selected in operation S310 is the last column of the pixel array 110. For example, the image sensor 100 can determine whether the first read operation is performed on all columns of the pixel array 110. When the column selected in operation S310 is not the last column of the pixel array 110, the image sensor 100 can perform operation S310 again so that a new (or different) column is selected next and the first read operation is performed on the newly selected column.

[0064] For example, in the embodiment shown in FIG. 6A, after the first read operation is performed on the first column, in operation S330, the image sensor 100 can perform operation S310 again to select the second column. When the image sensor 100 performs the first read operation on the second column, the floating diffusion regions FD3, FD4, FD7, and FD8 in the second column can be reset and the transfer gate signal TGL can be enabled first. In this way, the pixel voltages corresponding to the sub-pixels PIX3LA, PIX4LA, PIX7LA, and PIX8LA can be detected from the second column. Subsequently, when the transfer gate signals TGR and TGAR are enabled, the pixel voltages corresponding to the sub-pixels PIX3RA, PIX4RA, PIX7RA, and PIX8RA can be detected from the second column. The image processor 10 can perform autofocus processing based on the pixel voltages detected from the second column.

[0065] When the autofocus mode is determined to be the second mode, the image sensor 100 can perform operations S410 to S430. In operation S410, the image sensor 100 can select a column. For example, the image sensor 100 can perform operation S410 in the same manner as in operation S310.

[0066] In operation S420, the image sensor 100 may perform a second read operation on the selected column. In the second read operation, the image sensor 100 may first enable the reset signal RG to reset the floating diffusion regions of the selected column. Subsequently, the image sensor 100 may enable the transfer gate signals TGL and TGR to detect the relevant pixel voltages.

[0067] For example, in the embodiment shown in FIG. 6A, when the image sensor 100 performs a second read operation on the first column, all the floating diffusion regions FD1, FD2, FD5, and FD6 of the first column may be reset, and only the transfer gate signal TGL and the transfer gate signal TGR may be enabled simultaneously. In this case, as in pixel PIX1A, in a pixel in which two sub-pixels included therein receive the transfer gate signals TGL and TGR respectively, the total pixel voltage corresponding to the sum of the charges integrated at the photodiodes respectively included in the two sub-pixels may be detected once. For example, the total pixel voltages of sub-pixels PIX1A and PIX2A, the total pixel voltages of sub-pixels PIX5RA and PIX5LA, the total pixel voltages of sub-pixels PIX6LA and PIX6RA, and the pixel voltage corresponding to sub-pixel PIX2RA may be detected from the first column.

[0068] In operation S430, the image sensor 100 may determine whether the column selected in operation S410 is the last column of the pixel array 110. For example, the image sensor 100 may determine whether the second read operation is performed on all columns of the pixel array 110. When the column selected in operation S410 is not the last column of the pixel array 110, the image sensor 100 may perform operation S410 again such that a new (or different) column is selected next and the second read operation is performed on the newly selected column.

[0069] For example, in the embodiment shown in FIG. 6A, after performing the second read operation on the first column, in operation S430, the image sensor 100 may perform operation S410 again to select the second column. When the image sensor 100 performs a second read operation on the second column, the floating diffusion regions FD3, FD4, FD7, and FD8 of the second column may be reset and only the transfer gate signal TGL and the transfer gate signal TGR may be enabled simultaneously. In this way, the total pixel voltages of sub-pixels PIX3RA and PIX3LA, the total pixel voltages of sub-pixels PIX4RA and PIX4LA, the total pixel voltages of sub-pixels PIX8LA and PIX8RA, and the pixel voltage corresponding to sub-pixel PIX7LA may be detected from the second column.

[0070] The image processor 10 may perform autofocus processing based on at least a part of the pixel voltages detected in response to the transfer gate signals TGL and TGR, and may perform image processing based on the remaining pixel voltages. For example, the image processor 10 may perform autofocus processing based on the pixel voltages corresponding to the sub-pixels PIX2RA and PIX7LA among the detected pixel voltages, and may perform image processing based on the total pixel voltages of the remaining sub-pixels PIX1LA, PIX1RA, PIX3LA, PIX3RA, PIX4LA, PIX4RA, PIX5LA, PIX5RA, PIX6LA, PIX6RA, PIX8LA, and PIX8RA. For example, the image processor 10 may correct the image data corresponding to the sub-pixels PIX2LA, PIX2RA, PIX7LA, and PIX7RA.

[0071] In some embodiments, the image sensor 100 may further include a binning circuit. The image sensor 100 may output image data corresponding to one pixel based on the voltages respectively obtained from the sub-pixels included in one pixel. The image sensor 100 may generate a binned signal corresponding to the pixel group PIXGR1A by binning the pixel voltages corresponding to the pixels PIX1A, PIX2A, PIX3A, and PIX4A. The generated binned signal may be converted into a digital signal to be provided to the image processor 10.

[0072] The differences between the embodiment shown in FIG. 6A and the embodiment shown in FIG. 6B will be described with reference to FIGS. 1, 4, 6A, and 6B. The pixel group PIXGR1B and the pixel group PIXGR2B may be disposed adjacent to each other. Similar to the pixel groups PIXGR1A and PIXGR2A, each of the pixel groups PIXGR1B and PIXGR2B may include four pixels, and each of the four pixels may include two sub-pixels. In the embodiment shown in FIG. 6, the pixel group PIXGR1B includes the pixels PIX1B, PIX2B, PIX3B, and PIX4B, and the pixel group PIXGR2B includes the pixels PIX5B, PIX6B, PIX7B, and PIX8B.

[0073] Among the sub-pixels PIX1LB, PIX1RB, PIX2LB, PIX2RB, PIX5LB, PIX5RB, PIX6LB, and PIX6RB disposed in the first column, the sub-pixels PIX1LB, PIX5RB, and PIX6RB may include transfer transistors T1LB, T5RB, and T6RB respectively receiving a transfer gate signal TGL. The sub-pixels PIX1RB, PIX2RB, PIX5LB, and PIX6LB may include transfer transistors T1RB, T2RB, T5LB, and T6LB respectively receiving a transfer gate signal TGR. The sub-pixel PIX2LB may include a transfer transistor T2LB receiving a transfer gate signal TGAL different from the transfer gate signals TGR and TGL.

[0074] Among the sub-pixels PIX3LB, PIX3RB, PIX4LB, PIX4RB, PIX7LB, PIX7RB, PIX8LB, and PIX8RB disposed in the second column, the sub-pixels PIX3LB, PIX4LB, and PIX8RB may include transfer transistors T3LB, T4LB, and T8RB respectively receiving a transfer gate signal TGL. The sub-pixels PIX3RB, PIX4RB, PIX7LB, and PIX8LB may include transfer transistors T3RB, T4RB, T7LB, and T8LB respectively receiving a transfer gate signal TGR. The sub-pixel PIX7RB may include a transfer transistor T7RB receiving a transfer gate signal TGAR different from the transfer gate signals TGR and TGL.

[0075] In some embodiments, during auto-focus processing, the time taken to process a pixel signal corresponding to one of the two sub-pixels in a pixel may be longer than the time taken to process a pixel signal corresponding to the other of the two sub-pixels. For example, the time taken to process the pixel signal corresponding to the right sub-pixel PIX1RB among the sub-pixels PIX1LB and PIX1RB in the pixel PIX1B may be longer than the time taken to process the left pixel signal PIX1LB.

[0076] In some embodiments of the present disclosure, the pixel voltage of at least one photodiode may be detected in response to a transfer gate signal different from the transfer gate signals TGL and TGR (e.g., the transfer gate signal TGAL / TGAR). In such an embodiment, after performing a first detection operation corresponding to the enabling of a first transfer gate signal among the transfer gate signals, some pixel signals that take a longer time for signal processing may be provided to the image processor 10. While performing a second detection operation corresponding to the enabling of the remaining transfer gate signals, the image processor 10 may process the pixel signals input as a result of the first detection operation. Therefore, the total time used to perform the auto-focus processing can be shortened.

[0077] For example, when a first read operation is performed on the first column, all floating diffusion regions FD1, FD2, FD5, and FD6 of the first column can be reset, and the transfer gate signals TGL and TGAL can be enabled first. In this way, pixel voltages corresponding to the sub-pixels PIX1LB, PIX2LB, PIX5RB, and PIX6RB can be detected from the first column. Before enabling the remaining transfer gate signal TGR, the image processor 10 can start processing the image data corresponding to the detected pixel voltages. In this case, the time taken to process the pixel signals corresponding to the sub-pixels PIX5RB, PIX6RB, PIX7RB, and PIX8RB used for autofocus may be longer than the time taken to process the pixel signals corresponding to the sub-pixels PIX5LB, PIX6LB, PIX7LB, and PIX8LB. Subsequently, the transfer gate signal TGR can be enabled. In this way, pixel voltages corresponding to the sub-pixels PIX1RB, PIX2RB, PIX5LB, and PIX6LB can be detected from the first column.

[0078] Different from the embodiment shown in FIG. 6A, in the embodiment shown in FIG. 6B, when a first read operation is performed on the second column, the transfer gate signal TGAR and the transfer gate signal TGL can be enabled simultaneously. In this embodiment, the transfer gate signal TGAR can be referred to as the "transfer gate signal TGAL", which is different from the example shown in FIG. 6B. Therefore, when a first read operation is performed on the second column, the floating diffusion regions FD3, FD4, FD7, and FD8 of the second column can be reset, and the transfer gate signals TGL and TGAR can be enabled first. In this way, pixel voltages corresponding to the sub-pixels PIX3LB, PIX4LB, PIX7RB, and PIX8RB can be detected from the second column. Therefore, the pixel voltages that take a longer time in the processing of the image processor 10 (for example, the voltages of the sub-pixels PIX7RB and PIX8RB) can be processed by the image processor 10 first. Subsequently, the transfer gate signal TGR can be enabled. In this way, pixel voltages corresponding to the sub-pixels PIX3RB, PIX4RB, PIX7LB, and PIX8LB can be detected from the second column. The image processor 10 can perform autofocus processing by processing the image data based on the detected pixel voltages.

[0079] When performing the second read operation on the first column, all the floating diffusion regions FD1, FD2, FD5, and FD6 of the first column can be reset, and only the transfer gate signals TGL and TGR can be enabled. Subsequently, when performing the second read operation on the second column, all the floating diffusion regions FD3, FD4, FD7, and FD8 of the second column can be reset, and only the transfer gate signal TGL and the transfer gate signal TGR can be enabled simultaneously. For example, the image processor 10 can perform autofocus processing based on the pixel voltages corresponding to the sub-pixels PIX2RB and PIX7LB among the total voltages corresponding to the sub-pixels PIX1LB, PIX1RB, PIX3LB, PIX3RB, PIX4LB, PIX4RB, PIX5LB, PIX5RB, PIX6LB, PIX6RB, PIX8LB, and PIX8RB, and can perform image processing based on the pixel voltages corresponding to the remaining sub-pixels PIX1LB, PIX1RB, PIX3LB, PIX3RB, PIX4LB, PIX4RB, PIX5LB, PIX5RB, PIX6LB, PIX6RB, PIX8LB, and PIX8RB.

[0080] The differences between the embodiment shown in FIG. 6A and the embodiment shown in FIG. 6C will be described with reference to FIGS. 1, 4, 6A, and 6C. In the embodiment shown in FIG. 6C, the pixel group PIXGR1C and the pixel group PIXGR2C can be arranged adjacent to each other. Similar to the pixel groups PIXGR1A and PIXGR2A, each of the pixel groups PIXGR1C and PIXGR2C can include four pixels, and each of the four pixels can include two sub-pixels. Different from the embodiment shown in FIG. 6A, in the embodiment according to FIG. 6C, some sub-pixels do not include a photoelectric conversion element but can be connected to a local ground voltage.

[0081] For example, the configuration and operation of the pixels PIX1C, PIX3C, and PIX4C included in the pixel group PIXGR1C can be implemented similarly to the pixels PIX1A, PIX3A, and PIX4A included in the pixel group PIXGR1A. However, different from the sub-pixel PIX2LA of the pixel PIX2A, in the embodiment, the sub-pixel PIX2LC of the pixel PIX2C does not include a photodiode. Instead, the transfer transistor T2LC of the sub-pixel PIX2LC can be connected to the ground voltage. In some embodiments, different from the embodiment shown in FIG. 6C, the sub-pixel PIX2LC does not include the transfer transistor T2LC but can be provided with a ground node. In the embodiment, the transfer transistor of the sub-pixel can be directly connected to the ground node.

[0082] Pixel PIX1C includes sub-pixels PIX1LC and PIX1RC, and sub-pixels PIX1LC and PIX1RC include transfer transistors T1LC and T1RC. Pixel PIX2C includes sub-pixels PIX2LC and PIX2RC, and sub-pixels PIX2LC and PIX2RC include transfer transistors T2LC and T2RC. Pixel PIX3C includes sub-pixels PIX3LC and PIX3RC, and sub-pixels PIX3LC and PIX3RC include transfer transistors T3LC and T3RC. Pixel PIX4C includes sub-pixels PIX4LC and PIX4RC, and sub-pixels PIX4LC and PIX4RC include transfer transistors T4LC and T4RC.

[0083] The configuration and operation of pixels PIX5C, PIX6C, and PIX8C included in pixel group PIXGR2C can be implemented similarly to those of pixels PIX5A, PIX6A, and PIX8A included in pixel group PIXGR2A. However, different from sub-pixel PIX7RA of pixel PIX7A, in an embodiment, sub-pixel PIX7RC of pixel PIX7C does not include a photodiode. The configuration and operation of sub-pixel PIX7RC can be implemented similarly to those of sub-pixel PIX2LC.

[0084] Pixel PIX5C includes sub-pixels PIX5LC and PIX5RC, and sub-pixels PIX5LC and PIX5RC include transfer transistors T5LC and T5RC. Pixel PIX6C includes sub-pixels PIX6LC and PIX6RC, and sub-pixels PIX6LC and PIX6RC include transfer transistors T6LC and T6RC. Pixel PIX7C includes sub-pixels PIX7LC and PIX7RC, and sub-pixels PIX7LC and PIX7RC include transfer transistors T7LC and T7RC. Pixel PIX8C includes sub-pixels PIX8LC and PIX8RC, and sub-pixels PIX8LC and PIX8RC include transfer transistors T8LC and T8RC.

[0085] FIG. 7A and FIG. 7B more particularly illustrate pixel groups PIXGRTA and PIXGRTB repeatedly disposed in pixel array 110 according to some embodiments of the present disclosure.

[0086] Different from the embodiments shown in FIGS. 6A to 6C, each of the pixel group PIXGRTA shown in FIG. 7A and the pixel group PIXGRTB shown in FIG. 7B may include four unit pixel groups, and each of the four unit pixel groups may include four pixels. Each pixel may include two sub-pixels. For example, the pixel group PIXGRTA may include four unit pixel groups PIXUT1A, PIXUT2A, PIXUT3A, and PIXUT4A. The unit pixel group PIXUT1A may include four pixels PIXT11A, PIXT12A, PIXT13A, and PIXT14A. The pixel PIXT11A may include two sub-pixels PT11LA and PT11RA.

[0087] In some embodiments, similar to the first pixel group PIXGR1 shown in FIG. 2, a first unit color filter array including a green (G) color filter, a red (R) color filter, a green (G) color filter, and a blue (B) color filter arranged in clockwise order from its upper left end may be located on each of the unit pixel groups PIXUT1A, PIXUT2A, PIXUT3A, and PIXUT4A.

[0088] In the embodiment shown in FIG. 7A, each of the pixels PIXT11A, PIXT12A, PIXT13A, PIXT14A, PIXT21A, PIXT22A, PIXT24A, PIXT31A, PIXT33A, PIXT34A, PIXT41A, PIXT42A, PIXT43A, and PIXT44A may include a sub-pixel receiving a transfer gate signal TGL and a sub-pixel receiving a transfer gate signal TGR. However, the pixel PIXT23A may include a sub-pixel receiving a transfer gate signal TGAL, and the pixel PIXT32A may include a sub-pixel receiving a transfer gate signal TGAR. More specifically, the sub-pixel PT23LA of the pixel PIXT23A may include a transfer transistor receiving a transfer gate signal TGL, and the sub-pixel PT23RA of the pixel PIXT23A may include a transfer transistor receiving a transfer gate signal TGAL. The sub-pixel PT32LA of the pixel PIXT32A may include a transfer transistor receiving a transfer gate signal TGAR, and the sub-pixel PT32RA of the pixel PIXT32A may include a transfer transistor receiving a transfer gate signal TGR.

[0089] In the embodiment shown in FIG. 7A, when performing the first read operation for each column of the pixel group PIXGRTA, first, all floating diffusion regions of each column can be reset, and the transfer gate signals TGL and TGAL can be enabled (or in some columns where there is no connection to the transmission metal line to which the transfer gate signal TGAL is applied, only the transfer gate signal TGL can be enabled). Subsequently, the transfer gate signals TGR and TGAR can be enabled (or in some columns where there is no connection to the transmission metal line to which the transfer gate signal TGAR is applied, only the transfer gate signal TGR can be enabled). The image processor 10 can process the image data based on the pixel voltages detected from the pixel group PIXGRTA.

[0090] When performing the second read operation for each column of the pixel group PIXGRTA, first, all floating diffusion regions of each column can be reset, and only the transfer gate signals TGL and TGR can be enabled. For example, the image processor 10 can perform autofocus processing based on the pixel voltages corresponding to the sub-pixels PT23LA and PT32RA among the pixel voltages detected from the pixel group PIXGRTA, and can perform image processing based on the sum pixel voltages of the remaining sub-pixels. For example, the image processor 10 can correct the image data corresponding to the sub-pixels PT23LA, PT23RA, PT32LA, and PT32RA.

[0091] In some embodiments, such as the embodiment shown in FIG. 6A, the image sensor 100 can further include a coincidence circuit. The image sensor 100 can output the image data corresponding to the one pixel (e.g., pixel PIXT11A) by performing coincidence on the voltages respectively obtained from the sub-pixels (e.g., sub-pixels PT11LA and PT11RA) included in one pixel (e.g., pixel PIXT11A). The image sensor 100 can output the image data corresponding to the one unit pixel group (e.g., unit pixel group PIXUT1A) by performing coincidence on the voltages (or the voltages respectively obtained from the sub-pixels of the four pixels) respectively obtained from the four pixels (e.g., pixels PIXT11A, PIXT12A, PIXT13A, and PIXT14A) included in one unit pixel group (e.g., unit pixel group PIXUT1A).

[0092] The differences between the embodiment shown in FIG. 7A and the embodiment shown in FIG. 7B will be described with reference to FIGS. 1, 7A, and 7B. In the embodiment shown in FIG. 7B, each of the pixels PIXT11B, PIXT12B, PIXT13B, PIXT14B, PIXT21B, PIXT22B, PIXT31B, PIXT32B, PIXT33B, PIXT34B, PIXT41B, PIXT42B, PIXT43B, and PIXT44B may include a sub-pixel that receives the transfer gate signal TGL and a sub-pixel that receives the transfer gate signal TGR. However, each of the pixels PIXT23B and PIXT24B may include a sub-pixel that receives the transfer gate signal TGAL. More specifically, the sub-pixel PT23LB of the pixel PIXT23B may include a transfer transistor that receives the transfer gate signal TGAL, and the sub-pixel PT23RB of the pixel PIXT23B may include a transfer transistor that receives the transfer gate signal TGR. The sub-pixel PT24LB of the pixel PIXT24B may include a transfer transistor that receives the transfer gate signal TGR, and the sub-pixel PT24RB of the pixel PIXT24B may include a transfer transistor that receives the transfer gate signal TGAL. The pixel PIXT11B may include sub-pixels PT11LB and PT11RB, the pixel PIXT13B may include sub-pixels PT13LB and PT13RB, and the pixel PIXT22B may include sub-pixels PT22LB and PT22RB.

[0093] In the embodiment shown in FIG. 7B, when a first readout operation is performed for each column of the pixel group PIXGRTB, first, all floating diffusion regions of each column may be reset, and the transfer gate signals TGL and TGAL may be enabled (or in some columns where there is no connection to the transmission metal line to which the transfer gate signal TGAL is applied, only the transfer gate signal TGL may be enabled). Subsequently, the transfer gate signal TGR may be enabled. In this way, the pixel signals that are signal-processed for a relatively long time may be first transmitted to the image processor 10. For example, in the unit pixel group PIXUT1B among the unit pixel groups PIXUT1B, PIXUT2B, PIXUT3B, and PIXUT4B, the pixel signals corresponding to the sub-pixels PT12RB and PT14RB that are signal-processed for a long time may be transmitted to the image processor 10 before the pixel signals corresponding to the sub-pixels PT12LB and PT14LB. Therefore, the total time required for autofocus processing may be reduced. The image processor 10 may process the image data based on the detected pixel voltages.

[0094] When performing the second read operation for each column of the pixel group PIXGRTB, first, all floating diffusion regions of each column can be reset, and only the transfer gate signals TGL and TGR can be enabled. The image processor 10 can perform autofocus processing based on the pixel voltages corresponding to the sub-pixels PT23RB and PT24LB among the pixel voltages detected from the pixel group PIXGRTB, and can perform image processing based on the sum pixel voltages of the remaining sub-pixels. For example, the image processor 10 can correct the image data corresponding to the sub-pixels PT23LB, PT23RB, PT24LB, and PT24RB. In the embodiment shown in FIG. 7B, since the sub-pixel PT23RB and the sub-pixel PT24LB are arranged in the same column, the time spent detecting the pixel voltages for autofocus processing can be shortened.

[0095] FIGS. 8A and 8B show in more detail the pixel groups PIXGRHA and PIXGRHB repeatedly arranged in the pixel array 110 according to some embodiments of the present disclosure.

[0096] Similar to the pixel group PIXGRTA shown in FIG. 7A and the pixel group PIXGRTB shown in FIG. 7B, each of the pixel group PIXGRHA shown in FIG. 8A and the pixel group PIXGRHB shown in FIG. 8B can include four unit pixel groups, and each of the four unit pixel groups can include four pixels. Each pixel can include two sub-pixels. Different from the embodiments shown in FIGS. 7A and 7B, in the embodiment shown in FIG. 8A, some pixels can include two sub-pixels separated by a boundary in the diagonal direction rather than the row direction (e.g., the Y-axis direction). For example, the pixel PIXH21A of the unit pixel group PIXUH2A can include a pair of sub-pixels separated by a boundary in the first diagonal direction. The pixel PIXH31A of the unit pixel group PIXUH3A can include a pair of sub-pixels separated by a boundary in the second diagonal direction.

[0097] In some embodiments, similar to the first pixel group PIXGR1 shown in FIG. 2, a first unit color filter array including a green (G) color filter, a red (R) color filter, a green (G) color filter, and a blue (B) color filter arranged in clockwise order from its upper left end can be located on each of the unit pixel groups PIXUH1A, PIXUH2A, PIXUH3A, and PIXUH4A.

[0098] In the embodiment shown in FIG. 8A, each of pixels PIXH12A, PIXH13A, PIXH21A, PIXH22A, PIXH23A, PIXH24A, PIXH31A, PIXH32A, PIXH33A, PIXH34A, PIXH41A, PIXH42A, PIXH43A, and PIXH44A may include a sub-pixel that receives transfer gate signal TGL and a sub-pixel that receives transfer gate signal TGR. However, pixel PIXH11A may include a sub-pixel that receives transfer gate signal TGAL, and pixel PIXH14A may include a sub-pixel that receives transfer gate signal TGAR. More specifically, sub-pixel PH11LA of pixel PIXH11A may include a transfer transistor that receives transfer gate signal TGAL, and sub-pixel PH11RA of pixel PIXH11A may include a transfer transistor that receives transfer gate signal TGR. Sub-pixel PH14LA of pixel PIXH14A may include a transfer transistor that receives transfer gate signal TGL, and sub-pixel PH14RA of pixel PIXH14A may include a transfer transistor that receives transfer gate signal TGAR.

[0099] In the embodiment shown in FIG. 8A, when a first readout operation is performed for each column of pixel group PIXGRHA, first, all floating diffusion regions of each column may be reset, and transfer gate signals TGL and TGAL may be enabled (or in some columns where there is no connection to the transmission metal line to which transfer gate signal TGAL is applied, only transfer gate signal TGL may be enabled). Subsequently, transfer gate signals TGR and TGAR may be enabled (or in some columns where there is no connection to the transmission metal line to which transfer gate signal TGAR is applied, only transfer gate signal TGR may be enabled), and image processor 10 may process image data based on the detected pixel voltages.

[0100] When a second readout operation is performed for each column of pixel group PIXGRHA, first, all floating diffusion regions of each column may be reset, and only transfer gate signals TGL and TGR may be enabled. Image processor 10 may perform autofocus processing based on the pixel voltages corresponding to sub-pixels PH11RA and PH14LA among the pixel voltages detected from pixel group PIXGRHA, and may perform image processing based on the sum pixel voltages of the remaining sub-pixels. For example, image processor 10 may correct the image data corresponding to sub-pixels PH11LA, PH11RA, PH14LA, and PH14RA.

[0101] In some embodiments, such as the embodiment shown in FIG. 7A, the image sensor 100 may further include a coincidence circuit. The image sensor 100 may generate a coincidence signal corresponding to the one pixel by performing coincidence on two pixel voltages obtained from sub-pixels included in one pixel. The image sensor 100 may generate a coincidence signal corresponding to the one unit pixel group by performing coincidence on eight pixel voltages obtained from sub-pixels included in one unit pixel group.

[0102] The differences between the embodiment shown in FIG. 8A and the embodiment shown in FIG. 8B will be described with reference to FIGS. 1, 8A, and 8B. In the embodiment shown in FIG. 8B, each of the pixels PIXH13B, PIXH14B, PIXH21B, PIXH22B, PIXH23B, PIXH24B, PIXH31B, PIXH32B, PIXH33B, PIXH34B, PIXH41B, PIXH42B, PIXH43B, and PIXH44B may include a sub-pixel that receives the transfer gate signal TGL and a sub-pixel that receives the transfer gate signal TGR. However, each of the pixels PIXH11B and PIXH12B may include a sub-pixel that receives the transfer gate signal TGAL. More specifically, the sub-pixel PH11LB of the pixel PIXH11B may include a transfer transistor that receives the transfer gate signal TGAL, and the sub-pixel PH11RB of the pixel PIXH11B may include a transfer transistor that receives the transfer gate signal TGR. The sub-pixel PH12LB of the pixel PIXH12B may include a transfer transistor that receives the transfer gate signal TGR, and the sub-pixel PH12RB of the pixel PIXH12B may include a transfer transistor that receives the transfer gate signal TGAL.

[0103] In the embodiment shown in FIG. 8B, when the first read operation is performed for each column of the pixel group PIXGRHB, first, all floating diffusion regions of each column can be reset, and the transfer gate signals TGL and TGAL can be enabled (or in some columns where there is no connection to the transmission metal line to which the transfer gate signal TGAL is applied, only the transfer gate signal TGL can be enabled). Subsequently, the transfer gate signals TGR and TGAR can be enabled (or in some columns where there is no connection to the transmission metal line to which the transfer gate signal TGAR is applied, only the transfer gate signal TGR can be enabled). In this way, first, the pixel signals that take a relatively long time to process their signals can be transmitted to the image processor 10. For example, in the unit pixel group PIXUH1B, the pixel signals corresponding to the sub-pixels PH12RB and PH14RB that take a long time in signal processing can be transmitted to the image processor 10 before the pixel signals corresponding to the sub-pixels PH12LB and PH14LB. Therefore, the total time required for autofocus processing can be reduced. The image processor 10 can process the image data based on the detected pixel voltages.

[0104] When the second read operation is performed for each column of the pixel group PIXGRHA, first, all floating diffusion regions of each column can be reset, and only the transfer gate signals TGL and TGR can be enabled. The image processor 10 can perform autofocus processing based on the pixel voltages corresponding to the sub-pixels PH11RB and PH12LB among the pixel voltages detected from the pixel group PIXGRHB, and can perform image processing based on the sum pixel voltages of the remaining sub-pixels. For example, the image processor 10 can correct the image data corresponding to the sub-pixels PH11LB, PH11RB, PH12LB, and PH12RB.

[0105] FIG. 8B also shows the unit pixel groups PIXUH2B, PIXUH3B, and PIXUH4B, and the sub-pixels PH13LB and PH13RB.

[0106] FIG. 9 is a block diagram of an electronic device including a multi-camera module according to an embodiment of the present disclosure.

[0107] Referring to FIG. 9, the electronic device 2000 may include a camera module group 2100, an application processor 2200, a power management integrated circuit (PMIC) 2300, and an external memory 2400.

[0108] The camera module group 2100 may include multiple camera modules 2100a, 2100b, and 2100c. Although an embodiment in which three camera modules 2100a, 2100b, and 2100c are provided is shown in FIG. 9, the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the camera module group 2100 may be modified to include only two camera modules. Additionally, in some embodiments, the camera module group 2100 may be modified to include "n" camera modules (n is a natural number of 4 or greater than 4).

[0109] FIG. 10 is a detailed block diagram of the camera module shown in FIG. 9 according to an embodiment of the present disclosure. The detailed configuration of the camera module 2100b will be described more comprehensively with reference to FIG. 10, and it should be understood that the following description can be equally applied to the remaining camera modules 2100a and 2100c.

[0110] Referring to FIG. 10, the camera module 2100b may include a prism 2105, an optical path folding element (OPFE) 2110, an actuator 2130, an image sensing device 2140, and a storage unit 2150.

[0111] The prism 2105 may include a reflective plane 2107 of a light-reflective material and may change the path of the light "L" incident from outside the camera module 2100b.

[0112] In some embodiments, the prism 2105 may change the path of the light "L" incident in the first direction "X" to a second direction "Y" perpendicular to the first direction "X". Additionally, the prism 2105 may change the path of the light "L" incident in the first direction "X" to a second direction "Y" perpendicular to the first direction "X" by rotating the reflective plane 2107 of the light-reflective material around the central axis 2106 in the direction "A" or rotating the central axis 2106 in the direction "B". In this case, the OPFE 2110 may move in a third direction "Z" perpendicular to the first direction "X" and the second direction "Y".

[0113] In some embodiments, as shown in the figure, the maximum rotation angle of the prism 2105 in the direction "A" may be equal to or less than about 15 degrees in the positive A direction and greater than about 15 degrees in the reverse A direction. However, the embodiments are not limited thereto.

[0114] In some embodiments, the prism 2105 may move within about 20 degrees, between about 10 degrees and about 20 degrees, or between about 15 degrees and about 20 degrees in the positive B direction or the negative B direction. Here, the prism 2105 may move at the same angle in the positive B direction or the negative B direction, or may move at a similar angle, for example, within about 1 degree.

[0115] In some embodiments, the prism 2105 may move the reflection plane 2107 of the light reflecting material in a third direction (e.g., the Z direction) parallel to the direction in which the central axis 2106 extends.

[0116] The OPFE 2110 may include, for example, an optical lens composed of "m" groups (m is a natural number). Here, the "m" lenses may move in the second direction "Y" to change the optical zoom ratio of the camera module 2100b. For example, when the default optical zoom ratio of the camera module 2100b is "Z", the optical zoom ratio of the camera module 2100b may be changed to 3Z, 5Z, or an optical zoom ratio greater than 5Z by moving the "m" optical lenses included in the OPFE 2110.

[0117] The actuator 2130 may move the OPFE 2110 or the optical lens (hereinafter referred to as the "optical lens") to a specific position. For example, the actuator 2130 may adjust the position of the optical lens such that the image sensor 2142 is placed at the focal length of the optical lens for accurate sensing.

[0118] The image sensing device 2140 may include an image sensor 2142, control logic 2144, and a memory 2146. The image sensor 2142 may sense an image of a sensing target using the light "L" provided via the optical lens. In some embodiments, the configuration and operation of the image sensor 2142 may be implemented similarly to the configuration and operation of the image sensor 100 shown in FIG. 1. For example, the image sensor 2142 may include a pixel group that is substantially the same as or similar to one of the pixel groups shown in FIGS. 6A to 6C, FIGS. 7A, 7B, 8A, and 8B. The control logic 2144 may control the overall operation of the camera module 2100b. For example, the control logic 2144 may control the operation of the camera module 2100b based on a control signal provided via the control signal line CSLb.

[0119] The memory 2146 can store information for the operation of the camera module 2100b, such as (for example) calibration data 2147. The calibration data 2147 can include information for the camera module 2100b to generate image data using the light "L" provided from outside the camera module 2100b. The calibration data 2147 can include, for example, information about the above-mentioned rotation degree, information about the focal length, information about the optical axis, etc. In the case where the camera module 2100b is implemented in the form of a multi-state camera in which the focal length varies according to the position of the optical lens, the calibration data 2147 can include the focal length value of each position (or state) of the optical lens and information about autofocus.

[0120] The storage unit 2150 can store the image data sensed by the image sensor 2142. The storage unit 2150 can be provided outside the image sensing device 2140 and can be implemented in the form of a storage unit 2150 stacked with the sensor chips constituting the image sensing device 2140. In some embodiments, the storage unit 2150 can be implemented using an electrically erasable programmable read only memory (EEPROM). However, the embodiments are not limited thereto.

[0121] Referring to FIGS. 9 and 10 together, in some embodiments, each of the plurality of camera modules 2100a, 2100b, and 2100c can include an actuator 2130. In this way, the same calibration data 2147 or different calibration data 2147 can be included in the plurality of camera modules 2100a, 2100b, and 2100c according to the operation of the actuator 2130 therein.

[0122] In some embodiments, one of the plurality of camera modules 2100a, 2100b, and 2100c (for example, 2100b) can be a camera module in the shape of a folded lens including the above-mentioned prism 2105 and OPFE 2110, and the remaining camera modules (for example, 2100a and 2100c) can be camera modules in a vertical shape that do not include the above-mentioned prism 2105 and OPFE 2110. However, the embodiments are not limited thereto.

[0123] In some embodiments, one of the plurality of camera modules 2100a, 2100b, and 2100c (e.g., 2100c) may be a depth camera in a vertical shape that extracts depth information using infrared (IR) rays. In such a case, the application processor 2200 may merge the image data provided from the depth camera and the image data provided from any other camera module (e.g., 2100a or 2100b) and may generate a three-dimensional (3D) depth image.

[0124] In some embodiments, at least two of the plurality of camera modules 2100a, 2100b, and 2100c (e.g., 2100a and 2100b) may have different fields of view. In such a case, the at least two of the plurality of camera modules 2100a, 2100b, and 2100c (e.g., 2100a and 2100b) may include different optical lenses. However, the embodiments are not limited thereto.

[0125] Additionally, in some embodiments, the fields of view of the plurality of camera modules 2100a, 2100b, and 2100c may be different. In such a case, the plurality of camera modules 2100a, 2100b, and 2100c may include different optical lenses. However, the embodiments are not limited thereto.

[0126] In some embodiments, the plurality of camera modules 2100a, 2100b, and 2100c may be physically separated from each other. That is, in some embodiments, instead of using the sensing area of one image sensor 2142, the plurality of camera modules 2100a, 2100b, and 2100c may each include an independent image sensor 2142 therein.

[0127] Referring back to FIG. 9, the application processor 2200 may include an image processing device 2210, a memory controller 2220, and an internal memory 2230. The application processor 2200 may be implemented to be separated from the plurality of camera modules 2100a, 2100b, and 2100c. For example, the application processor 2200 and the plurality of camera modules 2100a, 2100b, and 2100c may be implemented using separate semiconductor wafers.

[0128] The image processing device 2210 may include a plurality of sub-image processors 2212a, 2212b, and 2212c, an image generator 2214, and a camera module controller 2216.

[0129] The image processing device 2210 may include the plurality of sub-image processors 2212a, 2212b, and 2212c, and the number of the plurality of sub-image processors 2212a, 2212b, and 2212c corresponds to the number of the plurality of camera modules 2100a, 2100b, and 2100c.

[0130] The image data respectively generated from the camera modules 2100a, 2100b, and 2100c may be respectively provided to the corresponding sub-image processors 2212a, 2212b, and 2212c via separate image signal lines ISLa, ISLb, and ISLc. For example, the image data generated from the camera module 2100a may be provided to the sub-image processor 2212a via the image signal line ISLa, the image data generated from the camera module 2100b may be provided to the sub-image processor 2212b via the image signal line ISLb, and the image data generated from the camera module 2100c may be provided to the sub-image processor 2212c via the image signal line ISLc. This image data transmission may be implemented, for example, using a camera serial interface (CSI) based on the Mobile Industry Processor Interface (MIPI). However, the embodiments are not limited thereto.

[0131] In some embodiments, one sub-image processor may be configured to correspond to a plurality of camera modules. For example, the sub-image processors 2212a and 2212c may be integrally implemented, rather than being separated from each other as shown in FIG. 9. In such a case, one of the multiple pieces of image data respectively provided from the camera modules 2100a and 2100c may be selected by a selection element (e.g., a multiplexer), and the selected image data may be provided to the integrated sub-image processor.

[0132] The image data respectively provided to the sub-image processors 2212a, 2212b, and 2212c may be provided to the image generator 2214. Depending on the image generation information ("Generating Information" in FIG. 9) or the mode signal, the image generator 2214 may generate an output image using the image data respectively provided from the sub-image processors 2212a, 2212b, and 2212c.

[0133] For example, depending on the image generating information Generating Information or the pattern signal, the image generator 2214 can generate an output image by combining at least a portion of the image data generated from the camera modules 2100a, 2100b, and 2100c having different fields of view, respectively. Additionally, depending on the image generating information Generating Information or the pattern signal, the image generator 2214 can generate an output image by selecting one of the image data generated from the camera modules 2100a, 2100b, and 2100c having different fields of view, respectively.

[0134] In some embodiments, the image generating information Generating Information can include a zoom signal or a zoom factor. Additionally, in some embodiments, the pattern signal can be, for example, a signal based on a mode selected by the user.

[0135] In a case where the image generating information Generating Information is a zoom signal (or a zoom factor) and the camera modules 2100a, 2100b, and 2100c have different visual fields (or fields of view), the image generator 2214 can perform different operations according to the type of the zoom signal. For example, in a case where the zoom signal is a first signal, the image generator 2214 can combine the image data output from the camera module 2100a and the image data output from the camera module 2100c, and can use the combined image signal and the image data output from the camera module 2100b that is not used in the combining operation to generate an output image. In a case where the zoom signal is a second signal different from the first signal, without an image data combining operation, the image generator 2214 can select one of the image data output from the camera modules 2100a, 2100b, and 2100c, respectively, and can output the selected image data as an output image. However, the embodiments are not limited thereto.

[0136] In some embodiments, the image generator 2214 can generate combined image data with an increased dynamic range by receiving multiple image data with different exposure times from at least one of the plurality of sub-image processors 2212a, 2212b, and 2212c and performing high dynamic range (HDR) processing on the multiple image data.

[0137] The camera module controller 2216 can respectively provide control signals to the camera modules 2100a, 2100b, and 2100c. The control signals generated from the camera module controller 2216 can be respectively provided to the corresponding camera modules 2100a, 2100b, and 2100c via the separated control signal lines CSLa, CSLb, and CSLc.

[0138] Depending on the image generating information Generating Information including the zoom signal or the mode signal, one of the multiple camera modules 2100a, 2100b, and 2100c can be designated as the main camera (e.g., 2100b), and the remaining camera modules (e.g., 2100a and 2100c) can each be designated as the slave cameras. The above designation information can be included in the control signal, and the control signal including the designation information can be respectively provided to the corresponding camera modules 2100a, 2100b, and 2100c via the separated control signal lines CSLa, CSLb, and CSLc.

[0139] The camera modules operating as the main camera module and the slave camera module can be changed according to the zoom factor or the operation mode signal. For example, in a case where the field of view of the camera module 2100a is wider than the field of view of the camera module 2100b and the zoom factor indicates a low zoom ratio, the camera module 2100b can operate as the main camera module, and the camera module 2100a can operate as the slave camera module. On the contrary, in a case where the zoom factor indicates a high zoom ratio, the camera module 2100a can operate as the main camera module, and the camera module 2100b can operate as the slave camera module.

[0140] In some embodiments, the control signals provided from the camera module controller 2216 to each of the camera modules 2100a, 2100b, and 2100c can include a synchronization enable signal. For example, in a case where the camera module 2100b is used as the main camera and the camera modules 2100a and 2100c are used as the slave cameras, the camera module controller 2216 can transmit a synchronization enable signal to the camera module 2100b. The camera module 2100b provided with the synchronization enable signal can generate a synchronization signal based on the provided synchronization enable signal, and can provide the generated synchronization signal to the camera modules 2100a and 2100c via the synchronization signal line SSL. The camera module 2100b and the camera modules 2100a and 2100c can be synchronized with the synchronization signal to transmit image data to the application processor 2200.

[0141] In some embodiments, the control signals provided by the camera module controller 2216 to each of the camera modules 2100a, 2100b, and 2100c may include mode information according to the mode signal. Based on the mode information, the plurality of camera modules 2100a, 2100b, and 2100c may operate in a first operation mode and a second operation mode for sensing speed.

[0142] In the first operation mode, the plurality of camera modules 2100a, 2100b, and 2100c may generate an image signal at a first speed (e.g., may generate an image signal at a first frame rate), may encode the image signal at a second speed higher than the first speed (e.g., may encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor 2200. In this case, the second speed may be about 30 times or less than 30 times the first speed.

[0143] The application processor 2200 may store the received image signal (i.e., the encoded image signal) in the internal memory 2230 provided in the application processor 2200 or in the external memory 2400 provided outside the application processor 2200. Subsequently, the application processor 2200 may read the encoded image signal from the internal memory 2230 or the external memory 2400 and decode the encoded image signal, and may display the image data generated based on the decoded image signal. For example, a corresponding one of the sub-image processors 2212a, 2212b, and 2212c of the image processing device 2210 may perform decoding and may also perform image processing on the decoded image signal.

[0144] In the second operation mode, the plurality of camera modules 2100a, 2100b, and 2100c may generate an image signal at a third speed (e.g., may generate an image signal at a third frame rate lower than the first frame rate) and transmit the image signal to the application processor 2200. The image signal provided to the application processor 2200 may be an unencoded signal. The application processor 2200 may perform image processing on the received image signal or may store the image signal in the internal memory 2230 or the external memory 2400.

[0145] The PMIC 2300 can supply power (e.g., power voltage) to the multiple camera modules 2100a, 2100b, and 2100c respectively. For example, under the control of the application processor 2200, the PMIC 2300 can supply a first power to the camera module 2100a via the power signal line PSLa, a second power to the camera module 2100b via the power signal line PSLb, and a third power to the camera module 2100c via the power signal line PSLc.

[0146] In response to the power control signal PCON from the application processor 2200, the PMIC 2300 can generate power corresponding to each of the multiple camera modules 2100a, 2100b, and 2100c and can adjust the power level. The power control signal PCON can include power adjustment signals for each operation mode of the multiple camera modules 2100a, 2100b, and 2100c. For example, the operation mode can include a low power mode. In such a case, the power control signal PCON can include information about the camera modules operating in the low power mode and the set power level. The power levels provided to the multiple camera modules 2100a, 2100b, and 2100c can be equal to each other or can be different from each other. In addition, the power level can change dynamically.

[0147] According to an embodiment of the present disclosure, some columns of the pixel array of the image sensor can include three transmission metal lines. The pixel can be electrically connected to two of the three transmission metal lines and can detect a pixel voltage for calculating a phase difference from the pixel in response to signals applied to the three transmission metal lines. In this way, the time and power required for processing autofocus can be reduced according to the embodiment of the present disclosure.

[0148] Although the present disclosure has been described with reference to the embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Brief Description of the Drawings

[0010] By elaborating on the embodiments of the present disclosure with reference to the accompanying drawings, the above and other features of the present disclosure will become more apparent. In the drawings: FIG. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure. FIG. 2 shows a part of the pixel array shown in FIG. 1 according to an embodiment of the present disclosure. FIG. 3 shows in more detail the pixel group shown in FIG. 2 according to an embodiment of the present disclosure. FIG. 4 is a circuit diagram of the pixel shown in FIG. 2 according to an embodiment of the present disclosure. FIG. 5 is a flowchart showing a method of operating the image sensor shown in FIG. 1 according to an embodiment of the present disclosure. FIGS. 6A to 6C show in more detail the pixel groups repeatedly arranged in the pixel array according to some embodiments of the present disclosure. FIGS. 7A and 7B show in more detail the pixel groups repeatedly arranged in the pixel array according to some embodiments of the present disclosure. FIGS. 8A and 8B show in more detail the pixel groups repeatedly arranged in the pixel array according to some embodiments of the present disclosure. FIG. 9 is a block diagram of an electronic device including a multi-camera module according to an embodiment of the present disclosure. FIG. 10 is a block diagram showing in more detail the camera module shown in FIG. 9 according to an embodiment of the present disclosure.

Claims

1. An electronic device comprising: Image sensors generate image data; and an image processor for processing the image data, wherein the image sensor includes: a pixel array including a plurality of pixels repeatedly arranged along a column direction and a row direction, wherein each of the pixels belonging to a first column of a plurality of columns of the pixel array includes a plurality of sub-pixels, each of the plurality of sub-pixels being connected to one of a first transmission metal line, a second transmission metal line and a third transmission metal line, wherein, in response to signals respectively applied to the first transmission metal line to the third transmission metal line, at least a portion of the charge integrated at the plurality of sub-pixels of the pixels belonging to the first column diffuses to a corresponding floating diffusion region, wherein the pixels of the first column include a first pixel, a second pixel and a third pixel arranged sequentially adjacent to each other along the column direction, wherein the first pixel includes a first sub-pixel connected to the second transmission metal line and a second sub-pixel connected to the third transmission metal line, wherein the second pixel includes a third sub-pixel and a fourth sub-pixel connected to the first transmission metal line or the second transmission metal line; and wherein the third pixel includes a fifth sub-pixel and a sixth sub-pixel connected to the first transmission metal line or the second transmission metal line.

2. The electronic device of claim 1, wherein each of the pixels belonging to a second column of the plurality of columns of the pixel array comprises a plurality of sub-pixels, each of the plurality of sub-pixels being connected to one of a fourth transmission metal line, a fifth transmission metal line, and a sixth transmission metal line, wherein a second pixel belonging to the second column comprises a first sub-pixel connected to the fourth transmission metal line and a second sub-pixel connected to the sixth transmission metal line, and wherein the first sub-pixel of the first pixel and the first sub-pixel of the second pixel are located in different rows.

3. The electronic device as claimed in claim 2, wherein the image processor performs autofocus processing based on one of a first mode and a second mode, wherein, In the first mode, the image processor performs the autofocus processing based on the pixel voltage output from the first column of the pixel array, and in the second mode, the image processor performs the autofocus processing based on a portion of the pixel voltage output from the first column of the pixel array and a portion of the pixel voltage output from the second column.

4. The electronic device of claim 2, wherein the image sensor: resets the floating diffusion region of the pixels belonging to the first column; enables a signal to be applied to the first transmission metal line and a signal to be applied to the second transmission metal line; outputs first image data from the pixel array; resets the floating diffusion region of the pixels belonging to the second column; enables a signal to be applied to the fourth transmission metal line and a signal to be applied to the fifth transmission metal line; and outputs second image data from the pixel array.

5. The electronic device of claim 4, wherein the image processor performs autofocus processing based on data in the first image data corresponding to the first sub-pixel of the first pixel and data in the second image data corresponding to the second sub-pixel of the second pixel.

6. The electronic device of claim 1, wherein the image sensor: resets the floating diffusion region of the first pixel, the floating diffusion region of the second pixel, and the floating diffusion region of the third pixel; generates first image data in response to enabling a signal to be applied to the first transmission metal line and a signal to be applied to the third transmission metal line; and generates second image data in response to enabling a signal to be applied to the second transmission metal line.

7. The electronic device of claim 6, wherein the image processor performs autofocus processing based on the first image data and the second image data.

8. An image sensor, comprising: A pixel array, wherein the pixel array includes a first pixel group, the first pixel group including a plurality of pixels generating image data, wherein a first column of the first pixel group includes: a first pixel, including a pair of sub-pixels, each of the pair of sub-pixels receiving one of a first transfer gate signal and a second transfer gate signal; and a second pixel, including a pair of sub-pixels, each of the pair of sub-pixels receiving one of a second transfer gate signal and a third transfer gate signal, wherein the pixel array further includes a second pixel group, wherein a first column of the second pixel group includes: a fourth pixel, which includes a pair of sub-pixels, each of the pair of sub-pixels receiving one of the first transfer gate signal and the second transfer gate signal; and a sixth pixel, which includes a pair of sub-pixels, each of the pair of sub-pixels receiving one of the first transfer gate signal and the second transfer gate signal, and wherein the first pixel, the second pixel, the fourth pixel and the sixth pixel are arranged sequentially adjacent to each other along the column direction.

9. The image sensor of claim 8, wherein the second column of the first pixel group includes a third pixel, the third pixel includes a pair of sub-pixels, each of the pair of sub-pixels receiving one of a fourth transfer gate signal and a fifth transfer gate signal, wherein the second column of the second pixel group includes a fifth pixel, the fifth pixel includes a pair of sub-pixels, each of the pair of sub-pixels receiving one of the fourth transfer gate signal and a sixth transfer gate signal.

10. The image sensor of claim 9, wherein the image sensor: resets the floating diffusion regions of pixels belonging to the first column of the first pixel group and the floating diffusion regions of pixels belonging to the first column of the second pixel group; enables the first transfer gate signal and the second transfer gate signal; resets the floating diffusion regions of pixels belonging to the second column of the first pixel group and the floating diffusion regions of pixels belonging to the second column of the second pixel group; enables the fourth transfer gate signal and the fifth transfer gate signal; and provides autofocus processing based on the pixel voltage corresponding to the sub-pixel receiving the second transfer gate signal in the pair of sub-pixels of the second pixel and the pixel voltage corresponding to the sub-pixel receiving the fourth transfer gate signal in the pair of sub-pixels of the fifth pixel.

11. The image sensor of claim 9, wherein the transfer transistor of the sub-pixel receiving the second transfer gate signal in the pair of sub-pixels of the second pixel of the first pixel group and the transfer transistor of the sub-pixel receiving the fourth transfer gate signal in the pair of sub-pixels of the fourth pixel of the second pixel group are directly connected to a ground node.

12. The image sensor of claim 8, wherein the second column of the first pixel group includes a third pixel, the third pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of a fourth transfer gate signal and a fifth transfer gate signal, wherein the pixel array further includes a second pixel group, wherein the first column of the second pixel group includes a fourth pixel, the fourth pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the first transfer gate signal and the second transfer gate signal, and wherein the second column of the second pixel group includes a fifth pixel, the fifth pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the fifth transfer gate signal and a sixth transfer gate signal.

13. An image sensor, comprising: A pixel array, wherein the pixel array includes a first pixel group, the first pixel group including a first unit pixel group, a second unit pixel group, a third unit pixel group and a fourth unit pixel group, wherein the first pixel group includes: a first pixel, including a pair of sub-pixels, each of the pair of sub-pixels receiving one of a first transfer gate signal and a second transfer gate signal; a second pixel, including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the first transfer gate signal and the second transfer gate signal and a third transfer gate signal; a fifth pixel, including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the first transfer gate signal and the second transfer gate signal; a sixth pixel, including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the first transfer gate signal and the second transfer gate signal; and wherein the fifth pixel, the sixth pixel, the second pixel and the first pixel are arranged sequentially adjacent to each other along the column direction.

14. The image sensor of claim 13, wherein the first unit pixel group includes the first pixel and the second pixel, wherein the second unit pixel group includes: The third pixel includes a pair of sub-pixels, each of which receives one of the fourth transfer gate signal and the fifth transfer gate signal; And a fourth pixel, comprising a pair of sub-pixels, each of the pair of pixels receiving one of the fifth transfer gate signal and the sixth transfer gate signal.

15. The image sensor of claim 14, wherein the image sensor: selects a first column of the first unit pixel group; enables the first transfer gate signal and the second transfer gate signal; detects a first pixel voltage from the pixel array; selects a first column of the second unit pixel group; enables the fourth transfer gate signal and the fifth transfer gate signal; detects a second pixel voltage from the pixel array; and provides autofocus processing based on the first pixel voltage and the second pixel voltage.

16. The image sensor of claim 14, wherein the first column of the first pixel group includes the first pixel and the second pixel, and wherein each of the pixels belonging to the second column of the first pixel group includes a pair of sub-pixels, each of the pair of sub-pixels receiving one of the fourth transfer gate signal and the fifth transfer gate signal.

17. The image sensor of claim 13, wherein the first unit pixel group includes the first pixel, wherein the second unit pixel group includes the second pixel, wherein the second unit pixel group further includes a third pixel, the third pixel including a pair of sub-pixels, each of the pair of sub-pixels receiving one of the second transfer gate signal and the third transfer gate signal, and wherein the pair of sub-pixels of the second pixel respectively receive the second transfer gate signal and the third transfer gate signal.

18. The image sensor of claim 17, wherein each of the pixels in the first unit pixel group includes a pair of sub-pixels separated by a boundary in a first diagonal direction, and wherein each of the pixels in the third unit pixel group includes a pair of sub-pixels separated by a boundary in a second diagonal direction.

19. The image sensor of claim 13, wherein the pair of sub-pixels of the second pixel respectively receive the second transfer gate signal and the third transfer gate signal, wherein the first column of the first unit pixel group includes the first pixel and the second pixel, and wherein the second column of the first unit pixel group includes: The third pixel includes a pair of sub-pixels, each of which receives one of the fourth transfer gate signal and the fifth transfer gate signal; And a fourth pixel, including a pair of sub-pixels, each of the pair of pixels receiving one of the fourth transfer gate signal and the sixth transfer gate signal.

Images