Semiconductor device and manufacturing method thereof

Abstract

This disclosure provides a method for forming a self-aligned via and an apparatus having a self-aligned via. In some embodiments, a method includes forming a first via on a conductive layer. A mask is formed over the conductive layer and has an opening that covers a portion of the conductive layer and at least partially covers the first via. A first line end of the conductive layer is formed by selectively removing a portion of the conductive layer, wherein the first via is aligned with the first line end of the conductive layer.

Description

[Technical Field]

[0001] None. [Previous Technology]

[0002] Advances in semiconductor integrated circuit (IC) manufacturing have led to an increase in functional density (i.e., the number of interconnect devices per wafer area) and a reduction in geometry (i.e., the smallest element (or line) that can be created using manufacturing processes). Increasing functional density while reducing geometry generally provides benefits through improved production efficiency and lower associated costs. However, this advancement in the size and density of devices or components has also been accompanied by increased complexity in designing and manufacturing devices that incorporate these integrated circuits.

[0003] For example, reducing the size and spacing between integrated circuit components formed on a semiconductor substrate typically involves using multiple different photomasks and performing a dicing process to produce patterned components used in the integrated circuit. [Summary of the Invention]

[0004] None

Implementation Method

[0006] In the following description, numerous thicknesses and materials are described for various layers and structures within an integrated circuit chip. Specific dimensions and materials are given by way of example for various embodiments. Those skilled in the art will recognize from this disclosure that other dimensions and materials may be used in many cases without departing from the scope of this disclosure.

[0007] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. As used herein, forming a first feature on a second feature means that the first feature is formed in direct contact with the second feature. Additionally, numbers and / or words may be repeatedly referenced in various examples in this disclosure. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms (e.g., "below," "below," "under," "above," "above," etc.) are used herein to simply describe the relationship between an element or feature as shown in the figure and another element or feature. In addition to the orientation shown in the figure, these spatially relative terms cover different orientations of the device during use or operation. These devices can be rotated in other ways (90 degrees or other angles), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0009] References to deposition techniques used in this disclosure for depositing dielectric layers, metals, or any other materials include techniques such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electroless plating, or similar techniques. Detailed descriptions in this disclosure are given with reference to examples of such processes. However, this disclosure and references to certain deposition techniques should not be limited to those described.

[0010] References in this disclosure to etching techniques for selectively removing semiconductor materials, dielectric materials, metals, or any other materials include, but are not limited to, dry etching, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing (CMP), etc. Detailed embodiments are described in this disclosure with reference to examples of such processes. However, this disclosure and references to certain etching techniques should not be limited to those described.

[0011] As the size or dimensions of the components formed in an integrated circuit decrease, the spacing, distance, or gap between the ends of adjacent components may be limited by the process steps used to form the components. For example, the photolithography and dicing processes used to fabricate patterned components for integrated circuits may have lower limitations in terms of the practically achievable spacing between components. For example, these lower limits may be defined by the size of the photomask that can be physically produced based on the layout of the integrated circuit.

[0012] As described in this disclosure, this disclosure provides methods and apparatus in which the ends of conductive layers (e.g., conductive lines) are self-aligned relative to conductive vias, thereby helping to reduce the distances or gaps that can be achieved between patterned elements of an integrated circuit. In some embodiments, the via can be formed prior to a metal cutting process that selectively removes a portion of the conductor, thereby forming the end of the conductor aligned with and located below the via. The cutting process can be performed using a single cut metal pattern or mask. The reduced use of masks reduces production costs and time compared to conventional techniques. Furthermore, the methods and apparatus provided in this disclosure can alleviate the via-to-metal line end enclosure budget and the via-to-cut metal spacing budget.

[0013] Figures 1 to 3 are cross-sectional views illustrating a method of manufacturing an apparatus according to one or more embodiments of the present disclosure, the apparatus being a semiconductor device. Additional steps may be provided before, during, and after the method, and some described steps may be replaced or removed in other embodiments of the method.

[0014] As shown in Figure 1, a conductive layer 12 is formed on the substrate 10, and a via 14 is formed on the conductive layer 12. The substrate 10 can be any suitable substrate, such as any suitable semiconductor substrate. In various embodiments, the substrate 10 can be formed of a crystalline semiconductor material, such as single-crystal silicon, polycrystalline silicon, or some other type of crystalline semiconductor material. In some embodiments, the substrate 10 is a silicon substrate; however, the embodiments provided in this disclosure are not limited thereto. For example, in various embodiments, the substrate 10 may include gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any other semiconductor material. Depending on the design specifications, the substrate 10 may include a variety of doping configurations. In some embodiments, the substrate 10 is a p-type substrate with a p-type dopant concentration. In other embodiments, the substrate 10 is an n-type substrate with an n-type dopant concentration.

[0015] In various embodiments, substrate 10 may have a substantially uniform composition or may include various layers. These layers may have similar or different compositions, and in some embodiments, some substrate layers have non-uniform compositions to cause device strain and thereby adjust device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates. In some embodiments, the layers of substrate 10 may include insulators, such as semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, semiconductor carbides, and / or other suitable insulating materials.

[0016] In some embodiments, through-holes may be formed to extend into the semiconductor substrate 10, wherein the through-holes are used to electrically couple features on opposite sides of the semiconductor substrate to each other. Integrated circuit devices may be formed on the active side of the semiconductor substrate 10, which may include active elements such as transistors and / or passive elements such as capacitors, resistors, or similar components.

[0017] The conductive layer 12 can be formed of any conductive material, and in some embodiments, it can be formed of one or more of Co, Ru, or W. In various embodiments, the conductive layer 12 can be patterned by any suitable technique to have any shape or size that may be required. For example, in some embodiments, the conductive layer 12 can be a conductive line and can have a substantially linear shape patterned by conventional photolithography processes or any other suitable process. In some embodiments, the conductive layer 12 is part of a metal interconnect layer of a semiconductor device.

[0018] In some embodiments, via 14 may be a conductive via, such as a metal via, that electrically couples the conductive layer 12 to one or more components of a semiconductor device. Via 14 may be formed by any suitable technique, including, for example, a deposition process. The deposition process may be any suitable deposition process for depositing a hard mask layer, including, for example, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), or similar processes.

[0019] In some embodiments, the via 14 may extend through one or more layers (not shown) on the conductive layer 12 or the substrate 10. For example, in various embodiments, the via 14 may extend through one or more dielectric layers (e.g., semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, semiconductor carbides, metal oxides, other metal compounds, etc.), metal layers, metal alloy layers, polycrystalline silicon layers, or any other material layer that may be present in the semiconductor device.

[0020] In some embodiments, a portion of one or more layers on the conductive layer 12 is selectively removed, for example by etching or any other suitable technique. Vias 14 can then be formed in the grooves or voids where portions of one or more layers have been removed, for example by depositing a conductive material.

[0021] The through hole 14 may have any shape as needed. In some embodiments, as shown in Figure 1, the through hole 14 may have a substantially cylindrical shape; however, the embodiments disclosed herein are not limited thereto, and in various embodiments, the through hole 14 may have a rectangular shape, a tapered shape, an inverted tapered shape, or any other shape.

[0022] As shown in Figure 2, the mask 18 is located over the structure including the via 14, the conductive layer 12, and the substrate 10. The mask 18 includes an opening 20, and the opening 20 covers at least a portion of the conductive layer 12a. The mask 18 may be referred to as a cut metal mask or cut metal pattern, and is used to pattern or cut the conductive layer by selectively removing a portion 12a of the conductive layer 12.

[0023] In various embodiments, mask 18 can be any suitable mask, such as a hard mask, including masking materials for protecting underlying regions (e.g., conductive layer 12 and substrate 10) during the manufacturing process. Suitable materials for mask 18 may include dielectric materials (e.g., semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, semiconductor carbides, metal oxides, other metal compounds, etc.), metals, metal alloys, polycrystalline silicon, or other suitable materials. In some embodiments, mask 18 is a silicon nitride film.

[0024] The mask 18 can be formed by any suitable process, including, for example, deposition, anodizing, thermal oxidation, or similar processes. In some embodiments, the mask 18 is formed by a deposition process. The deposition process can be any suitable deposition process for depositing the mask layer, including, for example, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), or similar processes. In some embodiments, the mask 18 is patterned from a patterned photoresist layer (not shown). For example, the mask 18 can be formed by depositing a mask material on the via 14, the conductive layer 12, the substrate 10, and any layer on the substrate 10 adjacent to the conductive layer 12, and photoresist can be formed on the mask material (e.g., by spin coating). Subsequently, the photoresist layer may undergo a photoresist process, which may include one or more steps, such as exposure, post-exposure baking, development, rinsing, or similar, to form a patterned photoresist layer, which may then be used to pattern a mask material to define the pattern or shape of the mask 18, including the opening 20.

[0025] A mask 18 is located above the via 14 and the conductive layer 12, with an opening 20 at least covering a portion 12a of the conductive layer 12. In some embodiments, the via 14 is at least partially exposed through the opening 20 of the mask 18, as shown in Figure 2. As will be discussed in further detail herein, a portion 12a of the conductive layer 12 may be removed, and the via 14 may protect the underlying portion of the conductive layer 12 such that the conductive layer 12 is self-aligned with the via 14 after the portion 12a is removed.

[0026] Once the mask 18 is positioned as desired on the via 14 and the conductive layer 12, portions 12a of the conductive layer 12 are selectively removed, for example, by an etching process. The etching process may include, for example, wet etching, dry etching, reactive ion etching (RIE), ashing, or any other suitable etching process. In some embodiments, portions 12a of the conductive layer 12 are removed by an etchant (which may be a wet etchant, plasma etchant, etchant gas, etc.) having etchant chemistry that selectively removes portions 12a of the conductive layer 12 exposed through the opening 20, while the via 14 is substantially resistant to the etchant. The conductive layer 12 and the via 14 may be formed of different materials with different selectivity to the etchant. For example, the etchant may have etchant chemistry that is highly selective to the conductive layer 12. For example, an etchant gas may be used to remove the conductive layer 12 at a higher etching rate than that used to remove the via 14. In some embodiments, a portion 12a of the conductive layer 12 is removed by an etchant gas, which includes carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), other suitable etchants, or combinations thereof.

[0027] The etching process for removing portion 12a of the conductive layer 12 can be performed with various etching parameters as needed. For example, in some embodiments, the etching process uses a chloride / chlorine-based etchant with an etching deviation between about 50 volts and about 150 volts, and an etching time / duration between about 100 seconds and about 300 seconds.

[0028] As shown in Figure 3, after selectively removing portion 12a of the conductive layer 12, the conductive layer 12 is separated into a first segment 12b and a second segment 12c facing each other. The first segment 12b has an end profile aligned with the through-hole 14 and having a substantially the same shape as the through-hole 14, because the through-hole 14 is used as a mask for the end of the first segment 12b during the removal of portion 12a, as previously described.

[0029] Figure 4A is a top view illustrating the cut metal pattern or mask 18, and Figure 4B is a top view illustrating the effective area of ​​the cut metal pattern or mask 18, including the masking performed by the through-hole 14. As can be seen from Figures 4A and 4B, the through-hole 14 effectively extends the masking area because it extends at least partially into the area of ​​the opening 20. Therefore, a cutting process (e.g., selectively removing a portion 12a of the conductive layer) can be performed on the conductive layer 12, while the conductive layer 12 is confined by the through-hole 14. This results in the through-hole 14 being self-aligned with the end of the first segment 12b of the conductive layer 12. Therefore, the embodiments disclosed herein have a significant advantage over conventional techniques where the underlying metal or conductive layer has a surrounding budget with respect to the through-hole, such that the metal or conductive layer has a line end extending laterally outward beyond the edge of the through-hole, possibly because the metal or conductive layer is cut before the through-hole is formed.

[0030] Figure 5A is a top view illustrating the alignment of the via 14 and the first segment 12b of the conductive layer 12, and Figure 5B is a side view illustrating the alignment of the via 14 and the first segment 12b of the conductive layer 12. As can be seen from Figures 5A and 5B, the via 14 is aligned to the line end of the first segment 12b without any surrounding budget (e.g., a portion of the first segment 12b does not extend laterally outward beyond the edge of the via 14 into the cut area or toward the second segment 12c). According to some embodiments, the first segment 12b may have a rounded curved edge and may fit to the corresponding rounded or circular edge of the via 14. Furthermore, as shown in Figure 5B, the via 14 and the line end segment 12b of the first segment together form a smooth vertical sidewall. The sidewall profile can vary, for example, by different angles or a bowl shape, but this disclosure and reference to certain etched profiles should not be limited to those described. For example, the sidewall of the via 14 may be inclined upward or downward at 80 to 90 degrees relative to the bottom surface of the via.

[0031] Figures 6-17D illustrate a method for forming a semiconductor device having a self-aligned via according to one or more embodiments of the present disclosure. In Figures 6-17D, the figure labeled "A" is a top view, and the figures labeled "B", "C", and "D" are cross-sectional views taken along the corresponding cut lines shown in the top view. However, it should be noted that not all features of the corresponding structure are necessarily depicted in these views; rather, the cross-sectional views and top views may only depict portions or features of the structure that are relevant to the description of forming the via, and other structures or features may be omitted from the cross-sectional views and top views.

[0032] As shown in Figure 6, the semiconductor device structure 100 includes a first transistor 101, a second transistor 102, and a third transistor 103 already formed on a semiconductor substrate 106. The first, second, and third transistors 101-103 may have the same or substantially similar structures. Therefore, although the reference numerals are primarily provided for the structure of the first transistor 101, the second and third transistors 102 and 103 may have the same or equivalent structures.

[0033] In some embodiments, the first transistor 101 may be a gate-all-around (GAA) transistor. Transistor 101 includes a plurality of semiconductor nanosheets 120 or nanowires. The semiconductor nanosheets 120 are multilayer semiconductor materials. The semiconductor nanosheets 120 correspond to channel regions of transistor 101. The semiconductor nanosheets 120 are formed over substrate 106 and may be formed on semiconductor substrate 106. The semiconductor nanosheets 120 may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the semiconductor nanosheets 120 are formed of the same semiconductor material as substrate 106. Other semiconductor materials may be used for semiconductor nanosheets 120 without departing from the scope of this disclosure.

[0034] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the gate-all-around structure.

[0035] In some embodiments, the semiconductor nanosheet 120 is formed from the substrate 106 via alternating epitaxial growth processes. For example, a first epitaxial growth process may result in the formation of a sacrificial semiconductor nanosheet on the top surface of the substrate 106. A second epitaxial growth process may result in the formation of the semiconductor nanosheet 120 on the sacrificial semiconductor nanosheet. Alternating epitaxial growth processes may be performed until a selected number of semiconductor nanosheets 120 and sacrificial semiconductor nanosheets have been formed.

[0036] After forming the semiconductor nanosheets 120 and the sacrificial nanosheets between the semiconductor nanosheets 120, the sacrificial nanosheets can be removed. The removal of the sacrificial nanosheets results in gaps between the semiconductor nanosheets 120.

[0037] As shown in Figure 6, transistor 101 may have four semiconductor nanosheets 120. However, in practice, transistor 101 may have a number of semiconductor nanosheets 120 other than four. For example, in some embodiments, transistor 101 may include 2 to 10 semiconductor nanosheets 120. Other numbers of semiconductor nanosheets 120 may be used without departing from the scope of this disclosure.

[0038] The semiconductor nanosheet 120 may have a thickness between 2 nm and 100 nm. In some embodiments, the thickness of the semiconductor nanosheet 120 is between 2 nm and 20 nm. This range provides suitable conductivity for the semiconductor nanosheet while maintaining a low thickness. In some embodiments, each nanosheet 120 is thicker than the semiconductor nanosheet 120 above it. The semiconductor nanosheets 120 may have other thicknesses without departing from the scope of this disclosure.

[0039] In some embodiments, a bottom dielectric layer (not shown) may be located between the bottom semiconductor nanosheet 120 and the substrate 106. The bottom dielectric layer may include silicon nitride or other suitable materials.

[0040] A sheet-like internal spacer layer 128 is located between semiconductor nanosheets 120. The sheet-like internal spacer layer 128 can be deposited by atomic layer deposition, chemical vapor deposition, or other suitable processes. In one example, the sheet-like internal spacer layer 128 comprises silicon nitride.

[0041] A semiconductor nanosheet 120 extends between a source and a drain region 130. The source and drain regions 130 comprise semiconductor material. In some embodiments, the source and drain regions 130 may be epitaxially grown from the semiconductor nanosheet 120 or from a substrate 106. In the case of an N-type transistor, the source and drain regions 130 may be doped with N-type dopant. In the case of a P-type transistor, the source and drain regions 130 may be doped with P-type dopant. Doping may be performed in situ during epitaxial growth. Although the source and drain regions 130 are labeled with a common reference numeral and heading, in practice, the transistor 101 will have a source region and a separate drain region. For example, the region 130 on the left side of the transistor 101 may correspond to the source of the transistor 101, and the region 130 on the right side of the transistor 101 may correspond to the drain of the transistor 101. Alternatively, the drain may be on the left and the source may be on the right.

[0042] The gate structure 150 is located on the stack of semiconductor nanosheets 120. In some embodiments, the gate structure 150 includes a gate spacer 126 located on the sidewall of a gate trench formed above the semiconductor nanosheets 120. In some embodiments, the gate spacer 126 may include SiCON. The gate spacer 126 may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Other materials and deposition processes may be used for the gate spacer 126 without departing from the scope of this disclosure.

[0043] Although not shown in Figure 6, a thin interface dielectric layer may be formed on the surface of the semiconductor nanosheet 120. The interface dielectric layer may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interface dielectric layer may be formed by a thermal oxidation process, a chemical vapor deposition process, or an atomic layer deposition process. The interface dielectric layer may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interface dielectric layer without departing from the scope of this disclosure.

[0044] An interface dielectric layer surrounds the semiconductor nanosheet 120. Specifically, the semiconductor nanosheet 120 may have a shape corresponding to a strip or line extending between the source and drain regions 130. The interface dielectric layer surrounds each semiconductor nanosheet 120. The interface dielectric layer surrounds or partially surrounds the semiconductor nanosheet 120.

[0045] Although not shown in Figure 6, a high-dielectric gate dielectric layer may be formed on the interface dielectric layer, on the sidewalls of the gate spacer 126, and on the sidewalls of the sheet-like internal spacer layer 128. In common, the dielectric layer and the interface dielectric layer correspond to the gate dielectric layer of the transistor 101. The high-dielectric dielectric layer surrounds or partially surrounds the semiconductor nanosheet 120 in the same manner as described with respect to the interface dielectric layer, except that the interface dielectric layer is located between the semiconductor nanosheet 120 and the high-dielectric gate dielectric layer.

[0046] The high-dielectric gate dielectric layer may include one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-dielectric dielectric materials, or combinations thereof. The high-dielectric gate dielectric layer may be formed by chemical vapor deposition, atomic layer deposition, or any suitable method. In some embodiments, a highly conformal deposition process, such as atomic layer deposition, is used to form the high-dielectric gate dielectric layer to ensure that a gate dielectric layer with a uniform thickness is formed around each semiconductor nanosheet 120. In some embodiments, the thickness of the high-dielectric dielectric layer is in the range of about 1 nm to about 4 nm. Other thicknesses, deposition processes, and materials may be used for the high-dielectric gate dielectric layer without departing from the scope of this disclosure.

[0047] Gate 148 fills the remaining space between semiconductor nanosheet 120 and trench, which is located above the semiconductor nanosheet 120 between gate spacers 126. Gate 148 may include multiple individual gate metal layers. The material and thickness of the various gate metal layers can be selected to provide the desired threshold voltage of transistor 101.

[0048] In some embodiments, the gate 148 includes a metal layer and a gate filler material located on the metal layer in the trench and between the metal layer and the semiconductor nanosheet 120. In one example, the gate filler material includes tungsten. The gate filler material can be deposited using PVD, ALD, CVD, or other suitable deposition processes. The gate filler material fills the remaining space in the trench between the semiconductor nanosheet 120. The gate filler material is highly conductive.

[0049] The metal layer and the gate filling material surround or partially surround the semiconductor nanosheet 120 in the same manner as the above-mentioned interface dielectric layer and high dielectric gate dielectric layer, except that the interface dielectric layer and the high dielectric gate dielectric layer are located between the semiconductor nanosheet 120 and the metal layer and the gate filling material.

[0050] In some embodiments, the conductive layer 134 is formed on the source and drain regions 130 of each of the first, second, and third transistors 101-103. The conductive layer 134 may be an interconnecting metal connecting the source and drain regions 130 to one or more vias, as will be described in more detail below. In various embodiments, the conductive layer 134 may be formed of any conductive material.

[0051] As shown in Figures 7A and 7B, the semiconductor device structure 200 may include a wafer 202 and a semiconductor substrate 204 on the wafer 202. In some embodiments, the wafer 202 is a semiconductor wafer. The semiconductor device structure 200 may include various electrical features or devices. In some embodiments, the semiconductor device structure 200 includes one or more semiconductor devices, such as finfield-effect transistor (FFET) devices, nanoplate transistors, or nanoplate semiconductor devices or the like. In some embodiments, the semiconductor device structure 200 includes one or more conductive wiring layers, interconnect layers, bottom interconnect layers, or the like. In some embodiments, the semiconductor device structure 200 may be or include the semiconductor device structure 100 described with respect to Figure 6.

[0052] As shown in Figure 7B, a first dielectric layer 206 and a first conductive layer 208 may be formed on the semiconductor device 200. In some embodiments, the first conductive layer 208 may correspond to the conductive layer 134 of the semiconductor device structure 100 shown in Figure 6.

[0053] The first dielectric layer 206 and the conductive layer 208 are formed in an alternating sequence, with portions of the first dielectric layer 206 alternately arranged between portions of the conductive layer 208. The first dielectric layer 206 and the conductive layer 208 can be formed by any suitable technique, including, for example, by deposition, standard photolithography steps, etching, metal etching, chemical mechanical polishing (CMP) or similar techniques.

[0054] The first dielectric layer 206 may include any suitable dielectric material. In some embodiments, the first dielectric layer 206 may be a low-dielectric dielectric layer. In some embodiments, the first dielectric layer 206 may be an oxide layer. In some embodiments, the first dielectric layer 206 may include silicon oxide.

[0055] As shown in Figures 8A and 8B, a second dielectric layer 210 is formed over the first dielectric layer 206 and the conductive layer 208, and a resist layer or photoresist layer 212 is formed over the second dielectric layer 210. The second dielectric layer 210 may include any suitable dielectric material. In some embodiments, the second dielectric layer 210 may be a low-dielectric dielectric layer. In some embodiments, the second dielectric layer 210 may be an oxide layer. In some embodiments, the second dielectric layer 210 may include silicon oxide. In some embodiments, the first and second dielectric layers 206 and 210 may be formed of the same material.

[0056] In some embodiments, the resist layer 212 may be a single-layer or multi-layer structure, which may be selected as needed according to design considerations, such as patterning and etching steps to be performed via the resist layer 212.

[0057] As shown in Figures 9A and 9B, the opening 214 is formed in the resist layer 212 by selectively removing a portion of the resist layer 212 corresponding to the opening 214. The opening 214 can be formed by any suitable technique, including, for example, by developing and selectively etching the resist layer 212 using a standard photolithography process. The opening 214 may correspond to a via pattern to be formed on the semiconductor device structure 200. The opening 214 may extend through the resist layer 212 and expose a portion of the second dielectric layer 210, as shown. In some embodiments, the opening 214 may cover and align (e.g., vertically align) a portion of the conductive layer 208.

[0058] As shown in Figures 10A and 10B, a cavity 216 extends through the second dielectric layer 210. The cavity 216 at least partially exposes a portion of the conductive layer 208. In some embodiments, the cavity 216 may at least partially expose a portion of the conductive layer 134 on each of the source and drain regions 130 of the semiconductor device structure 100 of Figure 6.

[0059] The cavity 216 can be formed by any suitable process. In some embodiments, the cavity 216 is formed by photolithography and etching processes that define the cavity 216, for example, by selective etching and removal of portions of the second dielectric layer 210. The cavity 216 can be formed into any desired shape, and in some embodiments the shape of the cavity 216 can define the shape of the subsequently formed via. In some embodiments, the cavity 216 may have a substantially cylindrical or elliptical shape; however, the embodiments disclosed herein are not limited thereto, and in various embodiments, the cavity 216 may have a rectangular shape, a conical shape, an inverted conical shape, or any other shape.

[0060] As shown in Figures 11A and 11B, a dummy material (dummy via or masking via) 144 may be formed within cavity 142 and may fill cavity 216. The dummy material 144 may extend through each cavity 216 and may contact the lower portion of the conductive layer 208. The dummy material 144 may be formed to fill cavity 216 by any suitable technique, including, for example, by a deposition process. The deposition process may be any suitable deposition process, including, for example, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), or similar. The dummy material 144 may be any suitable dummy material. In some embodiments, the dummy material 144 may be a dielectric material. In some embodiments, the dummy material may include one or more of SiCN, SiOCN, SiOC, AlOx, AlN, AlCN, TiN, TiO, or any other suitable dummy material.

[0061] In some embodiments, a chemical mechanical polishing (CMP) process is performed on the surfaces of the dummy material 144 and the second dielectric layer 210 (e.g., on its upper surface) to planarize the surfaces of the dummy material 144 and the second dielectric layer 210.

[0062] As shown in Figures 12A, 12B, 12C, and 12D, mask 218 is located above the structure shown in Figures 11A and 11B. Mask 218 may be the same as or substantially similar to mask 18 previously described in this disclosure. For example, mask 218 may include openings 220 that cover at least a portion 208a of each conductive layer 208, as shown in the cross-sectional view of Figure 12B, which is taken along the cut line X2-X2'. Mask 218 may be a cut metal mask or a cut metal pattern and is used to pattern or cut the conductive layer 208 by selectively removing portions 208a of the conductive layer 208. In some embodiments, mask 218 is a hard mask or resist layer formed on the second dielectric layer 210 and the dummy layer 144 by a deposition process and patterned to form the openings 220, for example by photolithography and etching processes.

[0063] As shown in Figures 13A, 13B, 13C, and 13D, a portion of the second dielectric layer 210 exposed through the opening 220 of the mask 218 is selectively removed by, for example, an etching process. In some embodiments, the opening 220 covers at least a portion of the dummy material 144, for example, as shown in the cross-sectional view of Figure 13C, which is taken along cut line X2-X2'. The etching process may be a dielectric film etching process, wherein an etchant is used to selectively remove a portion of the second dielectric layer 210 exposed through the opening 220, but not to remove the exposed portion of the dummy material 144 in the opening 220. As shown, the mask 218 can be removed. As shown in Figure 13C, taken along cut line X2-X2', the second dielectric layer 210 remains in the area covered by the mask 218.

[0064] As shown in Figures 14A, 14B, 14C, and 14D, portions of the conductive layer 208 are selectively removed. For example, as shown in Figures 14C and 14D, a cavity 217 is formed by selectively removing exposed portions of the conductive layer 208. In some embodiments, the cavity 217 may at least partially expose the lower layer portion of the semiconductor substrate 204.

[0065] The cavity 217 can be formed by any suitable process. In some embodiments, the cavity 217 is formed by a metal etching process that defines the cavity 217 by, for example, selective etching and removal of portions of the conductive layer 208. The cavity 217 can be formed to have any desired shape.

[0066] As shown in Figures 14C and 14D, a portion 208a of the conductive layer 208 remains under the dummy material 144 after the etching process. That is, the portion 208a of the conductive layer 208 is protected by the overlying dummy material 144 and therefore is not removed by the etching process. After the etching process, the portion 208a of the conductive layer 208 may have a shape substantially the same as the shape of the dummy material 144 (e.g., in the top view).

[0067] In some embodiments, the dummy material 144 is a different material from the conductive layer 208. In some embodiments, the dummy material 144 is a non-conductive material. In some embodiments, the cavity 217 is formed by removing portions of the conductive layer 208 with an etchant (which may be a wet etchant, plasma etchant, etchant gas, or the like), the etchant having etchant chemistry that selectively removes portions of the conductive layer 208 aligned with and patterned by the opening 220, while the dummy material 144 is substantially resistant to the etchant. The conductive layer 208 and the dummy material 144 may be formed from different materials with different selectivity to the etchant. For example, the etchant may have etchant chemistry that is highly selective to the conductive layer 208. For example, an etchant gas may be used, which removes the conductive layer 208 at a higher etching rate than the dummy material 144. Therefore, after the cavity 217 is formed by etching away portions of the conductive layer 208, the dummy material 144 may have substantially the same size and shape as before etching.

[0068] As shown in Figures 15A, 15B, 15C and 15D, the third dielectric layer 232 is formed on an exposed portion of the semiconductor substrate 204 on the first dielectric layer 206, for example in a cavity 217. In some embodiments, the third dielectric layer 232 may be formed of the same material as the first dielectric layer 206.

[0069] In some embodiments, a chemical mechanical polishing (CMP) process is performed on the surfaces (e.g., on the upper surface of) the dummy material 144, the first dielectric layer 206, and the third dielectric layer 232 to planarize the surfaces after the third dielectric layer 232 is formed.

[0070] As shown in Figures 16A, 16B, 16C, and 16D, the cavity 237 is formed by removing the dummy material 144. The cavity 237 can be formed by any suitable process. In some embodiments, the cavity 237 is formed by an etching process that defines the cavity 237, for example, by selective etching and removal of portions of the dummy material 144. The cavity 237 can be formed with any desired shape. The removal of the dummy material 144 exposes the surface of a portion 208a of the conductive layer 208.

[0071] As shown in Figures 17A, 17B, 17C and 17D, a through-hole 214 is formed in the cavity 237. The through-hole 214 can be formed by any suitable technique, including by deposition or any other suitable process.

[0072] The via 214 can be formed of any conductive material. In some embodiments, the via 214 may include one or more of Co, Ru, or W. A chemical mechanical polishing (CMP) process may be performed on the surfaces of the via 214, the first dielectric layer 206, the second dielectric layer 210, and the third dielectric layer 232 (e.g., on its upper surface) to planarize the surfaces after the via 214 is formed.

[0073] Therefore, when the process shown in Figures 17A, 17B, 17C and 17D is completed, the via 214 is self-aligned with the line end of the lower portion 208a of the conductive layer 208. The via 214 thus provides an electrical connection between one or more components (not shown) that can be formed on the semiconductor substrate 204, such as between the source and drain regions 130 of the semiconductor device structure 100 shown in Figure 6.

[0074] As previously explained with respect to Figures 5A and 5B, the via 214 can be self-aligned to the line end of the first segment 134b without any surrounding budget, and the via 214 and the line end of the first segment 134b together form a smooth vertical sidewall. In some embodiments, one or more vias 214 can be staggered or biased relative to different vias 214. In some embodiments, one or more of the vias 214 can be self-aligned to the associated line end of the first segment 134b without any surrounding budget, while one or more biased vias can have an associated surrounding budget.

[0075] Although the process shown in Figures 6-17D is described as including dummy material 144, in some embodiments, dummy material 144 may be omitted from the process. For example, in some embodiments, via 214 may be formed directly in cavity 216 before the mask 218 is placed (see Figure 10B). In such embodiments, via 214 may be formed of any conductive material having an etch selectivity different from that of conductive layer 208. Thus, cavity 217 (see Figures 14C and 14D) may be formed by selectively removing portions of conductive layer 208 aligned with opening 220 using an etchant having etchant chemistry that selectively removes conductive layer 208, while via 214 is substantially resistant to the etchant. After forming self-aligned via 214, a third dielectric layer 232 may be formed in cavity 217.

[0076] Figure 18A is a comparative example illustrating the effect of the overlay offset between the through-hole and the cut metal pattern according to an embodiment of the present disclosure, and Figure 18B illustrates the effect of the overlay offset between the through-hole and the cut metal pattern according to an embodiment of the present disclosure.

[0077] In the comparative example shown in Figure 18A, a metal cutting process is performed to define the line ends of the conductive layer 334 before the via 314 is formed on the conductive layer 334. Therefore, if there is a cover offset between the via 314 and the cut metal pattern 318, the via 314 may experience via landing failure because the via 314 can be formed in the area of ​​the conductive layer 334 that is offset due to the cover offset. This could be due to a cover offset in the formation of the via 314 (e.g., the via 314 is offset relative to its intended position) or a cover offset in the cut metal pattern 318 (e.g., the cut metal pattern 318 moves relative to its intended position), and in either case, the result could be the formation of a via 314 that extends at least partially over the cut portion (e.g., the removed portion) of the conductive layer 334.

[0078] Conversely, as shown in Figure 18B, in the embodiments disclosed herein, the via 414 remains self-aligned with the conductive layer 434 even in the event of a cover offset between the via 414 and the conductive layer 434. This is due to the formation of the self-aligned via 414 as described in this disclosure. For example, since the via 414 is formed before the conductive layer 434 is selectively removed (e.g., by etching), the via 414 is self-aligned with the conductive layer 434 and no additional surround budget is required. Therefore, the via 414 has a higher tolerance for cover offset without causing landing errors.

[0079] Figure 19A is a comparative example illustrating the spacing between through holes, and Figure 19B illustrates the spacing between through holes that can be obtained according to embodiments of the present disclosure.

[0080] In the comparative example illustrated in Figure 19A, a via 614 is formed on the conductive layer 634 before the conductive layer 634 is cut through the opening 620 of the cutting metal layer. Therefore, the underlying conductive layer 634 has a surrounding budget with respect to the via 614, such that the conductive layer 634 has a line end extending laterally outward beyond the edge of the via 614. The minimum via spacing, which can be measured as the distance between the center points of each via 614 in the direction through the opening 620, is equal to the distance (d) through the opening 620 plus the length (∅) of the via 614 (which may be the diameter in the case of a circular or cylindrical shape). In some embodiments, the via 614 (∅) may be equal to or less than 50 nm. The distance (d) may be between 10 and 50 nm or greater.

[0081] Conversely, as shown in Figure 19B, in the embodiments disclosed herein, the via 714 is self-aligned with the lower line end of the conductive layer 734. In this way, a portion of the via 714 can protrude into the region of the opening 720 that cuts through the metal layer. Therefore, the minimum via spacing can be reduced relative to the minimum spacing shown in Figure 19A. More specifically, the minimum via spacing between vias 714 according to the embodiments disclosed herein can be equal to or substantially equal to the distance (d) across the opening 720. In some embodiments, the spacing between vias 714 can be equal to or less than 50 nm. In some embodiments, the spacing between vias 714 can be equal to or less than 30 nm.

[0082] Figure 20A illustrates a comparative example of the formation of a bias via, and Figure 20B illustrates the formation of a bias via according to an embodiment of the present disclosure.

[0083] In the comparative example illustrated in Figure 20A, a cut metal pattern with a curved opening 820 is used to form a biased via 814 with an offset distance (t). The offset distance (t) can be measured as the distance between the center of the via 814a and the edge of the offset via 814b. In some embodiments, the distance (t) may be equal to or less than 30 nm. However, it is difficult to pattern cut metal with biased vias using conventional techniques, at least in part because the cut metal pattern should have a curved opening 820 that is difficult to form and use.

[0084] However, as shown in Figure 20B, in the embodiment of this disclosure where the via 914 is self-aligned with the line ends of the conductive layer 934, the cut metal pattern can have substantially rectangular openings 920. This facilitates the formation of biased vias 914a, 914b while avoiding the difficulties associated with curved metal cut openings.

[0085] This disclosure provides methods and apparatus in various embodiments, wherein conductive vias are self-aligned relative to the wire ends of conductors, thereby helping to reduce the distance or gap that can be achieved between patterned components of an integrated circuit. In some embodiments, the vias can be formed prior to a dicing metal process that selectively removes a portion of the conductor, thereby forming the wire ends of the conductors aligned with the vias. The dicing process can be performed using a single dicing metal pattern or mask. The reduced use of masks reduces production costs and time compared to conventional techniques. Furthermore, the methods and apparatus provided in this disclosure can alleviate the via-to-metal wire end surround budget and the via-to-dicing metal spacing budget.

[0086] According to one embodiment, a method includes forming a first via on a conductive layer. A mask is formed over the conductive layer and has an opening that covers a portion of the conductive layer and at least partially covers the first via. The first via is aligned with the first line end of the conductive layer by selectively removing a portion of the conductive layer to form a first line end of the conductive layer.

[0087] According to another embodiment, a method is provided, comprising forming a conductive via on a conductive layer. The conductive layer is disposed on the source or drain region of a transistor with a gate fully surrounding it. A mask is formed over the conductive layer and has an opening that covers a portion of the conductive layer and at least partially covers the conductive via. The conductive layer is separated into a first segment and a second segment by selectively removing a portion of the conductive layer, and the conductive via is aligned with the end of the first segment of the conductive layer and has the same shape.

[0088] According to yet another embodiment, a device includes a first segment of a conductive layer, the first segment terminating at a curved end. A second segment of the conductive layer is aligned with the first segment and separated by a gap. A conductive via is disposed on the first segment of the conductive layer, the outer periphery of the conductive via being aligned with and having the same shape as the curved end of the first segment of the conductive layer.

[0089] The foregoing disclosure outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0090] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the scope of the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents enjoyed by such claims. Therefore, the scope of the claims is not limited by this disclosure. [Simplified Explanation of the Diagram]

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figures 1 through 3 are cross-sectional views illustrating methods of manufacturing apparatus according to some embodiments of this disclosure. Figure 4A is a top view illustrating a cut metal pattern or mask used in the methods shown in Figures 1 through 3 according to some embodiments, and Figure 4B is a top view illustrating the effective area of ​​the cut metal pattern or mask according to some embodiments. Figure 5A is a top view and Figure 5B is a side view illustrating the alignment of a via with a first segment of a conductive layer after performing the methods shown in Figures 1 through 3 according to some embodiments. Figures 6 through 17D illustrate methods of manufacturing a semiconductor device having self-aligned vias according to some embodiments of this disclosure. Figure 18A illustrates a comparative example of the effect of overlap offset between through-holes and cut metal patterns, and Figure 18B illustrates the effect of overlap offset between through-holes and cut metal patterns according to embodiments of the present disclosure. Figure 19A illustrates a comparative example of the spacing between through-holes, and Figure 19B illustrates the spacing between through-holes obtainable according to embodiments of the present disclosure. Figure 20A illustrates a comparative example of forming offset through-holes, and Figure 20B illustrates the formation of offset through-holes according to embodiments of the present disclosure. [Biomaterial Storage]

[0092] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor device, comprising: A first segment of a conductive layer, the first segment terminating at a curved end; a second segment of the conductive layer, the second segment aligned with the first segment and spaced apart by a gap; and a conductive via on the first segment of the conductive layer, an outer periphery of the conductive via aligned with the curved end of the first segment of the conductive layer and having the same shape, wherein the conductive layer and the conductive via comprise different conductive materials with different etching selectivity.

2. The semiconductor device as claimed in claim 1, further comprising: A gate-surround transistor having a source region or a drain region, wherein the first segment of the conductive layer is contacted and electrically connected to the source region or the drain region.

3. The semiconductor device as claimed in claim 2, further comprising: A first dielectric layer is disposed on the gate-surrounding transistor, wherein the conductive via extends through the first dielectric layer.

4. The semiconductor device as claimed in claim 3, further comprising: A second dielectric layer is disposed on the gate-surround transistor, the second dielectric layer covers the gap between the first segment and the second segment of the conductive layer, and the second dielectric layer is in contact with the first dielectric layer.

5. A method of manufacturing a semiconductor device, comprising: forming a first via on a conductive layer; forming a mask on the conductive layer, the mask having an opening that covers a portion of the conductive layer and at least partially covers the first via; and forming a first line end of the conductive layer, wherein the portion of the conductive layer is selectively removed by using the mask and the first via as an etch mask, the first via being aligned with the first line end of the conductive layer.

6. A method of manufacturing a semiconductor device as claimed in claim 5, wherein forming the mask on the conductive layer includes forming a hard mask layer on the conductive layer.

7. A method of manufacturing a semiconductor device as claimed in claim 5, wherein selectively removing the portion of the conductive layer comprises etching the conductive layer with an etchant.

8. A method for manufacturing a semiconductor device as claimed in claim 5, wherein the first via is a dummy via, the method for manufacturing the semiconductor device further comprising: A cavity is formed by removing the dummy via after the first line end of the conductive layer is formed; A conductive via is formed in the cavity, and the conductive via is aligned with the first line end of the conductive layer.

9. A method for manufacturing a semiconductor device, comprising: A conductive via is formed on a conductive layer disposed on a source region or a drain region of a gate-surround transistor; a shield is formed on the conductive layer having an opening that covers a portion of the conductive layer; and the conductive layer is divided into a first segment and a second segment, and by selectively removing the portion of the conductive layer, the conductive via is aligned with an end of the first segment of the conductive layer, and the conductive via and the end of the first segment of the conductive layer have the same shape.

10. The method of manufacturing a semiconductor device as described in claim 9, further comprising: A dielectric layer is formed on the gate-surround transistor, and the opening of the shield covers a portion of the dielectric layer; And selectively remove that portion of the dielectric layer.

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