Package, package apparatus, and method for fabricating package

Abstract

A package includes a substrate comprising a cavity, a first integration device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects, a second integration device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects, and a plurality of wire connections coupled to the first integration device and the second integration device, wherein the plurality of wire connections are located above the cavity of the substrate.

Description

[Technical Field]

[0001] This patent application claims priority and benefit to non-provisional application S / N. 17 / 213,875 filed on March 26, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein in their entirety and for all applicable purposes.

[0002] The various features relate to a package including an integrated device, and more particularly to a package including an integrated device and a substrate. [Previous Technology]

[0003] Figure 1 illustrates a package 100 including a substrate 102, an integrated device 104, and an integrated device 106. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. There has always been a need to provide packages with better performance. [Summary of the Invention]

[0004] Various features relate to packaging including integrated devices, and more particularly to packaging including integrated devices and substrates.

[0005] One example provides a package including a substrate containing a cavity, a first integrated device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects, and a plurality of wire connections coupled to the first integrated device and the second integrated device, wherein the plurality of wire connections are located on the cavity of the substrate.

[0006] Another example provides an apparatus comprising a substrate including a cavity, a first integration device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects, a second integration device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects, and means for wire interconnection coupled to the first integration device and the second integration device, wherein the means for wire interconnection is located above the cavity of the substrate.

[0007] Another example provides a method for manufacturing a package. The method provides a substrate including a cavity. The method couples a first integrated device to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects. The method couples a second integrated device to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects. The method forms a plurality of wire connections between the first integrated device and the second integrated device, wherein the plurality of wire connections are located above the cavity of the substrate.

Implementation Method

[0023] In the following description, specific details are provided to provide a thorough understanding of the various forms of this invention. However, those skilled in the art will understand that these forms can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these forms in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these forms of this invention.

[0024] This application describes a package including a substrate comprising a cavity, a first integrated device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects, and a plurality of wire connections coupled to the first integrated device and the second integrated device, wherein the plurality of wire connections are located over the cavity of the substrate. The first integrated device includes a first row of a plurality of pads and a second row of a plurality of pads. The second integrated device includes a first row of a plurality of pads and a second row of a plurality of pads. The plurality of wire connections include first plurality of wire connections coupled to (i) the first row of a plurality of pads of the first integrated device and (ii) the first row of a plurality of pads of the second integrated device. The plurality of wire connections include second plurality of wire connections coupled to (i) the second row of a plurality of pads of the first integrated device and (ii) the second row of a plurality of pads of the second integrated device. The use of multiple wire connections facilitates higher density interconnects between integrated devices. Multiple wire connections can help provide shorter and more direct electrical paths between integrated devices. The package may include a bottom filler and / or encapsulation layer. The bottom filler and / or encapsulation layer can help provide strong structural integrity for the integrated devices and the substrate, which in turn helps to provide a package including reliable interconnects between two or more integrated devices. An exemplary package including wire connections between integrated devices.

[0025] Figure 2 illustrates a cross-sectional view of a package 200 including a plurality of lead connections between integrated devices. The package 200 may be coupled to a board (e.g., a printed circuit board (PCB)) via a plurality of solder interconnects 280. The package 200 provides a package with high-density interconnects between integrated devices.

[0026] As shown in FIG2, the package 200 includes a substrate 202, a first integration device 204, a second integration device 206, a plurality of wire bonds 210, a bottom filler 244, a bottom filler 264, and an encapsulation layer 208.

[0027] As will be further described below, a plurality of lead connections 210 may be coupled to integrated devices (e.g., 204, 206) such that when at least one electrical signal (e.g., a first electrical signal, a second electrical signal) travels between at least two integrated devices (e.g., 204, 206), the electrical signal bypasses the substrate 202. However, the at least one electrical signal may travel through at least one electrical path defined by the interconnects of the package, the integrated devices, and / or the substrate.

[0028] The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226. The substrate 202 also includes a cavity 209 extending through the substrate 202. The cavity 209 may extend through at least one dielectric layer 220, the first solder resist layer 224, and the second solder resist layer 226. The cavity 209 may have any shape (e.g., rectangular, square). The substrate 202 may include more than one cavity 209. As will be further described below, the cavity 209 may be at least partially filled (e.g., completely filled) with an encapsulation layer 208 and / or other materials. In some implementations, the cavity 209 of the substrate 202 may be a region or void without the dielectric layer 220 and / or the plurality of interconnects 222 of the substrate 202. The substrate 202 may be considered to have a cavity 209 even if the cavity 209 is subsequently filled with one or more materials. As will be further described below, the cavity 209 in the substrate 202 may allow a plurality of wire connections 210 to be formed between integrated devices (e.g., 204, 206). The plurality of wire connections 210 may be located above the cavity 209 (e.g., above or below the cavity 209, depending on whether above or below can be arbitrarily defined). In some implementations, the plurality of wire connections 210 may be located at least partially within the cavity 209 of the substrate 202.

[0029] A plurality of interconnects 222 may be configured to provide at least one electrical path to and / or from the board. A plurality of interconnects 222 may be configured to provide at least one electrical path to at least one integrated device (e.g., 204, 206). A plurality of interconnects 222 may be configured to provide at least one electrical path (e.g., electrical connection) between two or more integrated devices (e.g., 204, 206). The plurality of interconnects 222 may have a first minimum pitch and a first minimum linewidth and spacing (L / S). In some implementations, the first minimum linewidth and spacing (L / S) of the plurality of interconnects 222 is in the range of about 9 / 9 to 12 / 12 micrometers (µm) (e.g., a minimum linewidth of about 9-12 micrometers (µm) and a minimum spacing of about 9-12 micrometers (µm)). Different implementations may use different substrates. The substrate 202 may be a laminated substrate, a coreless substrate, an organic substrate, and / or a cored substrate (e.g., including a core layer). In some implementations, the at least one dielectric layer 220 may include a core layer and / or a prepreg layer. The at least one dielectric layer 220 may have a dielectric constant in the range of about 3.5-3.7. Examples of substrate fabrication are further described below in Figures 10A–10C. As will be further described below, in some implementations, the substrate 202 may be fabricated using a modified semi-additive process (mSAP) or a semi-additive process (SAP).

[0030] A first integration device 204 is coupled to a first surface (e.g., the top surface) of a substrate 202. In some implementations, the first integration device 204 is coupled to the substrate 202 via a plurality of solder interconnects 240 and / or a plurality of solder interconnects 242. The plurality of solder interconnects 240 and / or the plurality of solder interconnects 242 may be coupled to a plurality of interconnects 222 of the substrate 202. The plurality of solder interconnects 240 may help provide a higher density of interconnects between the first integration device 204 and the substrate 202. The plurality of solder interconnects 240 may be optional. Thus, the first integration device 204 may be coupled to the substrate 202 via a plurality of solder interconnects 242. A portion of the first integration device 204 may be located above the cavity 209. The front side of the first integration device 204 may face the substrate 202. The first integration device 204 includes a plurality of pads 241. As will be further described below, a plurality of pads 241 may be arranged into multiple rows of pads, including a first row of pads and a second row of pads. The first row of pads may be staggered relative to the second row of pads, and vice versa. Note that the plurality of pads 241 may include more than two rows of pads.

[0031] The second integration device 206 is coupled to a first surface of the substrate 202. In some implementations, the second integration device 206 is coupled to the substrate 202 via a plurality of solder interconnects 260 and / or a plurality of solder interconnects 262. The plurality of solder interconnects 260 and / or a plurality of solder interconnects 262 may be coupled to a plurality of interconnects 222. The plurality of solder interconnects 260 may help provide a higher density of interconnects between the second integration device 206 and the substrate 202. The plurality of solder interconnects 260 may be optional. Thus, the second integration device 206 may be coupled to the substrate 202 via a plurality of solder interconnects 262. A portion of the second integration device 206 may be located above the cavity 209. The front side of the second integration device 206 may face the substrate 202. The second integration device 206 includes a plurality of pads 261. As will be further described below, the plurality of pads 261 may be arranged in multiple rows of pads, including a first row of pads and a second row of pads. The first row of pads can be staggered relative to the second row of pads, and vice versa. Note that a plurality of pads 261 may include more than two rows of pads.

[0032] A plurality of wire bonds 210 are coupled to a first integrated device 204 and a second integrated device 206. For example, the plurality of wire bonds 210 are coupled to (i) a plurality of pads 241 of the first integrated device 204 and (ii) a plurality of pads 261 of the second integrated device 206. In some implementations, each of the plurality of wire bonds 210 may have a diameter of at least 15 micrometers. The plurality of wire bonds 210 may have different heights and / or distances from the surfaces of the integrated devices (e.g., 204, 206), and the plurality of pads 241 and / or the plurality of pads 261 may have different vertical offsets (e.g., different maximum heights and / or maximum vertical offsets). The use of a plurality of wire bonds 210 with different heights and / or vertical offsets allows for high-density interconnects between the first integrated device 204 and the second integrated device 206. In some implementations, the plurality of wire bonds 210 may have a density of at least 40 wire bonds per millimeter (e.g., 40 interconnects per millimeter) between the first integration device 204 and the second integration device 206. The number of interconnects per millimeter provided by the plurality of wire bonds 210 may be greater than the number of interconnects per millimeter provided in the substrate 202. This can be achieved even though one or more wire bonds from the plurality of wire bonds 210 have a minimum diameter of 15 micrometers, while the interconnects in the substrate 202 may have a first minimum line width and pitch (L / S) in the range of approximately 9 / 9 to 12 / 12 micrometers (µm) (e.g., a minimum line width of approximately 9-12 micrometers (µm) and a minimum pitch of approximately 9-12 micrometers (µm)). Therefore, despite the thicker dimensions of the wire bonds 210, the use of wire bonds with different heights and / or offsets allows for more interconnects per millimeter than the interconnects in the substrate 202. Furthermore, the plurality of wire connections 210 provide a shorter and more direct electrical path between the first integrated device 204 and the second integrated device 206. Shorter and more direct electrical paths between integrated devices can result in better integrated device and / or package performance. Examples of wire connection 210 configurations and arrangements are further described below in at least Figures 4-6.

[0033] As shown in FIG. 2, bottom filler 244 is located between the first integration device 204 and the substrate 202. Similarly, bottom filler 264 is located between the second integration device 206 and the substrate 202. Bottom filler 244 may surround a plurality of solder interconnects (e.g., 240) and / or a plurality of solder interconnects (e.g., 242). Bottom filler 264 may surround a plurality of solder interconnects (e.g., 260) and / or a plurality of solder interconnects (e.g., 262). Bottom filler 244 and / or 264 may be located at other locations, such as within cavity 209 and / or above the first integration device 204 and the second integration device 206. Bottom filler 244 and bottom filler 264 may be part of the same bottom filler or separate bottom fillers.

[0034] The bottom filler 244 and / or 264 helps provide structural stability for the package 200. Specifically, the bottom filler 244 and / or 264 helps provide a strong and reliable mechanical coupling between the first integrated device 204, the second integrated device 206, and the substrate 202. By helping to structurally hold the first integrated device 204 and the second integrated device 206 together with the substrate 202, the bottom filler 244 and / or 264 helps ensure a strong and reliable electrical connection (e.g., an electrical path) between the first integrated device 204 and the second integrated device 202.

[0035] Different implementations may provide underfillers 244 and / or 264 with different materials and / or properties. Underfiller 244 and / or 264 may include one or more underfillers (e.g., individual underfiller layers). For example, underfiller 244 and / or 264 may be formed by a single formation of the underfiller. In some implementations, underfiller 244 and / or 264 may represent several portions and / or layers of underfiller formed and cured separately. In some implementations, underfiller 244 and / or 264 may include a viscosity of about 10-30 Pa·s. These viscosity values ​​may be for a temperature of about 80 degrees Celsius. In some implementations, underfiller 244 and / or 264 may include a coefficient of thermal expansion (CTE) of about 10-15 ppm. In some implementations, underfiller 244 and / or 264 may include a filler representing about 50-90% of the weight of underfiller 244 and / or 264. As will be further described below, underfill 244 and / or 264 may have capillary properties, allowing underfill 244 and / or 264 to fill small spaces between the integrated device and / or substrate. For example, the aforementioned viscosity values ​​of underfill 244 and / or 264 allow underfill 244 and / or 264 to travel and fill between small spaces between the integrated device and / or substrate. Underfill 244 and / or 264 and / or other materials that may be located around the weld post and between the integrated device and substrate are further described below.

[0036] An encapsulation layer 208 is located on and formed on the substrate 202. The encapsulation layer 208 may include molding compound, resin, epoxy resin, and / or polymer. The encapsulation layer 208 may be a device for encapsulation. The encapsulation layer 208 may at least partially encapsulate the first integrated device 204 and / or the second integrated device 206. The encapsulation layer 208 may be located in a cavity 209 of the substrate 202. The encapsulation layer 208 may at least partially fill the cavity 209 of the substrate 202. Note that even if all portions of the cavity 209 are filled with the encapsulation layer 208 and / or other materials, the substrate 202 may still be considered to have a cavity 209. The encapsulation layer 208 may help provide structural stability for the package 200.

[0037] The integrated device (e.g., 204, 206) may include a die (e.g., a semiconductor bare die). The integrated device may include a logic die, a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light-emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, a power management processor (e.g., a power management integrated circuit (PMIC)), and / or combinations thereof. The integrated device (e.g., 204, 206) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0038] FIG3 illustrates a plan view of a package 200 including a plurality of wire connections between integrated devices. The package 200 includes a substrate 202, a cavity 209, a first integrated device 204, a second integrated device 206, and a plurality of wire connections 210. The first integrated device 204 and the second integrated device 206 are coupled to the substrate 202. The plurality of wire connections 210 are coupled to the first integrated device 204 and the second integrated device 206. The plurality of wire connections 210 are located on the cavity 209 of the substrate 202. A portion of the first integrated device 204 and / or a portion of the second integrated device 206 may be located on the cavity 209 of the substrate 202. As mentioned above, the cavity 209 may be at least partially filled with an encapsulation layer and / or other materials.

[0039] Figure 4 illustrates a close-up plan view of a plurality of wire connections coupled to pads of an integrated device. As shown in Figure 4, a plurality of wire connections 210 are coupled to a first integrated device 204 and a second integrated device 206. The plurality of wire connections 210 includes wire connections 210a, 210b, 210c, 210d, 210e, and 210f. Wire connections 210a, 210b, and 210c may be part of a first plurality of wire connections. Wire connections 210d, 210e, and 210f may be part of a second plurality of wire connections.

[0040] The first integration device 204 includes a plurality of pads 241 arranged in rows of pads. The plurality of pads 241 includes pads 241a, 241b, 241c, 241d, 241e, and 241f. Pads 241a, 241b, and 241c may be part of a first row of the plurality of pads for the first integration device 204. Pads 241d, 241e, and 241f may be part of a second row of the plurality of pads for the first integration device 204. The second row of the plurality of pads may intersect with the first row of the plurality of pads for the first integration device 204, or vice versa. The first row of the plurality of pads may be an inner row of pads. The second row of the plurality of pads may be an outer row of pads.

[0041] The second integration device 206 includes a plurality of pads 261 arranged in rows of pads. The plurality of pads 261 includes pads 261a, 261b, 261c, 261d, 261e, and 261f. Pads 261a, 261b, and 261c may be part of a first row of the plurality of pads for the second integration device 206. Pads 261d, 261e, and 261f may be part of a second row of the plurality of pads for the second integration device 206. The second row of the plurality of pads may interleave with the first row of the plurality of pads for the second integration device 206, or vice versa. The first row of the plurality of pads may be an inner row of pads. The second row of the plurality of pads may be an outer row of pads. The inner and outer rows of pads may be arbitrarily defined. For example, an outer pad row can be a pad row that is closer to the edge of the integrated device (e.g., the edge of the integrated device facing another integrated device) than an inner pad row. An inner pad row can be a pad row that is closer to the center of the integrated device than an outer pad row. In some implementations, the integrated device may include several inner pad rows.

[0042] A first plurality of lead joints (including lead joints 210a, 210b and 210c) are coupled to (i) a first row of a plurality of pads of a first integration device 204 (including pads 241a, 241b and 241c) and (ii) a first row of a plurality of pads of a second integration device 206 (including pads 261a, 261b and 261c).

[0043] A second plurality of lead joints (including lead joint 210d, lead joint 210e and lead joint 210f) are coupled to (i) a second row of a plurality of pads of the first integration device 204 (including pads 241d, pads 241e and pads 241f) and (ii) a second row of a plurality of pads of the second integration device 206 (including pads 261d, pads 261e and pads 261f).

[0044] Figure 4 illustrates two rows of pads for each integrated device. However, different implementations may have different numbers of rows of pads coupled to a plurality of lead bonds. For example, the first integrated device 204 may include a third row of a plurality of pads interleaved with the first row of a plurality of pads, while the second integrated device 206 may include a third row of a plurality of pads interleaved with the first row of a plurality of pads. The third row of the plurality of pads in the first integrated device 204 and the third row of the plurality of pads in the second integrated device 206 may be coupled to a third plurality of lead bonds. The third plurality of lead bonds may have a different vertical offset than the first plurality of lead bonds and the second plurality of lead bonds.

[0045] As will be further illustrated and described below in at least FIG6, the vertical offset (e.g., maximum vertical offset) of the surface of the first plurality of lead bonding distance (plural) integration devices may be different from the vertical offset (e.g., maximum vertical offset) of the surface of the second plurality of lead bonding distance (plural) integration devices.

[0046] The use of staggered pad configurations and lead joints with different vertical offsets facilitates the provision of high-density electrical connections between integrated devices. For example, the configuration shown in Figure 4 illustrates a configuration that accommodates at least 40 lead joints per millimeter. The plurality of lead joints 210 may have lead joints with a minimum diameter of 15 micrometers. In some implementations, the configuration shown accommodates at least 50 lead joints per millimeter. In some implementations, the configuration shown accommodates 40-60 lead joints per millimeter (e.g., 40, 41, ... 59, 60 lead joints per millimeter). The high-density electrical connections provided by the plurality of lead joints 210 can facilitate the provision of more than 200 channels (e.g., electrical connections) for signal, power, and ground between two integrated devices, each with a minimum length and / or minimum width of approximately 4 millimeters.

[0047] Figure 5 illustrates a plan view of how wire bonds are coupled to pads of an integrated device. Figure 5 may be a close-up view of the wire bond connection shown in Figure 4. Wire bond 210a is coupled to pads 241a and 261a. Wire bond 210b is coupled to pads 241b and 261b. Wire bond 210d is coupled to pads 241d and 261d. Wire bond 210a may be partially located on pads 241d and 261d. For example, wire bond 210a may at least partially and perpendicularly overlap with pads 241d and 261d. Wire bond 210b may be partially located on pads 241d and 261d. For example, wire bond 210b may at least partially and perpendicularly overlap with pads 241d and 261d.

[0048] In some implementations, the first row of pads and the second row of pads may have a center-to-center pitch of approximately 61 micrometers (e.g., row-to-row pitch (A)). In some implementations, the first row of pads may have a center-to-center pitch (B) of approximately 40.5 micrometers between pads (e.g., pads 241a and 241b). In some implementations, the second row of pads may have a center-to-center pitch (B) of approximately 40.5 micrometers between pads (e.g., pads 241d and 241f). In some implementations, the staggered pitch (C) (e.g., the center-to-center pitch between pads 241a and 241d) is approximately 20.25 micrometers. However, different implementations may use different scales for various pitches.

[0049] Figure 6 illustrates a cross-sectional view of how wire bonds are coupled to pads of an integrated device. Figure 6 illustrates that different wire bonds may have different vertical offsets (e.g., maximum vertical offsets) from the surface of the integrated device. For example, wire bond 210a may be vertically offset (E) (e.g., vertical distance, maximum vertical distance) of approximately 55 micrometers from the surface of the integrated device (e.g., 204, 206). Other wire bonds from the plurality of wire bonds 210 (such as wire bonds 210b and / or wire bonds 210c) may be vertically offset at a similar height. In other instances, wire bond 210d may be vertically offset (D) (e.g., vertical distance, maximum vertical distance) of approximately 35 micrometers from the surface of the integrated device (e.g., 204, 206). Other wire bonds from the plurality of wire bonds 210 (such as wire bonds 210e and / or wire bonds 210f) may be vertically offset at a similar height. Wire bond 210a may be at least partially located above wire bond 210d. By applying more interconnects per millimeter between integrated devices, using different vertical offsets for different lead bonding sets helps to provide high-density interconnects between integrated devices.

[0050] FIG. 7 illustrates a package 700 including a plurality of wire connections between integrated devices. Package 700 is similar to package 200 of FIG. 2 and thus includes the same or similar components as package 200. As shown in FIG. 7, package 700 includes a substrate 202, a first integrated device 204, a second integrated device 206, a plurality of wire connections 210, and an encapsulation layer 708. Encapsulation layer 708 may be the same as, similar to, or different from encapsulation layer 208. Encapsulation layer 708 may include molded bottom filler (MUF). Encapsulation layer 708 may be located on substrate 202 and in cavity 209 of substrate 202. Encapsulation layer 708 may encapsulate the first integrated device 204 and / or the second integrated device 206. Encapsulation layer 708 may encapsulate a plurality of solder interconnects 240, a plurality of solder interconnects 242, a plurality of solder interconnects 260, a plurality of solder interconnects 262 and / or a plurality of wire bonds 210.

[0051] Note that the number of lead connections shown in Figures 2-7 is exemplary. Different implementations may have different numbers of lead connections coupled to the integrated device.

[0052] As mentioned above, the bottom filler 244, bottom filler 264, encapsulation layer 208 and / or encapsulation layer 708 may have specific properties to ensure that the space around the weld post interconnect and the space between the integrated device and the substrate are properly filled, thereby ensuring a strong and secure connection between the integrated device and the substrate.

[0053] For example, the underfill (e.g., 244, 264) may include a capillary underfill with good flowability. The capillary underfill (CUF) may comprise a polymer composite of silica particles and epoxy liquid. One property of the capillary underfill is its good flowability upon heating, allowing it to flow into the narrow space between the integration device and the substrate under the drive of capillary forces. The capillary underfill may have sufficient silica filler to obtain a final cured material with low CTE. The capillary underfill may be of liquid type, typically frozen below -40 degrees Celsius, and thawed and heated before application.

[0054] The encapsulation layer 208 may include an encapsulation material and / or an epoxy molding compound (EMC) used to cover the entire package after capillary bottom filler application so that it can protect the entire package. The encapsulation layer 208 may include solid particles that can be stored at room temperature. The encapsulation layer 208 may be heated into a liquid and processed under transfer molding flow to cover the integrated device.

[0055] In some implementations, a molded underfill (MUF) can be used instead of the underfill (e.g., 244, 264) and / or the encapsulation layer 208, or in combination with the underfill 208 and / or the encapsulation layer 508. The molded underfill can be a combination of capillary underfill (e.g., underfill 244) and EMC (e.g., encapsulation layer 208). The material properties and application form of the molded underfill are the same as or similar to those of general EMC, but it has a finer filler size, so it can be pressed into the gap between the integration device and the substrate during the transfer molding process. In this way, the molded underfill can replace the capillary underfill and reduce the number of process steps.

[0056] EMC and MUF can have much higher filler loadings, up to 90 wt%, thus the properties of the cured material are superior to those of capillary underfills with lower CTE and higher modulus. In some implementations, MUF can be used instead of CUF if an encapsulation layer is required. For packages without an encapsulation layer, CUF can be used alone. Table 1 below illustrates exemplary properties of various materials, underfills, and encapsulation layers. Note that the values ​​for materials are exemplary. Different materials may have different properties. Furthermore, the values ​​shown in Table 1 are not limiting. Capillary bottom packing (CUF) Epoxy molding compounds (EMC) Molded bottom filler (MUF) Polyimide (PI) or PBO dielectric film Filler load 50~70 wt% Up to 90 wt% Up to 90 wt% 0% Infill size 0.1~3 μm Top cut to up to 100 μm Top cut 20 μm N / A Form before curing liquid solid solid liquid Curing temperature 150C 180C 180C 250-390C Glass transition temperature of cured materials 120~150C 150~160C 150~160C 250~320C Modulus of cured material 5~10 GPa 12-20 GPa 12-20 GPa 2~3GPa CTE Curing Materials 20~30 ppm / C 1~5 ppm / C 1~5 ppm / C 30-80 ppm / C Table 1 - Exemplary properties of various materials, underfills, and / or encapsulations

[0057] Note that encapsulation layer 708 may be applied to package 200 of FIG. 2 or any package described herein. Similarly, note that encapsulation layer 208 may be applied to package 700 of FIG. 7 or any package described herein. Note that encapsulation layers (e.g., 208, 708) may be formed of one or more encapsulation layers. Note that each integrated device may include additional electrical paths between each other and / or substrate 202. Note that the electrical signal paths shown and / or described herein are exemplary and / or conceptual. Different implementations may use different paths for electrical signals. Furthermore, electrical signals and / or electrical paths may travel through different types of interconnects (e.g., vias, traces, pads, pillars), solder interconnects, and / or components (e.g., passive devices). Thus, for example, in some implementations, electrical signals traveling between integrated devices may travel through at least one intermediary component (e.g., passive device, capacitor) between integrated devices. The paths shown and / or described for electrical signals may also be applied to power and / or ground. It is also noted that more than one set of multiple wire bonds can be used to facilitate bypassing the substrate. Multiple wire bonds can be used to facilitate electrical coupling between more than two integrated devices. For example, a first integrated device can be configured to be electrically coupled to a second integrated device via a first set of multiple wire bonds. A first integrated device can be configured to be electrically coupled to a third integrated device via a second set of multiple wire bonds. The terms "first surface" and "second surface" regarding the substrate are arbitrary and can refer to any surface of the substrate. For example, the first surface of the substrate can be the bottom surface of the substrate, and the second surface of the substrate can be the top surface of the substrate. In another example, the first surface of the substrate can be the top surface of the substrate, and the second surface of the substrate can be the bottom surface of the substrate. Exemplary steps for manufacturing integrated devices with bond post interconnects.

[0058] Figures 8A-8B illustrate exemplary steps for providing or manufacturing an integrated device with weld bar interconnections. In some implementations, the steps of Figures 8A-8B may be used to provide or manufacture the integrated device of Figure 2 (e.g., 204, 206) or any integrated device described in this case.

[0059] It should be noted that the processes in Figures 8A-8B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the integrated device. In some implementations, the order of the procedures can be changed or modified. In some implementations, one or more procedures can be substituted or replaced without departing from the scope of this invention. Different implementations can manufacture the integrated device differently.

[0060] As shown in FIG8A, stage 1 illustrates the state after the integration device 204 is provided. The integration device 204 may include a die (e.g., a bare semiconductor die). The integration device 204 may include a substrate (e.g., a silicon substrate) and a plurality of transistors (e.g., active devices). The integration device 204 may include a plurality of pads 241.

[0061] Stage 2 illustrates the state after a seed layer 811 has been formed on the front side of the integrated device 204. The seed layer 811 may include a metal layer. The seed layer 811 may be deposited on the integrated device 204. A plating process may be used to form the seed layer 811.

[0062] Stage 3 illustrates the state after the photoresist layer 800 is formed on the seed layer 811. The photoresist layer 800 can be deposited on the seed layer 811.

[0063] Stage 4 illustrates the state after the photoresist layer 800 is patterned, thereby creating at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811.

[0064] As shown in FIG8B, stage 5 illustrates the state after a plurality of bond interconnects 830 and a plurality of solder interconnects 832 are formed on the seed layer 811 via openings 801 in the photoresist layer 800. The plurality of bond interconnects 830 can be formed on the seed layer 811 via a plating process. The plurality of solder interconnects 832 can be formed on the plurality of bond interconnects 830 via a deposition process.

[0065] Stage 6 illustrates the state after the photoresist layer 800 has been removed and a portion of the seed layer 811 has been removed (e.g., etched). Removing the photoresist layer 800 may include stripping the photoresist layer 800.

[0066] Stage 7 illustrates the state after a reflow soldering process in which a plurality of solder interconnects 832 are coupled (e.g., bonded) to a plurality of pillar interconnects 830. Stage 7 may illustrate an integrated device (e.g., 204, 206) having pillar interconnects that can be coupled to a substrate. The plurality of pillar interconnects 830 may represent a plurality of pillar interconnects 240. The plurality of solder interconnects 832 may represent a plurality of solder interconnects 242. A seed layer 811 may be considered as part of the pillar interconnects 830. An exemplary flowchart of a method for manufacturing an integrated device including pillar interconnects.

[0067] In some implementations, manufacturing an integrated device with solder pillar interconnects includes several procedures. FIG9 illustrates an exemplary flowchart of a method 900 for providing or manufacturing an integrated device with solder pillar interconnects. In some implementations, method 900 of FIG9 may be used to provide or manufacture the integrated device of FIG2 described in this document (e.g., 204, 206). However, method 900 may be used to provide or manufacture any of the integrated devices described in this document.

[0068] It should be noted that the method of Figure 9 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing an integrated device with weld post interconnections. In some implementations, the order of the procedures can be changed or modified.

[0069] The method (at 905) provides an integration device (e.g., 204, 206). Phase 1 of FIG8A illustrates and describes the provided first integration device 204. The first integration device 204 may include a die having an active device (such as a transistor). The integration device may include a plurality of pads.

[0070] The method (at 910) forms a seed layer (e.g., 811) over the front side of the integrated device. The seed layer 811 may include a metal layer. The seed layer 811 may be deposited over the integrated device 204. A plating process may be used to form the seed layer 811. Stage 2 of FIG8A illustrates and describes an example of forming a seed layer.

[0071] The method (at 915) forms a photoresist layer (e.g., 800) on a seed layer (e.g., 811). The photoresist layer 800 may be formed and patterned on the seed layer 811. The photoresist layer 800 may be deposited on the seed layer 811 and patterned to create at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811. Stages 3-4 of Figure 8A illustrate and describe examples of forming and patterning a photoresist layer on a seed layer.

[0072] This method (at 920) forms a plurality of solder interconnects (e.g., 830) and / or solder interconnects (e.g., 832) on a seed layer (e.g., 811) via an opening 801 in a photoresist layer (e.g., 800). The plurality of solder interconnects can be formed on the seed layer via a deposition process. The plurality of solder interconnects can be formed on the seed layer via a plating process. The plurality of solder interconnects can be formed on the plurality of solder interconnects via a deposition process. Stage 5 of Figure 8B illustrates and describes an example of forming a plurality of solder interconnects and / or a plurality of solder interconnects.

[0073] This method (at 925) removes a photoresist layer (e.g., 800). Removing the photoresist layer may include stripping the photoresist layer. Stage 6 of Figure 8B illustrates an example of photoresist layer removal. In some implementations, a partial seed layer 811 may also be removed (at 925). An etching process may be used to remove the partial seed layer. Stage 6 of Figure 8B illustrates and describes an example of the partial seed layer being removed. Note that the formation of the photoresist layer, solder interconnects, and / or solder interconnects as described at 915, 920, and 925, and the removal of the photoresist layer, may be repeated.

[0074] This method (at 930) performs a reflow soldering process that couples (e.g., joins) a plurality of solder interconnects (e.g., 832) to a plurality of solder pillar interconnects (e.g., 830). Stage 7 of Figure 8B illustrates and describes an example of a reflow soldering process.

[0075] In some implementations, the integrated device is part of a wafer, and a dicing process can be performed to cut the wafer into individual integrated devices. Method 900 can be used to manufacture any integrated device described in this case. Exemplary steps for manufacturing a substrate.

[0076] In some implementations, manufacturing the substrate includes several processes. Figures 10A-10C illustrate exemplary processes for providing or manufacturing the substrate. In some implementations, the processes of Figures 10A-10C can be used to provide or manufacture the substrate 202 of Figure 2. However, the processes of Figures 10A-10C can be used to manufacture any substrate described in this case.

[0077] It should be noted that the processes in Figures 10A-10C can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this invention.

[0078] As shown in FIG10A, stage 1 illustrates the state after a carrier 1000 is provided and a metal layer is formed on the carrier 1000. The metal layer can be patterned to form interconnects 1002. The metal layer and interconnects can be formed using plating and etching processes.

[0079] Stage 2 illustrates the state after a dielectric layer 1020 has been formed over the carrier 1000 and interconnect 1002. The dielectric layer 1020 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0080] Stage 3 illustrates the state after a plurality of cavities 1010 have been formed in the dielectric layer 1020. The plurality of cavities 1010 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0081] Stage 4 illustrates the state after interconnects 1012 are formed in and over the dielectric layer 1020 (including in and over the plurality of cavities 1010). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0082] Stage 5 illustrates the state after another dielectric layer 1022 is formed on top of dielectric layer 1020. Dielectric layer 1022 can be made of the same material as dielectric layer 1020. However, different implementations may use different materials for the dielectric layer.

[0083] As shown in Figure 10B, stage 6 illustrates the state after a plurality of cavities 1030 have been formed in the dielectric layer 1022. The cavities 1030 can be formed using an etching process or a laser process.

[0084] Stage 7 illustrates the state after interconnects 1014 are formed in and over the dielectric layer 1022 (including in and over the plurality of cavities 1030). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0085] Stage 8 illustrates the state after another dielectric layer 1024 is formed on top of dielectric layer 1022. Dielectric layer 1024 can be made of the same material as dielectric layer 1020. However, different implementations may use different materials for the dielectric layer.

[0086] Stage 9 illustrates the state after a plurality of cavities 1040 have been formed in the dielectric layer 1024. The cavities 1040 can be formed using an etching process or a laser process.

[0087] As shown in FIG10C, stage 10 illustrates the state after interconnects 1016 are formed in and over dielectric layer 1024 (including in and over the plurality of cavities 1040). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0088] Some or all of interconnects 1002, 1012, 1014 and / or 1016 may define a plurality of interconnects 222 of substrate 202. Dielectric layers 1020, 1022, 1024 may be represented by at least one dielectric layer 220.

[0089] Stage 11 illustrates the state after the carrier 1000 is decoupled from the dielectric layer 220 (e.g., removed, ground away) to leave a substrate 202 including at least one dielectric layer 220 and a plurality of interconnects 222.

[0090] Stage 12 illustrates the state after the first solder mask 224 and the second solder mask 226 are formed on the substrate 202. The first solder mask 224 and the second solder mask 226 can be formed using a deposition process.

[0091] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or solid vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. An exemplary flowchart of a method for manufacturing a substrate is provided.

[0092] In some implementations, manufacturing the substrate includes several procedures. FIG11 illustrates an exemplary flowchart of a method 1100 for providing or manufacturing a substrate. In some implementations, the method 1100 of FIG11 can be used to provide or manufacture the substrate of FIG2. For example, the method of FIG11 can be used to manufacture substrate 202.

[0093] It should be noted that the method of FIG11 may combine one or more procedures to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the procedures may be changed or modified.

[0094] The method (at 1105) provides a carrier 1000. Different implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or a carrier strip. Phase 1 of Figure 10A illustrates and describes an example of the carrier provided.

[0095] The method (at 1110) forms a metal layer on a carrier 1000. This metal layer can be patterned to form interconnects. A plating process can be used to form the metal layer and interconnects. In some implementations, the carrier may include a metal layer. The metal layer on the carrier can be patterned to form interconnects (e.g., 1002). Phase 1 of Figure 10A illustrates and describes an example of a metal layer and interconnects formed on a carrier.

[0096] The method (at 1115) forms a dielectric layer 1020 over a carrier 1000 and an interconnect 1002. The dielectric layer 1020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Stages 2-3 of FIG10A illustrate and describe examples of forming a dielectric layer and forming cavities in the dielectric layer.

[0097] This method (at 1120) forms interconnects in and over the dielectric layer. For example, interconnect 1012 may be formed in and over the dielectric layer 1020. These interconnects may be formed using a plating process. Forming interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 4 of FIG10A illustrates and describes an example of forming interconnects in and over the dielectric layer.

[0098] The method (at 1125) forms a dielectric layer 1022 over the dielectric layer 1020 and these interconnects. The dielectric layer 1022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Stages 5-6 of Figures 10A-10B illustrate and describe examples of forming a dielectric layer and forming cavities in the dielectric layer.

[0099] The method (at 1130) forms interconnects in and / or on the dielectric layer. For example, interconnect 1014 may be formed. These interconnects may be formed using a plating process. Forming interconnects may include providing a patterned metal layer on and in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 7 of FIG10B illustrates and describes an example of forming interconnects in and on the dielectric layer.

[0100] This method can form additional dielectric layers and additional interconnects, as described at 1125 and 1130. Stages 8-10 of Figures 10B-10C illustrate examples of forming interconnects in and on the dielectric layers.

[0101] Once all dielectric layers and additional interconnects are formed, the method can decouple (e.g., remove, grind away) the carrier (e.g., 1000) from dielectric layer 1020, thereby leaving the substrate. In some implementations, the method can form a solder mask layer (e.g., 224, 226) on the substrate.

[0102] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or solid vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary processes for manufacturing packages including lead bonding coupled to an integrated device.

[0103] Figures 12A-12B illustrate exemplary steps for providing or manufacturing a package including lead bonding coupled to an integrated device. In some implementations, the steps of Figures 12A-12B may be used to provide or manufacture the package 200 of Figure 2 including a substrate 202 and lead bonding coupled to an integrated device, or any package described herein.

[0104] It should be noted that the processes in Figures 12A-12B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this invention. The processes in Figures 12A-12B can be used to manufacture one or more packages (as part of a wafer) at a time.

[0105] As shown in FIG12A, stage 1 illustrates the state after substrate 202 has been provided. Substrate 202 may be provided by a supplier or manufactured. Substrate 202 may be manufactured using a process similar to that shown in FIG10A-10C. However, different implementations may use different processes to manufacture substrate 202. Examples of processes that may be used to manufacture substrate 202 include semi-additive process (SAP) and modified semi-additive process (mSAP). Substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Substrate 202 may be a laminated substrate, a coreless substrate, an organic substrate, or a substrate including a core layer. In some implementations, the at least one dielectric layer 220 may include a core layer and / or a prepreg layer. Substrate 202 includes a cavity 209. Cavity 209 may be manufactured using a laser process (e.g., laser ablation). Cavity 209 may be formed after manufacturing and / or providing substrate 202. In some embodiments, the substrate 202 is provided with a cavity 209.

[0106] Phase 2 illustrates the state after the integrated device 204 and integrated device 206 are coupled to a first surface (e.g., top surface) of the substrate 202. The integrated device 204 is coupled to the substrate 202 via a plurality of solder interconnects 240 and / or a plurality of solder interconnects 242. The integrated device 206 is coupled to the substrate 202 via a plurality of solder interconnects 260 and / or a plurality of solder interconnects 262. A portion of the integrated device 204 and a portion of the integrated device 206 may be located above the cavity 209. The integrated device 204 may be coupled to the substrate 202 such that the front side (e.g., the effective side) of the integrated device 204 faces the substrate 202. Similarly, the integrated device 206 may be coupled to the substrate 202 such that the front side of the integrated device 206 faces the substrate 202.

[0107] Phase 3 illustrates the state after underfill 244 is provided (e.g., formed) between substrate 202 and integration device 204, and after underfill 264 is provided (e.g., formed) between substrate 202 and integration device 206. Underfill (e.g., 244, 264) can be provided around solder interconnects (e.g., 240, 260) and / or solder interconnects (e.g., 242, 262) via capillary action and / or force. The capillary properties of the underfill allow it to fill small spaces and / or gaps between the integration device and the substrate.

[0108] As shown in FIG12B, stage 4 illustrates the state after a plurality of wire bonds 210 are coupled to the first integrated device 204 and the second integrated device 206. For example, the plurality of wire bonds 210 may be formed between the first integrated device 204 and the second integrated device 206. The plurality of wire bonds 210 may be coupled to a plurality of pads 241 (of the first integrated device 204) and a plurality of pads 261 (of the second integrated device 206). The plurality of wire bonds 210 may be formed via cavities 209 of the substrate 202. One advantage of forming the plurality of wire bonds 210 after the integrated devices have been coupled to the substrate is that, since the integrated devices are fixed relative to each other after being coupled to the substrate, the plurality of wire bonds 210 are less likely to break and / or fail due to movement between the integrated devices. Examples of how the plurality of wire bonds 210 are coupled to the integrated devices are shown and described in at least FIG4-6.

[0109] Stage 5 illustrates the state after an encapsulation layer 208 is formed on a first surface of substrate 202 such that the encapsulation layer 208 encapsulates the first integrated device 204 and the second integrated device 206. The encapsulation layer 208 may encapsulate a plurality of wire bonds 210. The encapsulation layer 208 may at least partially fill the cavity 209 of substrate 202. The process of forming and / or depositing the encapsulation layer 208 may include using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Note that in some implementations, the encapsulation layer 208 may replace the underfill (e.g., 244, 264), as described in FIG7. Therefore, in some implementations, the encapsulation layer 208 may be formed in and located in the area occupied by the underfill 244 and / or 264.

[0110] Stage 6 illustrates the state after the plurality of solder interconnects 280 are coupled to the substrate 202. A reflow soldering process can be used to couple the plurality of solder interconnects. Stage 8 may illustrate a package 200 including the substrate 202, a first integration device 204, a second integration device 206, an underfill 244, an underfill 264, and an encapsulation layer 208, as described in at least Figure 2.

[0111] The packages described in this case (e.g., 200, 700) can be manufactured one at a time, or they can be manufactured together (as part of one or more wafers) and subsequently diced into individual packages. An exemplary flowchart of a method for manufacturing a package including wire connections coupled to an integrated device is provided.

[0112] In some implementations, manufacturing a package including wire connections coupled between integrated devices comprises several procedures. FIG13 illustrates an exemplary flowchart of a method 1300 for providing or manufacturing a package with wire connections coupled to an integrated device. In some implementations, method 1300 of FIG13 may be used to provide or manufacture the package 200 of FIG2 described in this document. However, method 1300 may be used to provide or manufacture any package described in this document.

[0113] It should be noted that the method of Figure 13 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing a package including lead contacts coupled to an integrated device. In some implementations, the order of the procedures may be changed or modified.

[0114] The method (at 1305) provides a substrate (e.g., 202). The substrate 202 may be supplied by a supplier or manufactured. The substrate 202 includes a first surface and a second surface. The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The substrate 202 may include at least one cavity 209. Different implementations may provide different substrates. The substrate 202 may be manufactured using a process similar to that shown in Figures 10A-10C. However, different implementations may use different processes to manufacture the substrate 202. Stage 1 of Figure 12A illustrates and describes an example of providing a substrate.

[0115] This method (at 1310) couples an integrated device to a substrate. For example, the method may couple integrated device 204 and integrated device 206 to a first surface (e.g., top surface) of substrate 202. Integrated device 204 is coupled to substrate 202 via a plurality of solder interconnects 240 and / or a plurality of solder interconnects 242. Integrated device 206 is coupled to substrate 202 via a plurality of solder interconnects 260 and / or a plurality of solder interconnects 262. Part of integrated device 204 and part of integrated device 206 may be located above cavity 209. Integrated device 204 may be coupled to substrate 202 such that the front side (e.g., effective side) of integrated device 204 faces substrate 202. Similarly, integrated device 206 may be coupled to substrate 202 such that the front side of integrated device 206 faces substrate 202. Stage 2 of FIG12A illustrates and describes an example of coupling an integrated device to a substrate.

[0116] The method (at 1315) forms at least one underfill between the integrated device and the substrate. For example, the method may provide underfill 244 between substrate 202 and integrated device 204, and underfill 264 between substrate 202 and integrated device 206. Underfill (e.g., 244, 264) may be provided around solder interconnects (e.g., 240, 260) and / or solder interconnects (e.g., 242, 262) via capillary action and / or force. The capillary properties of the underfill allow the underfill to fill small spaces and / or gaps between the integrated device and the substrate. Stage 3 of FIG12A illustrates and describes an example of providing underfill.

[0117] This method (at 1320) couples a plurality of wire bonds 210 to a first integrated device 204 and a second integrated device 206. The plurality of wire bonds 210 may be formed between the first integrated device 204 and the second integrated device 206. The plurality of wire bonds 210 are coupled to a plurality of pads 241 (of the first integrated device 204) and a plurality of pads 261 (of the second integrated device 206). Examples of how the plurality of wire bonds 210 are coupled to the integrated devices are shown and described at least in Figures 4-6. Stage 4 of Figure 12B illustrates and describes an example of coupling wire bonds to the integrated devices.

[0118] This method may (at 1325) form an encapsulation layer on a substrate. For example, the method may form an encapsulation layer 208 on a first surface of substrate 202 such that the encapsulation layer 208 encapsulates a first integrated device 204 and a second integrated device 206. The encapsulation layer 208 may encapsulate a plurality of wire bonds 210. The encapsulation layer 208 may at least partially fill a cavity 209 of substrate 202. The process of forming and / or depositing the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that in some implementations, the encapsulation layer 208 may replace the underfill (e.g., 244, 264), as described in FIG2. Thus, in some implementations, the encapsulation layer 208 may be formed in and located in the area occupied by the underfill. Stage 5 of FIG12B illustrates and describes an example of forming an encapsulation layer.

[0119] This method (at 1330) couples multiple solder interconnects (e.g., 280) to a second surface of a substrate (e.g., 202). A reflow soldering process can be used to couple multiple solder interconnects. Stage 6 of Figure 12B illustrates and describes an example of coupling solder interconnects to a substrate. Exemplary electronic device

[0120] Figure 14 illustrates various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, chips, intermediaries, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1402, laptop device 1404, fixed-location terminal device 1406, wearable device 1408, or motor vehicle 1410 may include the device 1400 as described herein. Device 1400 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. Devices 1402, 1404, 1406, and 1408, and vehicle 1410 illustrated in Figure 14 are merely exemplary. Other electronic devices may also be characterized by device 1400, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0121] One or more of the components, programs, features and / or functions illustrated in Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B and / or 13-14 may be rearranged and / or combined into a single component, program, feature or function, or may be implemented in several components, programs, or functions. Additional elements, components, programs and / or functions may also be added without departing from this invention. It should also be noted that Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B and / or 13-14 and their corresponding descriptions in this invention are not limited to chips and / or ICs. In some implementations, Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B and / or 13-14 and their corresponding descriptions may be used to manufacture, build, provide, and / or produce apparatus and / or integrate apparatus. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a heat dissipation device, and / or an intermediary.

[0122] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all parts and / or components are illustrated for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some implementations, the various parts and / or components in the drawings may be optional.

[0123] The term "exemplary" is used herein to mean "example, instance, or illustration". Any implementation or manner described herein as "exemplary" need not be construed as superior to or better than other manners in this case. Similarly, the term "manner" does not require that all manners in this case include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact with each other. The term "electrical coupling" can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transferred between the two objects. Electrically coupled objects may or may not have current transferred between them. The use of the terms "first", "second", "third", and "fourth" (and / or anything above fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosure" means that an object can partially or completely enclose another object. The terms "top" and "bottom" are arbitrary. A component located at the top can be situated on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this case, a first component situated "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another instance, a first component can be situated above (e.g., above) a first surface of a second component, while a third component can be situated above (e.g., below) a second surface of a second component, where the second surface is opposite the first surface. Further note that the term "above," as used in this case in the context of a component being above another component, can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "above a second component" can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. As used in this case, the terms "about 'value X'" or "approximately value X" mean within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0124] In some implementations, an interconnect is a component or part in a device or package that allows or facilitates an electrical connection between two points, parts, and / or parts. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or part. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0125] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, diagrams, block diagrams, or block diagrams. Although a flowchart can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0126] The following provides an overview of the various forms of this case:

[0127] Form 1: A package including a substrate containing a cavity; a first integrated device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects; a second integrated device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects; and a plurality of wire connections coupled to the first integrated device and the second integrated device, wherein the plurality of wire connections are located above (e.g., above, below) the cavity of the substrate.

[0128] State 2: Package as in State 1, wherein the plurality of wire connections includes: a first plurality of wire connections coupled to the first integrated device and the second integrated device; and a second plurality of wire connections coupled to the first integrated device and the second integrated device. A second vertical distance between the second plurality of wire connections and the first integrated device is different from a first vertical distance between the first plurality of wire connections and the first integrated device. The second plurality of wire connections may be partially located above the first plurality of wire connections. The vertical distance between the wire connections and the surface of the integrated device and / or the pads of the integrated device may be a vertical distance relative to the surface of the integrated device and / or the pads of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0129] State 3: Package as in States 1 to 2, wherein the first integrated device includes a first row of a plurality of pads and a second row of a plurality of pads, wherein the second integrated device includes a first row of a plurality of pads and a second row of a plurality of pads, wherein the plurality of wire connections include: a first plurality of wire connections coupled to (i) the first row of a plurality of pads of the first integrated device and (ii) the first row of a plurality of pads of the second integrated device, and a second plurality of wire connections coupled to (i) the second row of a plurality of pads of the first integrated device and (ii) the second row of a plurality of pads of the second integrated device.

[0130] State 4: Package as in State 3, wherein the first row of a plurality of pads from the first integration device is staggered relative to the second row of a plurality of pads from the first integration device.

[0131] State 5: Packages as in States 1 to 4, wherein the plurality of lead connections between the first integrated device and the second integrated device have a density of at least 40 lead connections per millimeter.

[0132] State 6: Packages as in States 1 to 5, wherein each lead junction from a plurality of lead junctions has a minimum diameter of 15 micrometers.

[0133] State 7: The package as in States 1 to 6 further includes a bottom filler located between (i) the first integrated device and the substrate and (ii) the second integrated device and the substrate. In some implementations, the bottom filler includes an encapsulation layer.

[0134] State 8: The encapsulation of State 7, wherein the bottom filler comprises a viscosity of approximately 10-30 Pa·s.

[0135] State 9: The package of states 7 to 8, wherein the bottom filler includes capillary bottom filler and / or molded bottom filler.

[0136] State 10: The package as in States 1 to 9, further comprising an encapsulation layer located on the substrate, the first integrated device and the second integrated device.

[0137] State 11: Package as in State 10, wherein the cavity of the substrate is at least partially filled with an encapsulation layer. In some implementations, the cavity of the substrate is completely filled with an encapsulation layer.

[0138] In some implementations, state 1 may be a package including a substrate comprising a cavity; a first integrated device coupled to the substrate via a first plurality of interconnects; a second integrated device coupled to the substrate via a second plurality of interconnects; and a plurality of wire connections coupled to the first integrated device and the second integrated device, wherein the plurality of wire connections are located above (e.g., above, below) the cavity of the substrate. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0139] In some implementations, the sample 1 may be a package including a substrate; a first integrated device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects; a second integrated device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects; and a plurality of wire connections coupled to the first integrated device and the second integrated device.

[0140] Form 12: An apparatus comprising a substrate including a cavity; a first integration device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects; a second integration device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects; and means for wire interconnection coupled to the first integration device and the second integration device, wherein the means for wire interconnection is located above (e.g., above, below) the cavity of the substrate.

[0141] State 13: The apparatus of State 12, wherein the means for wire interconnection includes: a first plurality of wire connections coupled to the first integrated device and the second integrated device; and a second plurality of wire connections coupled to the first integrated device and the second integrated device, wherein a second vertical distance between the second plurality of wire connections and the first integrated device is different from the first vertical distance between the first plurality of wire connections and the first integrated device. The second plurality of wire connections may be partially located above the first plurality of wire connections. The vertical distance between the wire connections and the surface of the integrated device and / or the pads of the integrated device may be a vertical distance relative to the surface of the integrated device and / or the pads of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0142] State 14: The apparatus of States 12 to 13, wherein the first integrated device includes a first row of a plurality of pads and a second row of a plurality of pads, wherein the second integrated device includes a first row of a plurality of pads and a second row of a plurality of pads, wherein the means for wire interconnection includes: a first plurality of wire connections coupled to (i) the first row of a plurality of pads of the first integrated device and (ii) the first row of a plurality of pads of the second integrated device, and a second plurality of wire connections coupled to (i) the second row of a plurality of pads of the first integrated device and (ii) the second row of a plurality of pads of the second integrated device.

[0143] State 15: The equipment as in State 14, wherein the first row of the plurality of pads from the first integration device is staggered relative to the second row of the plurality of pads from the first integration device.

[0144] Pattern 16: The equipment as in Patterns 12 to 15, wherein the means for lead interconnection between the first integration device and the second integration device has a density of at least 40 lead connections per millimeter.

[0145] State 17: The equipment as in States 12 to 16, wherein each lead joint from the device for lead interconnection has a minimum diameter of 15 micrometers.

[0146] State 18: The apparatus of states 12 to 17 further includes a bottom filler located between (i) the first integrated device and the substrate and (ii) the second integrated device and the substrate. In some implementations, the bottom filler includes an encapsulation layer.

[0147] State 19: The apparatus of states 12 to 18 further includes an encapsulation device located on the substrate, the first integration device and the second integration device.

[0148] State 20: The apparatus of State 19, wherein the encapsulation means is further located in a cavity of the substrate. The cavity of the substrate may be at least partially filled with the encapsulation means. The cavity of the substrate may be completely filled with the encapsulation means.

[0149] Format 21: Equipment as in Formats 12 to 20, wherein the equipment includes devices selected from the group comprising: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0150] In some implementations, state 12 may be an apparatus comprising a substrate including a cavity; a first integrated means coupled to the substrate via a first plurality of interconnects; a second integrated means coupled to the substrate via a second plurality of interconnects; and means for wire interconnection coupled to the first integrated means and the second integrated means, wherein the means for wire interconnection is located above (e.g., above, below) the cavity of the substrate. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0151] In some implementations, the sample 12 may be an apparatus including a substrate; a first integration device coupled to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects; a second integration device coupled to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects; and means for wire interconnection coupled to the first integration device and the second integration device.

[0152] State 22: A method for manufacturing a package, the method comprising providing a substrate including a cavity; coupling a first integrated device to the substrate via a first plurality of solder interconnects and a first plurality of solder interconnects; coupling a second integrated device to the substrate via a second plurality of solder interconnects and a second plurality of solder interconnects; and forming a plurality of wire connections between the first integrated device and the second integrated device, wherein the plurality of wire connections are located above (e.g., above, below) the cavity of the substrate.

[0153] State 23: The method of State 22, wherein forming a plurality of wire connections includes: coupling a first plurality of wire connections to the first integrated device and the second integrated device; and coupling a second plurality of wire connections to the first integrated device and the second integrated device, wherein a second vertical distance between the second plurality of wire connections and the first integrated device is different from a first vertical distance between the first plurality of wire connections and the first integrated device. The second plurality of wire connections may be partially located above the first plurality of wire connections. The vertical distance between the wire connections and the surface of the integrated device and / or the pads of the integrated device may be a vertical distance relative to the surface of the integrated device and / or the pads of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0154] State 24: The method of States 22 to 23, wherein the first integration device includes a first row of a plurality of pads and a second row of a plurality of pads, wherein the second integration device includes a first row of a plurality of pads and a second row of a plurality of pads, and wherein forming a plurality of wire connections includes: coupling the first plurality of wire connections to (i) the first row of a plurality of pads of the first integration device and (ii) the first row of a plurality of pads of the second integration device, and coupling the second plurality of wire connections to (i) the second row of a plurality of pads of the first integration device and (ii) the second row of a plurality of pads of the second integration device.

[0155] State 25: The method of State 24, wherein the first row of the plurality of pads from the first integration device is staggered relative to the second row of the plurality of pads from the first integration device.

[0156] State 26: The method of states 22 to 25, wherein a plurality of lead joints between the first integration device and the second integration device form a density of at least 40 lead joints per millimeter.

[0157] State 27: The method of states 22 to 26 further includes forming a bottom filler located between (i) the first integrated device and the substrate and (ii) the second integrated device and the substrate.

[0158] State 28: The method of states 22 to 27 further includes forming an encapsulation layer on the substrate, the first integrated device and the second integrated device.

[0159] State 29: The method of State 28, wherein the encapsulation layer is further formed at least partially in the cavity of the substrate.

[0160] In some implementations, state 22 may be a method for manufacturing a package, the method comprising: providing a substrate including a cavity; coupling a first integrated device to the substrate via a first plurality of interconnects; coupling a second integrated device to the substrate via a second plurality of interconnects; and forming a plurality of wire connections between the first integrated device and the second integrated device, wherein the plurality of wire connections are located above (e.g., above, below) the cavity of the substrate. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0161] The various features of the present case described herein can be implemented in different systems without departing from the present case. It should be noted that the above states in this case are instances only and should not be construed as limiting this case. The description of the various forms in this case is intended to be illustrative and not to limit the scope of the attached claim. Thereby, the teachings of the present case can be readily applied to other types of devices, and many substitutions, modifications, and deformations will be obvious to those with usual knowledge in the field to which the invention belongs. [Brief explanation of the diagram]

[0008] The various features, essences and advantages will become apparent when understanding the detailed description elaborated below in conjunction with the drawings, in which similar component symbols are always marked accordingly.

[0009] illustrates a cross-sectional view of a package including an integrated device and a substrate.

[0010] FIG.

[0011] Figure 3 illustrates a plan view of a package including lead joining coupled to the integrated device.

[0012] Figure 4 illustrates a plan view of the joining of the leads coupled to the integrated device.

[0013] Figure 5 illustrates a close-up plan view of the lead joining coupled to the integrated device.

[0014] Figure 6 illustrates a cross-sectional view of the lead joining coupled to the integrated device.

[0015] Figure 7 illustrates a cross-sectional view of a package including lead junction coupled to the integrated device.

[0016] Figures 8A-8B illustrate an exemplary process for fabricating an integrated device having a welding column interconnect.

[0017] Figure 9 illustrates an exemplary flowchart of a method for fabricating an integrated device having a welding column interconnect.

[0018] Figures 10A-10C illustrate an exemplary process for fabricating a substrate.

[0019] Figure 11 illustrates an exemplary flowchart of a method for fabricating a substrate.

[0020] Figures 12A-12B illustrate an exemplary process for fabricating a package including a lead joining coupled to an integrated device.

[0021] Figure 13 illustrates an exemplary flowchart of a method for manufacturing a package with lead bonding coupled to an integrated device.

[0022] Figure 14 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. [Biomaterial Storage]

[0163] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A package, comprising: Includes a substrate with a cavity; A first integrated device coupled to the substrate via a first plurality of solder interconnects and / or a first plurality of solder interconnects; A second integrated device coupled to the substrate via a second plurality of solder interconnects and / or a second plurality of solder interconnects; and a plurality of parallel wire connections coupled to the first integrated device and the second integrated device, wherein the plurality of parallel wire connections are located above the cavity of the substrate; wherein the first integrated device includes a first row of pads and a second row of pads, wherein the second integrated device includes a first row of pads and a second row of pads, and wherein the plurality of parallel wire connections include: a first plurality of wire connections coupled to (i) the first row of pads of the first integrated device and (ii) the first row of pads of the second integrated device, and a second plurality of wire connections coupled to (i) the second row of pads of the first integrated device and (ii) the second row of pads of the second integrated device; The first row of pads from the first integration device is staggered relative to the second row of pads from the first integration device; and a second vertical distance between the second plurality of lead joints and the first integration device is different from a first vertical distance between the first plurality of lead joints and the first integration device.

2. The package as claimed in claim 1, wherein the plurality of parallel lead connections between the first integrated device and the second integrated device have a density of at least 40 lead connections per millimeter.

3. The package as requested in claim 1, wherein each lead junction from the plurality of parallel lead junctions has a minimum diameter of 15 micrometers.

4. The package as claimed in claim 1 further includes a bottom filler located between (i) the first integrated device and the substrate and (ii) the second integrated device and the substrate.

5. The encapsulation as requested in item 4, wherein the bottom filler comprises a viscosity of about 10 to 30 Pa·s.

6. The encapsulation as requested in item 4, wherein the bottom filler comprises a capillary bottom filler and / or a molded bottom filler.

7. The package as claimed in claim 1 further includes an encapsulation layer located on the substrate, the first integrated device, and the second integrated device.

8. The package of claim 7, wherein the cavity of the substrate is at least partially filled with the encapsulation layer.

9. The package of any one of claims 1 to 8, wherein the first row of pads has a center-to-center pitch of 40.5 micrometers between the pads; and / or wherein the second row of pads has a center-to-center pitch of 40.5 micrometers between the pads; and / or the first row of pads and the second row of pads have a row-to-row pitch of 61 micrometers.

10. A packaging apparatus comprising a package as claimed in any one of claims 1 to 9.

11. A method for manufacturing a package, comprising the steps of: providing a substrate including a cavity; coupling a first integrated device to the substrate via a first plurality of solder interconnects and / or a first plurality of solder interconnects; coupling a second integrated device to the substrate via a second plurality of solder interconnects and / or a second plurality of solder interconnects; and forming a plurality of parallel wire connections between the first integrated device and the second integrated device, wherein the plurality of parallel wire connections are located over the cavity of the substrate; wherein the first integrated device includes a first row of pads and a second row of pads, wherein the second integrated device includes a first row of pads and a second row of pads, and wherein forming the plurality of parallel wire connections includes: A first plurality of wire connections are coupled to (i) the first row of pads of the first integrated device and (ii) the first row of pads of the second integrated device, and a second plurality of wire connections are coupled to (i) the second row of pads of the first integrated device and (ii) the second row of pads of the second integrated device; wherein the first row of pads from the first integrated device is staggered relative to the second row of pads from the first integrated device; and wherein a second vertical distance between the second plurality of wire connections and the first integrated device is different from a first vertical distance between the first plurality of wire connections and the first integrated device.

12. The method of claim 11, wherein the plurality of parallel lead connections between the first integrated device and the second integrated device are formed at a density of at least 40 lead connections per millimeter.

13. The method of claim 11 further includes forming a bottom filler located between (i) the first integrated device and the substrate and (ii) the second integrated device and the substrate.

14. The method of claim 11 further includes forming an encapsulation layer on the substrate, the first integrated device, and the second integrated device.

15. The method of claim 14, wherein the encapsulation layer is further formed at least partially in the cavity of the substrate.

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