An electronic apparatus having an embedded etch stop to control cavity depth in glass layers therein

Abstract

An electronic substrate can be manufactured having at least two glass layers separated by an etch stop layer, wherein a bridging element is embedded within one of these glass layers. The depth of the cavity formed to embed the bridging element is controlled by the thickness of the glass layers, rather than by controlling the etching process used to form the cavity, which allows for higher precision in the manufacture of the electronic substrate. In one embodiment of this specification, an integrated circuit package can be formed on an electronic substrate, wherein at least two integrated circuit devices can be attached to the electronic substrate such that the bridging element provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package can be electrically attached to an electronic board.

Description

Technical Field

[0001] The embodiments in this specification are generally related to the field of integrated circuit packaging manufacturing, and more specifically, to integrated circuit assemblies including electronic substrates having bridging for electrical signal connections between integrated circuit devices, wherein the bridging is embedded in a glass layer of the electronic substrate. Prior Technology

[0002] The integrated circuit industry is constantly striving to produce faster, smaller, and thinner integrated circuit packages for a variety of electronic products, including but not limited to computer servers and portable products such as laptops, tablets, cell phones, and digital cameras.

[0003] As part of this effort, integrated circuit packages (ICPs) incorporating multiple integrated circuit devices (e.g., microelectronic dies) have been developed. These ICP packages are referred to in the art as multi-device, multi-chip packages (MCPs) or partitioned devices, and offer the potential for increased architectural flexibility at a reduced cost, but this must be done to provide a suitable ICP-to-ICP interconnect density. As those skilled in the art will understand, interconnect density is an important consideration because an insufficient number of ICP connections limits the bandwidth capabilities of the affected ICP interfaces, thereby reducing the efficiency and capability of communication between ICPs.

[0004] To address interconnection issues, bridging can be embedded in the substrate to which the integrated circuit devices (ICDs) are attached. These bridgings support dense ICD-to-ICD interconnects, such as from the edge of a first ICD to the edge of a second ICD, and can support multiple signal lines through the bridging itself. Instead of using expensive silicon interposers with vias, bridging can be passive silicon structures or active silicon devices embedded in the substrate, enabling dense ICD-to-ICD interconnects only when needed. Standard flip-chip processes can be used to connect ICDs to the substrate for robust power delivery and to the bridging within the substrate. Therefore, the resulting ICD package can be significantly smaller than an ICD package that is only interconnected to conductive wiring within the substrate. Summary of the Invention

[0005] and Simple Explanation of the Diagram

[0006] The subject matter of the invention is specifically pointed out and clearly claimed in the concluding section of the specification. The foregoing and other features of the invention will become more apparent from the following description and the appended claims in conjunction with the accompanying drawings. It should be understood that the accompanying drawings only illustrate a few embodiments according to the invention and should therefore not be considered as limiting its scope. The advantages of the invention can be more readily identified by describing it with additional specificity and detail using the drawings, wherein:

[0007] [Figure 1] is a side cross-sectional view of an integrated circuit package according to an embodiment of this specification.

[0008] [Figure 2-12] is a side cross-sectional view of a process for manufacturing an electronic substrate according to an embodiment of this specification.

[0009] [Figure 13] is a side cross-sectional view of a glass layer stack according to an embodiment of this specification.

[0010] [Figure 14] is a top view of a glass layer configuration according to another embodiment of this specification.

[0011] [Figure 15] is a side cross-sectional view of an integrated circuit package according to another embodiment of this specification.

[0012] [Figures 16-31] are side cross-sectional views of the manufacturing process of an electronic substrate according to another embodiment of this specification.

[0013] [Figure 32] is an electronic system according to one embodiment of this specification. Implementation

[0014] In the following detailed description, with reference to the accompanying drawings, specific embodiments of the claimed subject matter are shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to implement the subject matter. It should be understood that the various embodiments, while different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter. The reference to "one embodiment" or "an embodiment" in this specification means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one implementation covered by this specification. Therefore, the use of the phrase "one embodiment" or "in one embodiment" does not necessarily refer to the same embodiment. Furthermore, it should be understood that the position or arrangement of various elements in each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description should not be construed as limiting, and the scope of the subject matter is defined only by the appended claims as suitably interpreted and the full scope of the equivalents enjoyed by the appended claims. In the drawings, similar reference numerals in multiple drawings refer to the same or similar elements or functions, and the elements depicted therein are not necessarily scaled up to each other, but may be enlarged or reduced to make them easier to understand in the context of this specification.

[0015] As used herein, the terms “above,” “to,” “between,” and “on” can refer to the relative position of a layer with respect to other layers. A layer that is “above,” “on,” or “adhere” to another layer may be in direct contact with the other layer or may have one or more interlayers. A layer that is “between” layers may be in direct contact with these layers or may have one or more interlayers.

[0016] The term "package" typically refers to a self-contained carrier of one or more dies, wherein the dies are attached to a package substrate and can be encapsulated for protection, with integrated or wire-bonded interconnects between the dies and leads, pins, or bumps located outside the package substrate. A package can contain a single die or multiple dies, providing a specific function. Packages are typically mounted on printed circuit boards for interconnection with integrated circuits and discrete components in other packages to form a larger circuit.

[0017] Here, the term "cored" typically refers to a substrate for an integrated circuit package built on a board, card, or wafer that comprises a non-flexible, rigid material. Typically, a small printed circuit board serves as the core, on which integrated circuit devices and discrete passive components can be soldered. The core usually has through-holes extending from one side to the other, allowing circuitry on one side of the core to be directly coupled to circuitry on the other side. The core can also serve as a platform for building layers of conductors and dielectric materials.

[0018] Here, the term "corless" typically refers to the substrate of an integrated circuit package without a core. Corless allows for higher density package architectures because vias have relatively large size and spacing compared to high-density interconnects.

[0019] Here, if used herein, the term "pin side" generally refers to the side of the substrate of an integrated circuit package that is closest to the attachment plane of the printed circuit board, motherboard, or other package. This contrasts with the term "die side," which is the side of the substrate of an integrated circuit package that is attached to the die or chips.

[0020] Here, the term "dielectric" generally refers to any number of non-conductive materials constituting the package substrate structure. For the purposes of this invention, the dielectric material may be incorporated into the integrated circuit package as a laminate layer or as a resin molded onto integrated circuit dies mounted on a substrate.

[0021] Here, the term "metallization" generally refers to a metal layer formed on and through the dielectric material of a package substrate. The metal layer is typically patterned to form metallic structures such as traces and bonding pads. Metallization of the package substrate can be confined to a single layer or in multiple layers separated by dielectric layers.

[0022] Here, the term "bonding pad" generally refers to the metallized structure that terminates integrated circuit packages and vias in the die. The term "solder pad" is sometimes used instead of "bonding pad" and has the same meaning.

[0023] Here, the term "solder bump" generally refers to a layer of solder formed on the bonding pad. The solder layer is usually circular, hence the name "solder bump".

[0024] Here, the term "substrate" generally refers to a planar platform comprising dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more IC dies onto a single platform, wherein the one or more IC dies are encapsulated by a moldable dielectric material. The substrate typically includes solder bumps as bonding interconnects on both sides. One side of the substrate, typically referred to as the "die side," contains solder bumps for die or chip bonding. The opposite side of the substrate, typically referred to as the "pin side," contains solder bumps for bonding the package to a printed circuit board.

[0025] Here, the term "assembly" generally refers to the combination of components into a single functional unit. These components can be separate and mechanically assembled into a functional unit, where they can be removable. In another case, these components can be permanently combined together. In some situations, these components are integrated together.

[0026] Throughout the specification and the scope of the patent application, the term "connection" refers to a direct connection, such as an electrical, mechanical, or magnetic connection between connected things, without any intermediate means.

[0027] The term "coupling" refers to a direct or indirect connection through one or more passive or active intermediaries, such as a direct electrical, mechanical, magnetic, or fluid connection or indirect connection between connected things.

[0028] The terms "circuit" or "module" can refer to one or more passive and / or active components configured to cooperate to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes both "in" and "on."

[0029] The vertical direction is the z-direction, and it should be understood that the terms "top," "bottom," "above," and "below" refer to relative positions in the z-dimensional dimension with their usual meaning. However, it should be understood that embodiments are not necessarily limited to the orientations or configurations shown in the figures.

[0030] The terms "substantially," "nearly," "approximately," "close to," and "roughly" generally refer to within + / - 10% of the target value (unless otherwise specified). Unless otherwise stated, the ordinal adjectives "first," "second," and "third," etc., used to describe a common object merely indicate different instances of the similar objects referred to, and are not intended to imply that the objects described must be arranged in a given order, whether temporally, spatially, or in any other way.

[0031] For the purposes of this invention, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this invention, the phrases "A, B and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0032] Views labeled "section," "outline," and "plan" correspond to orthogonal planes in a Cartesian coordinate system. Therefore, sectional and side views are taken from the xz plane, while plan views are taken from the xy plane. Typically, a side view in the xz plane is a sectional view. Where appropriate, the diagram is labeled with axes to indicate the orientation of the diagram.

[0033] As previously mentioned, to reduce the size of integrated circuit packages and components, the integrated circuit industry is utilizing bridging, such as interposers and patches, embedded in the electronic substrate to form interconnects between segmented integrated circuit devices. For future generations of such integrated device segmentation, multiple bridging devices need to be connected with much finer bump pitches (25 micrometers or less) than currently available technology. Understandably, current embedded bridging methods suffer from high cumulative bump thickness variation (BTV), and embedding costs and yields are impacted as the number of bridging devices increases. Alternative architectures and methods have been proposed and investigated. However, warpage issues arise in these alternative methods. To address these issues, at least one substantially rigid glass layer can be bonded to the electronic substrate, resulting in a significant reduction in warpage. However, this method relies on wet etching of the glass to define the cavities of the bridging, exhibiting significant and unacceptable cavity depth variations (+ / - 10%).

[0034] Embodiments of this specification include an electronic substrate having at least two glass layers separated by an etch stop layer, wherein a bridging is embedded within one of these glass layers. The depth of the cavity formed for embedding the bridging is controlled by the thickness of the glass layers, rather than by controlling the etching process used to form the cavity, which allows for higher precision in the fabrication of the electronic substrate. In one embodiment of this specification, an integrated circuit package may be formed together with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate such that the bridging provides device-to-device interconnection between the at least two integrated circuit devices. In another embodiment, the integrated circuit package may be electrically attached to an electronic board or a package interposer.

[0035] An integrated circuit package 100 can be formed by first forming an electronic substrate 110, such as an interposer or patch, as shown in FIG1. ​​The electronic substrate 110 may include at least two glass layers, illustrated as a first glass layer 120 having a first surface 122 and an opposing second surface 124, and a second glass layer 130 having a first surface 132 and an opposing second surface 134, with an etch stop layer 140 between the first surface 122 of the first glass layer 120 and the first surface 132 of the second glass layer 130.

[0036] The first glass layer 120 and the second glass layer 130 can be any suitable glass material, including but not limited to silicate-based glasses (lithium silicate, borosilicate, aluminum silicate, etc.), as well as low-quality soda lime and high-quality fused silica. As those skilled in the art will understand, integrated circuit packages will include materials with various thicknesses and coefficients of thermal expansion (CTE), particularly concerning integrated circuit devices, molding material layers, and even the rigid carrier used to form the integrated circuit package. Large CTE mismatches between materials can lead to cell-level and / or panel-level warping. The first glass layer 120 and the second glass layer 130 can provide rigidity to mitigate this warping.

[0037] The etch stop layer 140 can be any suitable material relative to the etchant, such as hydrofluoric acid, for forming openings within the first glass layer 120 and the second glass layer 130 during the fabrication of the electronic substrate 110, as will be discussed. In one embodiment of this specification, the etch stop layer 140 is a dielectric material. In one embodiment of this specification, the etch stop layer 140 may include a light-absorbing material. In a particular embodiment, the etch stop layer 140 may absorb ultraviolet light, particularly when using a laser-induced deep etching (LIDE) process, as will be discussed. The etch stop layer 140 may include, but is not limited to, polymers (e.g., polytetrafluoroethylene, polyethylene, polyvinyl chloride, polyvinylidene fluoride, and ultra-high molecular weight polyethylene) and metal oxides (e.g., alumina). Although the etch stop layer 140 is depicted as a single layer, the embodiments of this specification are not limited thereto, as the etch stop layer 140 may consist of multiple layers of different or similar materials.

[0038] At least one bridging opening 142 may be formed in at least one of the first glass layer 120 and the second glass layer 130. As shown in FIG1, the bridging opening 142 may be defined by at least one sidewall 144 extending from a first surface 122 of the first glass layer 120 to a second surface 124 of the first glass layer 120. At least one bridging point 150 may be disposed within the bridging opening 142. As shown, at least one bridging point 150 may include a first surface 152, an opposing second surface 154, and at least one side surface 156 extending between the first surface 152 and the second surface 154. A bridging 150 may include a device-to-device interconnect wiring 160 (shown as dashed lines) extending between at least one pair of associated bonding pads 162 in or on a first surface 152 of at least one bridging 150, and may include a plurality of through-bridging conductive vias 158, wherein each of the plurality of through-bridging conductive vias 158 extends between a bonding pad 162 in or on the first surface 152 of the bridging 150 and a bonding pad 164 in or on a second surface 154 of the bridging 150. At least one bridging 150 may be attached within the bridging opening 142 as an adhesive layer 166, such as a thermally adhesive film, between the second surface 152 of the bridging 150 and the etch stop layer 140. Note that an interconnect layer 168 may be formed on the bonding pads 164 at the second surface 154 of the bridging 150 to facilitate subsequent electrical attachment, as will be discussed.

[0039] In one embodiment, bridging 150 may include silicon-containing components. As those skilled in the art will understand, silicon bridging may be preferred because silicon processing technology is relatively advanced, and the interconnect spacing and linewidth of device-to-device interconnect wiring 160 achievable using existing silicon process technologies can be significantly smaller and therefore denser compared to copper signal line technology in currently available polymer layers (common in electronic substrate manufacturing).

[0040] As further shown in FIG1, the bridging 150 may be at least partially encapsulated within the bridging opening 142 in a molding material 170 (e.g., epoxy resin). The molding material may extend on the first surface 152 of the bridging 150 and the second surface 124 of the first glass layer 120. In one embodiment, at least one high-density through-hole conductive via 172 may extend through the molding material 170 and be electrically attached to a bonding pad 162 in or on the first surface 152 of the bridging 150.

[0041] As shown in Figure 1, at least one first through-glass conductive via 182 may extend through the first glass layer 120, the second glass layer 130, and the etch stop layer 140. At least one first through-glass conductive via 182 may contain at least one through-glass conductive wiring 180. At least one first through-glass conductive via 182 may be electrically attached to a corresponding through-hole conductive via 174 adjacent to the second surface 122 of the first glass layer 120. At least one second through-glass conductive via 184 may extend through the second glass layer 130, the etch stop layer 140, and a portion of the adhesive layer 166, wherein the at least one second through-glass conductive via 184 may be electrically attached to an interconnect layer 168 on a corresponding bonding pad 164 at the second surface 154 of the bridging 150.

[0042] As further shown in FIG1, the electronic substrate 110 may include a first signal wiring layer 210 formed on a molding material 170. The first signal wiring layer 210 may include a plurality of conductive traces 212 (including wiring and bonding pads) electrically coupled to respective through-hole conductive vias 174 on the molding material 170, and a plurality of high-density conductive traces 214 (including wiring and bonding pads) electrically attached to the respective high-density through-hole conductive vias 172 on the molding material 170. The first signal wiring layer 210 may further include at least one dielectric layer 216, such as a solder mask layer, on the plurality of conductive traces 212, the plurality of high-density conductive traces 214, and the molding material 170. A plurality of conductive vias 222 may be formed to extend through at least one dielectric layer 216 and be electrically attached to the respective conductive traces 212, and a plurality of high-density conductive vias 224 may be formed to extend through at least one dielectric layer 216 and be electrically attached to the respective high-density conductive traces 214. Multiple device-to-substrate bonding pads 232 may be formed on at least one dielectric layer 216 and electrically attached to respective conductive vias 222, and multiple high-density device-to-substrate bonding pads 234 may be formed on at least one dielectric layer 216 and electrically attached to respective high-density conductive vias 224.

[0043] As further shown in FIG1, the electronic substrate 110 may include a second signal wiring layer 250 formed on a second surface 134 of the second glass layer 130. The second signal wiring layer 250 may include at least one dielectric layer 256, such as a solder resist layer, a plurality of conductive traces 258 electrically coupled to at least one of a first through-glass conductive via 182 and a second through-glass conductive via 184, and a plurality of conductive vias 252 electrically coupled to the respective conductive traces 258. A plurality of substrate-to-board bonding pads 260 may be formed on at least one dielectric layer 256 and electrically attached to the respective conductive vias 252. External interconnects 262, such as solder, may be attached to the substrate-to-board bonding pads 260. The external interconnects 262 may be used to attach the integrated circuit package 100 to an external substrate (not shown), such as a motherboard. The first signal wiring layer 210 and / or the second signal wiring layer 250 may comprise multiple dielectric material layers, which may include multilayer films and / or solder mask layers, and may be composed of suitable dielectric materials, including but not limited to bismaleimide triazine resin, flame retardant grade 4 materials, polyimide materials, silicon dioxide-filled epoxy materials, glass-reinforced epoxy materials, and their stacks or multilayers, as well as low-k and ultra-low-k dielectrics (dielectric constant less than about 3.6), including but not limited to carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, etc. Conductive traces 212, 214, 258, bonding pads 232, 260, and conductive vias 222, 224, and 252 may be made of any suitable conductive material, including but not limited to metals such as copper, silver, nickel, gold, aluminum, and their alloys.

[0044] As further shown in FIG1, multiple integrated circuit devices (illustrated as first integrated circuit device 270 1 and second integrated circuit device 270 2) can be electrically attached to the electronic substrate 110. The first integrated circuit device 270 1 and the second integrated circuit device 270 2 (and any other integrated circuit devices that may be used) can be any suitable device, including but not limited to microprocessors, chipsets, graphics devices, wireless devices, memory devices, application-specific integrated circuit devices, combinations thereof, stacks thereof, etc. The first integrated circuit device 270 1 and the second integrated circuit device 270 2 can be attached to the electronic substrate 110 via multiple device-to-substrate interconnects 280 (e.g., reflowable solder bumps or solder balls) in a configuration commonly referred to as flip-chip or controlled collapse die connection (“C4”). Device-to-substrate interconnects 280 may extend between bonding pads 2721 on the first surface 2741 of the first integrated circuit device 270 1 and corresponding device-to-substrate bonding pads 232, and between the first integrated circuit device bonding pads 2721 and corresponding high-density device-to-substrate bonding pads 234, to form an electrical connection therebetween. Device-to-substrate interconnects 280 may also extend between bonding pads 2722 on the first surface 2742 of the second integrated circuit device 270 2 and corresponding device-to-substrate bonding pads 232, and between the second integrated circuit device bonding pads 2722 and corresponding high-density device-to-substrate bonding pads 234, to form an electrical connection therebetween. It should be understood that the first integrated circuit device bonding pad 2721 may be electrically connected to an integrated circuit (not shown) within the first integrated circuit device 270 1, and the second integrated circuit device bonding pad 2722 may be electrically connected to an integrated circuit (not shown) within the second integrated circuit device 270 2. Bridge 150 can establish an electrical signal connection between the first integrated circuit device 270 1 and the second integrated circuit device 270 2, wherein at least one device-to-device interconnect wiring 160 extends between a bonding pad 164 of bridge 150 electrically connected to the first integrated circuit device 270 1 and another bonding pad 164 of bridge 150 electrically connected to the second integrated circuit device 270 2. In one embodiment of this specification, bridge 150 may be a microprocessor, and each of the first integrated circuit device 270 1 and the second integrated circuit device 270 2 may be a memory device.

[0045] The device-to-substrate interconnect 280 can be any suitable conductive material or structure, including but not limited to solder balls, metal bumps or pillars, metal-filled epoxy resin, or combinations thereof. In one embodiment of this specification, the device-to-substrate interconnect 280 can be solder balls formed of tin, lead / tin alloys (e.g., 63% tin / 37% lead solder), and high-tin content alloys (e.g., 90% or more tin—e.g., tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, and similar alloys). In another embodiment of this specification, the device-to-substrate interconnect 280 can be copper bumps or pillars. In yet another embodiment of this specification, the device-to-substrate interconnect 280 can be metal bumps or pillars coated with solder material.

[0046] In one embodiment of this specification, an underfill material 292, such as an epoxy resin material, may be disposed between the electronic substrate 110 and the integrated circuit devices 2701 and 2702, and around the plurality of device-to-substrate interconnects 280. As those skilled in the art will understand, the underfill material 292 may be dispensed as a viscous liquid between the first surfaces 2721, 2722 of the integrated circuit devices 2701, 2702 and the electronic substrate 110, and then cured by a curing process. The underfill material 292 may also be a molded underfill material. As those skilled in the art will understand, the underfill material 292 can provide structural integrity and prevent contamination. An encapsulation material 294 may be disposed on and between the integrated circuit devices 2701, 2702 for further structural integrity and contamination prevention.

[0047] Figure 2-12 illustrates one embodiment of the fabrication of the electronic substrate 110 of Figure 1. As shown in Figure 2, a first glass layer 120 may be attached to a second glass layer 130, with an etch stop layer 140 located therebetween. As shown in Figure 3, at least one opening 302 may be formed in the first glass layer 120, extending from a second surface 124 to a first surface 122 of the first glass layer 120 to expose a portion of the etch stop layer 140. As further shown in Figure 3, at least one opening 304 may be formed in the second glass layer 130, extending from a second surface 134 to a first surface 132 of the second glass layer 130 to expose a portion of the etch stop layer 140. The openings 302 in the first glass layer 120 may be paired with corresponding openings 304 in the second glass layer 130 such that they are substantially aligned with each other over the entire etch stop layer 140.

[0048] The openings 302 in the first glass layer 120 and 304 in the second glass layer 130 can be formed by any known process. In one embodiment of this specification, the openings 302 in the first glass layer 120 and 304 in the second glass layer 130 can be formed by a laser-induced deep etching (LIDE) process. The LIDE process is well known in the art and therefore will not be described in detail, but only in general terms, for clarity and brevity. The LIDE process is a two-step process for creating deep, high aspect ratio structures in glass. The first step involves modifying the glass with laser pulses of the desired pattern. The second step involves removing the modified glass with wet chemical etching, since etching chemicals remove modified glass much faster than unmodified glass. Therefore, using the LIDE process, in one embodiment of this specification, the etch stop layer 140 can be made of a material that can absorb light (e.g., from ultraviolet lasers), modify the glass, and resist wet etching chemicals that etch the modified glass to form the openings.

[0049] As shown in FIG4, a portion of the etch stop layer 140 between the opening 302 in the first glass layer 120 and the corresponding opening 304 in the second glass layer 130 can be removed, for example by etching, and a conductive material can be deposited, for example by electroplating, to form a first through-glass conductive via 182 extending through at least one of the first glass layer 120, the second glass layer 130 and the etch stop layer 140.

[0050] As shown in Figure 5, a bridging opening 142 may be formed in the first glass layer 120, as previously described, exposing a portion of the etch stop layer 140. In one embodiment of this specification, the bridging opening 142 in the first glass layer 120 may be formed by a LIDE process, as previously described.

[0051] As further shown in FIG. 5, at least one opening 306 may be formed in the second glass layer 130, wherein the at least one opening 306 may extend from the second surface 134 of the second glass layer 130 to the first surface 132 of the second glass layer 130 to expose the etch stop layer 140. The opening 306 in the second glass layer 130 may be formed aligned with the bridging opening 142 in the first glass layer 120. In one embodiment of this specification, the opening 306 in the second glass layer 130 may be formed by a LIDE process as previously described.

[0052] As shown in Figure 6, at least one bridging element 150 may be disposed within the bridging opening 142 and attached to the etch stop layer 140 by an adhesive layer 166, as previously described. It should be noted that the high-density through-hole conductive vias 172 may be formed on the bridging element 150 before being disposed in the bridging opening 142. As shown in Figure 7, molding material 170 may be deposited on the second surface 124 of the second glass layer 120 and the bridging element 150. In one embodiment of this specification, a portion of the molding material 170 may extend into the opening 142.

[0053] As shown in FIG8, the opening 306 can be extended by etching through the etch stop layer 140 and the adhesive layer 166 to expose the interconnect layer 168 of the bridging 150, as previously described. As shown in FIG9, the molding material 170 can be planarized, for example by chemical mechanical polishing, to expose the high-density through-hole conductive vias 172 of the bridging 150. As shown in FIG10, at least one through-hole opening 308 through the molding material 170 can be formed, for example by etching, to expose at least a portion of each first through-glass conductive via 182.

[0054] As shown in Figure 11, the through-holes 308 and 306 in the second glass layer 120 can be simultaneously filled with conductive material to form through-hole conductive vias 174 and 184 through glass, respectively. Further shown in Figure 11, conductive traces 212 can be formed on the through-hole conductive via 174, and conductive traces 258 can be formed on the first through-hole conductive via 182 and the second through-hole conductive via 184. As shown in Figure 12, as previously described, a first signal wiring layer 210 and a second signal wiring layer 250 can be formed to form the electronic substrate 110.

[0055] Although the embodiments shown in Figures 1-12 depict the first glass layer 120 and the second glass layer 130 having substantially similar thicknesses, the embodiments described herein are not limited thereto. For example, in Figure 13, the thickness T1 of the first glass layer 120 may be less than the thickness T2 of the second glass layer 130. As will be understood, a thicker second glass layer 130 can reduce warping. Furthermore, the first glass layer 120 and the second glass layer 130 may have different form factors. For example, as shown in Figure 14, the first glass layer (illustrated as elements 120A, 120B, 120C, and 120D) may be a quarter panel bonded to the entire panel, i.e., the second glass layer 130.

[0056] In another embodiment of this specification, as shown in FIG15, the process may allow the fabrication of inter-glass conductive traces 264 within each etch stop layer 140. Therefore, the embodiment illustrated in FIG15 includes all the components of the embodiment illustrated in FIG1, except that each through-glass conductive wiring 180 includes a second portion 284 of conductive wiring extending through the first glass layer 120, a first portion 282 of conductive wiring extending through the second glass layer 130, and the associated inter-glass conductive trace 264.

[0057] Figures 16-31 illustrate one embodiment of the fabrication of the electronic substrate 110 of Figure 15. As shown in Figure 16, a second glass layer 130 may be formed having at least one first portion 282 of conductive wiring extending from a first surface 132 to a second surface 134 of the second glass layer 130. The first portion 282 of conductive wiring may be formed by any method known in the art, including but not limited to, for example, etching an opening through the second glass layer 130 using a LIDE process, followed by filling the opening with a conductive material, such as electroplating metal therein. As shown in Figure 17, at least one inter-glass conductive trace 264 may be formed on the first surface 132 of the second glass layer 130, wherein each inter-glass conductive trace 264 may be electrically attached to a corresponding first portion 282 of conductive wiring. As known in the art, the inter-glass conductive trace 264 may be a fan-out trace. As further shown in Figure 17, an etch stop layer 140 may be formed over the inter-glass conductive trace 264 and the first surface 132 of the second glass layer 130. In one embodiment, the etch stop layer 140 may have more than one layer, such as a dielectric material layer adjacent to the inter-glass conductive trace 264, wherein a resist / light-absorbing layer is present on the dielectric layer. As will be understood, the inter-glass conductive trace 264 can achieve a loose interlayer interconnect spacing.

[0058] As shown in Figure 18, the first glass layer 120 may be attached to the etch stop layer 140 and at least one opening 402 may be formed in the first glass layer 120, wherein the at least one opening 402 may extend from the second surface 124 of the first glass layer 120 to the first surface 122 of the first glass layer 120 to expose a portion of the etch stop layer 140. The opening 402 may be formed by any known process, including but not limited to the LIDE process, as previously described.

[0059] As shown in FIG19, the opening 402 can extend through the etch stop layer 140 by etching (e.g., dry etching) to expose a portion of the corresponding inter-glass conductive trace 264. As shown in FIG20, the opening 402 in the first glass layer 120 (see FIG19) can be filled with a conductive material to form at least one second portion 284 of conductive wiring. Therefore, each through-glass conductive wiring 180 can include a combination of a corresponding second portion 284 of conductive wiring, a corresponding inter-glass conductive trace 264, and a corresponding first portion 282 of conductive wiring.

[0060] As shown in Figure 21, which is a close-up of illustration A of Figure 20, etching through the etch stop layer 140, as shown in Figure 19, can produce an undercut with a substantially sloping profile, such that the second portion 284 of the conductive wiring can have a flange 286 adjacent to the inter-glass conductive trace 264.

[0061] As shown in FIG. 22, a bridging opening 142 may be formed in the second glass layer 130, as previously described, exposing a portion of the etch stop layer 140. As shown in FIG. 23, at least one bridging 150 may be disposed within the bridging opening 142 and attached to the etch stop layer 140 with an adhesive layer 166, as previously described. As shown in FIG. 24, molding material 170 may be deposited on the second surface 124 of the second glass layer 120 and the bridging 150. In one embodiment of this specification, a portion of the molding material 170 may extend into the bridging opening 142. Note that the high-density through-hole conductive vias 172 may be formed on the bridging 150 before being disposed in the bridging opening 142.

[0062] As shown in FIG. 25, at least one opening 404 may be formed through the second glass layer 130, wherein the opening 404 may extend from the second surface 134 of the second glass layer 130 to the first surface 132 of the second glass layer 130 to expose a portion of the etch stop layer 140. The opening 404 in the second glass layer 130 may be formed to align with the corresponding bonding pad 164 and interconnect layer 168 at the second surface 154 of the bridging 150. As shown in FIG. 26, the opening 404 may extend through the etch stop layer 140 and the adhesive layer 166 by etching to expose the interconnect layer 168 of the bridging 150, as previously described. As shown in FIG. 27, the opening 404 in the second glass layer 130 (see FIG. 26) may be filled with a conductive material to form a second through-glass conductive via 184.

[0063] As shown in FIG28, the molding material 170 can be planarized, for example, by chemical mechanical polishing, to expose the high-density through-hole conductive vias 172 of the bridging 150. As shown in FIG29, at least one through-hole opening 406 can be formed, for example, by etching through the molding material 170, to expose at least a portion of each conductive wiring second portion 284.

[0064] As shown in Figure 30, the through-hole 406 can be filled with conductive material to form a through-hole conductive via 174. As shown in Figure 31, conductive traces 212 can be formed on the through-hole conductive via 174, and conductive traces 258 can be formed on the first portion 282 of the conductive wiring and the second through-hole conductive via 184. As shown in Figure 31, as previously described, a first signal wiring layer 210 and a second signal wiring layer 250 can be formed to form an electronic substrate 110.

[0065] Figure 32 illustrates an embodiment of an electronic or computing device 500 according to this specification. The computing device 500 may include a housing 501, wherein a board 502 is disposed. The computing device 500 may include a plurality of integrated circuit components, including but not limited to a processor 504, at least one communication chip 506A, 506B, volatile memory 508 (e.g., DRAM), non-volatile memory 510 (e.g., ROM), flash memory 512, a graphics processor or CPU 514, a digital signal processor (not shown), an encryption processor (not shown), a chipset 516, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (such as a hard disk drive, an optical disc (CD), a digital multifunction disc (DVD), etc.). Any integrated circuit component may be physically and electrically coupled to board 502. In some implementations, at least one integrated circuit component may be part of processor 504.

[0066] Communication chips enable wireless communication for transmitting data to and from computing devices. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., that transmit data through a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, although they may be absent in some embodiments. Communication chips can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and above. Computing devices may include multiple communication chips. For example, the first communication chip can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, while the second communication chip can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0067] The term "processor" can mean any device or part of a device that processes electronic data from a register and / or memory to convert that electronic data into other electronic data that can be stored in the register and / or memory.

[0068] At least one of the integrated circuit components may include an integrated circuit package, the integrated circuit package including an electronic substrate, the electronic substrate including a first glass layer having a first surface and an opposing second surface, a second glass layer having a first surface and an opposing second surface, an etch stop layer adjacent to the first surface of the first glass layer and adjacent to the first surface of the second glass layer, wherein the first glass layer includes an opening at the etch stop layer extending from the first surface of the first glass layer to the second surface of the first glass layer.

[0069] In various embodiments, the computing device can be a laptop, netbook, notebook computer, ultra-thin laptop, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, the computing device can be any other electronic device for processing data.

[0070] It should be understood that the subject matter of this specification is not necessarily limited to the specific applications shown in Figures 1-32. As will be understood by those skilled in the art, this subject matter can be applied to other integrated circuit devices and assemblies, as well as any suitable electronic applications.

[0071] The following examples relate to further embodiments, and the details in the examples may be used anywhere in one or more embodiments, wherein Example 1 is an apparatus comprising: a first glass layer having a first surface and an opposing second surface; a second glass layer having a first surface and an opposing second surface; and an etch stop layer adjacent to the first surface of the first glass layer and the first surface of the second glass layer, wherein the first glass layer includes an opening extending from the first surface of the first glass layer to the second surface of the first glass layer at the etch stop layer.

[0072] In Example 2, the target of Example 1 may optionally include an etch stop layer containing a light-absorbing material.

[0073] In Example 3, the object of any of Examples 1 to 2 may optionally include a bridging having the opening in the first glass layer, wherein the bridging is attached to the etch stop layer.

[0074] In Example 4, the object of Example 3 may optionally include a through-glass conductive via extending through the second glass layer and the etch stop layer, wherein the through-glass conductive via is electrically attached to the bridging.

[0075] In Example 5, the object of either Example 3 or 4 may optionally include the bridge, which includes at least one through-bridging conductive via.

[0076] In Example 6, the target of Examples 3 to 5 may optionally include the bridging, which includes at least one interconnect wiring.

[0077] In Example 7, the object of any of Examples 1 to 6 may optionally include at least one conductive wiring extending from the second surface of the first glass layer to the second surface of the second glass layer.

[0078] In Example 8, the object of Example 7 may optionally include at least one conductive wiring, the at least one conductive wiring comprising: an inter-glass conductive trace within the etch stop layer; a first portion of the conductive wiring extending through the second glass layer and electrically attached to the inter-glass conductive trace; and a second portion of the conductive wiring extending through the first glass layer and electrically attached to the inter-glass conductive trace.

[0079] Example 9 is an apparatus comprising an electronic substrate, wherein the electronic substrate comprises: a first glass layer having a first surface and an opposing second surface; a second glass layer having a first surface and an opposing second surface; an etch stop layer adjacent to the first surface of the first glass layer and adjacent to the first surface of the second glass layer, wherein the first glass layer includes an opening extending from the first surface of the first glass layer to the second surface of the first glass layer at the etch stop layer; a bridging element having the opening in the first glass layer, wherein the bridging element is attached to the etch stop layer; and at least one integrated circuit device electrically attached to the electronic substrate.

[0080] In Example 10, the target of Example 9 may optionally include an etch stop layer comprising a light-absorbing material.

[0081] In Example 11, the object of any of Examples 9 to 10 may optionally include at least one conductive wiring extending from the second surface of the first glass layer to the second surface of the second glass layer.

[0082] In Example 12, the object of Example 11 may optionally include the at least one conductive wiring, the at least one conductive wiring comprising: an inter-glass conductive trace within the etch stop layer; a first portion of the conductive wiring extending through the second glass layer and electrically attached to the inter-glass conductive trace; and a second portion of the conductive wiring extending through the first glass layer and electrically attached to the inter-glass conductive trace.

[0083] In Example 13, the object of any of Examples 9 to 12 may optionally include a through-glass conductive via extending through the second glass layer and the etch stop layer, wherein the through-glass conductive via is electrically attached to the bridging.

[0084] In Example 14, the object of Example 13 may optionally include the bridging, the bridging including a through-bridging conductive via, wherein the through-glass conductive via is electrically attached to the through-bridging conductive via.

[0085] In Example 15, the object of any of Examples 9 to 14 may optionally include the bridging, which includes at least one interconnect wiring, wherein the at least one integrated circuit device includes a first integrated circuit device and a second integrated circuit device, and the at least one interconnect wiring electrically couples the first integrated circuit device and the second integrated circuit device.

[0086] Example 16 is an electronic system comprising a board and an integrated circuit package electrically attached to the board, wherein the integrated circuit package includes an electronic substrate, wherein the electronic substrate includes: a first glass layer having a first surface and an opposing second surface; a second glass layer having a first surface and an opposing second surface; an etch stop layer adjacent to the first surface of the first glass layer and adjacent to the first surface of the second glass layer, wherein the first glass layer includes an opening extending from the first surface of the first glass layer to the second surface of the first glass layer at the etch stop layer; and a bridging layer having the opening in the first glass layer, wherein the bridging layer is attached to... The bridging is connected to the etch stop layer, wherein the bridging includes at least one interconnect wiring; a plurality of conductive wirings extending from the second surface of the first glass layer to the second surface of the second glass layer; and a first integrated circuit device electrically attached to one of the plurality of conductive wirings of the electronic substrate and at least one interconnect wiring of the electronic substrate; and a second integrated circuit device electrically attached to the electronic substrate, wherein the electronic substrate is attached to another of the plurality of conductive wirings of the electronic substrate and the at least one interconnect wiring of the electronic substrate, wherein the at least one interconnect wiring is electrically connected to the first integrated circuit device and the second integrated circuit device.

[0087] In Example 17, the target of Example 16 may optionally include an etch stop layer comprising a light-absorbing material.

[0088] In Example 18, the object of any of Examples 16 to 17 may optionally include the at least one conductive wiring, the at least one conductive wiring comprising an inter-glass conductive trace within the etch stop layer; a first portion of the conductive wiring extending through the second glass layer and electrically attached to the inter-glass conductive trace; and a second portion of the conductive wiring extending through the first glass layer and electrically attached to the inter-glass conductive trace.

[0089] In Example 19, the object of any of Examples 14 to 16 may optionally include a through-glass conductive via extending through the second glass layer and the etch stop layer, wherein the through-glass conductive via is electrically attached to the bridging.

[0090] In Example 20, the object of Example 19 may optionally include the bridging, the bridging including at least one through-bridging conductive via, wherein the through-glass conductive via is electrically attached to the through-bridging conductive via.

[0091] Since the embodiments of the invention have been described in such detail, it should be understood that the invention as defined by the appended claims is not limited to the specific details set forth in the foregoing description, as many obvious variations are possible without departing from its spirit or scope.

[0092] 100: Integrated circuit package 110: Electronic substrate 120: First glass layer 122: First Surface 124: Second Surface 130: Second glass layer 132: First Surface 134: Second Surface 140: Etching Stop Layer 142: Bridging opening 144: Sidewall 150: Bridging 152: First Surface 154: Second Surface 156: Side view 158: Through-bridging conductive via 160: Device-to-device interconnect wiring 162: Joint Pad 164: Joint Pad 166: Adhesive layer 168: Interconnection Layer 170: Molding material 172: High-density through-hole conductive via 174: Through-hole conductive hole 180: Conductive wiring through glass 182: First through-hole glass conductive via 184: Second through-glass conductive via 210: First signal routing layer 212: Conductive traces 214: High-density conductive traces 216: Dielectric layer 222: Conductive via 224: High-density conductive via 232: Device to substrate bonding pad 234: High-density device to substrate bonding pad 250: Second signal routing layer 252: Conductive via 256: Dielectric layer 258: Conductive traces 260: Substrate-to-board bonding pad 262: External Interconnection 264: Conductive traces between glass panes 2701: First integrated circuit device 2702: Second integrated circuit device 2721: First integrated circuit device bonding pad 2722: Second integrated circuit device bonding pad 2741: First Surface 2742: First Surface 280: Device-to-board interconnect 282: Conductive wiring, part one 284: Conductive Wiring Part 2 286: Flange 292: Bottom filling material 294: Packaging Materials 302: Opening 304: Opening 306: Opening 308: Mold Opening 402: Opening 404: Opening 406: Mold Opening 500: Computing device 501: Outer shell 502: Board / Mother Board 504: Processor 506A: Communication chip 506B: Communication chip 508: Volatile Memory 510: Non-volatile memory / ROM 512: Flash Memory 514: CPU / Graphics CPU 516: Chipset

Claims

1. An electronic device comprising: a first glass layer having a first surface and an opposing second surface; a second glass layer having a first surface and an opposing second surface; and an etch stop layer adjacent to the first surface of the first glass layer and the first surface of the second glass layer, wherein... The first glass layer includes an opening extending from the first surface of the first glass layer to the second surface of the first glass layer at the etch stop layer, a bridge within the opening of the first glass layer, wherein the bridge is attached to the etch stop layer; and a through-glass conductive via extending through the second glass layer and the etch stop layer, wherein the through-glass conductive via is electrically attached to the bridge.

2. The electronic device as described in claim 1, wherein, The etch stop layer contains light-absorbing material.

3. The electronic device as described in claim 1, wherein, The etch stop layer comprises either a polymer or a metal oxide.

4. The electronic device as described in claim 1, wherein, The bridging includes a through-bridging conductive via, wherein the through-glass conductive via is electrically attached to the through-bridging conductive via.

5. The electronic device of claim 1 further includes at least one conductive wiring extending from the second surface of the first glass layer to the second surface of the second glass layer.

6. The electronic device of claim 1 further comprises: an electronic substrate including the first glass layer, the second glass layer and the etch stop layer; and an integrated circuit device and / or board electrically attached to the electronic substrate.

7. An electronic device comprising: a first glass layer having a first surface and an opposing second surface; a second glass layer having a first surface and an opposing second surface; and a layer adjacent to the first surface of the first glass layer and adjacent to the first surface of the second glass layer, wherein... The layer comprises one of a polymer and a metal oxide, and wherein the first glass layer includes an opening extending from the first surface of the first glass layer to the second surface of the first glass layer; and a bridging in the opening of the first glass layer, wherein the bridging is attached to the layer; and a through-glass conductive via extending through the second glass layer and the layer, wherein the through-glass conductive via is electrically attached to the bridging.

8. The electronic device as described in claim 7, wherein, The layer contains a metal oxide, which contains aluminum and oxygen.

9. The electronic device as described in claim 7, wherein, The layer contains a polymer, which is one of polytetrafluoroethylene, polyethylene, polyvinyl chloride, polyvinylidene fluoride, or ultra-high molecular weight polyethylene.

10. The electronic device as described in claim 7, wherein, The bridging includes a through-bridging conductive via, wherein the through-glass conductive via is electrically attached to the through-bridging conductive via.

11. The electronic device of claim 7 further includes at least one conductive wiring extending from the second surface of the first glass layer to the second surface of the second glass layer.

12. The electronic device of claim 7 further comprises: an electronic substrate including the first glass layer, the second glass layer and the layer; and an integrated circuit device and / or board electrically attached to the electronic substrate.

13. An electronic device comprising: a first glass layer having a first surface and an opposing second surface; a second glass layer having a first surface and an opposing second surface; and an etch stop layer adjacent to the first surface of the first glass layer and adjacent to the first surface of the second glass layer, wherein... The first glass layer includes an opening extending from the first surface of the first glass layer to the second surface of the first glass layer at the etch stop layer; and at least one conductive wiring extending from the second surface of the first glass layer to the second surface of the second glass layer.

14. The electronic device as described in claim 13, wherein, The etch stop layer contains light-absorbing material.

15. The electronic device as described in claim 13, wherein, The etch stop layer comprises either a polymer or a metal oxide.

16. The electronic device of claim 13 further includes a bridge having the opening in the first glass layer, wherein, The bridge is attached to the etch stop layer.

17. The electronic device as described in claim 13, wherein, The at least one conductive wiring includes: an inter-glass conductive trace within the etch stop layer; a first portion of the conductive wiring extending through the second glass layer and electrically attached to the inter-glass conductive trace; and a second portion of the conductive wiring extending through the first glass layer and electrically attached to the inter-glass conductive trace.

18. The electronic device of claim 13 further comprises: an electronic substrate including the first glass layer, the second glass layer and the etch stop layer; and an integrated circuit device and / or board electrically attached to the electronic substrate.

19. An electronic device comprising: a first glass layer having a first surface and an opposing second surface; a second glass layer having a first surface and an opposing second surface; and a layer adjacent to the first surface of the first glass layer and adjacent to the first surface of the second glass layer, wherein... The layer comprises one of a polymer and a metal oxide, wherein the first glass layer includes an opening extending from the first surface of the first glass layer to the second surface of the first glass layer; and at least one conductive wiring extending from the second surface of the first glass layer to the second surface of the second glass layer.

20. The electronic device as described in claim 19, wherein, The layer contains a metal oxide, which contains aluminum and oxygen.

21. The electronic device of claim 19, wherein the layer comprises a polymer, the polymer being one of polytetrafluoroethylene, polyethylene, polyvinyl chloride, polyvinylidene fluoride, or ultra-high molecular weight polyethylene.

22. The electronic device of claim 19 further includes a bridge having the opening in the first glass layer, wherein, The bridge is attached to this floor.

23. The electronic device as described in claim 19, wherein, The at least one conductive wiring includes: an inter-glass conductive trace within the layer; a first portion of the conductive wiring extending through the second glass layer and electrically attached to the inter-glass conductive trace; and a second portion of the conductive wiring extending through the first glass layer and electrically attached to the inter-glass conductive trace.

24. The electronic device of claim 19 further comprises: an electronic substrate including the first glass layer, the second glass layer and the layer; and at least one integrated circuit device electrically attached to the electronic substrate.

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