Package comprising integrated devices and bridge coupling top sides of integrated devices

Abstract

A package includes a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge, and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to the top of the first integrated device and the top of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

Description

[Technical Field]

[0001] This patent application claims priority and benefit to non-provisional application No. 17 / 357,811 filed on June 24, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth in their entirety below and for all applicable purposes.

[0002] Various features relate to the packaging of integrated devices. [Previous Technology]

[0003] The package may include a substrate and several integrated devices. The integrated devices can communicate with each other via the substrate. That is, electrical input and output signals can travel between the integrated devices via the substrate. The performance of the package may be constrained by the speed at which these electrical signals can travel between the integrated devices and / or the signal integrity between the integrated devices. There has always been a need to provide packages with better performance. [Summary of the Invention]

[0004] Various features involve the packaging of integrated devices.

[0005] One example provides a package including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge, and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to the top of the first integrated device and the top of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0006] Another embodiment provides an apparatus including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge interconnect device, and a second bridge interconnect device. The first bridge interconnect device is coupled to the first integrated device and the second integrated device. The first bridge interconnect device is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge interconnect device is coupled to the top of the first integrated device and the top of the second integrated device. The second bridge interconnect device is coupled to the first integrated device and the second integrated device. The second bridge interconnect device is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0007] Another example provides a method for manufacturing a package. The method provides a substrate. The method couples a first integrated device to the substrate. The method couples a second integrated device to the substrate. The method couples a first bridge to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to the top of the first integrated device and the top of the second integrated device. The method couples a second bridge to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

Implementation Method

[0022] In the following description, specific details are provided to provide a thorough understanding of the various aspects of this invention. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these aspects of this invention.

[0023] This application describes a package including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge, and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to the top of the first integrated device and the top of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device. The second bridge may be at least partially located in the substrate. The second bridge may be located above the substrate. The first integrated device may include one or more dies. The second integrated device may include one or more dies. This package can provide better signal integrity for input / output signals between integrated devices, thereby resulting in a package with better performance. Exemplary package including a bridge coupled to an integrated device.

[0024] FIG1 illustrates a cross-sectional outline view of package 100, which includes a substrate 102, an integration device 105 (e.g., a first integration device), an integration device 107 (e.g., a second integration device), a bridge 110, and a bridge 130. Package 100 is coupled to board 106 via a plurality of solder interconnects 124. Board 106 may include a printed circuit board (PCB).

[0025] The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Different substrates may have different numbers of metal layers. Different implementations may use different substrates for the substrate 102. The substrate 102 may include an embedded trace substrate (ETS), a laminated substrate, a coreless substrate, and / or a cored substrate. The substrate 202 may be manufactured using different processes, including ETS process, semi-additive process (SAP) process, and / or modified semi-additive process (mSAP).

[0026] Bridge 130 may be at least partially located in substrate 102. In some implementations, bridge 130 may be located in a cavity of substrate 102. Bridge 130 may be embedded in substrate 102. Bridge 130 may be a second bridge. Bridge 130 may include at least one bridge interconnect 132. As will be further described below, bridge 130 may include bridge dies and / or bridge structures. Bridge 130 may be a second bridge interconnect device. In some implementations, bridge 130 may be located above substrate 102. In some implementations, bridge 130 is not located in substrate 102.

[0027] The integrated device 105 is coupled to the substrate 102 via a plurality of solder interconnects 154. The integrated device 105 is also coupled to the bridge 130 via at least one of the plurality of solder interconnects 154a. The integrated device 107 is coupled to the substrate 102 via a plurality of solder interconnects 174. The integrated device 107 is also coupled to the bridge 130 via at least one of the plurality of solder interconnects 174a. The bridge 130 may be configured to provide at least one second electrical path between the integrated device 105 and the integrated device 107. For example, the at least one second electrical path between the integrated device 105 and the integrated device 107 may include at least one solder interconnect 154a, at least one bridge interconnect 132, and / or at least one solder interconnect 174a.

[0028] Bridge 110 may be coupled to the top of integrated device 105 via at least one solder interconnect 125. Bridge 110 may also be coupled to the top of integrated device 107 via at least one solder interconnect 127. Bridge 110 may be a first bridge. Bridge 110 may include at least one bridge interconnect 112. As will be further described below, bridge 110 may include bridge dies and / or bridge structures. Bridge 110 may be a first bridge interconnect device. Bridge 110 may be configured to provide at least one first electrical path between integrated device 105 and integrated device 107. For example, the at least one first electrical path between integrated device 105 and integrated device 107 may include at least one solder interconnect 125, at least one bridge interconnect 112, and / or at least one solder interconnect 127. In some implementations, one or more input / output (I / O) signals between integrated device 105 and integrated device 107 may be configured to travel through bridge 110 (e.g., configured to travel through at least one solder interconnect 125, at least one bridge interconnect 112, and at least one solder interconnect 127). In some implementations, input / output signals traveling through bridge 110 may have better signal integrity because the path is located further away from interconnects configured for other current (e.g., power) paths. In some implementations, bridge 110 provides a short electrical path between integrated device 105 and integrated device 107, thereby providing improved package performance. In some implementations, bridge 110 releases solder interconnects to the substrate for use in power and / or ground, thereby improving power distribution network (PDN) performance. In some implementations, signals between integrated device 105 and integrated device 107 may be configured to travel through the back side of integrated device 105 and / or the back side of integrated device 107. In some implementations, the top of the integration device 105 may include the back side of the integration device 105. In some implementations, the top of the integration device 107 may include the back side of the integration device 107. The back side of the integration device may be the side of the integration device that includes a substrate (e.g., silicon). The front side of the integration device may be the side opposite to the back side of the integration device.

[0029] Figure 2 illustrates a cross-sectional outline view of package 200, which includes a substrate 102, an integration device 105 (e.g., a first integration device), an integration device 107 (e.g., a second integration device), a bridge 110, and a bridge 130. Package 200 is similar to package 100. However, bridges 110 and 130 may be interconnected and coupled to integration devices 105 and 107 via a plurality of solder posts.

[0030] Integration device 105 is coupled to substrate 102 via a plurality of solder interconnects 254 and a plurality of solder interconnects 154. Integration device 105 is coupled to bridge 130 via at least one solder interconnect 254a and at least one solder interconnect 154a. Integration device 107 is coupled to substrate 102 via a plurality of solder interconnects 274 and a plurality of solder interconnects 174. Integration device 107 is coupled to bridge 130 via at least one solder interconnect 274a and at least one solder interconnect 174a. At least one second electrical path between integration device 105 and integration device 107 may include at least one solder interconnect 254a, at least one solder interconnect 154a, at least one bridge interconnect 132 (of bridge 130), at least one solder interconnect 274a, and / or at least one solder interconnect 174a.

[0031] Bridge 110 is coupled to the top of integrated device 105 via at least one solder post interconnect 225 and at least one solder interconnect 125. Bridge 110 is coupled to the top of integrated device 107 via at least one solder post interconnect 227 and at least one solder interconnect 127. At least one first electrical path between integrated device 105 and integrated device 107 may include at least at least one solder interconnect 125, one solder post interconnect 225, at least one bridge interconnect 112 (of bridge 110), at least one solder post interconnect 227, and / or at least one solder interconnect 127.

[0032] As will be further described below, integration device 105 may include one or more integration devices (e.g., dies). Similarly, integration device 107 may include one or more integration devices (e.g., dies).

[0033] FIG3 illustrates a cross-sectional outline view of package 300, which includes a substrate 102, an integration device 305 (e.g., a first integration device), an integration device 307 (e.g., a second integration device), a bridge 110, and a bridge 130.

[0034] The integrated device 305 may be a package including a first die 351, a second die 353, and an encapsulation layer 356. The first die 351 and / or the second die 353 may be examples of the integrated device. The second die 353 may be coupled to the first die 351 via a plurality of solder interconnects 354. The first die 351 may be located above (e.g., on top of) the second die 353. The encapsulation layer 356 may be located between the first die 351 and the second die 353. In some implementations, the encapsulation layer 356 may at least partially encapsulate the first die 351 and / or the second die 353. The integrated device 305 is coupled to the substrate 102 and the bridge 130 via a plurality of solder interconnects 154.

[0035] As will be further described below, the first die 351 and the second die 353 may be aligned and positioned in different orientations within the integration device 305. The first die 351 may include a front side and a back side. The second die 353 may also include a front side and a back side. In some implementations, the front side of the first die 351 may face the front side of the second die 353. In some implementations, the front side of the second die 353 may face the back side of the first die 351. In some implementations, the back side of the second die 353 may face the front side of the first die 351. The back side of a die may be the side of the die that includes the die substrate (e.g., silicon). The front side of a die may be the side opposite to the back side of the die.

[0036] The integrated device 307 may be a package including a third die 371, a fourth die 373, and an encapsulation layer 376. The third die 371 and / or the fourth die 373 may be examples of the integrated device. The fourth die 373 may be coupled to the third die 371 via a plurality of solder interconnects 374. The third die 371 may be located above (e.g., on top of) the fourth die 373. The encapsulation layer 376 may be located between the third die 371 and the fourth die 373. In some implementations, the encapsulation layer 376 may at least partially encapsulate the third die 371 and / or the fourth die 373. The integrated device 307 is coupled to the substrate 102 and the bridge 130 via a plurality of solder interconnects 174. The encapsulation layer (e.g., 356, 376) may include a molding compound, resin, and / or epoxy resin. The encapsulation layer (e.g., 356, 376) may be an encapsulation device.

[0037] As will be further described below, the third die 371 and the fourth die 373 can be aligned and positioned in different directions within the integration device 307. The third die 371 may include a front side and a back side. The fourth die 373 may also include a front side and a back side. In some implementations, the front side of the third die 371 may face the front side of the fourth die 373. In some implementations, the front side of the fourth die 373 may face the back side of the third die 371. In some implementations, the back side of the fourth die 373 may face the front side of the third die 371.

[0038] Different implementations may position the dies in the package 300 differently. In some implementations, the back side of the first die 351 and / or the back side of the third die 371 may face the bridge 110. In some implementations, the front side of the first die 351 and / or the front side of the third die 371 may face the bridge 110. In some implementations, the back side of the second die 353 and / or the back side of the fourth die 373 may face the bridge 130 and / or the substrate 102. In some implementations, the front side of the second die 353 and / or the front side of the fourth die 373 may face the bridge 130 and / or the substrate 102.

[0039] Bridge 110 is coupled to a first die 351 via at least one solder interconnect 125. Bridge 110 is coupled to a third die 371 via at least one solder interconnect 127. The first die 351 may be configured to be electrically coupled to the third die 371 via Bridge 110. At least one first electrical path (e.g., for input / output signals) between the first die 351 and the third die 371 may include at least one solder interconnect 125, at least one bridge interconnect 112, and / or at least one solder interconnect 127. Bridge 110 provides a shorter electrical path between the first die 353 and the third die 371 because it does not have to travel through the second die 353, the substrate 102, the bridge 130, and / or the fourth die 373.

[0040] Bridge 130 is coupled to a second die 353 via at least one solder interconnect 154a. Bridge 130 is coupled to a fourth die 373 via at least one solder interconnect 174a. The second die 353 may be configured to be electrically coupled to the fourth die 373 via bridge 130. At least one second electrical path (e.g., for input / output signals) between the second die 353 and the fourth die 373 may include at least one solder interconnect 154a, at least one bridge interconnect 132, and / or at least one solder interconnect 174a.

[0041] In some implementations, power to the integrated device 305 (including power to the first die 351 and / or the second die 353) may be provided via the substrate 102 (e.g., a plurality of interconnects 122) and at least one solder interconnect 154. In some implementations, power to the first die 351 may be provided via the substrate 102 (e.g., a plurality of interconnects 122), at least one solder interconnect 154, the second die 353, and at least one solder interconnect 354. In some implementations, power to the integrated device 307 (including power to the third die 371 and / or the fourth die 373) may be provided via the substrate 102 (e.g., a plurality of interconnects 122) and at least one solder interconnect 174. In some implementations, power to the third die 371 may be provided via the substrate 102 (e.g., a plurality of interconnects 122), at least one solder interconnect 174, the fourth die 373, and at least one solder interconnect 374. Note that the integration device 305 may include more than two stacked dies. Similarly, the integration device 307 may include more than two stacked dies.

[0042] FIG4 illustrates a cross-sectional profile view of the implementation of package 300. As shown in FIG4, a first die 351 is coupled to a second die 353 such that the front side of the first die 351 faces the front side of the second die 353. The back side of the die may be a side including a die substrate (e.g., silicon). The front side of the die may be a side opposite to the back side of the die. The first die 351 includes a plurality of through-substrate vias (TSVs) 451. The plurality of TSVs 451 may be located on the back side of the first die 351. The second die 353 includes a plurality of through-substrate vias (TSVs) 453. The plurality of TSVs 453 may be located on the back side of the second die 353.

[0043] Similarly, the third die 371 is coupled to the fourth die 373 such that the front side of the third die 371 faces the front side of the fourth die 373. The third die 371 includes a plurality of through-substrate vias (TSVs) 471. The plurality of TSVs 471 may be located on the back side of the third die 371. The fourth die 373 includes a plurality of through-substrate vias (TSVs) 473. The plurality of TSVs 473 may be located on the back side of the fourth die 373.

[0044] In some implementations, the back side of the first die 351 and the back side of the third die 371 may face the bridge 110. In some implementations, the front side of the first die 351 and the front side of the third die 371 may face the substrate 102 and / or the bridge 130. In some implementations, at least one current (e.g., an input / output signal) may travel between the first die 351 and the third die 371 through a plurality of TSVs 451, at least one solder interconnect 125, at least one bridge interconnect 112, at least one solder interconnect 127, and a plurality of TSVs 471.

[0045] In some implementations, at least one current (e.g., an input / output signal) may travel between the second die 353 and the fourth die 373 through a plurality of TSVs 453, at least one solder interconnect 154a, at least one bridge interconnect 132, at least one solder interconnect 174a, and a plurality of TSVs 473.

[0046] In some implementations, the first die 351 and the second die 353 may each be configured to be electrically coupled to the substrate 102. In some implementations, at least one current (e.g., power) between the first die 351 and the substrate 102 may travel through a plurality of solder interconnects 154, a plurality of TSVs 453, the second die 353, and the plurality of solder interconnects 354. In some implementations, at least one current (e.g., power) between the second die 353 and the substrate 102 may travel through the plurality of solder interconnects 154 and the plurality of TSVs 453.

[0047] In some implementations, the third die 371 and the fourth die 373 may each be configured to be electrically coupled to the substrate 102. In some implementations, at least one current (e.g., power) between the third die 371 and the substrate 102 may travel through a plurality of solder interconnects 174, a plurality of TSVs 473, the fourth die 373, and a plurality of solder interconnects 354. In some implementations, at least one current (e.g., power) between the fourth die 373 and the substrate 102 may travel through a plurality of solder interconnects 174 and a plurality of TSVs 473.

[0048] Figure 4 illustrates one example of how stacked dies can be implemented. However, as mentioned above, dies can be arranged in different directions and may include different numbers of dies. This invention illustrates and describes that bridge 130 is at least partially located (e.g., embedded) in substrate 102. However, in some implementations, bridge 130 may be located above substrate 102. For example, bridge 130 may be located between the integration device and substrate 102. Thus, in some implementations, bridge 130 is not located in substrate 102.

[0049] Figures 3 and 4 illustrate examples of packages in which a first integrated device (e.g., 305) includes two dies and a second integrated device (307) includes two dies. However, the package may include other configurations and combinations of integrated devices. For example, the first integrated device may include one die and the second integrated device may include two dies. In another example, the first integrated device may include two dies and the second integrated device may include three or more dies. In some implementations, the package may include a first integrated device, a second integrated device, a third integrated device, and a fourth integrated device, all of which are coupled to a substrate. Bridges may be coupled to the top of the first and second integrated devices. Another bridge may be coupled to the top of the third and fourth integrated devices. The top of the integrated device may include the side of the integrated device facing away from the substrate.

[0050] The integrated device (e.g., 105, 107, 305, 307) may include a die (e.g., a semiconductor bare die). The integrated device may include a wafer, a wafer set, a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a GaAs-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light-emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a processor, a memory, a power manager integrated device, and / or combinations thereof. The integrated device (e.g., 105, 107, 305, 307) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0051] Figure 5 illustrates a view of bridge 500. Bridge 500 may be a bridge die. Bridge 500 may be a passive bridge die. Bridge 500 may represent bridge 110 and / or bridge 130 in this case. Bridge 500 may be a bridge interconnect device. Bridge 500 includes a die substrate 510 (e.g., a bridge die substrate), at least one bridge interconnect 512, a passivation layer 520, a plurality of under-bump interconnects 514, and a plurality of solder interconnects 530. Die substrate 510 may include silicon (Si). At least one bridge interconnect 512 may be coupled to the plurality of under-bump interconnects 514. In some implementations, at least one bridge interconnect 512 may include multiple rows of bridge interconnects. The plurality of solder interconnects 530 may be coupled to the plurality of under-bump interconnects 514. Note that the plurality of under-bump interconnects 514 may be considered as part of the bridge interconnects used for bridge 500. Thus, bridge interconnect may also refer to at least one under-bump interconnect of the bridge. Bridge 500 is configured to allow one or more currents (e.g., input / output signals) to travel through under-bump interconnect 514a, at least one bridge interconnect 512, and under-bump interconnect 514b.

[0052] Figure 6 illustrates a view of bridge 600. Bridge 600 may be a bridge structure and / or a bridge substrate. Bridge 600 may represent bridge 110 and / or bridge 130 in this embodiment. Bridge 600 may be a bridge interconnect device. Bridge 600 includes at least one dielectric layer 610, at least one bridge interconnect 612, and a plurality of solder interconnects 530. At least one bridge interconnect 612 includes bridge interconnect 612a (e.g., bridge via, bridge pad), bridge interconnect 612c (e.g., bridge trace), and bridge interconnect 612b (e.g., bridge via, bridge pad). Bridge 600 is configured to allow one or more currents (e.g., input / output signals) to travel through bridge interconnects 612a, bridge interconnect 612c, and bridge interconnect 612b. In some implementations, there are several rows of bridge interconnects 612a, bridge interconnect 612c, and bridge interconnect 612b.

[0053] Figures 7 and 8 illustrate exemplary signal integrity diagrams between two integrated devices. Figure 7 illustrates an exemplary diagram 700 of signal integrity between two integrated devices, where a signal travels through a non-bridged connection. Figure 8 illustrates an exemplary diagram 800 of signal integrity between two integrated devices, where a signal travels through a bridge coupled to the top of the integrated device. Diagram 700 illustrates an eye diagram opening 710. Diagram 800 illustrates an eye diagram opening 810. The eye diagram opening 810 is larger than the eye diagram opening 710, which may indicate that the signal traveling through the bridge can have better signal integrity, including less crosstalk, improved differential insertion loss, improved in-line skew, and / or improved mode conversion signals compared to signals that may not travel through the bridge. These improvements in signal integrity may be due to shorter wiring distances between the integrated devices and / or greater availability of power and ground bumps on the integrated devices. In other words, the bumps and / or solder interconnects that are typically used for signal routing between the integrated device and the substrate can be replaced for power and ground, which can ultimately help improve the performance of the power distribution network (PDN) of the integrated device and package.

[0054] Various packages have been described, and the processes for manufacturing the packages will now be described below. Exemplary processes for manufacturing a package including a bridge coupled to an integrated device.

[0055] Figures 9A–9C illustrate exemplary steps for providing or manufacturing a package including a bridge coupled to an integrated device. In some implementations, the steps of Figures 9A–9C may be used to provide or manufacture the package 300 of Figure 3, or any package described in this document.

[0056] It should be noted that the processes in Figures 9A–9C can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be substituted or replaced without departing from the spirit of this invention. Different implementations can manufacture the package differently.

[0057] As shown in FIG9A, stage 1 illustrates the state after the substrate 102 is provided. The substrate 102 may be manufactured or supplied by a supplier. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include different numbers of metal layers. The substrate 102 may include a laminated substrate, a cored substrate, and / or a coreless substrate (e.g., ETS). Examples of substrate manufacturing are further described below, at least in FIG11A–11C.

[0058] Stage 2 illustrates the state after cavity 930 is formed in substrate 102. Different implementations may form cavity 930 differently. In some implementations, a laser process (e.g., laser ablation) may be used to form cavity 930. Different implementations may have cavities with different sizes, shapes, and depths. Note that when substrate 102 is provided in stage 1 of FIG. 9A, cavity 930 may already be formed in substrate 102.

[0059] As shown in FIG9B, stage 3 illustrates the state after the bridge 130 has been at least partially placed in the cavity 930 of the substrate 102. In some implementations, an adhesive (not shown) may be used to place and couple the bridge 130 to the substrate 102. The bridge 130 includes at least one bridge interconnect 132. The bridge 130 may include a bridge 500 or a bridge 600. Note that the bridge 130 may be provided during different stages of the process. For example, the bridge 130 may be coupled to an integrated device before it is coupled to the substrate 102. In some implementations, the bridge 130 may be coupled to the integrated device after it has been coupled to the substrate 102.

[0060] Phase 4 illustrates the state after the integrated device 305 and integrated device 307 are coupled to the substrate 102. Integrated device 305 is coupled to the substrate 102 via a plurality of solder interconnects 154. Integrated device 305 is also coupled to the substrate 130 via a plurality of solder interconnects 154. Integrated device 307 is coupled to the substrate 102 via a plurality of solder interconnects 174. Integrated device 307 is also coupled to the bridge 130 via a plurality of solder interconnects 174. As shown in Phase 4, integrated device 305 includes a first die 351 and a second die 353. Similarly, integrated device 307 includes a third die 371 and a fourth die 373. A solder reflow process can be used to couple integrated device 305 and integrated device 307 to the substrate 102 and the bridge 130. Note that in some implementations, a plurality of interconnecting posts (as depicted in FIG. 2) may be used to couple integrated devices 305 and 307 to substrate 102 and bridge 130. Thus, in some implementations, coupling integrated devices 305 and 307 to substrate 102 may also include coupling integrated devices 305 and 307 to bridge 130. However, in some implementations, integrated devices 305 and 307 may be coupled to bridge 130 during different processes. For example, bridge 130 may be coupled to integrated devices 305 and 307, and subsequently, integrated devices 305, 307, and bridge 130 may be coupled to substrate 102. In another example, bridge 130 may be coupled to integrated devices 305 and 307 after they have been coupled to substrate 102. For example, a cavity extending through substrate 102 may exist in substrate 102. Integration devices 305 and 307 can be coupled to substrate 102, and bridge 130 can be coupled to integration devices 305 and 307 via a cavity extending through substrate 102.

[0061] As shown in FIG9C, stage 5 illustrates the state after bridge 110 is coupled to the top of integrated device 305 and integrated device 307. Bridge 110 may be coupled to integrated device 305 via at least one solder interconnect 125. Bridge 110 may be coupled to integrated device 307 via at least one solder interconnect 127. A solder reflow process may be used to couple bridge 110 to integrated device 305 and integrated device 307. Note that in some implementations, a plurality of solder pillar interconnects (as described in FIG2) may be used to couple bridge 110 to integrated device 305 and integrated device 307.

[0062] Stage 6 illustrates a state in which a plurality of solder interconnects 124 are coupled to the bottom surface of substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 124 to substrate 102. The plurality of solder interconnects 124 can be coupled to pad interconnects in a plurality of interconnects 122. Stage 6 may illustrate package 300. An exemplary flowchart of a method for manufacturing a package including bridges coupled to an integrated device.

[0063] In some implementations, manufacturing the package includes several processes. Figure 10 illustrates an exemplary flowchart of a method 1000 for providing or manufacturing a package including a bridge coupled to an integrated device. In some implementations, the method 1000 of Figure 10 may be used to provide or manufacture the package 300 of Figure 3. However, the method 1000 of Figure 10 may be used to manufacture any package in this case.

[0064] It should be noted that the method of Figure 10 can combine one or more processes to simplify and / or clarify the method for providing or manufacturing the package. In some implementations, the order of the processes can be changed or modified.

[0065] The method (at 1005) provides a substrate (e.g., 102). The substrate 102 may include at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include different numbers of metal layers. The substrate 102 may include a laminated substrate, a cored substrate, and / or a coreless substrate (e.g., ETS). The substrate may be supplied by a supplier or manufactured. Examples of substrate manufacturing are further described below, at least in Figures 11A–11C. Stage 1 of Figure 9A illustrates and describes an example of providing a substrate.

[0066] The method (at 1010) forms a cavity (e.g., 930) in the substrate (e.g., 102). Different implementations may form the cavity 930 differently. In some implementations, a laser process (e.g., laser ablation) may be used to form the cavity 930. Different implementations may have cavities of different sizes, shapes, and depths. In some implementations, the cavity 930 may extend through the entire substrate 102. Note that when the substrate 102 is provided (at 1005), the cavity 930 may already be formed in the substrate 102. Stage 2 of FIG9A illustrates and describes an example of a cavity formed in the substrate.

[0067] The method (at 1015) places and couples a bridge (e.g., 130) into a cavity 930 of substrate 102. Bridge 130 may be at least partially placed in cavity 930. In some implementations, an adhesive (not shown) may be used to place and couple bridge 130 into cavity 930 of substrate 102. Bridge 130 includes at least one bridge interconnect 132. Bridge 130 may include bridge 500 or bridge 600. Note that bridge 130 may be coupled to substrate 102 in different ways. In some implementations, bridge 130 may be coupled to an integrated device before being coupled to substrate 102 or before being positioned on substrate 102. Phase 3 of FIG9C illustrates and describes an example of a bridge at least partially placed in a cavity of the substrate.

[0068] This method (at 1020) couples a plurality of integrated devices (e.g., 105, 107, 305, 307) to substrate 102 and bridge 130. The plurality of integrated devices may be coupled to substrate 102 and bridge 130 via a plurality of solder interconnects (e.g., 154, 174) and / or a plurality of solder post interconnects (e.g., 254, 274). A solder reflow process may be used to couple the integrated devices (e.g., 105, 107, 305, 307) to substrate 102 and bridge 130. In some implementations, bridge 130 may be coupled to the integrated devices before they are coupled to substrate 102. Note that in some implementations, a plurality of solder post interconnects (as described in Figure 2) may be used to couple the integrated devices to substrate 102 and bridge 130. Stage 4 of Figure 9B illustrates and describes an example of coupling integrated devices to the substrate and bridge.

[0069] This method (at 1025) couples a bridge (e.g., 110) to the top of a plurality of integrated devices. For example, bridge 110 may be coupled to the top of integrated device 305 and the top of integrated device 307. Bridge 110 may be coupled to integrated device 305 via at least one solder interconnect 125. Bridge 110 may be coupled to integrated device 307 via at least one solder interconnect 127. A solder reflow process may be used to couple bridge 110 to integrated device 305 and integrated device 307. Note that in some implementations, a plurality of solder pillar interconnects (as depicted in Figure 2) may be used to couple bridge 110 to integrated device 305 and integrated device 307. Stage 5 of Figure 9C illustrates and describes an example of coupling a bridge to an integrated device.

[0070] This method (at 1030) couples a plurality of solder interconnects (e.g., 124) to the bottom surface of a substrate (e.g., 102). A solder reflow process can be used to couple the plurality of solder interconnects 124 to the substrate 102. The plurality of solder interconnects 124 can be coupled to pad interconnects in a plurality of interconnects 122 of the substrate 102. Stage 6 of FIG9C illustrates and describes an example of solder interconnects coupled to a substrate. Exemplary process for manufacturing a substrate.

[0071] In some implementations, manufacturing the substrate includes several processes. Figures 11A-11C illustrate exemplary processes for providing or manufacturing the substrate. In some implementations, the processes of Figures 11A-11C can be used to provide or manufacture the substrate 202 and / or substrate 204 of Figure 2. However, the processes of Figures 11A-11C can be used to manufacture any substrate described in this case. In some implementations, at least some forms of the processes of Figures 11A-11C can be used to manufacture the bridge 600.

[0072] It should be noted that the processes in Figures 11A–11C may be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this application.

[0073] As shown in FIG11A, stage 1 illustrates the state after a carrier 1100 is provided and a metal layer is formed on the carrier 1100. The metal layer may be patterned to form interconnects 1102. The metal layer and interconnects may be formed using plating and etching processes. In some implementations, the carrier 1100 may be provided with a metal layer that is patterned to form interconnects 1102.

[0074] Stage 2 illustrates the state after the dielectric layer 1120 is formed on the carrier 1100 and the interconnect 1102. The dielectric layer 1120 can be formed using a deposition and / or lamination process. The dielectric layer 1120 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0075] Stage 3 illustrates the state after a plurality of cavities 1110 have been formed in the dielectric layer 1120. The plurality of cavities 1110 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0076] Stage 4 illustrates the state after interconnects 1112 are formed in and over the dielectric layer 1120 (including in and over the plurality of cavities 1110). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0077] Stage 5 illustrates the state after another dielectric layer 1122 is formed on top of dielectric layer 1120. Dielectric layer 1122 can be formed using deposition and / or lamination processes. Dielectric layer 1122 can be made of the same material as dielectric layer 1120. However, different implementations may use different materials for the dielectric layer.

[0078] As shown in FIG11B, stage 6 illustrates the state after a plurality of cavities 1130 are formed in the dielectric layer 1122. The cavities 1130 can be formed using an etching process or a laser process.

[0079] Stage 7 illustrates the state after interconnects 1144 are formed in and over the dielectric layer 1122 (including in and over the plurality of cavities 1130). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0080] Stage 8 illustrates the state after another dielectric layer 1124 is formed on top of dielectric layer 1122. Dielectric layer 1124 can be formed using deposition and / or lamination processes. Dielectric layer 1124 can be made of the same material as dielectric layer 1120. However, different implementations may use different materials for the dielectric layer.

[0081] Stage 9 illustrates the state after a plurality of cavities 1140 have been formed in the dielectric layer 1124. The cavities 1140 can be formed using an etching process or a laser process.

[0082] As shown in FIG11C, stage 10 illustrates the state after interconnects 1116 are formed in and over dielectric layer 1124 (including in and over the plurality of cavities 1140). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using plating processes.

[0083] Some or all of interconnects 1102, 1112, 1114 and / or 1116 may define a plurality of interconnects 122 of substrate 102. Dielectric layers 1120, 1122, 1124 may be represented by at least one dielectric layer 120.

[0084] Stage 11 illustrates the state after the carrier 1100 is decoupled from the dielectric layer 1150 (e.g., removed, ground away) to leave the substrate 102 including at least one dielectric layer 120 and a plurality of interconnects 122.

[0085] Stage 12 illustrates the state after the formation of the first solder mask 1160 and the second solder mask 1162 on the substrate 102. The first solder mask 1160 and the second solder mask 1162 can be formed using a deposition process. In some implementations, a solder mask layer may not be formed or may be formed on at least one dielectric layer 1150.

[0086] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or solid vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. An exemplary flowchart of a method for manufacturing a substrate is provided.

[0087] In some implementations, manufacturing the substrate includes several processes. FIG12 illustrates an exemplary flowchart of a method 1200 for providing or manufacturing a substrate. In some implementations, method 1200 of FIG12 can be used to provide or manufacture the substrates(s) of FIG1–4. For example, method 1200 of FIG12 can be used to manufacture substrate 102.

[0088] It should be noted that the method of Figure 12 can combine one or more processes to simplify and / or clarify the method for providing or manufacturing the substrate. In some implementations, the order of the processes can be changed or modified.

[0089] The method (at 1205) provides a carrier 1100. Different implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or a carrier strip. Figure 11A illustrates and describes an example of the carrier provided in stage 1.

[0090] The method (at 1210) forms a metal layer on a carrier 1100. This metal layer can be patterned to form interconnects. A plating process can be used to form the metal layer and the interconnects. In some implementations, the carrier may include a metal layer. The metal layer on the carrier can be patterned to form interconnects (e.g., 1102). Phase 1 of Figure 11A illustrates and describes an example of forming a metal layer and interconnects on a carrier.

[0091] The method (at 1215) forms a dielectric layer 1120 over a carrier 1100 and an interconnect 1102. The dielectric layer can be formed using deposition and / or lamination processes. The dielectric layer 1120 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1110) within the dielectric layer 1120. These cavities can be formed using etching processes (e.g., photolithography) or laser processes. Stages 2–3 of Figure 11A illustrate and depict examples of forming a dielectric layer and forming cavities within it.

[0092] This method (at 1220) forms interconnects in and over the dielectric layer. For example, interconnects 1112 may be formed in and over the dielectric layer 1120. These interconnects may be formed using a plating process. Forming interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 4 of FIG11A illustrates and describes an example of forming interconnects in and over the dielectric layer.

[0093] The method (at 1225) forms a dielectric layer 1122 over the dielectric layer 1120 and these interconnects. The dielectric layer can be formed using deposition and / or lamination processes. The dielectric layer 1122 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1130) in the dielectric layer 1122. These cavities can be formed using etching or laser processes. Figures 11A–11B, stages 5–6, illustrate and describe examples of forming a dielectric layer and forming cavities within it.

[0094] The method (at 1230) forms interconnects in and / or on the dielectric layer. For example, interconnect 1114 may be formed. These interconnects may be formed using a plating process. Forming interconnects may include providing a patterned metal layer on and in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 7 of Figure 11B illustrates and describes an example of forming interconnects in and on the dielectric layer.

[0095] This method can form additional dielectric layers and additional interconnects, as described in 1225 and 1230. Figures 11B–11C, stages 8–10, illustrate and describe examples of forming additional dielectric layers and forming interconnects in and on the dielectric layers.

[0096] Once all dielectric layers and additional interconnects are formed, the method can decouple (e.g., remove, grind away) the carrier (e.g., 1100) from dielectric layer 120, thereby leaving the substrate. In some implementations, the method can form a solder mask layer (e.g., 1160, 1162) on the substrate.

[0097] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or solid vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary electronic device

[0098] Figure 13 illustrates various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, chips, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1302, laptop device 1304, fixed-location terminal device 1306, wearable device 1308, or motor vehicle 1310 may include the device 1300 as described herein. Device 1300 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. The devices 1302, 1304, 1306, and 1308, and vehicle 1310 illustrated in Figure 13 are merely exemplary. Other electronic devices may also be characterized by device 1300, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0099] One or more of the components, programs, features, and / or functions illustrated in Figures 1–6, 9A–9C, 10, 11A–11C, and / or 12–13 may be rearranged and / or combined into a single component, program, feature, or function, or implemented in several components, programs, or functions. Additional components, programs, and / or functions may also be added without departing from this invention. It should also be noted that Figures 1–6, 9A–9C, 10, 11A–11C, and / or 12–13 and their corresponding descriptions in this invention are not limited to chips and / or ICs. In some implementations, Figures 1–6, 9A–9C, 10, 11A–11C, and / or 12–13 and their corresponding descriptions may be used to manufacture, establish, provide, and / or produce apparatus and / or integrate apparatus. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a heat dissipation device, and / or an intermediary.

[0100] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various components, parts, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are illustrated for clarity. In some instances, the positioning, location, size, and / or shape of the various components and / or parts in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0101] The term "exemplary" is used herein to mean "used as an example, illustration, or diagram." Any implementation or manner described herein as "exemplary" need not be construed as superior to or better than other manners of this application. Similarly, the term "manner" does not require that all manners of this application include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. Coupling component A to component B may mean that component A is coupled to component B, and / or component B is coupled to component A. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transferred between the two objects. Electrically coupled objects may or may not have current transferred between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as the second component can be a first component, a second component, a third component, or a fourth component. The term "enclose" means that an object can partially or completely enclose another object. The terms "top" and "bottom" are arbitrary. A component located at the top can be situated on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this case, a first component situated "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another instance, a first component can be situated above (e.g., above) a first surface of a second component, while a third component can be situated above (e.g., below) a second surface of a second component, where the second surface is opposite the first surface. It should be further noted that the term "above," as used in the context of one component being above another in this case, can be used to mean that the component is on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, "above a second component" can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. The terms "about 'value X'" or "approximately value X," as used in this case, mean within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0102] In some implementations, an interconnect is a component or part in a device or package that allows or facilitates an electrical connection between two points, parts, and / or parts. In some implementations, an interconnect may include traces, vias, pads, solder pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal compositions (e.g., a seed layer + metal layer). In some implementations, an interconnect is a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal, ground, or power supply). An interconnect may be part of a circuit. An interconnect may include more than one part or component. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or plating processes may be used to form interconnects.

[0103] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, diagrams, block diagrams, or block diagrams. Although a flowchart can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0104] The following provides an overview of the various forms of this case:

[0105] Form 1: A package comprising: a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; a first bridge coupled to the first integrated device and the second integrated device; wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to the top of the first integrated device and the top of the second integrated device; and a second bridge coupled to the first integrated device and the second integrated device, wherein the second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0106] State 2: Package as in State 1, wherein the at least one first electrical path includes the back side of the first integrated device and the back side of the second integrated device.

[0107] State 3: Packages as in States 1 to 2, wherein the first integrated device includes: a first die; and a second die coupled to the first die.

[0108] State 4: Packaged as in State 3, wherein the second integrated device includes: a third die; and a fourth die coupled to the third die.

[0109] State 5: Package as in State 4, wherein the first die is located on the second die, wherein the second die is coupled to the substrate, wherein the third die is located on the fourth die, and wherein the fourth die is coupled to the substrate.

[0110] State 6: Package as in State 4, wherein the first die is configured to be electrically coupled to the third die via the first bridge.

[0111] State 7: Package as in States 4 to 6, wherein the first integrated device includes a first encapsulation layer, and wherein the second integrated device includes a second encapsulation layer.

[0112] State 8: Packaged as in states 3 to 7, wherein the front side of the first die faces the front side of the second die.

[0113] State 9: Packaged as in States 3 to 7, wherein the front side of the first die faces the back side of the second die.

[0114] State 10: Packaged as in States 3 to 7, wherein the back side of the first die faces the front side of the second die.

[0115] State 11: Packages as in States 1 to 10, wherein the first bridge includes a bridge die, the bridge die including: a die substrate; and at least one bridge interconnect.

[0116] State 12: Packages as in States 1 to 10, wherein the first bridge includes a bridge structure comprising: at least one dielectric layer; and at least one bridge interconnect.

[0117] Type 13: Package as in Types 1 to 12, wherein the first bridge is configured to provide at least one first electrical path for input / output (I / O) signals between the first integrated device and the second integrated device.

[0118] Type 14: Packages as in Types 1 to 13, wherein the second bridge is configured to provide at least one second electrical path for input / output (I / O) signals between the first integrated device and the second integrated device.

[0119] State 15: Package as in States 1 to 2, wherein the first integrated device includes: a first die; and a second die coupled to the first die, wherein the second integrated device includes: a third die; and a fourth die coupled to the third die, and wherein the first bridge is configured to provide at least one first electrical path for input / output (I / O) signals between the first die and the third die, and wherein the second bridge is configured to provide at least one second electrical path for input / output (I / O) signals between the second die and the fourth die.

[0120] State 16: Packages as in States 1 to 15, wherein the second bridge is at least partially located in the substrate.

[0121] Form 17: An apparatus comprising: a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; a first bridge interconnection device coupled to the first integrated device and the second integrated device, wherein the first bridge interconnection device is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge interconnection device is coupled to the top of the first integrated device and the top of the second integrated device; and a second bridge interconnection device coupled to the first integrated device and the second integrated device, wherein the second bridge interconnection device is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0122] State 18: The equipment as in State 17, wherein the first integrated device includes: a first die; and a second die coupled to the first die.

[0123] State 19: The equipment as in State 18, wherein the second integrated device includes: a third die; and a fourth die coupled to the third die.

[0124] State 20: As in the configuration of states 18 to 19, wherein the front side of the first grain faces the front side of the second grain.

[0125] State 21: As in the configuration of states 18 to 19, wherein the front side of the first grain faces the back side of the second grain.

[0126] State 22: As in the configuration of states 18 to 19, wherein the back side of the first grain faces the front side of the second grain.

[0127] State 23: The equipment of states 17 to 22, wherein the first bridge interconnect device includes a bridge die, the bridge die including: a die substrate; and at least one bridge interconnect.

[0128] State 24: The equipment of states 17 to 22, wherein the first bridge interconnect device includes a bridge structure, the bridge structure including: at least one dielectric layer; and at least one bridge interconnect.

[0129] Type 25: Equipment as described in Types 17 to 24, wherein the equipment includes electronic devices selected from the group comprising: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0130] Sample 26: A method for manufacturing a package, comprising: providing a substrate; coupling a first integrated device to the substrate; coupling a second integrated device to the substrate; coupling a first bridge to the first integrated device and the second integrated device; wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to the top of the first integrated device and the top of the second integrated device; and coupling a second bridge to the first integrated device and the second integrated device, wherein the second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0131] State 27: The method of State 26, wherein the coupling of the second bridge to the first integrated device and the second integrated device is performed when the first integrated device and the second integrated device are coupled to the substrate.

[0132] State 28: The method of states 26 to 27, wherein the at least one first electrical path includes the back side of the first integrated device and the back side of the second integrated device.

[0133] State 29: The method of states 26 to 28, wherein the first integrated device includes: a first die; a second die coupled to the first die; a third die; and a fourth die coupled to the third die.

[0134] State 30: The method of State 29, wherein the first die is configured to be electrically coupled to the third die via the first bridge.

[0135] The various features of the present case described in this paper can be implemented in different systems without departing from the present case. It should be noted that the above states in this case are instances only and should not be construed as limiting this case. The description of the various forms in this case is intended to be illustrative and not to limit the scope of the attached claim. Thereby, the teachings of the present case can be readily applied to other types of devices, and many substitutions, modifications, and deformations will be obvious to those with usual knowledge in the field to which the invention belongs. [Brief explanation of the diagram]

[0008] The various characteristics, essences and advantages will become apparent when understanding the detailed description elaborated below in conjunction with the drawings, in which the symbols of similar parts are always marked accordingly.

[0009] illustrates a cross-sectional profile view of a package including a bridge coupled to an integrated device.

[0010] FIG.

[0011] Figure 3 illustrates a profile profile view of another package including a bridge coupled to an integrated device.

[0012] Figure 4 illustrates a profile profile view of another package including a bridge coupled to a stacked grain.

[0013] Figure 5 illustrates a cross-sectional profile view of a bridge grain.

[0014] Figure 6 illustrates a cross-sectional profile view of the bridge structure.

[0015] Figure 7 illustrates an exemplary graphic of signal integrity for a signal between an integrated device using a non-bridge connection.

[0016] Figure 8 illustrates an exemplary graphic of the signal integrity of a signal between an integrated device using a bridge connection.

[0017] Figures 9A–9C illustrate an exemplary process for fabricating a package including a bridge coupled to an integrated device.

[0018] FIG.

[0019] Figures 11A–11C illustrate an exemplary process for fabricating a substrate.

[0020] Figure 12 illustrates an exemplary flowchart of a method for fabricating a substrate.

[0021] Figure 13 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. [Biomaterial Storage]

[0137] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A package, comprising: One substrate; A first integrated device coupled to the substrate, wherein the first integrated device includes a first plurality of through-substrate vias; A second integrated device coupled to the substrate, wherein the second integrated device includes a second plurality of through-substrate vias; a first bridge coupled to the first integrated device and the second integrated device, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, wherein the at least one first electrical path includes (i) the first plurality of through-substrate vias of the first integrated device, (ii) the first bridge, and (iii) the second plurality of through-substrate vias of the second integrated device, and wherein the first bridge is coupled to a top of the first integrated device and a top of the second integrated device; and a second bridge coupled to the first integrated device and the second integrated device, wherein the second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

2. The package as claimed in claim 1, wherein the at least one first electrical path includes a back side of the first integrated device and a back side of the second integrated device.

3. The packaging as claimed in claim 1, wherein the first integrated device comprises: The first grain; And a second grain coupled to the first grain.

4. The packaging as claimed in claim 3, wherein the second integrated device comprises: A third grain; And a fourth grain coupled to the third grain.

5. The package as claimed in claim 4, wherein the first die is located on the second die, wherein the second die is coupled to the substrate, wherein the third die is located on the fourth die, and wherein the fourth die is coupled to the substrate.

6. The package as claimed in claim 4, wherein the first die is configured to be electrically coupled to the third die via the first bridge.

7. The packaging as claimed in claim 4, wherein the first integrated device includes a first encapsulation layer, and wherein the second integrated device includes a second encapsulation layer.

8. The package as claimed in claim 3, wherein the front side of the first die faces the front side of the second die.

9. The package as claimed in claim 3, wherein a front side of the first die faces a back side of the second die.

10. The package as claimed in claim 3, wherein a back side of the first die faces a front side of the second die.

11. The package as claimed in claim 1, wherein the first bridge includes a bridge die, the bridge die comprising: a grain substrate; and at least one bridge interconnection.

12. As encapsulated in request item 1, wherein the first bridge includes a bridge structure comprising: At least one dielectric layer; and at least one bridge interconnection.

13. The package as requested in claim 1, wherein the first bridge is configured to provide at least one first electrical path for input / output (I / O) signals between the first integrated device and the second integrated device.

14. The package as requested in claim 1, wherein the second bridge is configured to provide at least one second electrical path for input / output (I / O) signals between the first integrated device and the second integrated device.

15. The package as claimed in claim 1, wherein the first integrated device comprises: The first grain; and a second die coupled to the first die, wherein the second integrated device includes: a third die; and a fourth die coupled to the third die, wherein the first bridge is configured to provide at least one first electrical path for input / output (I / O) signals between the first die and the third die, and wherein the second bridge is configured to provide at least one second electrical path for input / output (I / O) signals between the second die and the fourth die.

16. The package of claim 1, wherein the second bridge is at least partially located in the substrate.

17. An apparatus for encapsulation, comprising: One substrate; A first integrated device coupled to the substrate, wherein the first integrated device includes a first plurality of through-substrate vias; A second integrated device coupled to the substrate, wherein the second integrated device includes a second plurality of through-substrate vias; a first bridge interconnect coupled to the first integrated device and the second integrated device, wherein the first bridge interconnect is configured to provide at least one first electrical path between the first integrated device and the second integrated device, wherein the at least one first electrical path includes (i) the first plurality of through-substrate vias of the first integrated device, (ii) the first bridge interconnect, and (iii) the second plurality of through-substrate vias of the second integrated device, wherein the first bridge interconnect is coupled to a top of the first integrated device and a top of the second integrated device, wherein the top of the first integrated device is part of a first back side of the first integrated device, wherein the first back side of the first integrated device includes the first plurality of through-substrate vias, and wherein the top of the second integrated device is part of a second back side of the second integrated device. The second back side of the second integrated device includes the second plurality of through-substrate vias; and a second bridge interconnect device coupled to the first integrated device and the second integrated device, wherein the second bridge interconnect device is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

18. The equipment as claimed in claim 17, wherein the first integrated device comprises: The first grain; And a second grain coupled to the first grain.

19. The equipment as claimed in claim 18, wherein the second integrated device comprises: A third grain; and a fourth die coupled to the third die, wherein the second die is coupled to the substrate, wherein a back side of the second die faces the substrate, wherein the fourth die is coupled to the substrate, wherein a back side of the fourth die faces the substrate, wherein a front side of the first die faces a front side of the second die, wherein a front side of the third die faces a front side of the fourth die, wherein the first die includes the first plurality of through-substrate vias, wherein the third die includes the second plurality of through-substrate vias, and wherein the first bridge interconnect device is coupled to the first die and the third die.

20. The equipment as claimed in claim 18, wherein a front side of the first die faces a front side of the second die.

21. The equipment as claimed in claim 18, wherein a front side of the first die faces a back side of the second die.

22. The equipment as claimed in claim 18, wherein a back side of the first die faces a front side of the second die.

23. The apparatus of claim 17, wherein the first bridge interconnect includes a bridge die, the bridge die comprising: a grain substrate; and at least one bridge interconnection.

24. The equipment as claimed in claim 17, wherein the first bridge interconnection device includes a bridge structure comprising: At least one dielectric layer; and at least one bridge interconnection.

25. The equipment as claimed in claim 17, wherein the equipment includes an electronic device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and an equipment in a motor vehicle.

26. A method for manufacturing a package, comprising the steps of: providing a substrate; coupling a first integrated device to the substrate, wherein the first integrated device includes a first plurality of through-substrate vias; coupling a second integrated device to the substrate, wherein the second integrated device includes a second plurality of through-substrate vias; coupling a first bridge to the first integrated device and the second integrated device, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, wherein the at least one first electrical path includes (i) the first plurality of through-substrate vias of the first integrated device, (ii) the first bridge, and (iii) the second plurality of through-substrate vias of the second integrated device, and wherein the first bridge is coupled to a top of the first integrated device and a top of the second integrated device; and coupling a second bridge to the first integrated device and the second integrated device, wherein the second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

27. The method of claim 26, wherein coupling the second bridge to the first integrated device and the second integrated device is performed when the first integrated device and the second integrated device are coupled to the substrate.

28. The method of claim 26, wherein the at least one first electrical path includes a back side of the first integrated device and a back side of the second integrated device.

29. The method of claim 26, wherein the first integrated device comprises: The first grain; and a second grain coupled to the first grain; Furthermore, the second integrated device includes: a third grain; And a fourth grain coupled to the third grain.

30. The method of claim 29, wherein the first die is configured to be electrically coupled to the third die via the first bridge.

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