Computing system and method of operating the same

Abstract

This invention relates to an electronic device. A computing system according to the invention may include a storage device and a host. The storage device may include multiple zones. The host can receive storage area information from the storage device, including optimal write sizes for open areas among the multiple zones. Based on the optimal write size, historical sizes of data previously flushed to the storage device, and the size of the host's buffer data, the host can determine a target size for the data to be flushed to the storage device, and can flush the data in the buffer data corresponding to the target size to the storage device.

Description

[Technical Field]

[0001] This invention relates to an electronic device, and more specifically, to a computing system and its operating method. [Previous Technology]

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are divided into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is off. Volatile memory devices include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), etc.

[0004] Non-volatile memory devices are memory devices that do not lose data even when power is off, including read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc.

[0005] The host can receive optimal write size information for zones to be written sequentially from the storage device, and can flush the write data to the storage device by resizing it, so as to perform write operations on the storage device corresponding to the optimal write size. The storage device can receive the write data corresponding to the optimal write size of the zone from the host and program it immediately, thereby reducing the cost caused by write buffer management. [Summary of the Invention]

[0006] Cross-reference to related applications: The entire disclosures of U.S. Provisional Application No. 63 / 212,349, filed June 18, 2021, under 35 USC 119(e), and Korean Patent Application No. 10-2022-0065009, filed May 26, 2022, are incorporated herein by reference.

[0007] Embodiments of the present invention provide a computing system and its operation method, wherein the host adjusts the size of the written data and refreshes it, so that the storage device performs a write operation corresponding to the optimal write size of the area, thereby improving the write performance.

[0008] A computing system according to an embodiment of the present invention may include a storage device and a host. The storage device may include multiple zones. The host may receive storage area information including the optimal write size of open zones among the multiple zones from the storage device, and may determine the target size of the data to be refreshed to the storage device based on the optimal write size, the historical size of data previously refreshed to the storage device, and the size of the host's buffer data, and may refresh the data in the buffer data corresponding to the target size to the storage device.

[0009] An operation method of a host controlling a storage device comprising multiple zones according to an embodiment of the present invention may include the following steps: receiving storage area information from the storage device of an optimal write size for an open area among the multiple zones; determining a target size for data to be refreshed to the storage device based on the optimal write size, a historical size of data previously refreshed to the storage device, and the size of the host's buffer data; and refreshing the data in the buffer data corresponding to the target size to the storage device.

[0010] The operation method of the host device according to an embodiment of the present invention may include the following steps: buffering data as represented by the following formula 1 while keeping the size of the buffer data constant, and refreshing at least a portion of the buffer data to a storage device. The size of said portion is an amount represented by the following formula 2: [Formula 1] A > B, where "A" represents the size of data that can be refreshed to the storage device within the optimal write capacity of the storage device, A is C, "B" represents the size of the buffer data, "C" represents the optimal write capacity, "D" represents the size of data previously refreshed from the buffer to the storage device within the optimal write capacity, D is E mod C, and "E" represents the size of data previously refreshed from the buffer to the storage device, and [Formula 2] when A ≤ B, A ≤ F ≤ B, where "F" represents the size of the portion.

[0011] According to the present technology, a computing system and its operation method are provided, wherein the host adjusts the size of the written data and refreshes it, so that the storage device performs a write operation corresponding to the optimal write size of the area, thereby improving the write performance.

Implementation Method

[0013] The specific structural or functional descriptions of embodiments of the concept of the present invention disclosed in this specification or application are merely for the purpose of illustrating embodiments of the concept of the present invention. Embodiments of the concept of the present invention may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0014] FIG1 is a diagram illustrating a computing system according to an embodiment of the present invention.

[0015] Referring to FIG1, the computing system may include a storage device 50 and a host 300.

[0016] Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device. Storage device 50 is a device for storing data under the control of host 300 such as a mobile phone, smartphone, MP3 player, laptop, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system.

[0017] Depending on the host interface used as the communication method with the host 300, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be configured as any of various types of storage devices, such as SSD, MMC, eMMC, RS-MMC, micro-MMC multimedia cards; SD, mini-SD, micro-SD secure digital cards; universal serial bus (USB) storage devices, universal flash storage (UFS) devices, personal computer memory card international association (PCMCIA) cards; peripheral component interconnection (PCI) cards; PCI-express (PCI-E) cards; compact flash (CF) cards; smart media cards; and memory sticks.

[0018] The storage device 50 can be manufactured in any of the various types of packages. For example, the storage device 50 can be manufactured in any of the various types of packages such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), and wafer-level stack package (WSP).

[0019] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data.

[0020] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0021] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or for reading data stored in the memory device 100.

[0022] A memory block can be a unit used to erase data. In embodiments, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), Phase-change RAM (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-torque random access memory (SRAM). Transfer torque random access memory, STT-RAM, etc. In this specification, for ease of explanation, it is assumed that memory device 100 is NAND flash memory.

[0023] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access a region selected according to the address in the memory cell array. That is, the memory device 100 can perform operations instructed by commands on the region selected according to the address. For example, the memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, the memory device 100 programs data into the region selected according to the address. During a read operation, the memory device 100 can read data from the region selected according to the address. During an erase operation, the memory device 100 can erase the data stored in the region selected according to the address.

[0024] In an embodiment, the memory device 100 may include a first storage area 150a and a second storage area 150b. The first storage area 150a may include multiple zones for sequential write operations. Since each zone stores data corresponding to consecutive logical addresses, garbage collection may not be performed. An optimal write size can be set for each zone. The optimal write size may be the maximum amount of data that can be written in a single programming operation. When data corresponding to the optimal write size of an open zone is flushed from the host 300 to the storage device 50, the storage device 50 can directly program the data flushed in the write buffer 210 into the open zone without requiring long-term storage, thereby reducing the maintenance and management costs of the write buffer 210.

[0025] The second storage area 150b may include multiple zone buffers corresponding to each of the multiple zones. A zone buffer may include memory cells that store fewer data bits than the memory cells included in a zone. For example, a zone may include a three-level cell storing three data bits. A zone buffer may include a single-level cell storing one data bit. Because a zone buffer stores fewer data bits per memory cell compared to a zone, it can achieve faster read and write speeds and higher reliability despite its smaller capacity.

[0026] When the size of the data to be stored from the write buffer 210 into the zone is less than the preset write size, the zone buffer can be used to temporarily store the data. The preset write size may include the optimal write size.

[0027] The memory controller 200 controls the overall operation of the storage device 50.

[0028] When power is applied to the storage device 50, the memory controller 200 can execute firmware (FW). When the memory device 100 is a flash memory device, the memory controller 200 can execute firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100.

[0029] In an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300 and convert the logical block address into a physical block address (PBA), which represents the address of a memory cell containing data to be stored in the memory device 100.

[0030] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, or erase operations according to the request of the host 300. During programming operations, the memory controller 200 can provide the memory device 100 with write commands, physical block addresses, and data. During read operations, the memory controller 200 can provide the memory device 100 with read commands and physical block addresses. During erase operations, the memory controller 200 can provide the memory device 100 with erase commands and physical block addresses.

[0031] In this embodiment, the memory controller 200 may generate commands, addresses, and data independently of requests from the host 300 and transmit them to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as programming operations for wear leveling or programming operations for garbage collection.

[0032] In this embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 in an interleaved manner to improve operational performance. The interleaved manner can be an operational mode in which the operating ranges of at least two memory devices 100 overlap.

[0033] The memory controller 200 can control a plurality of memory devices 100 connected through at least one channel. Each memory device 100 may include at least one plane. Each plane may include a plurality of memory blocks.

[0034] In an embodiment, the memory controller 200 may include a write buffer 210 and a memory operation controller 220.

[0035] The write buffer 210 can store data refreshed from the host 300. The data stored in the write buffer 210 can be programmed into a zone of the first storage area 150a or a zone buffer of the second storage area 150b.

[0036] The memory operation controller 220 can provide the host 300 with storage area information including optimal write size information for open areas included in the first storage area 150a. An open area can be one of multiple areas that is activated for writing data.

[0037] The memory operation controller 220 can store data refreshed from the host 300 in the write buffer 210, and can program the data stored in the write buffer 210 into the open area of ​​the first storage area 150a or into the area buffer corresponding to the open area of ​​the second storage area 150b. Specifically, the memory operation controller 220 can program the data stored in the write buffer 210 into the open area or the area buffer corresponding to the open area based on a comparison between the optimal write size and the size of the data stored in the write buffer 210.

[0038] The memory operation controller 220 can respond to a write request received from the host 300 by comparing the size of the data stored in the write buffer 210 with the optimal write size. When the size of the data stored in the write buffer 210 is greater than or equal to the optimal write size, the memory operation controller 220 can program the data in the write buffer 210 corresponding to the optimal write size into the open area. When the size of the data stored in the write buffer 210 is less than the optimal write size, the memory operation controller 220 may wait without programming the data stored in the write buffer 210 into the open area until the size of the data stored in the write buffer 210 is greater than or equal to the optimal write size due to data newly refreshed to the write buffer 210 from the host 300.

[0039] The memory operation controller 220 can respond to a synchronization request received from the host 300 by programming the data stored in the write buffer 210 into the area buffer corresponding to the open area. Since the synchronization request is a request to synchronize the storage device 50 and the host 300, the memory operation controller 220 can program the data into the area buffer even if the size of the data stored in the write buffer 210 is less than the optimal write size.

[0040] The memory operation controller 220 can reload the data stored in the area buffer into the write buffer 210 after performing the operation according to the synchronization request. The memory operation controller 220 can program the data corresponding to the optimal write size from the data loaded into the write buffer 210 and the data newly refreshed into the write buffer 210 from the host 300 into the open area.

[0041] The host 300 can utilize technologies such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MultiMedia Card (eMMC), Dual In-line Memory Module (DIMM), and Registered DIMM. At least one of various communication standards or interfaces of RDIMM, Load Reduced DIMM (LRDIMM), communicates with storage device 50.

[0042] In an embodiment, the host 300 may include a host buffer 310 and a refresh controller 320.

[0043] The host buffer 310 can store buffer data to be refreshed to the storage device 50.

[0044] The refresh controller 320 can receive storage area information from the storage device 50, including the optimal write size of the open area included in the first storage area 150a. The refresh controller 320 can determine the target size of the data to be refreshed to the storage device 50 based on the historical size of the data previously refreshed to the storage device 50, the size of the buffer data stored in the host buffer 310, and the optimal write size.

[0045] For example, the refresh controller 320 can set the target size based on the historical size and the optimal write size. The refresh controller 320 can set the initial value of the target size as the value obtained by subtracting the historical size from the optimal write size.

[0046] The refresh controller 320 can adjust the target size based on a comparison between the target size and the size of the buffer data. When the size of the buffer data is less than the target size, the refresh controller 320 can initialize the target size value. When the size of the buffer data is equal to the target size, the refresh controller 320 can maintain the target size value. When the size of the buffer data is greater than the target size, the refresh controller 320 can adjust the target size value within the range of the buffer data size to a value obtained by adding an integer multiple of the optimal write size to the initial value of the target size.

[0047] The refresh controller 320 can refresh the data corresponding to the target size in the buffer data stored in the host buffer 310, along with the write request, to the storage device 50. The refresh controller 320 can update the historical size after the refresh.

[0048] The refresh controller 320 may provide a synchronization request to the storage device 50 in response to a synchronization event that synchronizes the host 300 and the storage device 50. The refresh controller 320 may refresh the buffer data stored in the host buffer 310 together with the synchronization request to the storage device 50.

[0049] In this embodiment, the data processed in the host 300 can be managed through a file system. The file system may include a log-structured file system. The refresh controller 320 may be controlled by the log-structured file system.

[0050] Figure 2 is a diagram illustrating the structure of the memory device in Figure 1.

[0051] Referring to FIG2, the memory device 100 may include a memory cell array 110, peripheral circuitry 120 and control logic 130.

[0052] The memory cell array 110 includes a plurality of memory blocks BLK1~BLKz. The plurality of memory blocks BLK1~BLKz are connected to the address decoder 121 via row lines RL. The plurality of memory blocks BLK1~BLKz are connected to the read and write circuitry 123 via bit lines BL1~BLm. Each of the plurality of memory blocks BLK1~BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells. Among the plurality of memory cells, memory cells connected to the same word line are defined as a physical page. That is, the memory cell array 110 is composed of a plurality of physical pages. According to an embodiment of the present invention, each of the plurality of memory blocks BLK1~BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain-select transistor and the memory cell, and between the source-select transistor and the memory cell.

[0053] Each of the memory cells in the memory device 100 can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0054] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0055] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations.

[0056] The address decoder 121 is connected to the memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to an embodiment of the present invention, word lines may include normal word lines and virtual word lines. According to an embodiment of the present invention, row lines RL may further include pipe select lines.

[0057] Address decoder 121 is configured to operate in response to control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0058] Address decoder 121 is configured to decode block addresses in the received address ADDR. Address decoder 121 selects at least one memory block from memory blocks BLK1~BLKz based on the decoded block address. Address decoder 121 is configured to decode row addresses in the received address ADDR. Address decoder 121 can select at least one word line from the word lines of the selected memory blocks based on the decoded row address. Address decoder 121 can apply an operating voltage Vop supplied from voltage generator 122 to the selected word line.

[0059] During programming operations, the address decoder 121 can apply a programming voltage to the selected word line and can apply a pass voltage at a level lower than the programming voltage to the unselected word line. During programming verification operations, the address decoder 121 can apply a verification voltage to the selected word line and can apply a verification pass voltage at a level higher than the verification voltage to the unselected word line.

[0060] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and can apply a read voltage higher than the read voltage to the unselected word line.

[0061] According to an embodiment of the present invention, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the address ADDR input to the memory device 100 includes the block address. The address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line of the selected memory block.

[0062] According to an embodiment of the present invention, the address decoder 121 can be configured to decode column addresses in the transmitted address ADDR. The decoded column addresses can be transmitted to the read and write circuitry 123. For example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0063] Voltage generator 122 is configured to generate multiple operating voltages Vop using the external power supply voltage supplied to memory device 100. Voltage generator 122 operates in response to control of control logic 130.

[0064] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0065] In this embodiment, voltage generator 122 may generate multiple operating voltages Vop using an external power supply voltage or an internal power supply voltage. Voltage generator 122 may be configured to generate various voltages required by memory device 100. For example, voltage generator 122 may generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0066] Voltage generator 122 includes a plurality of pump capacitors that receive an internal power supply voltage to generate a plurality of operating voltages Vop with different voltage levels, and voltage generator 122 can selectively activate the plurality of pump capacitors to generate the plurality of operating voltages Vop in response to control of control logic 130. The generated plurality of operating voltages Vop can be supplied to memory cell array 110 through address decoder 121.

[0067] The read and write circuit 123 includes first to m page buffers PB1 to PBm. The first to m page buffers PB1 to PBm are respectively connected to the memory cell array 110 via first to m bit lines BL1 to BLm. The first to m page buffers PB1 to PBm operate in response to the control of the control logic 130.

[0068] The first to m-th page buffers PB1~PBm communicate with the data input / output circuit 124 via data DATA. During programming operations, the first to m-th page buffers PB1~PBm receive the data to be stored through the data input / output circuit 124 and the data line DL.

[0069] During programming operation, when a programming voltage is applied to the selected word line, the first to m-th page buffers PB1~PBm transmit the data to be stored, received through the data input / output circuit 124, to the selected memory cell via bit lines BL1~BLm. The memory cell of the selected page is programmed according to the transmitted data DATA. The memory cell connected to the bit line to which a programming enable voltage (e.g., ground voltage) is applied has an elevated threshold voltage. The threshold voltage of the memory cell connected to the bit line to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operation, the first to m-th page buffers PB1~PBm read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1~BLm.

[0070] During a read operation, the read and write circuit 123 can read data DATA from the memory cell of the selected page through the bit line BL, and can store the read data DATA into the first to m page buffers PB1 to PBm.

[0071] During an erase operation, the read and write circuit 123 can cause the bit line BL to float. In an embodiment, the read and write circuit 123 may include column select circuitry.

[0072] The data input / output circuit 124 is connected to the first to m page buffers PB1~PBm via data lines DL. The data input / output circuit 124 operates in response to the control logic 130.

[0073] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 outputs data DATA transferred from the first to the m-th page buffers PB1~PBm included in the read and write circuit 123 to the external controller.

[0074] During a read operation or a verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit VRYBIT signal generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current.

[0075] Control logic 130 can be connected to address decoder 121, voltage generator 122, read and write circuit 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can be configured to control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0076] Control logic 130 can generate various signals to control peripheral circuit 120 in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, address ADDR, read and write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, output address ADDR to address decoder 121, output read and write control signals to read and write circuit 123, and output enable bit VRYBIT to sensing circuit 125. In addition, control logic 130 can determine whether the verification operation is successful or unsuccessful in response to pass / fail signals (PASS / FAIL) output from sensing circuit 125.

[0077] Figure 3 is a diagram illustrating the structure and operation of the memory device of Figure 1.

[0078] Referring to FIG3, the memory device may include a first storage area 150a and a second storage area 150b. The first storage area 150a may include first to fourth zones, Zone_1 to Zone_4, for which sequential write operations are performed. Data corresponding to consecutive logical addresses can be stored in each zone. An optimal write size (OWS) can be set for each zone. The optimal write size (OWS) can be the maximum data size that can be programmed into the zone in a single programming operation.

[0079] The second storage area 150b may include Zone Buffers 1 to 4, corresponding to Zones 1 to 4 respectively. The number of data bits stored per memory cell in a zone buffer can be less than the number of data bits stored per memory cell in a zone. Because each memory cell in a zone buffer stores fewer data bits than each memory cell in a zone, the zone buffer, despite its smaller capacity, can achieve faster read and write speeds and higher reliability.

[0080] In an embodiment, the data stored in the write buffer 210 corresponding to the Optimal Write Size (OWS) can be programmed into an open area among a plurality of areas included in the first storage area 150a. The open area can be an area among the plurality of areas that is activated to write data.

[0081] When the size of the data stored in the write buffer 210 is less than the optimal write size (OWS), the data stored in the write buffer 210 may not be programmed into the first storage area 150a or the second storage area 150b and may remain in the write buffer 210 until the size of the data stored in the write buffer 210 is greater than or equal to the optimal write size (OWS). However, even if the size of the data stored in the write buffer 210 is less than the optimal write size (OWS), when a synchronization request to synchronize the storage device and the host is received, the data stored in the write buffer 210 may be programmed into the area buffer corresponding to the open area.

[0082] That is, data smaller than the optimal write size (OWS) can be temporarily programmed into the area buffer. Afterwards, the data programmed into the area buffer can be reloaded into the write buffer 210, and can be programmed into the open area together with the data newly refreshed from the host into the write buffer 210 as data corresponding to the optimal write size (OWS).

[0083] Figure 4 is a diagram illustrating information managed by the host and storage device to support write operations corresponding to the optimal write size.

[0084] Referring to Figure 4, the host management information may include OWS_PER_ZONE, Flushed_CNT, Buffered_CNT, and Target_Flush.

[0085] OWS_PER_ZONE can be the optimal write size for an open zone. The optimal write size can be the maximum amount of data that can be written to an open zone in a single programming operation. The host can obtain the OWS_PER_ZONE from the storage zone information received from the storage device.

[0086] Flushed_CNT is the amount of data with a preset size that was previously flushed to the storage device, and can represent the historical size of the data that was previously flushed to the storage device. Flushed_CNT can have values ​​from 0 (zero) to OWS_PER_ZONE-1.

[0087] Buffered_CNT is the amount of data with a preset size stored in the host buffer, indicating the size of the buffer data.

[0088] Target_Flush is the amount of data with a preset size to be flushed to the storage device, indicating the target size of the data to be flushed to the storage device.

[0089] Storage device management information may include OWS_PER_ZONE and WB_CNT.

[0090] WB_CNT is the amount of data with a preset size stored in the write buffer, indicating the size of the data stored in the write buffer.

[0091] According to the embodiment in Figure 4, Target_Flush can be determined before performing a flush. The initial value of Target_Flush can be set based on OWS_PER_ZONE and Flushed_CNT. Then, the value of Target_Flush can be adjusted based on the comparison result between Buffered_CNT and the initial value of Target_Flush. After determining the value of Target_Flush, when the value of Target_Flush is greater than 0 (zero) or a synchronization event occurs, the host can flush the data stored in the host buffer to the storage device. The host can update Flushed_CNT after the flush. In Figure 4, the arithmetic symbol "%" can be the arithmetic symbol "mod".

[0092] The storage device can program the data stored in the write buffer into an open area or into a zone buffer corresponding to the zone, based on the comparison result between WB_CNT and OWS_PER_ZONE. For example, when WB_CNT is greater than or equal to OWS_PER_ZONE, the storage device can program the data stored in the write buffer into an open area. When WB_CNT is less than OWS_PER_ZONE and the synchronization event condition is met, the storage device can program the data stored in the write buffer into a zone buffer.

[0093] Figure 5 is a diagram illustrating the programming operation of a zone according to one embodiment.

[0094] Referring to Figure 5, Flushed_CNT can be initially set to 0. The range of Flushed_CNT can be from 0 to OWS_PER_ZONE-1. The first to third data, with a unit size of 4Kbye, can be stored in the host buffer. Therefore, Buffered_CNT can be 3. In Figure 5, OWS_PER_ZONE can be 12. The unit size of the data, the amount of data stored in the host buffer, and the optimal write size of the open area are not limited to this embodiment.

[0095] Data from the fourth to the thirteenth can be newly stored in the host buffer. Buffered_CNT can be updated from 3 to 13.

[0096] Target_Flush can be initially set to 12 based on OWS_PER_ZONE and Flushed_CNT (i.e., the refresh size). Target_Flush is determined to be 12 based on the comparison of the initial values ​​of Buffered_CNT and Buffered_CNT. Since Target_Flush is greater than 0, the refresh condition is met. The first to twelfth data corresponding to Target_Flush can be flushed from the host to the write buffer of the storage device. After flushing, Flushed_CNT may be updated. Flushed_CNT remains 0 as a result of the update. Since WB_CNT is the same as OWS_PER_ZONE, the first to twelfth data flushed to the write buffer can be programmed into the open area.

[0097] Figure 5 illustrates the host refresh operation and storage device programming operation under normal circumstances. The host can adjust the size of the data to be refreshed by taking into account the size of the data previously refreshed to the storage device. The storage device can receive data corresponding to the optimal write size from the host, and therefore can directly perform programming operations on the open area without holding the data refreshed from the host in the write buffer. This reduces the maintenance and management costs of the write buffer and improves the write performance of the storage device.

[0098] Figure 6A is a diagram illustrating the programming operation of a zone buffer according to one embodiment.

[0099] Referring to Figure 6A, Flushed_CNT can be initially set to 0. The range of Flushed_CNT can be from 0 to OWS_PER_ZONE-1. The first to third data, with a unit size of 4Kbye, can be stored in the host buffer. Therefore, Buffered_CNT can be 3. In Figure 6A, OWS_PER_ZONE can be 12. The unit size of the data, the amount of data stored in the host buffer, and the optimal write size of the open area are not limited to this embodiment.

[0100] Target_Flush can be set to 12 (the refresh size) based on OWS_PER_ZONE and Flushed_CNT. Target_Flush can be determined to be 0 based on the comparison of the initial values ​​of Buffered_CNT and Target_Flush. Although Target_Flush is not greater than 0, the refresh condition can be met due to a synchronization event that synchronizes the storage device and the host. The first to third data corresponding to Buffered_CNT can be flushed from the host to the storage device's write buffer. After flushing, Flushed_CNT can be updated from 0 to 3. Since WB_CNT is less than OWS_PER_ZONE, the first to third data flushed to the write buffer can be programmed into the zone buffer corresponding to the open area. Buffered_CNT can be updated from 3 to 0.

[0101] Figure 6A illustrates the host refresh operation and storage device programming operation in the event of a synchronization event. When a synchronization event occurs, the data stored in the host should be programmed into the storage device regardless of the value of Target_Flush. Therefore, even if the size of the data refreshed from the host is less than the optimal write size, the data should still be programmed, and the data stored in the write buffer can be temporarily programmed into the area buffer. This is because if data smaller than the optimal write size is programmed into an open area, the continuity of sequential write operations may be disrupted. Furthermore, since the area buffer stores fewer data bits per memory cell compared to an area, faster read and write operations can be performed, and responses to synchronization events can be faster.

[0102] Figure 6B is a diagram illustrating the operation of programming data stored in a zone buffer into a zone according to one embodiment.

[0103] Referring to Figures 6A and 6B, after a synchronization event, the first to third data stored in the area buffer can be reloaded into the write buffer.

[0104] Data from the fourth to the thirteenth can be newly stored in the host buffer. Buffered_CNT can be updated from 0 to 10.

[0105] Target_Flush can be set to 9 based on OWS_PER_ZONE and Flushed_CNT (i.e., the refresh size). Based on the comparison between the initial values ​​of Buffered_CNT and Target_Flush, Target_Flush can be determined to be 9. Since Target_Flush is greater than 0, the refresh condition is met. The fourth to twelfth data corresponding to Target_Flush can be flushed from the host to the write buffer of the storage device. After the flush, Flushed_CNT can be updated from 3 to 0.

[0106] Since WB_CNT is the same as OWS_PER_ZONE, the first to third data loaded into the write buffer and the fourth to twelfth data flushed into the write buffer can be programmed into the open area.

[0107] By referring to the embodiments described with reference to FIG6A and FIG6B, even if a synchronization event occurs, sequential write operations can be maintained for programming data corresponding to the optimal write size of the open area.

[0108] Figure 7 is a flowchart illustrating a method of operating a host according to one embodiment.

[0109] Referring to Figure 7, in step S701, the host can receive storage area information, including the optimal write size of the open area, from the storage device.

[0110] In step S703, the host can determine the target size of the data to be refreshed based on the optimal write size, the size of the data to be refreshed to the storage device, and the size of the data stored in the host buffer.

[0111] In step S705, the host can refresh the data corresponding to the target size in the data stored in the host buffer to the storage device.

[0112] In step S707, the host may update the historical size of the data previously refreshed to the storage device.

[0113] Figure 8 is a flowchart illustrating a method of operating a host according to one embodiment.

[0114] Referring to Figure 8, in step S801, the host can sense the occurrence of a synchronization event that synchronizes the host and the storage device.

[0115] In step S803, the host can refresh the data stored in the host buffer to the storage device.

[0116] In step S805, the host may update the historical size of the data previously refreshed to the storage device.

[0117] FIG9 is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0118] Referring to FIG9, in step S901, the storage device may provide the host with storage area information including the optimal write size of the open area.

[0119] In step S903, the storage device may store the data refreshed from the host in the write buffer.

[0120] In step S905, the storage device may program the data stored in the write buffer into the open area or the area buffer based on the comparison result between the size of the data stored in the write buffer and the optimal write size and whether a synchronization request is received.

[0121] FIG10 is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0122] Referring to FIG10, in step S1001, the storage device may provide the host with storage area information including the optimal write size of the open area.

[0123] In step S1003, the storage device may store the data refreshed from the host in the write buffer.

[0124] In step S1005, the storage device can determine whether the size of the data stored in the write buffer is greater than or equal to the optimal write size. As a result of the determination, if the size of the data stored in the write buffer is greater than or equal to the optimal write size, step S1007 is executed; if the size of the data stored in the write buffer is less than the optimal write size, step S1009 is executed.

[0125] In step S1007, the storage device can program the data corresponding to the optimal write size in the data stored in the write buffer into the open area.

[0126] In step S1009, the storage device can determine whether a synchronization request has been received from the host. As a result of the determination, if a synchronization request is received from the host, step S1011 is executed; if no synchronization request is received from the host, the operation is terminated.

[0127] In step S1011, the storage device can program the data stored in the write buffer into the area buffer corresponding to the open area.

[0128] FIG11 is a flowchart illustrating an operation method of a storage device according to one embodiment.

[0129] Referring to FIG11, in step S1101, the storage device can load the data stored in the area buffer into the write buffer.

[0130] In step S1103, the storage device may store the data refreshed from the host in the write buffer.

[0131] In step S1105, the storage device may program the data corresponding to the optimal write size from the data stored in the write buffer into the open area. The data stored in the write buffer may include data loaded from the area buffer and data newly refreshed from the host.

[0132] FIG12 is a diagram illustrating another embodiment of the memory controller of FIG1.

[0133] Referring to FIG12, the memory controller 1000 is connected to the host and the memory device. The memory controller 1000 is configured to access the memory device in response to a request from the host. For example, the memory controller 1000 is configured to control write, read, erase, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0134] The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070.

[0135] Bus 1070 can be configured to provide a channel between components of memory controller 1000.

[0136] The processor 1010 can control the overall operation of the memory controller 1000 and perform logical operations. The processor 1010 can communicate with an external host through the host interface 1040 and with the memory device through the memory interface 1060. In addition, the processor 1010 can communicate with the memory buffer 1020 through the buffer controller 1050. The processor 1010 can control the operation of the storage device by using the memory buffer 1020 as operating memory, cache memory, or buffer memory.

[0137] The processor 1010 can perform the functions of the Flash Translation Layer (FTL). The processor 1010 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) through the FTL. The FTL can receive logical block addresses (LBAs) using a mapping table and translate them into physical block addresses (PBAs). Depending on the mapping unit, there are various address mapping methods for the FTL. Typical address mapping methods include page mapping, block mapping, and hybrid mapping.

[0138] The processor 1010 is configured to randomize data received from the host. For example, the processor 1010 may use a randomization seed to randomize the data received from the host. The randomized data may be provided to the memory device as data to be stored and programmed into the memory cell array.

[0139] The processor 1010 is configured to derandomize data received from the memory device during a read operation. For example, the processor 1010 may use a derandomization seed to derandomize the data received from the memory device. The derandomized data will be output to the host.

[0140] In an embodiment, the processor 1010 may perform randomization and derandomization through driver software or firmware.

[0141] The memory buffer 1020 can be used as the operating memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0142] The error correction circuit 1030 can perform error correction. The error correction circuit 1030 can perform error correction encoding (ECC encoding) based on data to be written to the memory device through the memory interface 1060. The error-corrected data can be transmitted to the memory device through the memory interface 1060. The error correction circuit 1030 can perform error correction decoding (ECC decoding) on ​​data received from the memory device through the memory interface 1060. For example, the error correction circuit 1030 can be included as a component of the memory interface 1060.

[0143] The host interface 1040 can communicate with an external host under the control of the processor 1010. The host interface 1040 can be configured to utilize technologies such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), and Registered DIMM. It communicates with at least one of the various communication standards or interfaces of RDIMM and Load Reduced DIMM (LRDIMM).

[0144] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

[0145] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 can transmit commands, addresses and data to the memory device through channels.

[0146] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer controller 1050.

[0147] For example, the processor 1010 can use code to control the operation of the memory controller 1000. The processor 1010 can load code from a non-volatile memory device (e.g., read-only memory) disposed within the memory controller 1000. As another example, the processor 1010 can load code from the memory device through the memory interface 1060.

[0148] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus are separate from each other and can operate independently without interference. The data bus can be connected to the host interface 1040, the buffer controller 1050, the error correction circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0149] FIG13 is a block diagram showing a memory card system using a storage device according to an embodiment of the present invention.

[0150] Referring to FIG13, the memory card system 2000 includes a memory controller 2100, a memory device 2200 and a connector 2300.

[0151] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 may be configured to control read, write, erase, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and the host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 may be implemented in the same manner as memory controller 200 described with reference to FIG1.

[0152] For example, the memory controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error correction circuitry.

[0153] The memory controller 2100 can communicate with an external device via the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 can be configured to communicate with external devices via at least one of various communication standards or interfaces, such as Universal Serial Bus (USB), MultiMediaCard (MMC), embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the aforementioned communication standards or interfaces.

[0154] For example, the memory device 2200 may be configured as a variety of non-volatile memory devices such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0155] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), or a universal flash memory (UFS).

[0156] FIG14 is a block diagram illustrating a solid state drive (SSD) system using a storage device according to an embodiment of the present invention.

[0157] Referring to FIG14, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 transmits signals (SIG) to the host 3100 and receives signals (SIG) from the host 3100 through a signal connector 3001, and receives power (PWR) through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221-322n, an auxiliary power supply device 3230, and a buffer memory module 3240.

[0158] According to an embodiment of the present invention, the SSD controller 3210 can perform the functions of the memory controller 200 described with reference to FIG1.

[0159] The SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a signal (SIG) received from the host 3100. For example, the signal (SIG) can be a signal based on the interface between the host 3100 and the SSD 3200. For example, a signal (SIG) can be defined by at least one of the following standards or interfaces: Universal Serial Bus (USB), MultiMedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0160] The auxiliary power supply unit 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power supply unit 3230 can receive power (PWR) from the host 3100 and charge it. When the power supply from the host 3100 is unreliable, the auxiliary power supply unit 3230 can supply power to the SSD 3200. For example, the auxiliary power supply unit 3230 can be located inside or outside the SSD 3200. For example, the auxiliary power supply unit 3230 can also be located on the motherboard to supply auxiliary power to the SSD 3200.

[0161] Buffer memory 3240 operates as buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221-322n, or buffer memory 3240 may temporarily store metadata (e.g., mapping tables) of flash memories 3221-322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM and PRAM.

[0162] FIG15 is a block diagram showing a user system using a storage device according to an embodiment of the present invention.

[0163] Referring to Figure 15, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0164] The application processor 4100 can drive components, operating systems (OS), or user programs included in the user system 4000. For example, the application processor 4100 may include controllers, interfaces, and graphics engines that control components included in the user system 4000. The application processor 4100 may be provided as a system-on-a-chip (SoC).

[0165] The memory module 4200 can operate as the main memory, operating memory, buffer memory, or high-speed cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as a single semiconductor package.

[0166] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0167] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or three-dimensional NAND flash memory. For example, storage module 4400 can be provided as a memory card for user system 4000 or a removable drive for external drives.

[0168] For example, storage module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as memory device 100 described with reference to FIG1. ​​Storage module 4400 may operate in the same manner as storage device 50 described with reference to FIG1.

[0169] User interface 4500 may include an interface for inputting data or commands to application processor 4100 or outputting data to an external device. For example, user interface 4500 may include a user input interface such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, or piezoelectric element. User interface 4500 may include a user output interface such as a liquid crystal display (LCD), organic light-emitting diode (OLED) display, active matrix OLED (AMOLED) display, LED, speaker, or monitor. [Simplified Explanation of the Diagram]

[0012] FIG1 is a diagram illustrating a computing system according to an embodiment of the present invention. FIG2 is a diagram illustrating the structure of the memory device of FIG1. ​​FIG3 is a diagram illustrating the structure and operation of the memory device of FIG1. ​​FIG4 is a diagram illustrating information managed by the host and storage device to support write operations corresponding to the optimal write size. FIG5 is a diagram illustrating a zone programming operation according to one embodiment. FIG6A is a diagram illustrating a zone buffer programming operation according to one embodiment. FIG6B is a diagram illustrating an operation of programming data stored in the zone buffer into the zone according to one embodiment. FIG7 is a flowchart illustrating a host operation method according to one embodiment. FIG8 is a flowchart illustrating a host operation method according to one embodiment. FIG9 is a flowchart illustrating a storage device operation method according to one embodiment. FIG10 is a flowchart illustrating a storage device operation method according to one embodiment. FIG11 is a flowchart illustrating a storage device operation method according to one embodiment. FIG12 is a diagram illustrating another embodiment of the memory controller of FIG1. ​​FIG13 is a block diagram showing a memory card system applying a storage device according to an embodiment of the present invention. Figure 14 is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present invention. Figure 15 is a block diagram illustrating a user system using a storage device according to an embodiment of the present invention.

Claims

1. A computing system, comprising: A storage device, including multiple zones; and a host, receiving from the storage device storage area information including the optimal write size of an open zone among the multiple zones, updating a historical size by accumulating the values ​​of data previously refreshed to the storage device, determining a target size of data to be refreshed to the storage device based on the optimal write size, the historical size, and the size of buffer data stored in a host buffer, and refreshing the data in the buffer data corresponding to the target size to the storage device.

2. The computing system as described in claim 1, wherein, The host includes: the host buffer for storing buffer data; and a refresh controller for determining the target size based on the optimal write size, the historical size, and the size of the buffer data, and refreshing the data in the buffer data corresponding to the target size to the storage device, wherein the historical size is initialized whenever the historical size reaches the optimal write size.

3. The computing system as described in claim 2, wherein, The refresh controller sets the target size based on the historical size and the optimal write size, and adjusts the target size based on a comparison between the target size and the size of the buffer data.

4. The computing system as described in claim 3, wherein, The refresh controller sets the initial value of the target size as the value obtained by subtracting the historical size from the optimal write size.

5. The computing system as described in claim 4, wherein, When the size of the buffer data is less than the target size, the refresh controller initializes the target size value; when the size of the buffer data is equal to the target size, the refresh controller maintains the target size value; and when the size of the buffer data is greater than the target size, the refresh controller adjusts the target size value within the range of the buffer data size to a value obtained by adding an integer multiple of the optimal write size to the initial value of the target size.

6. The computing system as described in claim 2, wherein, The refresh controller responds to a synchronization event that synchronizes the host and the storage device by providing a synchronization request to the storage device, and the refresh controller refreshes the buffer data to the storage device.

7. The computing system as described in claim 1, wherein, The storage device includes: a memory device including the plurality of regions; and a memory controller for storing data refreshed from the host and programming it into the open regions.

8. The computing system as described in claim 7, wherein, The memory device includes a plurality of zone buffers, each of the plurality of zone buffers corresponding to each of the plurality of zones, and the plurality of zone buffers include memory cells, each memory cell storing fewer data bits than memory cells included in the plurality of zones.

9. The computing system as described in claim 8, wherein, The memory controller includes: a write buffer for storing data refreshed from the host; and a memory operation controller for programming the data stored in the write buffer into the open area or a zone buffer corresponding to the open area.

10. The computing system as described in claim 9, wherein, The memory operation controller programs the data stored in the write buffer into the open area or the area buffer based on a comparison between the optimal write size and the size of the data stored in the write buffer.

11. The computing system as described in claim 10, wherein, When the size of the data stored in the write buffer is greater than or equal to the optimal write size, the memory operation controller programs the data in the write buffer corresponding to the optimal write size into the open area.

12. The computing system as described in claim 10, wherein, The memory operation controller receives a synchronization request from the host. When the size of the data stored in the write buffer is less than the optimal write size, the memory operation controller programs the data stored in the write buffer into the area buffer.

13. The computing system as described in claim 12, wherein, The memory operation controller loads data stored in the area buffer into the write buffer, and programs data in the write buffer corresponding to the optimal write size into the open area. The write buffer data includes data loaded from the area buffer into the write buffer and data newly refreshed from the host.

14. A method of operating a host, which is a method of operating a host that controls a storage device including multiple zones, the method of operating the host comprising the following steps: receiving from the storage device storage area information including an optimal write size of an open zone among the multiple zones; updating a historical size by accumulating the value of data previously refreshed to the storage device; determining a target size of data to be refreshed to the storage device based on the optimal write size, the historical size, and the size of buffer data stored in a host buffer; and refreshing the data in the buffer data corresponding to the target size to the storage device.

15. The method of operating the host as described in claim 14, wherein, The steps for determining the target size include: setting the target size based on the optimal write size and the historical size; and adjusting the target size based on a comparison between the target size and the size of the buffer data.

16. The method of operating the host as described in claim 15, wherein, In the step of setting the target size, the value obtained by subtracting the historical size from the optimal write size is set as the initial value of the target size.

17. The method of operating the host as described in claim 16, wherein, In the step of adjusting the target size, when the size of the buffer data is less than the target size, the value of the target size is initialized; when the size of the buffer data is equal to the target size, the value of the target size is maintained; and when the size of the buffer data is greater than the target size, the value of the target size is adjusted within the size range of the buffer data to a value obtained by adding an integer multiple of the optimal write size to the initial value of the target size.

18. The host operation method as described in claim 14 further includes the following steps: prior to the refresh, providing a synchronization request to the storage device in response to a synchronization event that synchronizes the host and the storage device.

19. A method of operating a host device, the method comprising: buffering buffer data as represented by Equation 1 while keeping the size of the buffer data constant; and refreshing at least a portion of the buffer data to a storage device, wherein the size of the portion is an amount represented by Equation 2: [Equation 1] A > B, where "A" represents the size of data that can be refreshed to the storage device within the optimal write capacity of the storage device, A is CD, "B" represents the size of the buffer data, "C" represents the optimal write capacity, "D" represents the size of data previously refreshed from the buffer to the storage device within the optimal write capacity, D is E mod C, and "E" represents the size of data previously refreshed from the buffer to the storage device, and [Equation 2] A ≤ B, A ≤ F ≤ B, where "F" represents the size of the portion.

20. The method of operation as described in claim 19, wherein the size of the portion is a quantity represented as follows: F = αC + A, where "α" represents zero (0) or a larger integer.

Images