Stacked die integrated circuit (IC) package employing interposer for coupling an upper stacked die(s) to a package substrate for package height reduction, and related fabrication methods

Abstract

A stacked die integrated circuit (IC) package employing an interposer to electrically couple upper stacked dies to a package substrate, and a related manufacturing method, are described. To reduce the height of the IC package while simultaneously providing stacked dies to be electrically coupled to the package substrate, the IC package includes an interposer. The stacked dies are disposed between the package substrate and the interposer. One or more wires are coupled (e.g., wire bonding) between the upper dies and the interposer to provide electrical connectivity between the upper dies and the interposer. One or more electrical interconnects (e.g., conductive pillars) are coupled between the interposer and the package substrate to route electrical connections between the upper dies and the package substrate. Therefore, the upper dies can be electrically coupled to the package substrate without requiring additional clearance above the upper dies for wire bonding.

Description

[Technical Field]

[0001] The field of this case relates to integrated circuit (IC) packaging, and more particularly to a packaging substrate for bonding semiconductor die wires to the IC package. [Previous Technology]

[0002] Integrated circuits (ICs) are the cornerstone of electronic components. ICs are packaged in IC packages (also known as "semiconductor packages" or "chip packages"). An IC package includes one or more semiconductor dies as ICs, which are mounted on and electrically coupled to the package substrate to provide physical support and electrical interfaces for the dies. The package substrate includes one or more metallization layers, which include electrical traces (e.g., metal lines) having vertical interconnects (vias) that couple the electrical traces together between adjacent metallization layers to provide electrical interfaces between the dies. The dies are electrically connected to exposed metal interconnects in the top or outer layers of the package substrate to electrically couple the semiconductor dies to the electrical traces of the package substrate. The package substrate includes an external metallization layer coupled to an external metal interconnect (e.g., solder bumps) to provide an external interface between the dies in the IC package for mounting the IC package on a circuit board to connect the dies to other circuit systems.

[0003] Some IC packages are referred to as "hybrid" IC packages, which include multiple chips for different purposes or applications. For example, a hybrid IC package may include a modem chip as part of a front-end circuit system to support a communication interface. A hybrid IC package may also include one or more memory chips that provide memory to support data storage and access performed by the modem chip, such as for buffering and outputting data to be modulated and / or demodulated. Therefore, in such hybrid IC packages, it is conventional to stack multiple chips on top of each other in the IC package. The bottommost chip, which is directly adjacent to the package substrate of the IC package, is electrically coupled to a metal interconnect in the upper metallization layer of the package substrate via a chip interconnect. Other stacked chips that are not directly adjacent to the package substrate of the IC package may be electrically coupled to the metallization layer of the package substrate via wire bonding. Electrical connections between memory chips and modem chips are formed via electrical connections in the package substrate. [Summary of the Invention]

[0004] The various embodiments disclosed herein include: stacked die integrated circuit (IC) packages in which an interposer is used to electrically couple the upper stacked dies to a package substrate in order to reduce package height. Related manufacturing methods are also disclosed. The IC package includes a package substrate supporting the stacked dies. The package substrate includes one or more metallization layers, each metallization layer including metal interconnects to provide electrical signal routing between external interconnects and dies, and between dies within the IC package. The stacked dies are electrically coupled to the package substrate for signal routing. The lower die in the IC package may be directly electrically coupled to the package substrate (e.g., via interconnect bumps), thereby coupling the active side of the lower die to the metal interconnects in the upper metallization layer of the package substrate. However, the upper dies stacked above the lower dies in the IC package are not placed directly adjacent to the package substrate. Wire bonding may be used to couple the active side of the upper dies to the package substrate. However, the wire bonding may need to be oriented to extend above the upper die to have sufficient headroom to extend outwards and subsequently downwards to the package substrate without interfering with the lower die or other packaged components. The wire bonding may also require a minimum bending radius to avoid damage, necessitating an additional headroom above the upper die that extends beyond the normal tolerance between the upper die and the top surface of the IC package's plastic coating. This additional headroom contributes to the overall height of the IC package, which may be undesirable.

[0005] Therefore, in an exemplary embodiment, to reduce the height of the IC package while still providing a stacked die arrangement to be electrically coupled to the package substrate, the IC package includes an interposer. The stacked dies are disposed between the package substrate and the interposer. One or more wires are coupled (e.g., wire bonding) between the active side of the upper die and the interposer to provide electrical connectivity between the upper die and the interposer. One or more electrical interconnects (e.g., conductive pillars) are coupled between the interposer and the package substrate to route electrical connections between the wires coupled to the upper die and the package substrate. In this way, the upper die can be electrically coupled to the package substrate without requiring additional clearance for wire bonding to be coupled to the upper die and downward to the package substrate. The height of the interposer added to the overall height of the IC package may be less than the clearance height originally required to wire bond the upper die to the package substrate.

[0006] In this regard, in one exemplary embodiment, an IC package is disclosed. The IC package includes a package substrate. The IC package also includes an interposer. The IC package also includes a first die electrically coupled to the package substrate. The IC package also includes a second die disposed between the first die and the interposer. The IC package also includes one or more second conductors coupled to the second die and the interposer. The IC package also includes one or more electrical interconnects coupled to the interposer and the package substrate, and each electrical interconnect electrically couples one of the one or more second conductors to the package substrate.

[0007] In another exemplary embodiment, a method for manufacturing an IC package is disclosed. The method includes the steps of: providing a package substrate. The method also includes the steps of: providing an interposer. The method also includes the steps of: electrically coupling a first die to the package substrate. The method also includes the steps of: disposing a second die between the first die and the interposer. The method also includes the steps of: coupling one or more second wires to the second die and the interposer. The method also includes the steps of: coupling one or more electrical interconnects to the package substrate and the interposer, such that one of the one or more second wires is electrically coupled to the package substrate.

Implementation Method

[0021] Several exemplary forms of this case are now described with reference to the accompanying drawings. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any form described herein as "exemplary" is not necessarily to be construed as superior to or better than other forms.

[0022] The various embodiments disclosed herein include: a stacked die integrated circuit (IC) package in which an interposer is used to electrically couple the upper stacked dies to a package substrate in order to reduce package height. Related manufacturing methods are also disclosed. The IC package includes a package substrate supporting the stacked dies. The package substrate includes one or more metallization layers, each metallization layer including metal interconnects to provide electrical signal routing between external interconnects and dies, and between dies within the IC package. The stacked dies are electrically coupled to the package substrate for signal routing. The lower die in the IC package may be directly electrically coupled to the package substrate (e.g., via interconnect bumps), thereby coupling the active side of the lower die to the metal interconnects in the upper metallization layer of the package substrate. However, the upper dies stacked above the lower dies in the IC package are not placed directly adjacent to the package substrate. Wire bonding may be used to couple the active side of the upper dies to the package substrate. However, the wire bonding may need to be oriented to extend above the upper die to have sufficient headroom to extend outwards and subsequently downwards to the package substrate without interfering with the lower die or other packaged components. The wire bonding may also require a minimum bending radius to avoid damage, necessitating an additional headroom above the upper die that extends beyond the normal tolerance between the upper die and the top surface of the IC package's plastic coating. This additional headroom contributes to the overall height of the IC package, which may be undesirable.

[0023] Therefore, in an exemplary embodiment, to reduce the height of the IC package while still providing a stacked die arrangement to be electrically coupled to the package substrate, the IC package includes an interposer. The stacked dies are disposed between the package substrate and the interposer. One or more wires are coupled (e.g., wire bonding) between the active side of the upper die and the interposer to provide electrical connectivity between the upper die and the interposer. One or more electrical interconnects (e.g., conductive pillars) are coupled between the interposer and the package substrate to route electrical connections between the wires coupled to the upper die and the package substrate. In this way, the upper die can be electrically coupled to the package substrate without requiring additional clearance for wire bonding to be coupled to the upper die and downward to the package substrate. The height of the interposer added to the overall height of the IC package may be less than the clearance height originally required to wire bond the upper die to the package substrate.

[0024] In this regard, FIG1A is a side view of an exemplary IC package 100, which includes two (2) stacked dies 102 (1), 102 (2) disposed between a package substrate 104 and an interposer 106. In this example, the first die 102 (1) is considered a "lower" die, which means that it is disposed below the second "upper" die 102 (2) in the vertical Z-axis direction, as shown in FIG1A. The lower die 102 (1) is disposed adjacent to the package substrate 104. The upper die 102 (2) is disposed adjacent to the interposer 106. A plastic coating 105 (e.g., epoxy resin) surrounds the stacked dies 102 (1), 102 (2) between the interposer 106 and the package substrate 104. The stacked dies 102 (1), 102 (2) include an IC for performing electronic functions according to its design. For example, the lower die 102 (1) may be a communication modem. The upper die 102(2) may be a memory device designed to provide data storage and access to a data processor in the lower die 102(1), such as for buffering data to be modulated for transmission as a radio frequency (RF) signal and demodulated data from received RF signals.

[0025] The package substrate 104 supports stacked dies 102(1), 102(2) and also includes metallization layers 108(1), 108(2), each metallization layer including metal interconnects 110(1), 110(2) (e.g., metal lines, metal traces, vertical interconnect vias (vias)) that can provide electrical signal routing between external interconnects 112 (e.g., solder bumps) and dies 102(1), 102(2). The metallization layers 108(1), 108(2) may be formed as inter-bonded laminates and / or as redistribution layers (RDLs). Although not shown, it should be noted that the package substrate 104 may also include a core portion to serve as a cored substrate instead of a coreless substrate. In this example, the package substrate 104 includes an external metallization layer 108(3) having metal interconnects 110(3) exposed from the package substrate 104, wherein external interconnects 112 are coupled to the metal interconnects 110(3) to provide external signal routing access to the IC package 100. For example, the external interconnects 112 may be soldered to contacts on a printed circuit board (PCB) to physically mount the IC package 100 on the PCB and to couple the IC package 100 to other circuit systems. Certain metal interconnects 110(1), 110(2) in the package substrate 104 may also be designated to provide internal signal routing between the dies 102(1), 102(2) themselves.

[0026] Continuing with reference to FIG1A, stacked dies 102(1) and 102(2) are electrically coupled to package substrate 104 for signal routing. The lower die 102(1) in the IC package 100 is shown to be directly electrically coupled to the package substrate 104 via interconnect bumps 114. The active side 116 of the lower die 102(1) adjacent to the package substrate 104 is coupled to the interconnect bumps 114, which are coupled to the metal interconnects 110(1) in the upper metallization layer 108(1) of the package substrate 104. However, the upper die 102(2) stacked above the lower die 102(1) in the IC package 100 is not placed directly adjacent to the package substrate 104. The active side 118 of the upper die 102(2) can be directly coupled to the metal interconnects 110(1) in the upper metallization layer 108(1) of the package substrate 104 using wire bonding. However, the wire bonding may need to be oriented to extend vertically (Z-axis) above the upper die 102(2) to have sufficient clearance to extend outward and subsequently downward to the package substrate 104 without interfering with the lower die 102(1) or other package components. The wire bonding may also require a minimum bending radius to avoid damage, which would otherwise require an additional clearance area in the IC package 100 above the upper die 102(2) to have sufficient area for such wire bonding and to accommodate its required minimum bending radius. This additional clearance area (if present) would otherwise contribute to the overall height H1 of the IC package 100, which may be undesirable.

[0027] Therefore, as shown in the additional side view of the IC package 100 in FIG1B, in order to reduce the height of the IC package 100 while still providing stacked dies 102(1), 102(2) to be electrically coupled to the package substrate 104, the IC package 100 in FIG1B includes an interposer 106. The interposer 106 provides electrical interface routing between components, in this case, the interposer 106 is located between the upper die 102(2) and electrical interconnects 120 (e.g., metal pillars, metal posts, metal vias), which couple the interposer 106 to the package substrate 104. For example, the interposer 106 may include one or more metallization layers 122, each metallization layer 122 including one or more metal interconnects electrically coupled to the upper die 102(2) and also electrically coupled to one or more electrical interconnects 120 for routing electrical signals from the upper die 102(2) to the package substrate 104. In this manner, the upper die 102(2) is electrically coupled to the package substrate 104 for signal routing to external interconnects 112 and / or electrically coupled to other metal interconnects 110(1), 110(2) in the metallization layers 108(1), 108(2) coupled to the lower die 102(1) for die-to-die connections. As shown in FIG1B, in this example, one or more lines 124 are coupled (e.g., wire bonding) between the active side 118 of the upper die 102(2) and the interposer 106 to provide an electrical interface connection between the upper die 102(2) and the interposer 106. Electrical interconnects 120 are coupled between the interposer 106 and the package substrate 104 to route electrical connections between the wires 124 coupled to the upper die 102(2) and the package substrate 104. In this way, the upper die 102(2) can be electrically coupled to the package substrate 104 without requiring additional clearance for wire bonding extending upwards on the upper die 102(2) in the vertical (Z-axis) direction and then downwards back to the package substrate 104 to be coupled to the active side 118 of the upper die 102(2). Adding the height H2 of the interposer 106 to the overall height H1 of the IC package 100 may be less than the additional height that the encapsulation 105 would originally require to provide additional clearance above the upper die 102(2) for bonding the wires of the upper die 102(2) to the package substrate 104. For example, the height H2 of the interposer 106 may be 50 micrometers (μm).

[0028] To further illustrate the exemplary differences between the IC package 100 in FIG1A and FIG1B, which includes an intermediary layer 106 for providing electrical connection between the upper die 102 (2) and the package substrate 104, and an IC package that would otherwise use wire bonding to electrically connect the upper die 102 (2) to the package substrate 104, FIG2A and FIG2B are provided. FIG2B is a side view of the IC package 100 in FIG1A. As shown therein, the IC package 100 has an overall height H1, wherein the intermediary layer has a height H2 that contributes to the overall height H1 of the IC package 100. FIG2A is a side view of an alternative IC package 200, which includes the same package substrate 104 and stacked dies 102 (1) and 102 (2) as in the IC package 100 in FIG1A. However, as shown in FIG2A, the upper IC die 102 (1) is wire bonded to the package substrate 104 via wire 202. To enable the conductor 202 to connect to the package substrate 104, the conductor 202 has a bent portion 204 that extends upward from the upper die 102(2) in the vertical (Z-axis) direction and then extends outward in the horizontal (X-axis) direction, bending downward back towards the package substrate 104 to be routed to the package substrate 104 with a clearance path. The minimum radius of the bent portion 204 and the angle θ1 at which the conductor 202 needs to extend downward to the package substrate 104 define a minimum conductor bonding clearance area 205 height H4 that must be reserved above the upper die 102(2) for the conductor 202. Moreover, an additional area 206 of height H5 is required above the conductor bonding clearance area 205 to provide tolerance between the upper surfaces 208 of the encapsulation 210 of the IC package 200. Therefore, by providing a wire bond between the upper die 102(2) and the package substrate 104 in the IC package 200 of FIG. 2A, a minimum wire bond clearance area 205 height H4 contributing to the overall height H3 of the IC package 200 is added. It should be noted that in this example, the overall height H3 of the IC package 200 is greater than the overall height H1 of the IC package 100 in FIG. 1A using an interposer 106. For example, the height H2 of the interposer 106 could be 50 μm compared to the minimum wire bond clearance area 205 and the additional area 206 height of 125 μm, thereby providing an additional 75 μm difference in the overall height H3 of the IC package 200 in FIG. 2A relative to the overall height H1 of the IC package 100 in FIG. 1A to FIG. 1B and FIG. 2B.

[0029] Referring back to FIG1B, the lower die 102(1) of IC package 100 has a passive side 126 on the opposite side of the active side 116. In this example, the active side 118 of the upper die 102(2) is adjacent to the passive side 126 of the lower die 102(4). At least a portion of the active side 118 of the upper die 102(2) may be bonded to at least a portion of the passive side 126 of the lower die 102(1), for example, via epoxy resin or compression bonding. The upper die 102(2) has a passive side 128 on the opposite side of the active side 118 of the upper die 102(2). A wire 124 is coupled to the active side 118 of the upper die 102(2) and also coupled to the interposer 106 to electrically couple the upper die 102(2) to the interposer 106. In this example, to make room for the wire 124 to be coupled between the upper die 102(2) and the interposer 106, the upper die 102(2) is staggered so that it only partially overlaps with the lower die 102(1) in the horizontal (X-axis) direction. In this regard, the active side 118 of the upper die 102(2) includes a first active side portion 130 that overlaps with a portion of the passive side 126 of the lower die 102(2) in the vertical (Z-axis) direction, and a second active side portion 132 that does not overlap with the lower die 102(1) in the vertical (Z-axis) direction. In this way, space is provided for the wire 124 to extend downward from the active side 118 of the upper die 102(2) toward the package substrate 104 and then bend upward toward the interposer 106 to subsequently extend and couple to the interposer 106. This arrangement avoids the bending portion 134 of the conductor 124 extending vertically above the upper die 102(2), thus avoiding the need to retain additional area above the upper die 102(2), which would otherwise increase the height of the IC package 100. In this example, the conductor 124 includes a concave bending portion 134 extending downward from the upper die 102(2) (vertically extending downward toward the package substrate 104 below the active side 118 of the upper die 102(2)) and then turning upward toward the interposer 106.

[0030] It should be noted that although the IC package 100 in Figures 1A and 1B includes only two dies 102(1) and 102(2), other IC packages including an interposer for electrical coupling to the upper die can be provided, wherein such IC packages include more than two (2) dies. In this regard, Figure 3A is a side view of an exemplary IC package 300, which includes three (3) stacked dies 302(1)-302(3) disposed between the package substrate 304 and the interposer 306. In this example, the first die 302(1) is considered to be the "lower" die, which means that it is disposed below the second "upper" die 302(2) and the third die 302(3) in the vertical Z-axis direction, as shown in Figure 3A. In this example, the third die 302(3) is considered a "middle" die, meaning it is positioned between the lower die 302(1) and the upper die 302(2) in the vertical Z-axis direction, as shown in Figure 3A. The lower die 302(1) is disposed adjacent to the package substrate 304. The upper die 302(2) is disposed adjacent to the interposer 306. A plastic coating 305 (e.g., epoxy resin) surrounds the stacked dies 302(1)-302(3) between the interposer 306 and the package substrate 304. The stacked dies 302(1)-302(3) include an IC for performing electronic functions according to its design. For example, the lower die 302(1) may be a communication modem. The middle and upper dies 302(3) and 302(2) may be memory devices designed to provide data storage and access to the data in the lower die 302(1), such as buffering data to be modulated for transmission as radio frequency (RF) signals and demodulated data from received RF signals.

[0031] The package substrate 304 supports stacked dies 302(1)-302(3) and also includes metallization layers 308(1), 308(2), each metallization layer including metal interconnects 310(1), 310(2) (e.g., metal lines, metal traces, vias) that can provide electrical signal routing between external interconnects 312 (e.g., solder bumps) and dies 302(1)-302(3). The metallization layers 308(1), 308(2) may be formed as inter-bonded laminates and / or formed as RDLs. Although not shown, it should be noted that the package substrate 304 may also include a core portion to serve as a cored substrate instead of a coreless substrate. In this example, the package substrate 304 includes an external metallization layer 308(3) having metal interconnects 310(3) exposed from the package substrate 304, wherein external interconnects 312 are coupled to the metal interconnects 310(3) to provide external signal routing access to the IC package 300. For example, the external interconnects 312 may be soldered to contacts on a PCB to physically mount the IC package 300 on the PCB and couple the IC package 300 to other circuit systems. Certain metal interconnects 310(1), 310(2) in the package substrate 304 may also be designated to provide internal signal routing between the dies 302(1)-302(3) themselves.

[0032] Continuing with reference to FIG3A, the stacked dies 302(1)-302(3) are electrically coupled to the package substrate 304 for signal routing. The lower die 302(1) in the IC package 300 is shown to be directly electrically coupled to the package substrate 304 via interconnect bumps 314. The active side 316 of the lower die 302(1) adjacent to the package substrate 304 is coupled to the interconnect bumps 314, which are coupled to the metal interconnects 310(1) in the upper metallization layer 308(1) of the package substrate 304. However, the middle and upper dies 302(3), 302(2) stacked above the lower die 302(1) are not placed directly adjacent to the package substrate 304. The active side 318 of the upper die 302(2) can be directly coupled to the metal interconnects 310(1) in the upper metallization layer 308(1) of the package substrate 304 by wire bonding. However, the wire bonding may need to be oriented to extend vertically (Z-axis) above the upper die 302(2) to have sufficient clearance to extend outward and subsequently downward to the package substrate 304 without interfering with the middle and / or lower dies 302(3), 302(1) or other package elements. The wire bonding may also require a minimum bending radius to avoid damage, which would otherwise require an additional clearance area in the IC package 300 above the upper die 302(2) to have sufficient area for such wire bonding and to accommodate its required minimum bending radius. This additional clearance area (if present) would contribute to the overall height H6 of the IC package 300, which may be undesirable.

[0033] Therefore, as shown in the additional side view of the IC package 300 in FIG3B, in order to reduce the height of the IC package 300 while still providing stacked dies 302(1)-302(3) to be electrically coupled to the package substrate 304, the IC package 300 in FIG3C includes an interposer 306. The interposer 306 provides electrical interface routing between components, and in this case, the interposer 306 is located between the upper die 302(1) and electrical interconnects 320 (e.g., metal pillars, metal posts, metal vias) that couple the interposer 306 to the package substrate 304. For example, the interposer 306 may include one or more metallization layers 322, each metallization layer 322 including one or more metal interconnects that are electrically coupled to the upper die 302(1) and also electrically coupled to one or more electrical interconnects 320 for routing electrical signals from the upper die 302(1) to the package substrate 304. In this manner, the upper die 302(2) is electrically coupled to the package substrate 304 for signal routing to external interconnects 312 and / or electrically coupled to other metal interconnects 310(1), 310(2) in the metallization layers 308(1), 308(2) coupled to the middle and lower dies 302(3), 302(1) for die-to-die connections. As shown in FIG3B, in this example, one or more lines 324 are coupled (e.g., wire bonding) between the active side 318 of the upper die 302(2) and the interposer 306 to provide an electrical interface connection between the upper die 302(2) and the interposer 306. Electrical interconnects 320 are coupled between the interposer 306 and the package substrate 304 to route electrical connections between the wires 324 coupled to the upper die 302(2) and the package substrate 304. In this way, the upper die 302(1) can be electrically coupled to the package substrate 304 without requiring additional clearance for wire bonding extending in the vertical (Z-axis) direction above the upper die 302(1) and then returning downward to the package substrate 304 to be coupled to the active side 318 of the upper die 302(1). Adding the height H7 of the interposer 306 to the overall height H6 of the IC package 300 may be less than the additional height that would otherwise be required to provide additional clearance above the upper die 302(2) for bonding the wires of the upper die 302(2) to the package substrate 304. For example, the height H7 of the interposer 306 may be 50 micrometers (μm).

[0034] Continuing to refer to FIG3B, the lower die 302(1) of the IC package 300 has a passive side 326 on the opposite side of the active side 316. The middle die 302(3) of the IC package 300 has a passive side 336 adjacent to the passive side 326 of the lower die 302(1). The middle die 302(3) has an active side 338 on the opposite side of the passive side 336 and adjacent to the active side 318 of the upper die 302(2). At least a portion of the passive side 336 of the middle die 302(3) may be bonded to at least a portion of the passive side 326 of the lower die 302(1) (e.g., via epoxy resin or compression bonding). At least a portion of the active side 318 of the upper die 302(2) may be bonded to at least a portion of the active side 338 of the middle die 302(3) (e.g., via epoxy resin or compression bonding). The upper die 302(2) has a passive side 328 on the opposite side of the active side 318 of the upper die 302(2). A wire 324 is coupled to the active side 318 of the upper die 302(2) and also to the interposer 306 to electrically couple the upper die 302(2) to the interposer 306. In this example, space is made for the wire 324 to be coupled between the upper die 302(2) and the interposer 306, and the upper die 302(2) is staggered to partially overlap with the middle die 302(3) in the horizontal (X-axis) direction. In this regard, the active side 318 of the upper die 302(2) includes a first active side portion 330 that overlaps with a portion of the active side 338 of the middle die 302(2) in the vertical (Z-axis) direction, and a second active side portion 332 that does not overlap with the middle die 302(3) in the vertical (Z-axis) direction. In this way, space is provided for the conductor 324 to extend downward from the active side 318 of the upper die 302(2) toward the package substrate 304 and then bend upward toward the interposer 306 to subsequently extend and couple to the interposer 306. This arrangement avoids the need for the bent portion 334 of the conductor 324 to extend vertically above the upper die 302(2), thus avoiding the requirement to retain additional area above the upper die 302(2), which would otherwise increase the height of the IC package 300. In this example, the conductor 324 includes a concave bend 334 that extends downward from the upper die 302(2) (in the vertical direction below the active side 318 of the upper die 302(2) toward the package substrate 304) and then bends upward toward the interposer 306.

[0035] Moreover, as shown in FIG3B, in this example, the middle die 302(3) is electrically coupled to the package substrate 304 via a wire 340 (e.g., a wire bond). Because the active side 338 of the middle die 302(3) includes a first active side portion 342 that does not overlap with the upper die 302(2) in the vertical (Z-axis) direction, there is space for the wire 340 to extend upward from the active side 338 of the middle die 302(3) toward the interposer 306 and then bend downward toward the package substrate 304 to subsequently extend and couple to the package substrate 304. Alternatively, the middle die 302(3) may be oriented inverted, wherein the active side 338 is adjacent to the lower die 302(1) and its passive side 336 is adjacent to the upper die 302(2). In this example, similar to the wire 324 that couples the upper die 302(2) to the interposer 306, the wire 340 may subsequently be oriented to couple the active side 338 of the middle die 302(3) to the interposer 306. In this latter exemplary scenario, the middle die 302(3) may be electrically coupled to the package substrate 304 via the connection between the interposer 306 and the electrical interconnect 320.

[0036] FIG4 is a flowchart illustrating an exemplary process 400 for manufacturing an IC package including stacked dies between a package substrate and an interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height. The exemplary process 400 in FIG4 can be used to manufacture IC packages 100 and 300 in FIGS. 1A-1B and 3A-3B, respectively. The process 400 in FIG4 will be discussed in conjunction with the IC packages 100 and 300 in FIGS. 1A-1B and 3A-3B.

[0037] In this regard, as shown in FIG4, an exemplary step in process 400 is to provide packaging substrates 104 and 304 (block 402 in FIG4). Another exemplary step in process 400 is to provide interposers 106 and 306 (block 404 in FIG4). Another exemplary step in process 400 is to electrically couple first dies 102(1) and 302(1) to packaging substrates 104 and 304 (block 406 in FIG4). Another exemplary step in process 400 is to dispose second dies 102(2) and 302(2) between the first dies 102(1) and 302(1) and interposers 106 and 306 (block 408 in FIG4). Another exemplary step in procedure 400 is to couple one or more second wires 124, 324 to the second dies 102(2), 302(2) and the interposers 106, 306 (block 410 in FIG. 4). Another exemplary step in procedure 400 is to couple one or more electrical interconnects 120, 320 to the package substrates 104, 304 and the interposers 106, 306 to electrically couple one of the one or more second wires 124, 324 to the package substrates 104, 304 (block 412 in FIG. 4).

[0038] An IC package comprising a lower die directly electrically coupled to a package substrate and an upper die electrically coupled to the package substrate via an interposer to reduce package height can be manufactured as a sub-assembly to be subsequently assembled together. For example, FIG5 is a flowchart illustrating an exemplary process 500 for manufacturing an interposer and upper die package to be included in an IC package comprising stacked dies between a package substrate and an interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via an interposer to reduce package height. This may include IC packages 100 and 300 as shown in FIG1A-1B and FIG3A-3B, respectively. FIG6A-6C illustrate exemplary manufacturing stages 600A-600C during the manufacturing of an interposer and upper die package for an IC package according to the exemplary manufacturing process 500 in FIG5, including but not limited to IC packages 100 and 300 as shown in FIG1A-1B and FIG3A-3B. The procedure 500 in Figure 5 will be discussed in conjunction with the manufacturing stages 600A to 600C in Figures 6A to 6C and with reference to the IC package 300 in Figures 3A to 3B.

[0039] In this regard, as illustrated in exemplary manufacturing stage 600A in FIG6A, the first step in process 500 of manufacturing interposer 106 and upper die 102(2) subpackage may be: setting the passive side 328 of upper die 102(2) on interposer 106 (block 502 in FIG5). Subsequently, as illustrated in exemplary manufacturing stage 600B in FIG6B, the next step of process 500 may be: providing wire 324 and coupling (e.g., wire bonding) wire 324 to active side 318 of upper die 302(2) and interposer 306 to provide interposer 306 and upper die 302(2) subpackage (block 504 in FIG5). Subsequently, as illustrated in exemplary manufacturing stage 600C in FIG6C, the next step of process 500 may be: flipping the interposer 306 and the upper die 302(2) subpackage to prepare to place it on the package substrate 304 and the lower die 302(1) subpackage, as will be described below with respect to FIG7 to FIG8C.

[0040] FIG7 is a flowchart illustrating an exemplary process 700 for manufacturing a package substrate and a lower die package to be included in an IC package, the IC package including stacked dies between the package substrate and an interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height. This may include IC packages 100 and 300 in FIG1A-1B and FIG3A-3B, respectively. FIG8A-8C illustrate exemplary manufacturing stages 800A-800C during the manufacturing of the package substrate and lower die package for an IC package according to the exemplary manufacturing process in FIG7, the IC package including but not limited to IC packages 100 and 300 in FIG1A-1B and FIG3A-3B. The process 700 in FIG7 will be discussed in conjunction with manufacturing stages 800A-800C in FIG8A-8C and with reference to IC package 300 in FIG3A-3B.

[0041] In this regard, as illustrated in exemplary manufacturing stage 800A of FIG8A, the first step in process 700 of manufacturing package substrate 304 and lower die 302(2) subpackage may be: providing package substrate 304 and forming electrical interconnects 320 coupled to package substrate 304 (block 702 in FIG7). As illustrated in exemplary manufacturing stage 800B of FIG8B, the next step in process 700 of manufacturing package substrate 304 and lower die 302(2) subpackage may be: coupling lower die 302(1) to package substrate 304 via interconnect bumps 314 to stack middle die 302(3) on lower die 302(1) (block 704 in FIG7). The passive side 336 of middle die 302(3) may be bonded to the passive side 326 of lower die 302(1). As previously discussed, in this example, the middle die 302 (3) is stacked on top of the lower die 302 (1) such that the middle die 302 (3) only partially overlaps with the lower die 302 (1). This provides space for the wires 340 to couple to the active side 338 of the middle die 302 (3) and the package substrate 304. As illustrated in the exemplary manufacturing stage 800C of FIG8C, the next step in the process 700 of manufacturing the package substrate 304 and the lower die 302 (2) subpackage may be: providing the wires 340 and coupling (e.g., wire bonding) the wires to the active side 338 of the middle die 302 (3) and the package substrate 304 to electrically couple the middle die 302 (3) to the package substrate 304 (block 706 in FIG7).

[0042] Figures 9A and 9B are flowcharts 900 illustrating an exemplary process for assembling an interposer and upper die package (including but not limited to the interposer 306 and upper die 302(2) subpackage in Figure 6C) with a package substrate and a lower die package (including but not limited to the package substrate 304 and lower die 302(1) subpackage in Figure 8C) to manufacture an IC package. The manufactured IC package includes stacked dies between the package substrate and the interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height. The IC package includes, but is not limited to, the IC packages 100 and 300 in Figures 1A to 1B and Figures 3A to 3B. Figures 10A to 10C illustrate exemplary manufacturing stages 1000A to 1000C during the assembly of an interposer and upper die package with a package substrate and a lower die package to form an IC package according to the exemplary manufacturing process in Figures 9A and 9B. The IC package includes, but is not limited to, IC packages 100 and 300 in Figures 1A to 1B and Figures 3A to 3B. Process 900 in Figures 9A and 9B will be discussed in conjunction with manufacturing stages 1000A to 1000C in Figures 10A to 10C and with reference to the interposer 306 and upper die 302(2) subpackage in Figures 3A to 3B and Figure 6C and the package substrate 304 and lower die 302(1) subpackage in Figure 8C.

[0043] In this regard, as illustrated in the exemplary manufacturing stage 1000A of FIG10A, the first step in process 900 of manufacturing IC package 300 including interposer 306 and upper die 302(2) subpackage in FIG6C and package substrate 304 and lower die 302(1) subpackage in FIG8C may be: providing interposer 306 and upper die 302(2) subpackage in FIG6C and package substrate 304 and lower die 302(1) subpackage in FIG8C (block 902 in FIG9A). As illustrated in exemplary manufacturing stage 1000B of FIG10B, a next step in process 900 of manufacturing an IC package 300 comprising an interposer 306 and an upper die 302(2) subpackage in FIG6C and a package substrate 304 and a lower die 302(1) subpackage in FIG8C may be: attaching the interposer 306 to the electrical interconnect 320 and bonding the upper die 302(2) to the middle die 302(3) such that the upper die 302(2) and the middle die 302(3) partially overlap (block 904 in FIG9A). This provides space for wires 340 and 324 to electrically couple the respective middle and upper dies 302(3), 302(2) to the respective interposer 306 and package substrate 304. As previously discussed, in this example, the active side 318 of the upper die 302(2) is bonded to the active side 338 of the middle die 302(3). As illustrated in the exemplary manufacturing stage 1000C of FIG10C, a next step in process 900 of manufacturing an IC package 300 comprising the interposer 306 and the upper die 302(2) subpackage in FIG6C and the package substrate 304 and the lower die 302(1) subpackage in FIG8C may be: filling the area between the interposer 306 and the package substrate 304 with a plastic coating material 344 to form a plastic coating 305 (block 906 in FIG9B). The plastic coating 305 is formed around the dies 302(1)-302(3) and the bonding wires 324, 340 to protect and insulate these components.

[0044] An IC package having stacked dies between a package substrate and an interposer can be provided in any processor-based device (where the lower and middle dies are directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height, the IC package including but not limited to the IC packages of Figures 1A to 1B, 3A to 3B, 6A to 6C, 8A to 8C and 10A to 10B and according to the exemplary manufacturing process in Figures 5, 7 and 9A to 9B) or the IC package can be integrated into any processor-based device. Examples not limited to these include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, automotive components, avionics systems, drones, and multi-rotor aircraft.

[0045] In this regard, FIG11 illustrates an example of a processor-based system 1100. The components of the processor-based system 1100 are ICs 1102. According to any of the configurations disclosed herein, some or all of the ICs 1102 in the processor-based system 1100 may be provided in an IC package having stacked dies between a package substrate and an interposer, wherein the lower and middle dies are directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via an interposer to reduce the package height. This IC package includes, but is not limited to, the IC packages of FIGS. 1A-1B, 3A-3B, 6A-6C, 8A-8C, and 10A-10B and the exemplary manufacturing processes shown in FIGS. 5, 7, and 9A-9B. In this example, the processor-based system 1100 may be formed as an IC package 1104 and as a system-on-a-chip (SoC) 1106. Processor-based system 1100 includes CPU 1108, which includes one or more processors 1110, also referred to as CPU cores or processor cores. CPU 1108 may have cache memory 1112 coupled to CPU 1108 for fast access to temporarily stored data. CPU 1108 is coupled to system bus 1114 and may be coupled to master and slave devices included in processor-based system 1100. As is well known, CPU 1108 communicates with these other devices by exchanging address, control, and data information on system bus 1114. For example, CPU 1108 may communicate bus transaction requests to memory controller 1116, which is an instance of a slave device. Although not shown in FIG11, multiple system buses 1114 may be provided, each forming a different texture.

[0046] Other master and slave devices may be connected to system bus 1114. As illustrated in FIG11, as an example, such devices may include a memory system 1120 comprising a memory controller 1116 and (various) memory arrays 1118, one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128. Each of the memory system 1120, one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128 may be provided in the same or different circuit packages. The (various) input devices 1122 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (various) output devices 1124 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (All) Network interface devices 1126 may be any device configured to allow data exchange to and from network 1130. Network 1130 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. (All) Network interface devices 1126 may be configured to support any type of communication protocol desired.

[0047] The CPU 1108 may also be configured to access the display controllers 1128 via the system bus 1114 to control information sent to one or more displays 1132. The display controllers 1128 send information to be displayed to the displays 1132 via one or more video processors 1134, which process the information to be displayed into a format suitable for the displays 1132. As an example, the display controllers 1128 and the video processors 1134 may be included as IC packages 1104 and the same or different circuit packages, and in the same or different circuit packages containing the CPU 1108. The displays 1132 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0048] FIG12 illustrates an exemplary wireless communication device 1200 comprising radio frequency (RF) components formed of one or more ICs 1202 according to any of the forms disclosed herein, wherein any IC 1202 may include (e) IC packages 1203 having stacked dies between a package substrate and an interposer, wherein the lower and middle dies are directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height. The IC package 1203 includes, but is not limited to, the IC packages of FIG1A-1B, FIG3A-3B, FIG6A-6C, FIG8A-8C and FIG10A-10B and the exemplary manufacturing process according to FIG5, FIG7 and FIG9A-9B. As an example, the wireless communication device 1200 may be included in or disposed in any of the above-described devices. As shown in FIG12, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include memory for storing data and code. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 supporting bidirectional communication. Generally, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0049] The transmitter 1208 or receiver 1210 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted in multiple stages between the RF and the baseband frequency; for example, for receiver 1210, it is converted from RF to intermediate frequency (IF) in one stage, and then from IF to the baseband frequency in another stage. In a direct conversion architecture, the signal is converted between the RF and the baseband frequency in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 1200 in Figure 12, the transmitter 1208 and receiver 1210 are implemented using a direct conversion architecture.

[0050] In the transmission path, the data processor 1206 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1208. In the exemplary wireless communication device 1200, the data processor 1206 includes digital-to-analog converters (DACs) 1212(1) and 1212(2) to convert the digital signals generated by the data processor 1206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0051] Within transmitter 1208, low-pass filters 1214(1) and 1214(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1216(1) and 1216(2) amplify the signals from low-pass filters 1214(1) and 1214(2), respectively, and provide I and Q baseband signals. Upconverter 1218 upconverts the I and Q baseband signals from the transmit (TX) local oscillator (LO) signal generator 1222 via mixers 1220(1) and 1220(2) to provide upconverted signal 1224. Filter 1226 filters upconverted signal 1224 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1228 amplifies the up-converted signal 1224 from filter 1226 to obtain the desired output power level and provide a transmitted RF signal. This transmitted RF signal is routed through duplexer or switch 1230 and transmitted via antenna 1232.

[0052] In the receiving path, antenna 1232 receives signals transmitted from the base station and provides received RF signals, which are routed through duplexer or switch 1230 and provided to low noise amplifier (LNA) 1234. Duplexer or switch 1230 is designed to operate with specific receive (RX) and TX duplexer frequencies separated, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Down-conversion mixers 1238(1) and 1238(2) mix the output of filter 1236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q fundamental frequency signals are amplified by AMPs 1242(1) and 1242(2) and further filtered by low-pass filters 1244(1) and 1244(2) to obtain I and Q analog input signals, which are provided to data processor 1206. In this example, data processor 1206 includes analog-to-digital converters (ADCs) 1246(1) and 1246(2) to convert the analog input signals into digital signals to be further processed by data processor 1206.

[0053] In the wireless communication device 1200 of FIG. 12, the TX LO signal generator 1222 generates I and Q TX LO signals for up-conversion, while the RX LO signal generator 1240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1248 receives timing information from the data processor 1206 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1222. Similarly, the RX PLL circuit 1250 receives timing information from the data processor 1206 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1240.

[0054] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative elements, blocks, modules, circuits, and steps have been generally described above in their functional form. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as deviating from the scope of this work.

[0055] The various illustrative logic blocks, modules, and circuits described herein can be implemented or executed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, individual gate or transistor logic, individual hardware elements, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternatives, it may be any known processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors coordinated with a DSP core, or any other such configuration).

[0056] The various forms disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. In an alternative, the processor and storage medium can reside as separate components in a remote station, base station, or server.

[0057] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order stated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowchart. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the foregoing description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0058] The prior description of this invention is provided so that anyone skilled in the art can make or use it. Various modifications to this invention will be apparent to those skilled in the art, and the universal principles defined herein can be applied to other variations. Therefore, this invention is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0059] Implementation examples are described in the following numbered clauses: 1. An integrated circuit (IC) package comprising: a package substrate; an interposer; a first die electrically coupled to the package substrate; a second die disposed between the first die and the interposer; one or more second conductors coupled to the second die and the interposer; and one or more electrical interconnects coupled to the interposer and the package substrate, each electrical interconnect electrically coupling one of the one or more second conductors to the package substrate. 2. The IC package of clause 1, wherein: the first die includes a first active side adjacent to and electrically coupled to the package substrate and a first passive side on the opposite side of the first active side; and the second die includes a second passive side adjacent to the interposer and a second active side on the opposite side of the second passive side, the one or more second conductors being electrically coupled to the interposer. 3. The IC package of clause 2, wherein the one or more second conductors are coupled to a second active side of the second die and the interposer. 4. An IC package as described in Clause 3, wherein: the second active side of the second die includes: a first active side portion that overlaps with at least a portion of the first die in a vertical direction; and a second active side portion that does not overlap with the first die in the vertical direction; and the one or more second conductors are coupled to the second active side portion of the second active side. 5. An IC package as described in Clause 4, wherein each of the one or more second conductors includes a concave bend that extends below the second die toward the package substrate and bends upward toward the interposer. 6. An IC package as described in Clause 4, wherein each of the one or more second conductors includes a concave bend that bends upward toward the interposer. 7. An IC package as described in any of Clauses 2 to 6, wherein at least a portion of the second active side of the second die is bonded to at least a portion of the first passive side of the first die. 8. An IC package as described in any of Clauses 1 to 7, wherein the second die is coupled to the first die in a stacked arrangement. 9. The IC package of claim 2, further comprising a compression bond between at least a portion of the second active side of the second die and at least a portion of the first passive side of the first die. 10. The IC package of claim 2, further comprising an epoxy resin coupling at least a portion of the second active side of the second die to at least a portion of the first passive side of the first die. 11. The IC package of any one of claims 1 to 10, further comprising one or more interconnect bumps, each interconnect bump coupling the first die to the package substrate. 12. The IC package of any one of claims 1 to 11, further comprising one or more first conductors electrically coupled to the first die and electrically coupled to the package substrate.13. An IC package as described in any of clauses 1 to 12, wherein a first die is electrically coupled via the package substrate to at least one of the one or more electrical interconnects to electrically couple the first die to a second die. 14. An IC package as described in any of clauses 1 to 13, further comprising a third die disposed between the first die and the second die. 15. An IC package as described in clause 14, further comprising one or more third conductors electrically coupled to the third die and the package substrate. 16. An IC package as described in clause 15, wherein each of the one or more third conductors includes a convex bend that extends above the third die toward the interposer and bends downward toward the package substrate from the third die. 17. An IC package as described in clause 14, further comprising one or more third conductors electrically coupled to the third die and the interposer. 18. The IC package of Clause 17, wherein each of the one or more third conductors includes a concave bend that extends below the third die toward the package substrate and bends upward toward the interposer. 19. The IC package of Clause 17, further including one or more second electrical interconnects coupled to the interposer and the package substrate, and each second electrical interconnect being electrically coupled to one of the one or more third conductors. 20. The IC package of Clause 19, wherein the third die is electrically coupled via the interposer to at least one of the one or more electrical interconnects to electrically couple the third die to the first die. 21. An IC package of any one of clauses 14 to 20, wherein: a first die includes a first active side adjacent to and electrically coupled to the package substrate and a first passive side on the opposite side of the first active side; a second die includes a second passive side adjacent to the interposer and a second active side on the opposite side of the second passive side; and a third die includes a third active side and a third passive side on the opposite side of the third active side. 22. An IC package of clause 21, wherein one or more third conductors are coupled to the third active side of the third die and the package substrate. 23. An IC package of any one of clauses 21 to 22, wherein: the third active side of the third die includes: a first active side portion that overlaps with at least a portion of the first die in a vertical direction; and a second active side portion that does not overlap with the first die in the vertical direction; and one or more third conductors are coupled to the second active side portion of the third active side.24. An IC package as described in any of Clauses 1 to 23, which is integrated into a device selected from the group consisting of: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, automotive components, avionics systems, unmanned aerial vehicles, and multi-rotor aircraft. 25. A method of manufacturing an integrated circuit (IC) package, comprising the steps of: providing a package substrate; providing an interposer; electrically coupling a first die to the package substrate; disposing a second die between the first die and the interposer; coupling one or more second wires to the second die and the interposer; and coupling one or more electrical interconnects to the package substrate and the interposer to electrically couple one of the one or more second wires to the package substrate. 26. The method of claim 25, wherein: electrically coupling the first die to the package substrate comprises: electrically coupling a first active side of the first die adjacent to the package substrate; and coupling the one or more second wires to the second die and the interposer comprises: coupling the one or more second wires to a second active side of the second die adjacent to the interposer. 27. The method of claim 26, wherein: disposing the second die between the first die and the interposer comprises: orienting the second die toward the first die such that a first active side portion of the second die overlaps with at least a portion of the first die in a vertical direction, and a second active side portion of the second die does not overlap with the first die in the vertical direction; and coupling the one or more second wires to the second die and the interposer comprises: coupling the one or more second wires to the second active side portion of the second active side. 28. The method of any one of claims 25 to 27, further comprising the step of: bonding the second die to the first die in a stacked arrangement. 29. The method of any one of claims 25 to 28, further comprising the step of: disposing the third die between the first die and the second die. 30. The method of claim 29, further comprising the step of: coupling one or more third wires to the third die and the package substrate.31. The method of claim 30, wherein: disposing the third die between the first die and the second die comprises: orienting the third die toward the first die such that a first active side portion of the third die overlaps with at least a portion of the first die in a vertical direction, and a second active side portion of the third die does not overlap with the first die in the vertical direction; and coupling the one or more third wires to the third die and the package substrate comprises: coupling the one or more third wires to the second active side portion of the third die and the package substrate. 32. The method of claim 29, further comprising the step of: coupling the one or more third wires to the third die and the interposer. 33. The method of claim 32, wherein: disposing the third die between the first die and the second die comprises: orienting the third die toward the first die such that a first active side portion of the third die overlaps with at least a portion of the first die in a vertical direction, and a second active side portion of the third die does not overlap with the first die in the vertical direction; and coupling the one or more third wires to the third die and the interposer comprises: coupling the one or more third wires to the second active side portion of the third die and the interposer. 34. The method of any one of claims 25 to 33, wherein electrically coupling the first die to the package substrate comprises: interconnecting one or more dies coupled to the first active side of the first die to the package substrate. 35. The method of claim 34, further comprising the steps of: coupling the third die to a first passive side of the first die on the opposite side of the first active side; and electrically coupling the third die to the package substrate. 36. The method of any one of clauses 25 to 35, wherein disposing the second die between the first die and the interposer further comprises: connecting a second passive side of the second die to the interposer. [Simplified Explanation of the Diagram]

[0008] Figures 1A and 1B are side views of an exemplary integrated circuit (IC) package including two (2) stacked semiconductor dies between a package substrate and an interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically connected to the package substrate via the interposer to reduce the package height.

[0009] Figure 2A is a side view of an IC package including stacked dies, but the upper die is directly electrically coupled to the package substrate;

[0010] Figure 2B is a side view of the IC package in Figures 1A and 1B for height comparison with the IC package in Figure 2A;

[0011] Figures 3A and 3B are side views of another exemplary IC package including three (3) stacked dies between the package substrate and the interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height.

[0012] FIG4 is a flowchart illustrating an exemplary process for manufacturing an IC package including stacked dies between a package substrate and an interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height. The IC package includes, but is not limited to, the IC packages in FIG1A to FIG1B and FIG3A to FIG3B.

[0013] FIG5 is a flowchart illustrating an exemplary process for manufacturing an interposer and a top die package to be included in an IC package, the IC package including stacked dies between a package substrate and an interposer, wherein the bottom die is directly electrically coupled to the package substrate and the top die is electrically coupled to the package substrate via the interposer to reduce the package height, the IC package including but not limited to the IC packages in FIG1A to FIG1B and FIG3A to FIG3B;

[0014] Figures 6A to 6C illustrate exemplary manufacturing stages during the manufacturing of an interposer and top die package for an IC package according to the exemplary manufacturing process in Figure 5, the IC package including but not limited to the IC packages in Figures 1A to 1B and Figures 3A to 3B.

[0015] FIG7 is a flowchart illustrating an exemplary process for manufacturing a packaging substrate and a lower die package to be included in an IC package, the IC package including stacked dies between the packaging substrate and an interposer, wherein the lower die is directly electrically coupled to the packaging substrate and the upper die is electrically coupled to the packaging substrate via the interposer to reduce the package height, the IC package including but not limited to the IC packages in FIG1A to FIG1B and FIG3A to FIG3B;

[0016] Figures 8A to 8C illustrate exemplary manufacturing stages during the manufacturing of a packaging substrate and a lower die package for an IC package according to the exemplary manufacturing process in Figure 7, the IC package including but not limited to the IC packages in Figures 1A to 1B and Figures 3A to 3B.

[0017] Figures 9A and 9B are flowcharts illustrating an exemplary procedure for assembling an interposer and upper die package (including but not limited to the interposer and upper die package in Figure 6C) with a package substrate and a lower die package (including but not limited to the package substrate and lower die package in Figure 8C) to manufacture an IC package including stacked dies between a package substrate and an interposer, wherein the lower die is directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height, the IC package including but not limited to the IC packages in Figures 1A to 1B and Figures 3A to 3B;

[0018] Figures 10A to 10C illustrate exemplary manufacturing stages during the assembly of an interposer and upper die package with a package substrate and a lower die package to form an IC package according to the exemplary manufacturing process in Figures 9A and 9B, including but not limited to the IC packages in Figures 1A to 1B and Figures 3A to 3B.

[0019] FIG11 is a block diagram of an exemplary processor-based system that may include components capable of containing stacked dies in an IC package having a package substrate and an interposer, wherein the lower and middle dies are directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height. The IC package includes, but is not limited to, the IC packages of FIGS. 1A-1B, 3A-3B, 6A-6C, 8A-8C, and 10A-10C and the exemplary manufacturing processes shown in FIGS. 5, 7, and 9A-9B; and

[0020] FIG12 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components that may include an IC package having stacked dies between a package substrate and an interposer, wherein the lower die and the middle die are directly electrically coupled to the package substrate and the upper die is electrically coupled to the package substrate via the interposer to reduce the package height. The IC package includes, but is not limited to, the IC packages of FIG1A to FIG1B, FIG3A to FIG3B, FIG6A to FIG6C, FIG8A to FIG8C and FIG10A to FIG10C and according to the exemplary manufacturing process in FIG5, FIG7 and FIG9A to FIG9B. [Biomaterial Storage]

[0061] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An integrated circuit (IC) package, comprising: One packaging substrate; An interposer layer; a first die electrically coupled to the package substrate, wherein the first die includes a first active side adjacent to and electrically coupled to the package substrate and a first passive side on an opposite side of the first active side; a second die disposed between the first die and the interposer layer, and the second die being directly coupled to the first die, wherein the second die includes: a second passive side adjacent to the interposer layer and a second active side on an opposite side of the second passive side, and the second active side of the second die includes: a first active side portion that overlaps with at least a portion of the first passive side of the first die in a vertical direction and a second active side portion that does not overlap with the first die in the vertical direction; one or more second wires coupled to the second die and the interposer layer; and one or more electrical interconnects coupled to the interposer layer and the package substrate, wherein each electrical interconnect electrically couples one of the one or more second wires to the package substrate.

2. The IC package of claim 1, wherein the one or more second wires are coupled to the second active side of the second die and the interposer.

3. As in request item 1, the IC package includes: One or more second wires are coupled to the second active side portion of the second active side.

4. The IC package of claim 3, wherein each of the one or more second conductors includes a concave bend that extends from the second die below the second die toward the package substrate and bends upward toward the interlayer.

5. The IC package of claim 3, wherein each of the one or more second conductors includes a concave bend that bends upward toward the interlayer.

6. The IC package of claim 1, wherein the second die is coupled to the first die in a stacked arrangement.

7. The IC package of claim 1 further includes a compression bond between at least a portion of the second active side of the second die and at least a portion of the first passive side of the first die.

8. The IC package of claim 1 further includes an epoxy resin coupling at least a portion of the second active side of the second die to at least a portion of the first passive side of the first die.

9. The IC package of claim 1 further includes one or more interconnect bumps, each interconnect bump coupling the first die to the package substrate.

10. The IC package of claim 1 further includes one or more first wires electrically coupled to the first die and electrically coupled to the package substrate.

11. The IC package of claim 1, wherein the first die is electrically coupled to at least one of the one or more electrical interconnects via the package substrate to electrically couple the first die to the second die.

12. The IC package of claim 1 further includes a third die disposed between the first die and the second die.

13. The IC package of claim 12 further includes one or more third conductors electrically coupled to the third die and the package substrate.

14. The IC package of claim 13, wherein each of the one or more third conductors includes a convex bend that extends from the third die over the third die toward the interposer and bends downward toward the package substrate.

15. The IC package of claim 12 further includes one or more third conductors electrically coupled to the third die and the interposer.

16. The IC package of claim 15, wherein each of the one or more third conductors includes a concave bend that extends from the third die below the third die toward the package substrate and bends upward toward the interlayer.

17. The IC package of claim 15 further includes one or more second electrical interconnects coupled to the interposer and the package substrate, and each second electrical interconnect is electrically coupled to a third conductor among the one or more third conductors.

18. The IC package of claim 17, wherein the third die is electrically coupled to at least one of the one or more electrical interconnects via the interposer to electrically couple the third die to the first die.

19. As in request item 12, the IC package includes: The first die includes: a first active side adjacent to and electrically coupled to the packaging substrate and a first passive side on an opposite side of the first active side; the second die includes: a second passive side adjacent to the interposer and a second active side on an opposite side of the second passive side; and the third die includes: a third active side and a third passive side on an opposite side of the third active side.

20. The IC package of claim 19, wherein one or more third conductors are coupled to the third active side of the third die and the package substrate.

21. As in request item 19, the IC package includes: The third active side of the third grain includes: a first active side portion that overlaps with at least a portion of the first grain in a vertical direction; and a second active side portion that does not overlap with the first grain in the vertical direction; and one or more third wires coupled to the second active side portion of the third active side.

22. The IC package of claim 1, wherein the IC package is integrated into a device selected from the group consisting of: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smartphone, a SIP phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, an in-vehicle component, an avionics system, a drone, and a multi-rotor aircraft.

23. A method of manufacturing an integrated circuit (IC) package, comprising the steps of: providing a package substrate; providing an interposer; electrically coupling a first die to the package substrate, wherein the first die includes a first active side adjacent to and electrically coupled to the package substrate and a first passive side on an opposite side of the first active side; directly coupling a second die to the first die and between the first die and the interposer; coupling one or more second wires to the interposer and a second active side of the second die adjacent to the interposer, wherein the second die is oriented to the first die such that a portion of the first active side of the second die overlaps with at least a portion of the first passive side of the first die in a vertical direction, and a portion of the second active side of the second die does not overlap with the first die in the vertical direction; and coupling one or more electrical interconnects to the package substrate and the interposer to electrically couple a second wire of the one or more second wires to the package substrate.

24. As in request item 23, wherein: The step of coupling one or more second wires to the second die and the interposer includes the following steps: The one or more second wires are coupled to the second active side portion of the second active side.

25. The method of claim 23 further includes the step of bonding the second die to the first die in a stacked arrangement.

26. The method of claim 23 further includes the step of: disposing a third die between the first die and the second die.

27. The method of claim 26 further includes the step of coupling one or more third wires to the third die and the package substrate.

28. As in request item 27, wherein: The step of disposing the third die between the first die and the second die includes the following steps: orienting the third die toward the first die such that a first active side portion of the third die overlaps with at least a portion of the first die in a vertical direction, and a second active side portion of the third die does not overlap with the first die in the vertical direction; and the step of coupling one or more third wires to the third die and the packaging substrate includes the following steps: coupling one or more third wires to the second active side portion of the third die and the packaging substrate.

29. The method of claim 26 further includes the step of coupling one or more third wires to the third die and the interposer.

30. As in request item 29, wherein: The step of placing the third die between the first die and the second die includes the following steps: orienting the third die toward the first die such that a first active side portion of the third die overlaps with at least a portion of the first die in a vertical direction, and a second active side portion of the third die does not overlap with the first die in the vertical direction; and the step of coupling one or more third wires to the third die and the interposer includes the following steps: coupling one or more third wires to the second active side portion of the third die and the interposer.

31. The method of claim 23, wherein the step of electrically coupling the first die to the package substrate includes the following steps: interconnecting one or more dies coupled to a first active side of the first die to the package substrate.

32. The method of claim 31 further includes the steps of: coupling a third die to a first passive side of the first die on an opposite side of the first active side; and electrically coupling the third die to the package substrate.

33. The method of claim 23, wherein the step of disposing the second die between the first die and the interposer further includes the step of connecting a second passive side of the second die to the interposer.

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