Controller of power conversion circuit and operating method thereof

Abstract

A controller for a power conversion circuit generates multiple pulse-width modulation (PWM) signals to control multiple output stage circuits to provide output voltage and load current to the output terminal. The controller includes a sensing circuit, a comparator circuit, a PWM generation circuit, and a control loop. The sensing circuit is coupled to the output stage circuits and generates a current sensing signal related to the load current. The comparator circuit compares the current sensing signal with a preset value representing a current threshold to generate a comparison result. The control loop is coupled to the output terminal, the PWM generation circuit, and the comparator circuit, and generates a trigger signal based on a reference voltage and the output voltage to control the PWM generation circuit to generate multiple PWM signals. When the comparison result indicates that the load current exceeds the current threshold, the comparison result causes the control loop to temporarily stop providing the trigger signal to the PWM generation circuit to delay the generation of multiple PWM signals.

Description

Technical Field

[0001] The present invention relates to a power conversion circuit, and in particular to a controller of the power conversion circuit and an operating method thereof. Prior Art

[0002] Generally speaking, when the current demanded by the load exceeds a specified level, the controller of the power conversion circuit needs to limit the output current of the power stage to achieve a current clamping effect.

[0003] A conventional current clamping method is PWM skip mode, which blocks the next pulse-width modulation signal to reduce output current when the output current exceeds a preset level. Implementing PWM skip mode directly in a multi-phase power conversion circuit system to limit total current can make current balancing difficult to control. Specifically, if the total current exceeds a preset level, the next pulse-width modulation signal is blocked to stop the corresponding phase current output. This can cause the pulse-width modulation signal of a particular phase to be frequently blocked, resulting in uneven output current across phases. If a single phase is frequently limited, causing its output current to be zero, the current balancing mechanism may even fail to function.

[0004] Another conventional method is phase shielding, which limits the total current by disabling certain phases when the total current exceeds a preset level. However, this method has the disadvantage of causing output instability when the shielded phases are reactivated, and this technology needs improvement. Summary of the Invention

[0005] In view of this, the present invention proposes a controller of a power conversion circuit and an operating method thereof to effectively solve the problems encountered in the prior art.

[0006] According to one embodiment of the present invention, a controller for a power conversion circuit is provided. In this embodiment, the controller is coupled to multiple output stage circuits and generates multiple pulse-width modulation signals to control the multiple output stage circuits, respectively, so that the power conversion circuit provides an output voltage and a load current to an output terminal. The controller includes a sensing circuit, a first comparison circuit, a pulse-width modulation generation circuit, and a control loop. The sensing circuit is coupled to the multiple output stage circuits and generates a current sensing signal related to the load current. The first comparison circuit is coupled to the sensing circuit and compares the current sensing signal with a preset value to generate a first comparison result. The preset value represents a current threshold. The pulse-width modulation generation circuit is coupled to the multiple output stage circuits. The control loop is coupled between the output terminal and the pulse-width modulation generation circuit and is also coupled to the first comparison circuit. The control loop generates a trigger signal based on a reference voltage and the output voltage to control the pulse-width modulation generation circuit to generate multiple pulse-width modulation signals. When the first comparison result indicates that the load current exceeds the current threshold, the first comparison result causes the control loop to temporarily stop providing the trigger signal to the pulse-width modulation generation circuit, thereby delaying the generation of the multiple pulse-width modulation signals.

[0007] In one embodiment, a control loop includes a ramp signal generating circuit, an error amplifier, a compensation circuit, and a second comparison circuit. The ramp signal generating circuit generates a ramp signal and also receives a trigger signal for resetting the ramp signal. The error amplifier is coupled to an output terminal and receives a reference voltage and a feedback voltage related to the output voltage to generate an error signal. The compensation circuit is coupled to the error amplifier and the second comparison circuit to provide a compensation signal. The second comparison circuit is coupled to the ramp signal generating circuit, the compensation circuit, and the pulse width modulation generating circuit, respectively, and compares the ramp signal with the compensation signal to generate a second comparison result for generating a trigger signal.

[0008] In one embodiment, the ramp signal generating circuit is further coupled to a first comparison circuit. When the current sensing signal is higher than a preset value, a first comparison result indicates that the load current exceeds a current threshold. The first comparison result causes the waveform slope of the ramp signal to be zero.

[0009] In one embodiment, the control loop further includes a logic gate, which is coupled to the first comparison circuit and the second comparison circuit respectively, and generates a trigger signal according to the first comparison result and the second comparison result, and is used to delay the resetting of the ramp signal.

[0010] In one embodiment, the control loop includes a second comparison circuit and a logic gate. The second comparison circuit is coupled to the output terminal and receives and compares a reference voltage with a feedback voltage related to the output voltage to generate a second comparison result. The logic gate is coupled to the first comparison circuit and the second comparison circuit, respectively, and generates a trigger signal based on the first and second comparison results.

[0011] Another embodiment of the present invention is a method for operating a controller for a power conversion circuit. In this embodiment, the controller is coupled to multiple output stage circuits and generates multiple pulse width modulation signals to control the multiple output stage circuits, respectively, so that the power conversion circuit provides an output voltage and a load current to an output terminal. The method includes the following steps: (a) generating a current sensing signal related to the load current; (b) comparing the current sensing signal with a preset value to generate a first comparison result, wherein the preset value represents a current threshold; (c) determining whether the first comparison result indicates that the load current exceeds the current threshold; (d) if the determination result of step (c) is negative, providing a trigger signal based on a reference voltage and the output voltage to generate multiple pulse width modulation signals; and (e) if the determination result of step (c) is positive, temporarily stopping providing the trigger signal to delay the generation of the multiple pulse width modulation signals.

[0012] In one embodiment, step (d) of the operating method further includes: generating a ramp signal and resetting the ramp signal according to the trigger signal; generating an error signal according to a reference voltage and a feedback voltage related to the output voltage; generating a compensation signal according to the error signal; and comparing the ramp signal and the compensation signal to generate a second comparison result for generating the trigger signal.

[0013] In one embodiment, step (e) of the operating method further includes: when the current sensing signal is higher than a preset value, a first comparison result indicates that the load current exceeds a current threshold, and the first comparison result causes the waveform slope of the ramp signal to be zero.

[0014] In one embodiment, step (e) of the operation method further includes: generating a trigger signal according to the first comparison result and the second comparison result, and using the trigger signal to delay the resetting of the ramp signal.

[0015] In one embodiment, step (d) of the operating method further includes: comparing a reference voltage and a feedback voltage related to the output voltage to generate a second comparison result; and generating a trigger signal according to the first comparison result and the second comparison result.

[0016] Compared to prior art, the controller and operating method of the power conversion circuit of the present invention clamps the load current (total output current) without changing the number of operating phases (full-phase, full-time operation) and ensuring balanced output currents on each phase. This ensures that the total output current does not exceed a preset level and that the output currents on each phase are balanced. This achieves the simultaneous effects of clamping the total output current and balancing the output currents on each phase.

[0017] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. Simple diagram description

[0018] The accompanying drawings of the present invention are described as follows: FIG1 is a schematic diagram of a controller of a power conversion circuit according to an embodiment of the present invention. FIG. 2 is a waveform timing diagram of each signal in FIG. 1 . FIG. 3A illustrates an embodiment of the ramp signal generating circuit in FIG. 1 . FIG. 3B is a waveform timing diagram of each signal in FIG. 3A . FIG. 4A shows another embodiment of the ramp signal generating circuit in FIG. 1 . FIG. 4B is a waveform timing diagram of each signal in FIG. 4A . FIG. 5 is a schematic diagram illustrating a controller of a power conversion circuit according to another embodiment of the present invention. FIG. 6 is a waveform timing diagram of each signal in FIG. 5 . FIG. 7 is a schematic diagram illustrating a controller of a power conversion circuit according to yet another embodiment of the present invention. FIG. 8 is a timing diagram showing waveforms of the signals in FIG. 7 . FIG9 shows a waveform timing diagram of an unbalanced state between the output currents of each phase when the prior art utilizes the skip mode to clamp the total output current of a multi-phase system. FIG. 10 is a waveform timing diagram showing the state in which the output currents of each phase are in a balanced state when the present invention performs total output current clamping. FIG. 11 is a flow chart illustrating an operation method of a controller of a power conversion circuit according to another embodiment of the present invention. Implementation Method

[0019] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements / components using the same or similar reference numerals in the drawings and embodiments are intended to represent the same or similar parts.

[0020] According to one embodiment of the present invention, a controller for a power conversion circuit is provided. In this embodiment, the power conversion circuit is a multi-phase constant on-time (COT) power conversion circuit, but the present invention is not limited thereto.

[0021] Please refer to FIG. 1 , which illustrates a schematic diagram of a controller 10 of a power conversion circuit 1 according to this embodiment. As shown in FIG. 1 , in the power conversion circuit 1 , the controller 10 is coupled to N output stage circuits OS1 through OSN and generates N pulse-width modulation signals PWM1 through PWMN to control the N output stage circuits OS1 through OSN, respectively, so that the power conversion circuit 1 provides an output voltage VOUT and a load current IL to an output terminal OUT. N is a positive integer greater than 1.

[0022] Each of the output stage circuits OS1-OSN includes drivers D1-D2, switches M1-M2, and an output inductor L. Driver D1 is coupled between the controller 10 and the control terminal of switch M1. Driver D2 is coupled between the controller 10 and the control terminal of switch M2. Switches M1 and M2 are connected in series between the input voltage VIN and the ground terminal GND. One end of the output inductor L is coupled between switches M1 and M2, and the other end of the output inductor L is coupled to the output terminal OUT. An output capacitor COUT and an output resistor ROUT are connected in series between the output terminal OUT and the ground terminal GND. A load RLD is coupled between the output terminal OUT and the ground terminal GND.

[0023] The controller 10 includes a sensing circuit 100, a preset value generation circuit 101, a first comparison circuit 102, a control loop 104, a sequence control circuit 105, and N pulse width modulation generation circuits 1061-106N. The sensing circuit 100 includes N phase current sensing circuits K1-KN and a summing circuit 1001. The N phase current sensing circuits K1-KN are respectively coupled to N output stage circuits OS1-OSN to sense N phase currents I1-IN of the N output stage circuits OS1-OSN, generating N sensing signals. The summing circuit 1001 then sums these N sensing signals to generate a current sensing signal IS related to the load current IL. The preset value generation circuit 101 generates a preset value DV, which serves as a current threshold for limiting the load current IL. The positive input terminal + of the first comparison circuit 102 is coupled to the preset value generation circuit 101 to receive the preset value DV. The negative input terminal - of the first comparison circuit 102 is coupled to the sensing circuit 100 to receive the current sensing signal IS. The first comparison circuit 102 compares the current sensing signal IS with a preset value DV to generate a first comparison result OCLB.

[0024] The control loop 104 is respectively coupled to the output terminal of the first comparison circuit 102, the output terminal OUT and the sequence control circuit 105 for respectively receiving the output voltage VOUT, the reference voltage VREF and the first comparison result OCLB to generate a trigger signal DTR to the sequence control circuit 105.

[0025] The sequence control circuit 105 is coupled between the control loop 104 and the N pulse width modulation generation circuits 1061-106N, and is configured to sequentially generate N control signals TR1-TRN to the corresponding N pulse width modulation generation circuits 1061-106N based on the trigger signal DTR, thereby controlling the N pulse width modulation generation circuits 1061-106N to respectively generate N pulse width modulation signals PWM1-PWMN to the N output stage circuits OS1-OSN, thereby respectively controlling the operation of the N output stage circuits OS1-OSN.

[0026] In this embodiment, the control loop 104 includes an error amplifier 1040, a compensation circuit 1042, a second comparison circuit 1044, and a ramp signal generation circuit 1046. The error amplifier 1040 is coupled between the output terminal OUT and the compensation circuit 1042 to receive a reference voltage VREF and an output voltage VOUT (or a feedback voltage related to the output voltage VOUT) to generate an error signal ERR. The compensation circuit 1042 is coupled between the error amplifier 1040 and the negative input terminal - of the second comparison circuit 1044 to convert the error signal ERR into a compensation signal COMP, which is input to the negative input terminal - of the second comparison circuit 1044.

[0027] The ramp signal generating circuit 1046 is coupled to the output terminal of the first comparison circuit 102 and the positive input terminal + and output terminal of the second comparison circuit 1044. The ramp signal generating circuit 1046 receives the first comparison result OCLB from the first comparison circuit 102 to generate a ramp signal RAMP to the positive input terminal + of the second comparison circuit 1044. The ramp signal generating circuit 1046 also receives a trigger signal DTR from the output terminal of the second comparison circuit 1044 to reset the ramp signal RAMP. The positive input terminal + of the second comparison circuit 1044 is coupled to the ramp signal generating circuit 1046, and the negative input terminal - of the second comparison circuit 1044 is coupled to the compensation circuit 1042. The output terminal of the second comparison circuit 1044 is coupled to the ramp signal generating circuit 1046 and the sequence control circuit 105, respectively. The second comparison circuit 1044 compares the ramp signal RAMP with the compensation signal COMP to generate a second comparison result as the trigger signal DTR, which is output to the sequence control circuit 105.

[0028] It should be noted that when the current sensing signal IS is below the preset value DV, the first comparison result OCLB generated by the first comparison circuit 102 indicates that the load current has not exceeded the current threshold. The control circuit 104 normally provides the trigger signal DTR to the sequence control circuit 105, causing the PWM generation circuit 106 to normally sequentially generate the N PWM signals PWM1-PWMN to the N output stage circuits OS1-OSN. When the current sensing signal IS is above the preset value DV, the first comparison result OCLB generated by the first comparison circuit 102 indicates that the load current has exceeded the current threshold. The first comparison result OCLB causes the control circuit 104 to temporarily stop providing the trigger signal DTR to the sequence control circuit 105, thereby delaying the time when the PWM generation circuit 106 generates the next PWM signal.

[0029] Specifically, in this embodiment, when the current sensing signal IS is greater than the preset value DV, the counter in the ramp signal generating circuit 1046 stops counting, and the current source stops charging the capacitor, thereby stopping the accumulation of the ramp signal RAMP. This causes the slope of the ramp signal RAMP to be zero, and the waveform stops rising, thereby delaying the time it takes for the ramp signal RAMP to intersect with the compensation signal COMP.

[0030] Please refer to Figure 2. Figure 2 illustrates the waveform timing diagram of each signal in Figure 1. Taking N=4 as an example, the PWM generation circuit 106 generates PWM signals PWM4, PWM3, PWM2, and PWM1 in sequence according to the control signals TR1-TR4 to the output stage circuits OS4, OS3, OS2, and OS1, respectively.

[0031] Before time t1, the current sensing signal IS is less than the predetermined value DV. The PWM generation circuit 106 generates a PWM signal for each phase based on the intersection of the ramp signal RAMP and the compensation signal COMP. For example, at time t0, the ramp signal RAMP and the compensation signal COMP intersect, causing the control loop 104 to generate a trigger signal DTR. The sequence control circuit 105 generates a control signal TR1 based on the trigger signal DTR, controlling the PWM generation circuit 106 to generate the PWM signal PWM1. Simultaneously, the ramp signal generation circuit 1046 resets the waveform of the ramp signal RAMP based on the trigger signal DTR.

[0032] At time t1, the current sensing signal IS begins to exceed the preset value DV, and the first comparison result OCLB output by the first comparison circuit 102 changes from the original high level (High) to the low level (Low), so that the slope of the ramp signal RAMP generated by the ramp signal generating circuit 1046 becomes zero, and the waveform remains at the current level.

[0033] Between time t1 and time t2, the waveform of the ramp signal RAMP stops changing. Therefore, the ramp signal RAMP and the compensation signal COMP do not cross over (i.e., the trigger signal DTR is not generated). Consequently, the PWM generation circuit 106 does not generate the next PWM signal (PWM4) during this period. During this period, the already generated PWM signal PWM1 continues until its on-time period ends according to the original generation mechanism, and the next period begins while the trigger signal DTR is generated.

[0034] At time t2, the current sensing signal IS is less than the preset value DV, and the first comparison result OCLB output by the first comparison circuit 102 changes from low level (Low) to high level (High), causing the waveform of the ramp signal RAMP generated by the ramp signal generating circuit 1046 to continue to rise.

[0035] At time t3, the ramp signal RAMP intersects the compensation signal COMP, causing the control loop 104 to generate a trigger signal DTR. The sequence control circuit 105 generates a control signal TR1 based on the trigger signal DTR to control the pulse width modulation generation circuit 106 to generate the pulse width modulation signal PWM4 of the next phase. At the same time, the ramp signal generation circuit 1046 resets the waveform of the ramp signal RAMP based on the trigger signal DTR.

[0036] Please refer to Figure 3A. Figure 3A illustrates an embodiment of the ramp signal generating circuit in Figure 1. As shown in Figure 3A, the ramp signal generating circuit 1046, which is a rising type, includes a logic gate 10460, a current source 10462, switches SW1 and SW2, and a capacitor C. The current source 10462, switch SW1, and capacitor C are connected in series between the operating voltage VDD and the ground terminal GND. The logic gate 10460 receives the first comparison result OCLB output by the first comparison circuit 102 and the trigger signal DTR output by the control circuit 104, respectively, and controls whether switch SW1 is conductive based on the first comparison result OCLB and the trigger signal DTR. Switch SW2 is coupled to both ends of capacitor C, and the conductive state of switch SW2 is controlled by the trigger signal DTR. The positive input terminal + of the second comparison circuit 1044 is coupled between switch SW1 and capacitor C to receive the ramp signal RAMP. The second comparison circuit 1044 compares the ramp signal RAMP with the compensation signal COMP and outputs a second comparison result as the trigger signal DTR.

[0037] Please refer to Figure 3B. Figure 3B illustrates the waveform timing diagram of the various signals in Figure 3A. As shown in Figure 3B, at time t1, the current sensing signal IS begins to exceed the preset value DV, and the first comparison result OCLB changes from a high level (High) to a low level (Low). This causes the logic gate 10460 to control the switch SW1 to be non-conductive, thereby disconnecting the charging path of the current source 10462 to the capacitor C. This causes the waveform of the ramp signal RAMP to stop rising and remain at its current level. Between time t1 and time t2, the waveform of the ramp signal RAMP stops changing. At time t2, the current sensing signal IS falls below the preset value DV, and the first comparison result OCLB changes from a low level (Low) to a high level (High), causing the waveform of the ramp signal RAMP to continue rising. At time t3, when the ramp signal RAMP intersects the compensation signal COMP, the second comparison circuit 1044 generates a trigger signal DTR, and the switch SW2 is simultaneously controlled by the trigger signal DTR to turn on, resetting the waveform of the ramp signal RAMP.

[0038] Please refer to Figure 4A. Figure 4A illustrates another embodiment of the ramp signal generating circuit in Figure 1. As shown in Figure 4A, the ramp signal generating circuit 1046, which is a falling type, includes a logic gate 10460, a current source 10462, switches SW1 and SW2, and a capacitor C. Switch SW1 and capacitor C are connected in series between the operating voltage VDD and the ground terminal GND. The conduction of switch SW1 is controlled by a trigger signal DTR. Switch SW2 and the current source 10462 are connected in series across capacitor C. Logic gate 10460 receives the first comparison result OCLB output by the first comparison circuit 102 and the trigger signal DTR output by the control loop 104, respectively, and controls the conduction of switch SW2 based on the first comparison result OCLB and the trigger signal DTR. The negative input terminal - of the second comparison circuit 1044 is coupled between switch SW1 and capacitor C to receive the ramp signal RAMP. The second comparison circuit 1044 compares the ramp signal RAMP with the compensation signal COMP and outputs a second comparison result as the trigger signal DTR.

[0039] Please refer to Figure 4B. Figure 4B illustrates a waveform timing diagram of the various signals in Figure 4A. As shown in Figure 4B, at time t1, the current sensing signal IS begins to exceed the preset value DV, and the first comparison result OCLB changes from a high level (High) to a low level (Low). This causes the logic gate 10460 to control the switch SW2 to be non-conductive, thus disconnecting the discharge path. This causes the waveform of the ramp signal RAMP to stop decreasing and remain at its current level. Between time t1 and time t2, the waveform of the ramp signal RAMP stops changing. At time t2, the current sensing signal IS falls below the preset value DV, and the first comparison result OCLB changes from a low level (Low) to a high level (High), causing the waveform of the ramp signal RAMP to continue decreasing. At time t3, when the ramp signal RAMP intersects the compensation signal COMP, the second comparison circuit 1044 generates a trigger signal DTR, and the switch SW1 is simultaneously controlled by the trigger signal DTR to turn on, resetting the waveform of the ramp signal RAMP.

[0040] Please refer to Figure 5. Figure 5 illustrates a schematic diagram of a controller for a power conversion circuit according to another embodiment of the present invention. As shown in Figure 5, the controller 30 of the power conversion circuit 3 includes a sensing circuit 300, a preset value generation circuit 301, a first comparison circuit 302, a control loop 304, a sequence control circuit 305, and N pulse width modulation generation circuits 3061-306N.

[0041] It should be noted that the operations of the sensing circuit 300, the preset value generating circuit 301, the first comparison circuit 302, the sequence control circuit 305, and the N pulse width modulation generating circuits 3061-306N in FIG5 are the same as the operations of the sensing circuit 100, the preset value generating circuit 101, the first comparison circuit 102, the sequence control circuit 105, and the N pulse width modulation generating circuits 1061-106N in FIG1 , and therefore are not further described herein.

[0042] Next, the control loop 304 in FIG5 will be described in detail.

[0043] The control loop 304 includes a second comparison circuit 3040 and a logic gate 3042. A positive input terminal + of the second comparison circuit 3040 receives a reference voltage VREF, and a negative input terminal - of the second comparison circuit 3040 is coupled to the output terminal OUT and receives the output voltage VOUT (or a feedback voltage related to the output voltage VOUT). The second comparison circuit 3040 compares the output voltage VOUT with the reference voltage VREF and generates a second comparison result CMP. The logic gate 3042 is coupled to the output terminals of the first comparison circuit 302 and the second comparison circuit 3040, respectively, to receive the first comparison result OCLB and the second comparison result CMP, and generates a trigger signal DTR to the sequence control circuit 305 based on the first comparison result OCLB and the second comparison result CMP.

[0044] When the current sensing signal IS is greater than the preset value DV, the first comparison result OCLB changes from a high level (High) to a low level (Low), causing the logic gate 3042 to suspend generating the trigger signal DTR to the sequence control circuit 305, thereby controlling the PWM generation circuit 306 to suspend generating the next PWM signal. Therefore, the next PWM signal will not be generated when the second comparison result CMP is at a high level (High).

[0045] Please refer to Figure 6. Figure 6 illustrates the waveform timing diagram of each signal in Figure 5. Taking N=4 as an example, the PWM generation circuit 306 generates PWM signals PWM4, PWM3, PWM2, and PWM1 in sequence according to the control signals TR1-TR4 to the output stage circuits OS4, OS3, OS2, and OS1.

[0046] At time t1, the current sensing signal IS is less than the preset value DV, and the first comparison result OCLB generated by the first comparison circuit 302 is a high level (High). At this time, the output voltage VOUT is less than the reference voltage VREF, and the second comparison result CMP generated by the second comparison circuit 3040 is a high level (High). Therefore, the logic gate 3042 is allowed to generate a trigger signal DTR to the sequence control circuit 305, thereby controlling the pulse width modulation generation circuit 306 to generate the pulse width modulation signal PWM2.

[0047] Between time t2 and t3, the current sensing signal IS is greater than the preset value DV, and the first comparison result OCLB generated by the first comparison circuit 302 is a low level (Low). At this time, the output voltage VOUT is greater than the reference voltage VREF, and the second comparison result CMP generated by the second comparison circuit 3040 is a low level (Low). At this time, the logic gate 3042 does not generate the trigger signal DTR to the sequence control circuit 305.

[0048] The period from time t3 to time t5 is the same as that from time t1 to time t3, so it will not be repeated.

[0049] At time t5, the current sensing signal IS is greater than the preset value DV, and the first comparison result OCLB generated by the first comparison circuit 302 is a low level (Low). At this time, the output voltage VOUT is less than the reference voltage VREF, and the second comparison result CMP generated by the second comparison circuit 3040 is a high level (High). Because the low level (Low) first comparison result OCLB obscures the high level (High) second comparison result CMP, the logic gate 3042 temporarily stops generating the trigger signal DTR to the sequence control circuit 305, thereby controlling the pulse width modulation generation circuit 306 to temporarily stop generating the next pulse width modulation signal.

[0050] At time t6, the current sensing signal IS is less than the preset value DV, and the first comparison result OCLB generated by the first comparison circuit 302 is a high level (High). At this time, the output voltage VOUT is less than the reference voltage VREF, and the second comparison result CMP generated by the second comparison circuit 3040 is a high level (High). Therefore, the logic gate 3042 is allowed to generate a trigger signal DTR to the sequence control circuit 305, thereby controlling the pulse width modulation generation circuit 306 to generate the pulse width modulation signal PWM4.

[0051] After time t7, since the output voltage VOUT is less than the reference voltage VREF, the second comparison result CMP generated by the second comparison circuit 3040 is a high level (High). Therefore, when the first comparison result OCLB generated by the first comparison circuit 302 is a high level (High), the logic gate 3042 generates a trigger signal DTR to the sequence control circuit 305 to control the PWM generation circuit 306 to sequentially generate a plurality of PWM signals.

[0052] Please refer to Figure 7. Figure 7 illustrates a schematic diagram of a controller for a power conversion circuit according to another embodiment of the present invention. As shown in Figure 7, the controller 50 of the power conversion circuit 5 includes a sensing circuit 500, a preset value generation circuit 501, a first comparison circuit 502, a control loop 504, a sequence control circuit 505, and N pulse width modulation generation circuits 5061-506N.

[0053] It should be noted that the operations of the sensing circuit 500, the preset value generating circuit 501, the first comparison circuit 502, the sequence control circuit 505, and the PWM generating circuits 5061-506N in FIG7 are the same as the operations of the sensing circuit 100, the preset value generating circuit 101, the first comparison circuit 102, the sequence control circuit 105, and the PWM generating circuits 1061-106N in FIG1 , and therefore are not further described herein.

[0054] Next, the control loop 504 in FIG. 7 will be described in detail.

[0055] The control loop 504 includes an error amplifier 5040, a compensation circuit 5042, a second comparison circuit 5044, a ramp signal generating circuit 5046, and a logic gate 5048. The error amplifier 5040 is coupled between the output terminal OUT and the compensation circuit 5042 to receive a reference voltage VREF and an output voltage VOUT (or a feedback voltage related to the output voltage VOUT) to generate an error signal ERR. The compensation circuit 5042 is coupled between the error amplifier 5040 and the negative input terminal - of the second comparison circuit 5044 to convert the error signal ERR into a compensation signal COMP and input the compensation signal COMP to the negative input terminal - of the second comparison circuit 5044.

[0056] The ramp signal generating circuit 5046 is coupled to the positive input terminal + of the second comparison circuit 5044 and the output terminal of the logic gate 5048 respectively, and is used to generate a ramp signal RAMP to the positive input terminal + of the second comparison circuit 5044 and receive a trigger signal DTR from the output terminal of the logic gate 5048 to reset the ramp signal RAMP.

[0057] The positive input terminal + of the second comparison circuit 5044 is coupled to the ramp signal generating circuit 5046, and the negative input terminal - of the second comparison circuit 5044 is coupled to the compensation circuit 5042. The output terminal of the second comparison circuit 5044 is coupled to the input terminal of the logic gate 5048. The second comparison circuit 5044 compares the ramp signal RAMP with the compensation signal COMP to generate a second comparison result CMP to the logic gate 5048. The logic gate 5048 is coupled to the output terminal of the first comparison circuit 502, the output terminal of the second comparison circuit 5044, and the sequence control circuit 505, respectively, to receive the first comparison result OCLB generated by the first comparison circuit 502 and the second comparison result CMP generated by the second comparison circuit 5044, and generate a trigger signal DTR accordingly, which is output to the sequence control circuit 505.

[0058] It should be noted that when the first comparison result OCLB generated by the first comparison circuit 502 indicates that the current sensing signal IS is not greater than the preset value DV, the control circuit 504 normally provides the trigger signal DTR to the sequence control circuit 505, causing the PWM generation circuit 506 to normally sequentially generate the N PWM signals PWM1-PWMN to the N output stage circuits OS1-OSN. When the first comparison result OCLB generated by the first comparison circuit 502 indicates that the current sensing signal IS is greater than the preset value DV, the first comparison result OCLB causes the control circuit 504 to temporarily stop providing the trigger signal DTR to the sequence control circuit 505, thereby delaying the time when the PWM generation circuit 506 generates the next PWM signal.

[0059] Please refer to Figure 8. Figure 8 illustrates the waveform timing diagram of the various signals in Figure 7. Figure 8 differs from Figure 2 in that, at time t0, when the ramp signal RAMP intersects the compensation signal COMP, the control loop 104 immediately issues a trigger signal DTR to activate the PWM generation circuit 106 to generate the next PWM signal. In Figure 8, at time t1, when the ramp signal RAMP intersects the compensation signal COMP, the control loop 504 does not immediately issue a trigger signal DTR. Instead, it waits until time t2, when the current sensing signal IS falls below the preset value DV, at which point the control loop 504 is allowed to issue a trigger signal DTR to activate the PWM generation circuit 506 to generate the next PWM signal.

[0060] Please refer to Figures 9 and 10 simultaneously. In Figure 9, the prior art uses a skip mode to clamp the total current. When the total current exceeds a preset level, a blanking signal is issued to block the next PWM signal. This results in the PWM signal of a specific phase being blanked more often, resulting in a significant imbalance between the output currents I1-I4 of each phase. In Figure 10, the present invention clamps the total output current (i.e., the current sensing signal IS) without changing the number of operating phases (full-phase, full-time operation) and averaging the output currents I1-I4 of each phase. This ensures that the total output current IS does not exceed the preset level and the output currents I1-I4 of each phase are balanced. Therefore, a comparison of Figures 9 and 10 shows that the present invention delays the entire PWM signal, achieving a current limiting effect without affecting the output current of each phase. This effectively solves the problem of imbalance in the output currents of each phase that often occurs when clamping the total output current in the prior art, achieving the simultaneous effect of clamping the total output current and balancing the output currents of each phase.

[0061] Another embodiment of the present invention provides an operating method for a controller of a power conversion circuit. In this embodiment, the power conversion circuit is a multi-phase constant on-time power conversion circuit. The controller is coupled to a plurality of output stage circuits and generates a plurality of pulse-width modulation signals to control the plurality of output stage circuits, respectively, so that the power conversion circuit provides an output voltage and a load current to an output terminal.

[0062] Please refer to FIG11, which is a flow chart illustrating the operation method of the controller of the power conversion circuit in this embodiment. As shown in FIG11, the operation method of the controller of the power conversion circuit includes the following steps:

[0063] Step S10: generating a current sensing signal associated with the load current;

[0064] Step S12: comparing the current sensing signal with a preset value to generate a first comparison result;

[0065] Step S14: determining whether the first comparison result indicates that the current sensing signal is higher than a preset value;

[0066] Step S16: If the determination result of step S14 is yes, temporarily stop providing the trigger signal to delay the generation of the PWM signal; and

[0067] Step S18: If the determination result of step S14 is no, providing a trigger signal according to the reference voltage and the output voltage to sequentially generate a plurality of pulse width modulation signals.

[0068] In practical applications, the operation method can generate a ramp signal according to the first comparison result and an error signal according to the reference voltage and the feedback voltage related to the output voltage, and then compare the ramp signal and the error signal to generate a second comparison result, but is not limited thereto.

[0069] In one embodiment, the operating method generates a trigger signal based on a first comparison result. For example, a second comparison result may be generated based on the first comparison result and directly provided as the trigger signal. Alternatively, the first and second comparison results may be logically combined to generate a trigger signal. Subsequently, the operating method resets the ramp signal based on the trigger signal that was delayed due to the temporary pause, but is not limited thereto.

[0070] In another embodiment, because the power conversion circuit is a multi-phase constant on-time power conversion circuit, the operating method further includes: separately sensing multiple output currents of multiple output stage circuits to obtain multiple phase sensing signals; and summing the multiple phase sensing signals to obtain a current sensing signal, but is not limited to this.

[0071] Compared to prior art, the controller and operating method of the power conversion circuit of the present invention do not employ conventional blanking or skipping methods. Instead, they temporarily stop generating trigger signals to delay the entire pulse-width modulation signal. This allows the total output current to be clamped without affecting the number of operating phases and ensuring balanced output currents across phases. Consequently, the total output current can be clamped without affecting the output voltage and maintaining balanced output currents across phases.

[0072] 1, 3, 5: Power conversion circuit 10, 30, 50: Controller 100, 300, 500: Sensing circuit 1001, 3001, 5001: Summing circuit 101, 301, 501: Preset value generation circuit 102, 302, 502: first comparison circuit 104, 304, 504: Control loop 1040, 5040: Error amplifier 1042, 5042: compensation circuit 1044, 3040, 5044: second comparison circuit 1046, 5046: Ramp signal generating circuit 3042, 5048: Logic Gate 105, 305, 505: Sequence control circuit 1061~106N, 3061~306N, 5061~506N: Pulse Width Modulation (PWM) Generation Circuit K1~KN: Phase current sensing circuit I1~IN: Phase sensing current DV: Default value IS: Current sensing signal +: positive input terminal -: Negative input terminal OCLB: First comparison results CMP: Second comparison result ERR: Error signal COMP: compensation signal RAMP: Ramp signal DTR: trigger signal TR1~TRN: control signal PWM1~PWMN: Pulse Width Modulation (PWM) signal OS1~OSN: output stage circuit D1~D2: Driver M1~M2: switch L: output inductor OUT: output terminal VIN: input voltage VOUT: output voltage COUT: output capacitance ROUT: output resistance RLD: load resistance GND: Ground terminal t0~t7: time 10460:Logic Gate 10462: Current Source SW1~SW2: switches C: Capacitor S10~S18: Steps

Claims

1. A controller for a power conversion circuit, coupled to multiple output stage circuits and generating multiple pulse width modulation signals to control the output stage circuits respectively, so that the power conversion circuit provides an output voltage and a load current to an output terminal, the controller comprising: A sensing circuit is coupled to the output stage circuits and generates a current sensing signal related to the load current. A first comparison circuit, coupled to the sensing circuit, compares the current sensing signal with a preset value to generate a first comparison result, wherein the preset value represents a current threshold; a pulse width modulation generation circuit, coupled to the output stage circuits. A control loop is coupled between the output terminal and the pulse width modulation generation circuit, and is also coupled to the first comparison circuit. The control loop generates a trigger signal based on a reference voltage and the output voltage to control the pulse width modulation generation circuit to generate the pulse width modulation signals. When the first comparison result indicates that the load current exceeds the current threshold, the first comparison result causes the control loop to temporarily stop providing the trigger signal to the pulse width modulation generation circuit to delay the generation of the pulse width modulation signals.

2. The controller as claimed in claim 1, wherein the control loop comprises: A ramp signal generating circuit generates a ramp signal and also receives a trigger signal to reset the ramp signal; An error amplifier, coupled to the output terminal, receives the reference voltage and a feedback voltage related to the output voltage to generate an error signal; a compensation circuit, coupled to the error amplifier, receives the error signal to generate a compensation signal. A second comparison circuit is also included, which is coupled to the ramp signal generation circuit, the compensation circuit, and the pulse width modulation generation circuit, respectively. The ramp signal is compared with the compensation signal to generate a second comparison result, which is used to generate the trigger signal.

3. The controller as claimed in claim 2, wherein the ramp signal generating circuit is further coupled to the first comparison circuit, wherein when the current sensing signal is higher than the preset value, the first comparison result indicates that the load current exceeds the current threshold, and the first comparison result makes the slope of the ramp signal waveform zero.

4. The controller as claimed in claim 2, wherein the control loop further comprises: A logic gate is coupled to the first comparison circuit and the second comparison circuit respectively, and generates the trigger signal based on the first comparison result and the second comparison result, and is used to delay the reset of the ramp signal.

5. The controller as claimed in claim 1, wherein the control loop comprises: A second comparator circuit, coupled to the output terminal, receives and compares the reference voltage and a feedback voltage related to the output voltage to generate a second comparison result; and a logic gate, coupled to the first comparator circuit and the second comparator circuit respectively, generates the trigger signal based on the first comparison result and the second comparison result.

6. A method of operating a controller for a power conversion circuit, the controller being coupled to a plurality of output stage circuits and generating a plurality of pulse width modulation (PWM) signals to control the output stage circuits respectively, so that the power conversion circuit provides an output voltage and a load current to an output terminal, the method comprising the following steps: (a) generating a current sensing signal related to the load current; (b) comparing the current sensing signal with a preset value to generate a first comparison result, the preset value representing a current threshold; (c) determining whether the first comparison result indicates that the load current exceeds the current threshold; (d) if the determination result of step (c) is negative, providing a trigger signal based on a reference voltage and the output voltage to generate the PWM signals; and (e) if the determination result of step (c) is positive, temporarily stopping the provision of the trigger signal to delay the generation of the PWM signals.

7. The method of operation as described in claim 6, wherein step (d) further comprises: A ramp signal is generated, and the ramp signal is reset according to the trigger signal; An error signal is generated based on the reference voltage and a feedback voltage related to the output voltage; a compensation signal is generated based on the error signal; and a second comparison result is generated by comparing the ramp signal and the compensation signal to generate the trigger signal.

8. The method of operation as described in claim 7, wherein step (e) further comprises: When the current sensing signal is higher than the preset value, the first comparison result indicates that the load current exceeds the current threshold, and the first comparison result makes the slope of the ramp signal waveform zero.

9. The method of operation as described in claim 7, wherein step (e) further includes generating the trigger signal based on the first comparison result and the second comparison result, and using it to delay the reset of the ramp signal.

10. The method of operation as described in claim 6, wherein step (d) further comprises: The reference voltage is compared with a feedback voltage associated with the output voltage to produce a second comparison result; And generate the trigger signal based on the first comparison result and the second comparison result.

Images