Semiconductor device

Abstract

The present invention provides a semiconductor device comprising: a first fin pattern located in a first region of a substrate and spaced apart from each other in a first direction; a second fin pattern located in a second region of the substrate and spaced apart from each other in a second direction; a first field insulating film located on the substrate and covering the sidewalls of the first fin pattern; a second field insulating film located on the substrate and covering the sidewalls of the second fin pattern; a first source / drain pattern located on the first field insulating film, connected to the first fin pattern and including a first silicon-germanium pattern; and a second source / drain pattern located on the second field insulating film, connected to the second fin pattern and including a second silicon-germanium pattern, wherein the second source / drain pattern and the second field insulating film define one or more first air gaps therebetween.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This application claims the priority of and all rights arising from Korean Patent Application No. 10 - 2021 - 0110811, filed on August 23, 2021, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

[0003] This disclosure relates to a semiconductor device. Prior Art

[0004] As one of the scaling techniques for increasing the density of semiconductor devices, a multi - gate transistor has been proposed in which a multi - channel active pattern (or silicon body) having a fin or nanowire shape is formed on a substrate and a gate is formed on the surface of the multi - channel active pattern.

[0005] This multi - gate transistor uses a three - dimensional channel and is thus easy to scale. In addition, the current control ability can be improved without increasing the gate length of the multi - gate transistor. Furthermore, the short - channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

[0006] Meanwhile, as the pitch size of semiconductor devices decreases, research has been required to reduce capacitance and ensure electrical stability between contacts in semiconductor devices. Summary of the Invention

[0007] Aspects of this disclosure provide a semiconductor device capable of improving the performance and reliability of components.

[0008] However, aspects of this disclosure are not limited to the aspects described herein. By referring to the detailed description of this disclosure given below, the above and other aspects of this disclosure will become more apparent to those of ordinary skill in the art to which this disclosure pertains.

[0009] According to one aspect of the present disclosure, a semiconductor device includes: a plurality of first fin patterns located in a first region of a substrate and spaced apart from each other in a first direction; a plurality of second fin patterns located in a second region of the substrate and spaced apart from each other in a second direction; a first field insulating film located on the substrate and covering sidewalls of the first fin patterns; a second field insulating film located on the substrate and covering sidewalls of the second fin patterns; a first source / drain pattern located on the first field insulating film, connected to the first fin patterns and including a first silicon-germanium pattern; and a second source / drain pattern located on the second field insulating film, connected to the second fin patterns and including a second silicon-germanium pattern, wherein one or more first air gaps are defined between the second source / drain pattern and the second field insulating film, wherein the first source / drain pattern includes a first bottom surface connected to respective ones of the first fin patterns and one or more first connecting surfaces each connecting corresponding adjacent pairs of the first bottom surfaces to each other, the second source / drain pattern includes a second bottom surface connected to respective ones of the second fin patterns and one or more second connecting surfaces each connecting corresponding adjacent pairs of the second bottom surfaces to each other, the number of the first air gaps is the same as the number of the second connecting surfaces, and at least one of the first connecting surfaces is in complete contact with an upper surface of the first field insulating film.

[0010] According to another aspect of the present disclosure, a semiconductor device includes: a plurality of first fin patterns located in a first region of a substrate and spaced apart from each other; a first field insulating film located on the substrate and covering sidewalls of the first fin patterns; and a first source / drain pattern located on the first field insulating film and connected to the first fin patterns, wherein the first source / drain pattern includes a plurality of first epitaxial regions, a connecting semiconductor region, and a second epitaxial region, the first epitaxial regions are located on respective ones of the first fin patterns, the connecting semiconductor region extends along an upper surface of the first field insulating film and is in contact with the first field insulating film, and the second epitaxial region is located on the first epitaxial regions and the connecting semiconductor region, the second epitaxial region connects the first epitaxial regions to the connecting semiconductor region, the first epitaxial regions, the connecting semiconductor region, and the second epitaxial region include silicon-germanium, and a germanium fraction in the connecting semiconductor region is less than a germanium fraction in the second epitaxial region.

[0011] According to another aspect of the present disclosure, a semiconductor device includes: a plurality of first fin patterns located in the I / O region of a substrate, and the first fin patterns are spaced apart from each other in a first direction; a plurality of second fin patterns located in the logic region of the substrate, and the second fin patterns are spaced apart from each other in a second direction; a first field insulating film located on the substrate and covering sidewalls of the first fin patterns; a second field insulating film located on the substrate and covering sidewalls of the second fin patterns; a first source / drain pattern located on the first field insulating film, connected to the first fin patterns and including a first silicon-germanium pattern on the first fin patterns; a second source / drain pattern located on the second field insulating film, connected to the second fin patterns and including a second silicon-germanium pattern; and one or more air gaps located between the second source / drain pattern and the second field insulating film, wherein the first source / drain pattern includes bottom surfaces connected to respective ones of the first fin patterns and one or more connecting surfaces each connecting corresponding adjacent pairs of the bottom surfaces to each other, the number of the first fin patterns is greater than the number of the second fin patterns, the number of the air gaps is one less than the number of the second fin patterns, and the one or more connecting surfaces are in complete contact with an upper surface of the first field insulating film. Brief Description of the Drawings

[0012] The above and other aspects and features of the present disclosure will become more apparent by referring to the detailed description of its example embodiments with reference to the accompanying drawings, in which: FIG. 1 is an illustrative layout diagram for describing a semiconductor device according to some example embodiments. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. FIG. 4 is a cross-sectional view taken along line C-C of FIG. 1. FIG. 5 is a cross-sectional view taken along line D-D of FIG. 1. FIGS. 6 and 7 are enlarged views of a portion P of FIG. 2. FIGS. 8 to 12 are diagrams respectively for describing a semiconductor device according to some example embodiments. FIG. 13 is a diagram for describing a semiconductor device according to an example embodiment. FIGS. 14 and 15 are diagrams for describing a semiconductor device according to an example embodiment. FIGS. 16 and 17 are diagrams for describing a semiconductor device according to an example embodiment. FIG. 18 is a diagram for describing a semiconductor device according to an example embodiment. FIG. 19 is a diagram for describing a semiconductor device according to an example embodiment. FIG. 20 is an illustrative layout diagram for describing a semiconductor device according to an example embodiment. FIG. 21 is a cross-sectional view taken along line A-A of FIG. 20. FIG. 22 is an illustrative layout diagram for describing a semiconductor device according to an exemplary embodiment. FIGS. 23 to 25 are cross-sectional views taken along line D-D, line E-E, and line F-F of FIG. 22, respectively. Embodiments

[0013] In the diagrams of semiconductor devices according to some exemplary embodiments, fin field effect transistors (FinFETs) including channel regions having a fin pattern shape, transistors including nanowires or nanosheets, and multi-bridge channel field effect transistors (MBCFET™) are shown by way of example, but the present disclosure is not limited thereto. A semiconductor device according to some exemplary embodiments may include a tunnel field effect transistor (FET) or a three-dimensional (3D) transistor. A semiconductor device according to some exemplary embodiments may include a planar transistor. In addition, the technical spirit or concept of the present disclosure may be applied to FETs based on two-dimensional (2D) materials and their heterostructures.

[0014] In addition, a semiconductor device according to some exemplary embodiments may include a bipolar junction transistor, a lateral double-diffused metal oxide semiconductor (LDMOS) transistor, or the like.

[0015] A semiconductor device according to some exemplary embodiments will be described with reference to FIGS. 1 to 7.

[0016] FIG. 1 is an illustrative layout diagram for describing a semiconductor device according to some exemplary embodiments. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. FIG. 4 is a cross-sectional view taken along line C-C of FIG. 1. FIG. 5 is a cross-sectional view taken along line D-D of FIG. 1. FIGS. 6 and 7 are enlarged views of part P of FIG. 2. For ease of explanation, the vias 206 and the wiring lines 207 are not shown in FIG. 1.

[0017] For reference purposes, first gate contact 175 and second gate contact 275 are shown in the figures as being disposed at one end of first gate electrode 120 and one end of second gate electrode 220, respectively, but this is for ease of explanation only and the present disclosure is not limited thereto.

[0018] Referring to FIGS. 1 to 7, a semiconductor device according to some example embodiments may include a plurality of first fin patterns 110, a plurality of second fin patterns 210, a first gate electrode 120, a second gate electrode 220, a first source / drain pattern 150, and a second source / drain pattern 250.

[0019] Substrate 100 may include a first region I and a second region II. The first region I and the second region II may perform different functions. For example, the first region I of substrate 100 may be an I / O region associated with the input / output of the semiconductor device, and the second region II of substrate 100 may be a logic region.

[0020] Transistors having the same conductivity type may be formed in the first region I of substrate 100 and the second region II of substrate 100. For example, each of the first region I of substrate 100 and the second region II of substrate 100 may be a P-channel metal oxide semiconductor (PMOS) formation region.

[0021] Substrate 100 may be bulk silicon or silicon on insulator (SOI). In some example embodiments, substrate 100 may be a silicon substrate or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.

[0022] A plurality of first fin patterns 110 may be disposed in the first region I of substrate 100. The first fin patterns 110 may be disposed in a first active region RX1. The first fin patterns 110 may protrude from substrate 100, more specifically from the first active region RX1.

[0023] The first fin patterns 110 may extend in an elongated manner along a first direction X1. The first fin patterns 110 may be spaced apart from each other in a second direction Y1 that intersects the first direction X1. That is, the plurality of first fin patterns 110 may be spaced apart from each other in the second direction Y1 and arranged in the second direction Y1.

[0024] The first fin-shaped pattern 110 may be defined by a first fin groove FT1 extending in a first direction X1. The first fin groove FT1 may define sidewalls 110SW of the first fin-shaped pattern.

[0025] A plurality of second fin-shaped patterns 210 may be disposed in a second region II of the substrate 100. The second fin-shaped patterns 210 may be disposed in a second active region RX2. The second fin-shaped patterns 210 may protrude from the substrate 100, more specifically, from the second active region RX2.

[0026] The second fin-shaped patterns 210 may extend in an elongated manner along a third direction X2. The second fin-shaped patterns 210 may be spaced apart from each other in a fourth direction Y2 that intersects the third direction X2. That is, the plurality of second fin-shaped patterns 210 may be spaced apart from each other in the fourth direction Y2 and arranged in the fourth direction Y2.

[0027] The second fin-shaped patterns 210 may be defined by a second fin groove FT2 extending in the third direction X2. The second fin groove FT2 may define sidewalls 210SW of the second fin-shaped pattern.

[0028] The first direction X1 and the second direction Y1 may intersect a fifth direction Z. The third direction X2 and the fourth direction Y2 may intersect the fifth direction Z. The fifth direction Z may be a direction perpendicular to the upper surface of the substrate 100.

[0029] The first active region RX1 and the second active region RX2 may be defined by a deep trench DT. The deep trench DT is deeper than the first fin groove FT1 and the second fin groove FT2. For example, the deep trench DT may extend in an elongated manner in the first direction X1 or the third direction X2.

[0030] The number of the first fin-shaped patterns 110 disposed in the first active region RX1 is greater than the number of the second fin-shaped patterns 210 disposed in the second active region RX2. For example, the number of the first fin-shaped patterns 110 may be four or more than four. The number of the second fin-shaped patterns 210 may be three or less than three.

[0031] The first fin-shaped pattern 110 and the second fin-shaped pattern 210 can be parts of the substrate 100 respectively, and can include an epitaxial layer grown from the substrate 100. Each of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 can include, for example, silicon or germanium as an elemental semiconductor material. In addition, each of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 can include a compound semiconductor, such as a Group-IV / IV compound semiconductor or a Group-III / V compound semiconductor.

[0032] The Group-IV / IV compound semiconductor can be, for example, a binary compound or a ternary compound, including two or more than two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn); and / or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with Group-IV elements.

[0033] The Group-III / V compound semiconductor can be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as Group-III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as Group-V elements.

[0034] As an example, the first fin-shaped pattern 110 and the second fin-shaped pattern 210 can be silicon fin-shaped patterns. As another example, the first fin-shaped pattern 110 and the second fin-shaped pattern 210 can be fin-shaped patterns including silicon-germanium patterns.

[0035] The first field insulating film 105 and the second field insulating film 106 can be formed on the substrate 100. The first field insulating film 105 can be disposed in the first region I of the substrate 100. The second field insulating film 106 can be disposed in the second region II of the substrate 100.

[0036] The first field insulating film 105 can fill the deep trench DT. The first field insulating film 105 can fill a part of the first fin trench FT1. The first field insulating film 105 can cover at least a part of the sidewalls 110SW of the plurality of first fin-shaped patterns.

[0037] The first field insulating film 105 may include a first internal field insulating film 105a and a first external field insulating film 105b. The first internal field insulating film 105a may be disposed between a pair of first fin patterns 110 adjacent to each other in the second direction Y1. The first external field insulating film 105b may be disposed around the first active region RX1. In the first fin pattern 110 disposed at the outermost portion of the first active region RX1, the first sidewall 110SW of the first fin pattern may be covered by the first internal field insulating film 105a, and the second sidewall 110SW of the first fin pattern may be covered by the first external field insulating film 105b. The first sidewall 110SW and the second sidewall 110SW of the first fin pattern are sidewalls opposite to each other in the second direction Y1.

[0038] A portion of the first fin pattern 110 may protrude above the upper surface 105a_US of the first internal field insulating film and the upper surface 105b_US of the first external field insulating film. Based on the bottom surface of the deep trench DT, the lowermost portion of the upper surface 105a_US of the first internal field insulating film is higher than the lowermost portion of the upper surface 105b_US of the first external field insulating film.

[0039] The second field insulating film 106 may fill the deep trench DT. The second field insulating film 106 may fill a portion of the second fin trench FT2. The second field insulating film 106 may cover the sidewalls 210SW of the plurality of second fin patterns.

[0040] The second field insulating film 106 may include a second internal field insulating film 106a and a second external field insulating film 106b. The second internal field insulating film 106a may be disposed between a pair of second fin patterns 210 adjacent to each other in the fourth direction Y2. The second external field insulating film 106b may be disposed around the second active region RX2. In the second fin pattern 210 disposed at the outermost portion of the second active region RX2, the first sidewall 210SW of the second fin pattern may be covered by the second internal field insulating film 106a, and the second sidewall 210SW of the second fin pattern may be covered by the second external field insulating film 106b. The first sidewall 210SW and the second sidewall 210SW of the second fin pattern are sidewalls opposite to each other in the fourth direction Y2.

[0041] A part of the second fin-shaped pattern 210 may protrude above the upper surface 106a_US of the second internal field insulating film and the upper surface 106b_US of the second external field insulating film. Based on the bottom surface of the deep trench DT, the lowermost part of the upper surface 106a_US of the second internal field insulating film is higher than the lowermost part of the upper surface 106b_US of the second external field insulating film.

[0042] Each of the first field insulating film 105 and the second field insulating film 106 may include an insulating material. For example, each of the first field insulating film 105 and the second field insulating film 106 may include an oxide film, a nitride film, a nitrogen oxide film, or a combined film thereof, but the present disclosure is not limited thereto. In the drawings, each of the first field insulating film 105 and the second field insulating film 106 is shown as a single layer, but this is only for ease of explanation and the present disclosure is not limited thereto.

[0043] The first gate electrode 120 may be disposed in the first region I of the substrate 100. The first gate electrode 120 may be disposed on the first field insulating film 105. The first gate electrode 120 may extend in the second direction Y1.

[0044] The first gate electrode 120 may be disposed on the first fin-shaped pattern 110. The first gate electrode 120 may cross a plurality of first fin-shaped patterns 110. Adjacent first gate electrodes 120 may be spaced apart from each other in the first direction X1.

[0045] The second gate electrode 220 may be disposed in the second region II of the substrate 100. The second gate electrode 220 may be disposed on the second field insulating film 106. The second gate electrode 220 may extend in the fourth direction Y2.

[0046] The second gate electrode 220 may be disposed on the second fin-shaped pattern 210. The second gate electrode 220 may cross a plurality of second fin-shaped patterns 210. Adjacent second gate electrodes 220 may be spaced apart from each other in the third direction X2.

[0047] For example, the distance W1 between adjacent first gate electrodes 120 in the first direction X1 may be greater than the distance W2 between adjacent second gate electrodes 220 in the third direction X2.

[0048] As shown in the drawings, the first gate electrode 120 only crosses the first fin pattern 110 disposed in the first active region RX1, but the present disclosure is not limited thereto. The first gate electrode 120 may extend in the second direction Y1 to cross the fin pattern in another active region adjacent to the first active region RX1 in the second direction Y1. Similarly, as shown in the drawings, the second gate electrode 220 only crosses the second fin pattern 210 disposed in the second active region RX2, but the present disclosure is not limited thereto.

[0049] Although not shown in the drawings, the cross-sectional view of the second gate electrode 220 taken along the fourth direction Y2 may be similar to FIG. 3. In addition, the cross-sectional view of the second fin pattern 210 taken along the third direction X2 may be similar to FIG. 4. Therefore, the first gate electrode 120, the first gate insulating film 130, the first gate spacer 140, and the first gate capping pattern 145 disposed in the first region of the substrate 100 will be mainly described hereinafter.

[0050] The first gate electrode 120 may surround the first fin pattern 110 protruding above the upper surface 105a_US and the upper surface 105b_US of the first field insulating film 105.

[0051] Each of the first gate electrode 120 and the second gate electrode 220 may include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof.

[0052] Each of the first gate electrode 120 and the second gate electrode 220 may include a conductive metal oxide, a conductive metal oxynitride, or the like, and may include an oxidized form of the above materials.

[0053] The first gate spacer 140 can be disposed on the sidewalls of the first gate electrode 120. The first gate spacer 140 can extend in the second direction Y1. The first gate spacer 140 can include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0054] The first gate insulating film 130 can extend along the sidewalls and the bottom surface of the first gate electrode 120. The first gate insulating film 130 can be formed on the first fin pattern 110 and the first field insulating film 105. The first gate insulating film 130 can be formed between the first gate electrode 120 and the first gate spacer 140.

[0055] The first gate insulating film 130 can be formed along the contour of the first fin pattern 110 protruding above the first field insulating film 105 and along the upper surface 105a_US and the upper surface 105b_US of the first field insulating film. Although not shown in the figures, an interface layer can further be formed along the contour of the first fin pattern 110 protruding above the first field insulating film 105. The first gate insulating film 130 can be formed on the interface layer.

[0056] The first gate insulating film 130 can include silicon dioxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon dioxide. The high-k material can include, for example, one or more of the following: boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0057] A semiconductor device according to some example embodiments can include a negative capacitance (NC) field effect transistor (FET) using a negative capacitor. For example, the first gate insulating film 130 can include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

[0058] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series with each other and the capacitance of each individual capacitor has a positive value, the total capacitance decreases compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

[0059] When the ferroelectric material film having a negative capacitance and the paraelectric material film having a positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series with each other may increase. Using the increase in the total capacitance value, a transistor including the ferroelectric material film may have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0060] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of the following: hafnium oxide, zirconium chromate oxide, barium strontium titanate oxide, barium titanate oxide, or lead zirconate titanate oxide. Here, as an example, zirconium chromate oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0061] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0062] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of the following: gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), or yttrium (Y).

[0063] When the dopant is aluminum (Al), the ferroelectric material film may include 3 atomic % (at%) to 8 atomic % of aluminum. Here, the ratio of the dopant may refer to the ratio of aluminum to the sum of hafnium and the dopant (e.g., aluminum).

[0064] When the dopant is silicon (Si), the ferroelectric material film may contain 2 atomic % to 10 atomic % silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 atomic % to 10 atomic % yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 atomic % to 7 atomic % gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 atomic % to 80 atomic % zirconium.

[0065] The paraelectric material film may have paraelectric characteristics. The paraelectric material film may contain at least one of, for example, silicon oxide or metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may contain at least one of, for example, hafnium oxide, zirconium oxide, or aluminum oxide, but the present disclosure is not limited thereto.

[0066] The ferroelectric material film and the paraelectric material film may contain the same material. The ferroelectric material film may have ferroelectric characteristics, but the paraelectric material film may not have ferroelectric characteristics. For example, when the ferroelectric material film and the paraelectric material film contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0067] The ferroelectric material film may have a thickness with ferroelectric characteristics. The thickness of the ferroelectric material film may be, for example, 0.5 nm to 10 nm, but the present disclosure is not limited thereto. Since the critical thickness indicating ferroelectric characteristics may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0068] As an example, the first gate insulating film 130 may include a ferroelectric material film. As another example, the first gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film 130 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0069] The first gate cap pattern 145 may be disposed on the upper surface of the first gate electrode 120 and the upper surface of the first gate spacer 140. The first gate cap pattern 145 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof.

[0070] In some exemplary embodiments, the first gate cap pattern 145 may be disposed between the first gate spacers 140. In this case, the upper surface of the first gate cap pattern 145 may be coplanar with the upper surface of the first gate spacers 140.

[0071] The first source / drain pattern 150 may be disposed on the first field insulating film 105. The first source / drain pattern 150 may be disposed in the first active region RX1.

[0072] The first source / drain pattern 150 may be disposed on the plurality of first fin patterns 110. The first source / drain pattern 150 may be connected to the plurality of first fin patterns 110. The first source / drain pattern 150 may be disposed between the first gate electrodes 120 adjacent to each other in the first direction X1.

[0073] The second source / drain pattern 250 may be disposed on the second field insulating film 106. The second source / drain pattern 250 may be disposed in the second active region RX2.

[0074] The second source / drain pattern 250 may be disposed on the plurality of second fin patterns 210. The second source / drain pattern 250 may be connected to the plurality of second fin patterns 210. The second source / drain pattern 250 may be disposed between the second gate electrodes 220 adjacent to each other in the third direction X2.

[0075] Since the first source / drain pattern 150 is connected to the plurality of first fin patterns 110 and the second source / drain pattern 250 is connected to the plurality of second fin patterns 210, each of the first source / drain pattern 150 and the second source / drain pattern 250 may be a common source / drain pattern.

[0076] The first source / drain pattern 150 and the second source / drain pattern 250 may be included in the source / drain of transistors that respectively use the first fin pattern 110 and the second fin pattern 210 as channel regions.

[0077] The first source / drain pattern 150 may include a bottom surface 150BS, sidewalls 150SW, and a connecting surface 150CS. The first source / drain pattern 150 may be connected to the respective first fin patterns 110 via the bottom surface 150BS of the first source / drain pattern. The connecting surface 150CS of the first source / drain pattern may connect the adjacent bottom surfaces 150BS of the first source / drain pattern to each other. As shown in the figure, the bottom surface 150BS of the first source / drain pattern is a curved surface, but the present disclosure is not limited thereto.

[0078] The number of the bottom surfaces 150BS of the first source / drain pattern included in the first source / drain pattern 150 is the same as the number of the first fin patterns 110. The first source / drain pattern 150 includes a plurality of bottom surfaces 150BS of the first source / drain pattern. The number of the connection surfaces 150CS of the first source / drain pattern included in the first source / drain pattern 150 is one less than the number of the first fin patterns 110. The first source / drain pattern 150 includes one or more connection surfaces 150CS of the first source / drain pattern.

[0079] When viewed in the first direction X1, the sidewalls 150SW of the first source / drain pattern may extend in the fifth direction Z. The sidewalls 150SW of the first source / drain pattern may be directly connected to the bottom surfaces 150BS of the first source / drain pattern. The sidewalls 150SW of the first source / drain pattern may include lower sidewalls 150SW1 and upper sidewalls 150SW2.

[0080] The lower sidewalls 150SW1 of the first source / drain pattern may be directly connected to the bottom surfaces 150BS of the first source / drain pattern. The facet intersection of the first source / drain pattern may be the point where the lower sidewalls 150SW1 of the first source / drain pattern meet the upper sidewalls 150SW2 of the first source / drain pattern. The width of the first source / drain pattern 150 between the lower sidewalls 150SW1 of the first source / drain pattern in the second direction Y1 may increase as the position in the first source / drain pattern 150 becomes farther from the substrate 100. The width of the first source / drain pattern 150 between the upper sidewalls 150SW2 of the first source / drain pattern in the second direction Y1 may decrease as the position of the first source / drain pattern 150 becomes farther from the substrate 100. The facet intersection of the first source / drain pattern may be the point where the width of the first source / drain pattern 150 in the second direction Y1 stops increasing and then begins to decrease as the first source / drain pattern 150 becomes farther from the substrate 100.

[0081] The first source / drain pattern 150 may include a plurality of first lower epitaxial regions 151, one or more connection semiconductor regions 153, and a first upper epitaxial region 152.

[0082] The first lower epitaxial regions 151 may be disposed on each of the first fin patterns 110. The first source / drain pattern 150 may be connected to the first fin patterns 110 via the first lower epitaxial regions 151. The first lower epitaxial regions 151 may define the bottom surfaces 150BS of the first source / drain pattern.

[0083] The connecting semiconductor region 153 extends along the upper surface of the first field insulating film 105. For example, the connecting semiconductor region 153 may extend along the upper surface 105a_US of the first internal field insulating film. The connecting semiconductor region 153 may be in contact with the first lower epitaxial region 151. The connecting semiconductor region 153 may define the connecting surface 150CS of the first source / drain pattern.

[0084] In FIG. 6, the connecting semiconductor region 153 may include a facet 153FC having a specific angle. In FIG. 7, the connecting semiconductor region 153 does not include a facet. The following description will be mainly provided with reference to FIG. 6.

[0085] The first upper epitaxial region 152 may be disposed on the first lower epitaxial region 151 and the connecting semiconductor region 153. The first upper epitaxial region 152 may connect the first lower epitaxial region 151 and the connecting semiconductor region 153 to each other. The first upper epitaxial region 152 is disposed on the plurality of first fin patterns 110. The first upper epitaxial region 152 is formed above the plurality of first fin patterns 110.

[0086] Each of the first lower epitaxial region 151, the first upper epitaxial region 152, and the connecting semiconductor region 153 may include silicon-germanium. The first lower epitaxial region 151 and the first upper epitaxial region 152 may be silicon-germanium patterns grown using an epitaxial process. The connecting semiconductor region 153 may be formed by moving a portion of the first upper epitaxial region 152 during the manufacturing process.

[0087] The germanium fraction in the first lower epitaxial region 151 is less than the germanium fraction in the first upper epitaxial region 152. The germanium fraction in the connecting semiconductor region 153 is less than the germanium fraction in the first upper epitaxial region 152. As an example, the germanium fraction in the first lower epitaxial region 151 may be greater than the germanium fraction in the connecting semiconductor region 153. As another example, the germanium fraction in the first lower epitaxial region 151 may be the same as the germanium fraction in the connecting semiconductor region 153. As still another example, the germanium fraction in the first lower epitaxial region 151 may be less than the germanium fraction in the connecting semiconductor region 153.

[0088] The second source / drain pattern 250 may include a bottom surface 250BS, sidewalls 250SW, and a connecting surface 250CS. The second source / drain pattern 250 may be connected to respective second fin patterns 210 via the bottom surface 250BS of the second source / drain pattern. The connecting surface 250CS of the second source / drain pattern may connect the second source / drain patterns adjacent to the bottom surface 250BS to each other. As shown in the figure, the bottom surface 250BS of the second source / drain pattern is a curved surface, but the present disclosure is not limited thereto.

[0089] The number of the bottom surfaces 250BS of the second source / drain pattern included in the second source / drain pattern 250 is the same as the number of the second fin patterns 210. The second source / drain pattern 250 includes a plurality of bottom surfaces 250BS of the second source / drain pattern. The number of the connecting surfaces 250CS of the second source / drain pattern included in the second source / drain pattern 250 is one less than the number of the second fin patterns 210. The second source / drain pattern 250 includes one or more connecting surfaces 250CS of the second source / drain pattern.

[0090] When viewed in the third direction X2, the sidewalls 250SW of the second source / drain pattern may extend in the fifth direction Z. The sidewalls 250SW of the second source / drain pattern may be directly connected to the bottom surface 250BS of the second source / drain pattern. The sidewalls 250SW of the second source / drain pattern may include a lower sidewall 250SW1 and an upper sidewall 250SW2.

[0091] The lower sidewall 250SW1 of the second source / drain pattern may be directly connected to the bottom surface 250BS of the second source / drain pattern. The facet intersection point of the second source / drain pattern may be the point where the lower sidewall 250SW1 of the second source / drain pattern meets the upper sidewall 250SW2 of the second source / drain pattern. The width of the second source / drain pattern 250 between the lower sidewalls 250SW1 of the second source / drain pattern in the fourth direction Y2 may increase as the position in the second source / drain pattern 250 becomes farther from the substrate 100. The width of the second source / drain pattern 250 between the upper sidewalls 250SW2 of the second source / drain pattern in the fourth direction Y2 may decrease as the position in the second source / drain pattern 250 becomes farther from the substrate 100. The facet intersection point of the second source / drain pattern may be the point where the width of the second source / drain pattern 250 in the fourth direction Y2 stops increasing and then begins to decrease as the second source / drain pattern 250 becomes farther from the substrate 100.

[0092] The second source / drain pattern 250 may include a plurality of second lower epitaxial regions 251 and second upper epitaxial regions 252.

[0093] Each of the second lower epitaxial regions 251 may be disposed on each of the second fin patterns 210. The second source / drain pattern 250 may be connected to the second fin pattern 210 via the second lower epitaxial regions 251. The second lower epitaxial regions 251 may define a bottom surface 250BS of the second source / drain pattern.

[0094] The second upper epitaxial regions 252 may be disposed on the second lower epitaxial regions 251. The second upper epitaxial regions 252 may provide connections between the second lower epitaxial regions 251 spaced apart from each other. The second upper epitaxial regions 252 are disposed on the plurality of second fin patterns 210. The second upper epitaxial regions 252 are formed above the plurality of second fin patterns 210.

[0095] Each of the second lower epitaxial regions 251 and the second upper epitaxial regions 252 may include silicon-germanium. The second lower epitaxial regions 251 and the second upper epitaxial regions 252 may be silicon-germanium patterns grown using an epitaxial process. The germanium fraction in the second lower epitaxial regions 251 is less than the germanium fraction in the second upper epitaxial regions 252.

[0096] In the first source / drain pattern 150, one or more of the connection surfaces 150CS of the first source / drain pattern are in complete contact with the upper surface of the first field insulating film 105. More specifically, one or more of the connection surfaces 150CS of the first source / drain pattern 150 are in complete contact with the upper surface 105a_US of the first internal field insulating film 105a. For example, one or more of the connection surfaces 150CS of the first source / drain pattern are in direct contact with the upper surface 105a_US of the first internal field insulating film 105a.

[0097] Here, the phrase "complete contact" means that in the cross-sectional view shown in FIG. 2, there is no air gap between the connection surface 150CS of the first source / drain pattern 150 and the upper surface 105a_US of the first internal field insulating film 105a.

[0098] In a semiconductor device according to some example embodiments, all connection surfaces 150CS of the first source / drain pattern 150 are in full contact with the upper surface 105a_US of the first internal field insulating film 105a. For example, the first internal field insulating film 105a may include a first portion 105a_1, a second portion 105a_2, and a third portion 105a_3. The second portion 105a_2 of the first internal field insulating film 105a is disposed between the first portion 105a_1 and the third portion 105a_3 of the first internal field insulating film 105a. The connection surface 150CS of the first source / drain pattern 150 corresponding to the first portion 105a_1 of the first internal field insulating film 105a is in full contact with the upper surface 105a_US1 of the first portion 105a_1 of the first internal field insulating film 105a. In other words, the entire upper surface 105a_US1 of the first portion 105a_1 of the first internal field insulating film 105a is in contact with the first source / drain pattern 150. The connection surface 150CS of the first source / drain pattern 150 corresponding to the second portion 105a_2 of the first internal field insulating film is in full contact with the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a. The connection surface 150CS of the first source / drain pattern 150 corresponding to the third portion 105a_3 of the first internal field insulating film 105a is in full contact with the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0099] One or more first air gaps AG_L may be disposed between the second field insulating film 106 and the second source / drain pattern 250. The first air gap AG_L may be disposed between the second internal field insulating film 106a and the second source / drain pattern 250. The first air gap AG_L may be defined between the upper surface 106a_US of the second internal field insulating film 106a and the connection surface 250CS of the second source / drain pattern 250. The first air gap AG_L may have a first air gap width AG_W1 in a fourth direction Y2 and a first air gap height AG_H1 in a fifth direction Z.

[0100] For example, the first air gap AG_L may be disposed between all connection surfaces 250CS of the second source / drain pattern 250 and the upper surface 106a_US of the second internal field insulating film 106a. The number of the first air gaps AG_L is the same as the number of the connection surfaces 250CS of the second source / drain pattern 250. The number of the first air gaps AG_L is one less than the number of the second fin patterns 210.

[0101] In FIG. 6, the second part 105a_2 of the first internal field insulating film 105a may be adjacent to the first part 105a_1 of the first internal field insulating film 105a. Here, the phrase "adjacent to" means that another first internal field insulating film 105a is not disposed between the second part 105a_2 and the first part 105a_1 of the first internal field insulating film 105a. The second part 105a_2 of the first internal field insulating film 105a may be adjacent to the third part 105a_3 of the first internal field insulating film 105a.

[0102] Based on the bottom surface of the first fin trench FT1, the height of the upper surface 105a_US1 of the first part 105a_1 of the first internal field insulating film 105a may be a first height H1. The height of the upper surface 105a_US2 of the second part 105a_2 of the first internal field insulating film 105a may be a second height H2. The height of the upper surface 105a_US3 of the third part 105a_3 of the first internal field insulating film 105a may be a third height H3. Here, the height of the upper surface 105a_US of the first internal field insulating film 105a may be the height from the bottom surface of the first fin trench FT1 to the lowest point in the upper surface 105a_US of the first internal field insulating film 105a.

[0103] The connection surface 150CS of the first source / drain pattern 150 contacts the upper surface 105a_US of the first internal field insulating film 105a. The height from the bottom of the first fin trench FT1 to the first source / drain pattern 150 contacting the first part 105a_1 of the first internal field insulating film 105a may be a first height H1. The height from the bottom of the first fin trench FT1 to the first source / drain pattern 150 contacting the second part 105a_2 of the first internal field insulating film 105a may be a second height H2. The height from the bottom of the first fin trench FT1 to the first source / drain pattern 150 contacting the third part 105a_3 of the first internal field insulating film 105a may be a third height H3.

[0104] In a semiconductor device according to some example embodiments, the height H2 of the upper surface 105a_US2 of the second part 105a_2 of the first internal field insulating film 105a may be the same as the height H1 of the upper surface 105a_US1 of the first part 105a_1 of the first internal field insulating film 105a. The height H2 of the upper surface 105a_US2 of the second part 105a_2 of the first internal field insulating film 105a may be the same as the height H3 of the upper surface 105a_US3 of the third part 105a_3 of the first internal field insulating film 105a.

[0105] The first etch stop film 195 may extend along the upper surface 105b_US of the first external field insulating film 105b, a portion of the sidewall 150SW of the first source / drain pattern 150, the upper surface 106b_US of the second external field insulating film 105b, and a portion of the sidewall 250SW of the second source / drain pattern 250.

[0106] The first etch stop film 195 may include a material having an etch selectivity with respect to the first interlayer insulating film 191 to be described later. The first etch stop film 195 may include, for example, at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), boron oxy silicon nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0107] The first interlayer insulating film 191 may be disposed on the first etch stop film 195. The upper surface of the first interlayer insulating film 191 may be coplanar with the upper surface of the first gate cap pattern 145.

[0108] The first source / drain contact 170 may be disposed on the first source / drain pattern 150. The first source / drain contact 170 is connected to the first source / drain pattern 150. The first source / drain contact 170 may be disposed in the first interlayer insulating film 191.

[0109] The upper surface of the first source / drain contact 170 may be coplanar with the upper surface of the first interlayer insulating film 191. In addition, the upper surface of the first source / drain contact 170 may be coplanar with the upper surface of the gate cap pattern 145.

[0110] The second source / drain contact 270 may be disposed on the second source / drain pattern 250. The second source / drain contact 270 is connected to the second source / drain pattern 250. The second source / drain contact 270 may be disposed in the first interlayer insulating film 191.

[0111] The upper surface of the second source / drain contact 270 may be coplanar with the upper surface of the first interlayer insulating film 191.

[0112] The first silicide film 155 can be disposed between the first source / drain contact 170 and the first source / drain pattern 150. The second silicide film 255 can be formed between the second source / drain contact 270 and the second source / drain pattern 250. Each of the first silicide film 155 and the second silicide film 255 can include a metal silicide material.

[0113] In some example embodiments, each of the first source / drain contact 170 and the second source / drain contact 270 can have an L shape. As another example, each of the first source / drain contact 170 and the second source / drain contact 270 can have a T shape rotated 180°.

[0114] The first gate contact 175 can be disposed on the first gate electrode 120. The first gate contact 175 is connected to the first gate electrode 120. The first gate contact 175 can be disposed in the first gate cap pattern 145. The upper surface of the first gate contact 175 can be coplanar with the upper surface of the first gate cap pattern 145.

[0115] The second gate contact 275 can be disposed on the second gate electrode 220. The second gate contact 275 is connected to the second gate electrode 220. Although not shown in the figures, the second gate contact 275 can be disposed in a gate cap pattern on the second gate electrode 220.

[0116] Each of the first source / drain contact 170, the second source / drain contact 270, the first gate contact 175, and the second gate contact 275 can include a conductive material and can include at least one of, for example, a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, or a conductive semiconductor material. As shown in the figures, each of the first source / drain contact 170, the second source / drain contact 270, and the first gate contact 175 is a single layer, but this is for ease of explanation only and the present disclosure is not limited thereto. As an example, each of the first source / drain contact 170, the second source / drain contact 270, the first gate contact 175, and the second gate contact 275 can include a contact barrier film and a contact fill film that fills the space defined by the contact barrier film. As another example, each of the first source / drain contact 170, the second source / drain contact 270, the first gate contact 175, and the second gate contact 275 can include only a contact fill film without a contact barrier film.

[0117] The second interlayer insulating film 192 can be disposed on the first interlayer insulating film 191. The second etch stop layer 196 can be disposed between the second interlayer insulating film 192 and the first interlayer insulating film 191.

[0118] Each of the first interlayer insulating film 191 and the second interlayer insulating film 192 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The low-k material can include, for example: fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), Tonen Silazene (TOSZ), fluoride silicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but the present disclosure is not limited thereto.

[0119] The second etch stop film 196 can include at least one of, for example, the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), boron oxy silicon nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), or a combination thereof.

[0120] The wiring structure 205 can be disposed in the second interlayer insulating film 192. The wiring structure 205 can include via plugs 206 and wiring lines 207. The wiring lines 207 can be connected to the source / drain contact 170 and the source / drain contact 270, as well as the gate contact 175 and the gate contact 275 via the via plugs 206.

[0121] The via plugs 206 and the wiring lines 207 can be formed through different manufacturing processes. The boundary between the via plugs 206 and the wiring lines 207 can be obvious. In some exemplary embodiments, the via plugs 206 and the wiring lines 207 can have an integrated structure. In this case, the boundary between the via plugs 206 and the wiring lines 207 may not be obvious.

[0122] Each of the via plugs 206 and the wiring lines 207 can include a conductive material and can include at least one of, for example, a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, or a conductive semiconductor material.

[0123] FIGS. 8 to 12 are diagrams respectively used to describe a semiconductor device according to some exemplary embodiments. For ease of explanation, the content different from that described with reference to FIGS. 1 to 7 will be mainly described. For reference purposes, FIGS. 8 to 12 are enlarged views of a portion P of FIG. 2.

[0124] Referring to FIGS. 8 and 9, in a semiconductor device according to some exemplary embodiments, the height H1 of the upper surface 105a_US1 of the first portion 105a_1 of the first internal field insulating film 105a can be the same as the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a.

[0125] The height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a can be different from the height H3 of the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0126] In FIG. 8, the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a can be greater than the height H3 of the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0127] In FIG. 9, the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be less than the height H3 of the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0128] Referring to FIGS. 10 to 12, in a semiconductor device according to some example embodiments, the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be different from the height H3 of the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0129] The height H1 of the upper surface 105a_US1 of the first portion 105a of the first internal field insulating film 105a_1 may be different from the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a.

[0130] In FIG. 10, the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be greater than the height H3 of the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0131] The height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be greater than the height H1 of the upper surface 105a_US1 of the first portion 105a_1 of the first internal field insulating film 105a.

[0132] In FIG. 11, the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be less than the height H3 of the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0133] The height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be less than the height H1 of the upper surface 105a_US1 of the first portion 105a_1 of the first internal field insulating film 105a.

[0134] In FIG. 12, the height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be greater than the height H3 of the upper surface 105a_US3 of the third portion 105a_3 of the first internal field insulating film 105a.

[0135] The height H2 of the upper surface 105a_US2 of the second portion 105a_2 of the first internal field insulating film 105a may be less than the height H1 of the upper surface 105a_US1 of the first portion 105a_1 of the first internal field insulating film 105a.

[0136] FIG. 13 is a diagram for describing a semiconductor device according to an exemplary embodiment. For ease of explanation, contents different from those described with reference to FIGS. 1 to 7 will be mainly described.

[0137] Referring to FIG. 13, in a semiconductor device according to an exemplary embodiment, a part of the sidewall 110SW of the first fin pattern disposed at the outermost portion of the first active region RX1 may be exposed from the first external field insulating film 105b.

[0138] The first external field insulating film 105b may not completely cover the sidewall 110SW of the first fin pattern disposed at the outermost portion of the first active region RX1.

[0139] The first lower epitaxial region 151 may cover the sidewall 110SW of the first fin pattern exposed from the first external field insulating film 105b.

[0140] FIGS. 14 and 15 are diagrams for describing a semiconductor device according to an exemplary embodiment. FIGS. 16 and 17 are diagrams for describing a semiconductor device according to an exemplary embodiment. For ease of explanation, contents different from those described with reference to FIGS. 1 to 7 will be mainly described.

[0141] For reference purposes, FIGS. 15 and 17 are enlarged views of a portion Q of FIGS. 14 and 16.

[0142] Referring to FIGS. 14 to 17, a semiconductor device according to some exemplary embodiments may include one or more second air gaps AG_S disposed between the first source / drain pattern 150 and the first field insulating film 105.

[0143] A second air gap AG_S may be disposed between the first internal field insulating film 105a and the first source / drain pattern 150. The second air gap AG_S may be defined between an upper surface 105a_US of the first internal field insulating film 105a and a connection surface 150CS of the first source / drain pattern 150.

[0144] The second air gap AG_S may have a second air gap width AG_W2 in a second direction Y1 and a second air gap height AG_H2 in a fifth direction Z. The size of the second air gap AG_S is smaller than the size of the first air gap AG_L (see FIG. 5). As an example, the second air gap width AG_W2 may be smaller than the first air gap width AG_W1. The second air gap height AG_H2 may be smaller than the first air gap height AG_H1. As another example, the second air gap width AG_W2 may be smaller than the first air gap width AG_W1. The second air gap height AG_H2 may be the same as the first air gap height AG_H1. As still another example, the second air gap height AG_H2 may be smaller than the first air gap height AG_H1. The second air gap width AG_W2 may be the same as the first air gap width AG_W1.

[0145] The number of the second air gaps AG_S may be smaller than the number of the connection surfaces 150CS of the first source / drain pattern 150. In other words, some of the connection surfaces 150CS of the first source / drain pattern 150 are in full contact with corresponding ones of the upper surface 105a_US of the first internal field insulating film 105a. One or more others of the connection surfaces 150CS of the first source / drain pattern 150 are not in full contact with the upper surface 105a_US of the first internal field insulating film 105a.

[0146] For example, the first internal field insulating film 105a may include a first portion and a second portion spaced apart from each other in the second direction Y1. An upper surface 105a_US of the first portion 105a_1 of the first internal field insulating film 105a is in full contact with the first source / drain pattern 150. An upper surface 105a_US of the second portion 105a_2 of the first internal field insulating film 105a is not in full contact with the first source / drain pattern 150. The second air gap AG_S is disposed between the second portion 105a_2 of the first internal field insulating film 105a and the first source / drain pattern 150. The second air gap AG_S is not disposed between the first portion 150a_1 of the first internal field insulating film 105a and the first source / drain pattern 150.

[0147] In FIG. 15, a connecting semiconductor region 153 may be disposed on the upper surface 105a_US of a first internal field insulating film 105a on which a second air gap AG_S is disposed.

[0148] In FIG. 17, a plurality of connecting semiconductor regions 153 spaced apart from each other may be disposed on the upper surface 105a_US of a first internal field insulating film 105a on which a second air gap AG_S is disposed.

[0149] The shape around the second air gap AG_S shown in FIGS. 15 and 17 is only an example, and the technical spirit (or concept) of this disclosure is not limited thereto.

[0150] FIG. 18 is a diagram for describing a semiconductor device according to an exemplary embodiment. FIG. 19 is a diagram for describing a semiconductor device according to an exemplary embodiment. For ease of explanation, the content different from that described with reference to FIGS. 1 to 7 will be mainly described.

[0151] Referring to FIG. 18, the semiconductor device according to the exemplary embodiment may further include dummy protruding patterns DFP disposed around a plurality of first fin patterns 110.

[0152] Deep trenches DT (see FIG. 2) are not formed around the plurality of first fin patterns 110. A first active region RX1 may be defined between the dummy protruding patterns DFP.

[0153] Although not shown in FIGS. 18 and 19, dummy protruding patterns DFP may be disposed around the plurality of first fin patterns 110. A second active region RX2 (see FIG. 5) may be defined between the dummy protruding patterns DFP.

[0154] The upper surface of the dummy protruding pattern DFP is covered by a first field insulating film 105. For example, the upper surface of the dummy protruding pattern DFP is covered by a first external field insulating film 105b. The dummy protruding pattern DFP may include a semiconductor material.

[0155] Referring to FIG. 19, the semiconductor device according to the exemplary embodiment may further include fin spacers 110FS disposed on the sidewalls 110SW of the first fin pattern.

[0156] The fin spacers 110FS may be disposed on the first field insulating film 105. The connecting semiconductor region 153 may cover the fin spacers 110FS.

[0157] The fin spacer 110FS may include, for example, at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbide nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0158] Although not shown in the drawings, the fin spacer may be disposed on the sidewall 210SW of the second fin pattern 210.

[0159] FIG. 20 is an illustrative layout diagram for describing a semiconductor device according to an example embodiment. FIG. 21 is a cross-sectional view taken along line A-A of FIG. 20. For ease of explanation, content different from that described with reference to FIGS. 1 to 7 will be mainly described.

[0160] Referring to FIGS. 20 and 21, the number of first fin patterns 110 disposed in the first active region RX1 is greater than four.

[0161] As shown in FIGS. 20 and 21, eight first fin patterns 110 are disposed in the first active region RX1, but the present disclosure is not limited thereto.

[0162] n first fin patterns 110 may be disposed in the first active region RX1. Here, n may be a natural number of 4 or greater than 4.

[0163] The first source / drain pattern 150 is connected to the n first fin patterns 110. The first source / drain pattern 150 includes a bottom surface 150BS of the n first source / drain patterns 150. The first source / drain pattern 150 includes a connection surface 150CS of the n - 1 first source / drain patterns 150.

[0164] n - 1 first internal field insulating films 105a may be disposed between the first source / drain pattern 150 and the substrate 100. Each first internal field insulating film 105a may fill the fin trench FT1.

[0165] As shown in FIGS. 6 and 8 to 12, three first internal field insulating films 105a that are continuous (e.g., adjacent to each other) in the second direction Y1 among the n - 1 first internal field insulating films 105a may illustrate the height relationship between the upper surfaces 105a_US of the three first internal field insulating films.

[0166] In addition, as an example, n-1 connection surfaces 150CS of the first source / drain pattern 150 may be in complete contact with the upper surface 105a_US of the first internal field insulating film 105a. As another example, some (but not all) of the connection surfaces 150CS of the first source / drain pattern 150 may be in complete contact with the upper surface 105a_US of the corresponding ones in the first internal field insulating film 105a. The second air gap AG_S described with reference to FIGS. 14 to 17 may be disposed between the other connection surfaces 150CS of the first source / drain pattern 150 and the upper surface 105a_US of the corresponding ones in the first internal field insulating film 105a.

[0167] FIG. 22 is an illustrative layout diagram for describing a semiconductor device according to an exemplary embodiment. FIGS. 23, 24, and 25 are cross-sectional views taken along lines D-D, E-E, and F-F of FIG. 22, respectively.

[0168] The description of the first region I of FIG. 22 is the same as or substantially similar to that described with reference to FIGS. 1 to 19, and thus the content related to the second region II of FIG. 22 will be mainly described hereinafter.

[0169] Referring to FIGS. 22 to 25, a semiconductor device according to an exemplary embodiment may include an active pattern 215, a second gate electrode 220, a second source / drain pattern 250, and a second source / drain contact 270.

[0170] The active pattern 215 may be disposed on the substrate 100. The active pattern 215 may extend in an elongated manner in the third direction X2. The active pattern 215 may include a lower pattern 215B and a plurality of fin patterns 215U.

[0171] The lower pattern 215B may protrude from the substrate 100. The lower pattern 215B may extend in an elongated manner in the third direction X2. The lower pattern 215B may be defined by a second fin trench FT2.

[0172] The plurality of fin patterns 215U may be disposed on the upper surface of the lower pattern 215B. The plurality of fin patterns 215U may be spaced apart from the lower pattern 215B in the fifth direction Z. Each individual fin pattern 215U may be spaced apart from each other in the fifth direction Z. In the drawings, three fin patterns 215U are shown disposed in the fifth direction Z, but this is only for ease of explanation and the present disclosure is not limited thereto.

[0173] The lower pattern 215B may be formed by etching a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. The lower pattern 215B may include silicon or germanium as elemental semiconductor materials. In addition, the lower pattern 215B may include compound semiconductors, such as group IV to group IV compound semiconductors or group III-V compound semiconductors. Each of the thin-film patterns 215U may include one of silicon or germanium as elemental semiconductor materials, group IV-IV compound semiconductors, or group III-V compound semiconductors.

[0174] The width of the thin-film pattern 215U in the fourth direction Y2 may increase or decrease proportionally to the width of the lower pattern 215B in the fourth direction Y2. As an example shown in the figure, the widths of the thin-film patterns 215U stacked in the fifth direction Z in the fourth direction Y2 are the same as each other, which is only for easy explanation, and this disclosure is not limited thereto. In some exemplary embodiments, when the thin-film pattern 215U becomes farther from the lower pattern 215B, the width of the thin-film pattern 215U stacked in the fifth direction Z in the fourth direction Y2 may decrease.

[0175] The second field insulating film 106 may cover the sidewalls of the lower pattern 215B. The second field insulating film 106 is not disposed on the upper surface of the lower pattern 215B. Each of the thin-film patterns 215U is disposed at a level higher than the upper surface of the second field insulating film 106.

[0176] The second gate electrode 220 may be disposed on the lower pattern 215B. The second gate electrode 220 may cross the lower pattern 215B. The second gate electrode 220 may surround the thin-film pattern 215U.

[0177] The second gate insulating film 230 may extend along the upper surface of the second field insulating film 106 and the upper surface of the lower pattern 215B. The second gate insulating film 230 may cover the thin-film pattern 215U. The second gate insulating film 230 may be disposed along the outer periphery of the thin-film pattern 215U.

[0178] The gate-to-gate structure GS_INT may be disposed between the thin-film patterns 215U and between the lower pattern 215B and the thin-film pattern 215U. The gate-to-gate structure GS_INT may include the second gate electrode 220 and the second gate insulating film 230 disposed adjacent to each other between the thin-film patterns 215U and between the lower pattern 215B and the thin-film pattern 215U.

[0179] The second gate spacer 240 can be disposed on the sidewall of the second gate electrode 220. The second gate spacer 240 can extend in the fourth direction Y2.

[0180] The second gate cap pattern 245 can be disposed on the upper surface of the second gate electrode 220 and the upper surface of the second gate spacer 240.

[0181] The material included in the second gate insulating film 230 is the same as or substantially similar to the material mentioned in the description of the first gate insulating film 130. The material included in the second gate spacer 240 is the same as or substantially similar to the material mentioned in the description of the first gate spacer 140. The material included in the second gate cap pattern 245 is the same as or substantially similar to the material mentioned in the description of the first gate cap pattern 145.

[0182] In summary, those of ordinary skill in the art will understand that many variations and modifications can be made to the disclosed exemplary embodiments without substantially departing from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the inventive concept are for general and descriptive purposes only and are not for restrictive purposes.

[0183] 100: Substrate 105: First field insulating film 105a: First internal field insulating film 105a_1: First part 105a_2: Second part 105a_3: Third part 105a_US, 105a_US1, 105a_US2, 105a_US3, 105b_US, 106a_US, 106b_US: Upper surface 105b: First external field insulating film 106: Second field insulating film 106a: Second internal field insulating film 106b: Second external field insulating film 110: First fin pattern 110FS: Fin spacer 110SW, 150SW, 210SW, 250SW: Sidewall 120: First gate electrode 130: First gate insulating film 140: First gate spacer 145: First gate top cover pattern 150: First source / drain pattern 150BS, 250BS: Bottom surface 150CS, 250CS: Connection surface 150SW1, 250SW1: Lower sidewall 150SW2, 250SW2: Upper sidewall 151: First lower epitaxial region 152: First upper epitaxial region 153: Connecting semiconductor region 153FC: Facet 155: First silicide film 170: First source / drain contact 175: First gate contact 191: First interlayer insulating film 192: Second interlayer insulating film 195: First etch stop film 196: Second etch stop layer 205: Wiring structure 206: Via plug 207: Wiring line 210: Second fin pattern 215B: Lower pattern 215U: Thin film pattern 215: Active pattern 220: Second gate electrode 230: Second gate insulating film 240: Second gate spacer 245: Second gate top cover pattern 250: Second source / drain pattern 251: Second lower epitaxial region 252: Second upper epitaxial region 255: Second silicide film 270: Second source / drain contact 275: Second gate contact A-A, B-B, C-C, D-D, D-D, E-E, F-F: Line AG_H1: First air gap height AG_H2: Second air gap height AG_L: First air gap AG_S: Second air gap AG_W1: First air gap width AG_W2: Second air gap width DFP: dummy protrusion pattern DT: deep trench FT1: First fin trench FT2: Second fin trench GS_INT: Gate-to-gate structure H1: First height H2: Second height H3: Third height I: First region / I / O region II: Second region / logic region P, Q: Portions RX1: First active region RX2: Second active region W1, W2: Distances X1: First direction X2: Third direction Y1: Second direction Y2: Fourth direction Z: Fifth direction

Claims

1. A semiconductor device, comprising: Multiple first fin-shaped patterns are located in a first region of the base and spaced apart from each other in a first direction; A plurality of second fin-shaped patterns are located in a second region of the substrate and spaced apart from each other in a second direction; a first field insulating film is located on the substrate and covers the sidewalls of the first fin-shaped patterns; A second field insulating film is located on the substrate and covers the sidewalls of the second fin pattern; a first source / drain pattern is located on the first field insulating film, connected to the first fin pattern and including a first silicon-germanium pattern; and a second source / drain pattern is located on the second field insulating film, connected to the second fin pattern and including a second silicon-germanium pattern, wherein the second source / drain pattern and the second field insulating film define one or more first air gaps therebetween; wherein the first source / drain pattern includes a first bottom surface connected to each of the first fin patterns and one or more first connecting surfaces that connect corresponding adjacent elements of the first bottom surface to each other; the second source / drain pattern includes a second bottom surface connected to each of the second fin patterns and one or more second connecting surfaces that connect corresponding adjacent elements of the second bottom surface to each other; the number of first air gaps is the same as the number of second connecting surfaces; and at least one of the first connecting surfaces is in complete contact with the upper surface of the first field insulating film.

2. The semiconductor device of claim 1, wherein the first connection surface is in complete contact with the upper surface of the first field insulating film.

3. The semiconductor device of claim 1, wherein the first source / drain pattern and the first field insulating film define one or more second air gaps therebetween, and the number of second air gaps is less than the number of first connection surfaces.

4. The semiconductor device as claimed in claim 3, wherein the size of the first air gap is greater than the size of the second air gap.

5. The semiconductor device of claim 1, wherein the number of first fin patterns is greater than the number of second fin patterns.

6. The semiconductor device of claim 5, wherein the number of the first fin pattern is four or more.

7. The semiconductor device of claim 1, wherein the first source / drain pattern includes a connection semiconductor region extending along the upper surface of the first field insulating film, and the connection semiconductor region includes silicon-germanium.

8. The semiconductor device of claim 1, wherein the first field insulating film includes a first region, a second region, and a third region, each of the first, second, and third regions being located between adjacent pairs of the first fin pattern, the second region of the first field insulating film being located between the first region of the first field insulating film and the third region of the first field insulating film, and the height of the upper surface of the second region of the first field insulating film being different from the height of the upper surface of the third region of the first field insulating film.

9. The semiconductor device of claim 8, wherein the height of the upper surface of the first region of the first field insulating film is the same as the height of the upper surface of the second region of the first field insulating film.

10. The semiconductor device of claim 8, wherein the height of the upper surface of the second region of the first field insulating film is greater than the height of the upper surface of the first region of the first field insulating film and less than the height of the upper surface of the third region of the first field insulating film.

11. The semiconductor device of claim 8, wherein the height of the upper surface of the first region of the first field insulating film and the height of the upper surface of the third region of the first field insulating film are less than the height of the upper surface of the second region of the first field insulating film.

12. The semiconductor device of claim 8, wherein the height of the upper surface of the first region of the first field insulating film and the height of the upper surface of the third region of the first field insulating film are greater than the height of the upper surface of the second region of the first field insulating film.

13. A semiconductor device, comprising: Multiple first fin-shaped patterns are located in the first region of the base and are spaced apart from each other; A first insulating film is located on the substrate and covers the sidewalls of the first fin pattern; A first source / drain pattern is located on the first field insulating film and connected to the first fin pattern. The first source / drain pattern includes a plurality of first epitaxial regions, a connecting semiconductor region, and a second epitaxial region. The first epitaxial regions are located on each of the first fin patterns. The connecting semiconductor region extends along the upper surface of the first field insulating film and contacts the first field insulating film. The second epitaxial region is located on the first epitaxial region and the connecting semiconductor region, and the second epitaxial region connects the first epitaxial region and the connecting semiconductor region to each other. The first epitaxial region, the connecting semiconductor region, and the second epitaxial region comprise silicon-germanium, and the germanium content in the connecting semiconductor region is less than the germanium content in the second epitaxial region.

14. The semiconductor device of claim 13, wherein the first source / drain pattern includes a first bottom surface connected to each of the first fin pattern and one or more first connection surfaces that connect corresponding adjacent pairs of the first bottom surfaces to each other, and the first connection surfaces are in complete contact with the upper surface of the first field insulating film.

15. The semiconductor device of claim 13, wherein the first source / drain pattern and the first field insulating film define an air gap therebetween, the first field insulating film comprising a first region and a second region located between respective adjacent pairs of the first fin pattern, the upper surface of the first region of the first field insulating film being entirely in contact with the first source / drain pattern, and the air gap being located between the second region of the first field insulating film and the first source / drain pattern.

16. The semiconductor device of claim 13, wherein the connection semiconductor region includes a facet.

17. The semiconductor device as claimed in claim 13, further comprising: Multiple second fin-shaped patterns are located in the second region of the substrate and are spaced apart from each other; A second field insulating film is located on the substrate and covers the sidewalls of the second fin pattern; and a second source / drain pattern is located on the second field insulating film and connected to the second fin pattern; wherein the second source / drain pattern and the second field insulating film define one or more air gaps therebetween, and the number of air gaps is one less than the number of second fin patterns.

18. The semiconductor device as claimed in claim 13, further comprising: The lower pattern is located in the second region of the substrate; Thin sheet pattern, spaced apart from the lower pattern; And a gate electrode, surrounding the outer periphery of the sheet pattern.

19. A semiconductor device, comprising: Multiple first fin patterns are located in the I / O area of ​​the substrate, and the first fin patterns are spaced apart from each other in a first direction; Multiple second fin patterns are located in the logic region of the substrate, and the second fin patterns are spaced apart from each other in a second direction; a first field insulating film is located on the substrate and covers the sidewalls of the first fin patterns; A second field insulating film is located on the substrate and covers the sidewalls of the second fin pattern; a first source / drain pattern is located on the first field insulating film, connected to the first fin pattern and including a first silicon-germanium pattern on the first fin pattern; and a second source / drain pattern is located on the second field insulating film, connected to the second fin pattern and including a second silicon-germanium pattern, the second source / drain pattern and the second field insulating film defining one or more air gaps, wherein the first source / drain pattern includes a bottom surface connected to each of the first fin patterns and one or more connecting surfaces that connect corresponding adjacent ones in the bottom surface to each other, the number of first fin patterns is greater than the number of second fin patterns, the number of air gaps is one less than the number of second fin patterns, and the one or more connecting surfaces are in complete contact with the upper surface of the first field insulating film.

20. The semiconductor device of claim 19, wherein the first source / drain pattern includes a connection semiconductor region extending along the upper surface of the first field insulating film, and the germanium fraction in the connection semiconductor region is less than the germanium fraction in the first silicon-germanium pattern.

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