Operation method of memory controller configured to control memory device

Abstract

This invention discloses a method for operating a memory controller of a memory device. The method includes: storing write data in a first region of the memory device; retrieving first error location information indicating the location of at least one error contained in the data stored in the first region; storing the first error location information in a second region of the memory device; reading read data from the first region of the memory device; reading the first error location information from the second region of the memory device; refining the read data based on the first error location information to generate refined data; performing soft decision decoding based on the refined data to generate corrected data; and outputting the corrected data.

Description

Technical Field

[0001] The exemplary embodiments of the present disclosure described herein relate to semiconductor memory devices, and / or more particularly to a method of operating a storage controller configured to control a non-volatile memory device. [Cross-reference to related applications]

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0124657, filed on September 17, 2021, with the Korean Intellectual Property Office, under 35 U.S.C. § 119, the disclosure of which is incorporated herein by reference in its entirety.

Background Art

[0003] Semiconductor memory devices are classified as: volatile memory devices, in which the stored data is lost when the power is turned off, such as static random access memory (SRAM) or dynamic random access memory (DRAM); or non-volatile memory devices, in which the stored data is retained even when the power is turned off, such as flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0004] Flash memory devices are widely used as high-capacity storage media in computing devices. A flash memory device can store data by adjusting the threshold voltage of a memory cell. As the number of bits to be stored per memory cell increases, the storage capacity of the flash memory device increases. However, in this case, since the read margin of each of the memory cells decreases, the number of errors in the data stored in the memory cells increases.

Summary of the Invention

[0005] The exemplary embodiments of the present disclosure provide a method of operating a memory controller configured to control a memory device with improved reliability.

[0006] According to some example embodiments, a method of operating a memory controller of a memory device includes storing write data in a first region of the memory device; retrieving first error location information indicating a location of at least one error included in the data stored in the first region; storing the first error location information in a second region of the memory device; reading read data from the first region of the memory device; reading the first error location information from the second region of the memory device; refining the read data based on the first error location information to generate refined data; performing soft decision decoding based on the refined data to generate corrected data; and outputting the corrected data.

[0007] According to some example embodiments, a method of operating a memory controller of a memory device includes transmitting a first program command, a first address, and first write data to the memory device; transmitting a first read command and the first address to the memory device to receive first read data from the memory device; comparing the first read data with the first write data to retrieve first error location information regarding a location of at least one error included in the first read data; and transmitting a second program command, a second address, and the first error location information to the memory device.

[0008] According to some example embodiments, a method of operating a memory controller of a memory device includes performing a first read operation on a first region of the memory device to read first read data; performing a plurality of second read operations on the first region of the memory device to read a plurality of soft decision data based on an error of the first read data not being corrected by a first error correction operation for the first read data; performing a second read operation on a second region of the memory device to read error location information; refining at least one of the plurality of soft decision data based on the error location information to generate a plurality of refined soft decision data; and performing a second error correction operation on the plurality of refined soft decision data to output corrected data.

Embodiments

[0010] Hereinafter, embodiments of the present disclosure may be described in detail and clearly to the extent that those of ordinary skill in the art can easily implement the present invention.

[0011] FIG. 1 is a block diagram showing a memory system according to some example embodiments of the present disclosure. Referring to FIG. 1, the memory system 100 may include a memory controller 110 and a memory device 120. In some example embodiments, the memory system 100 may be a high-capacity storage device (e.g., SSD) configured to store data in a computing system, but the present disclosure is not limited thereto.

[0012] The memory controller 110 can be configured to control the memory device 120. For example, the memory controller 110 can store data in the memory device 120 or can read data stored in the memory device 120. The memory device 120 can operate under the control of the memory controller 110. In some example embodiments, the memory device 120 can be a flash memory device, but the present disclosure is not limited thereto.

[0013] The memory controller 110 can include an error correction code (ECC) engine 111 and an error position information (EPI) manager 112. The ECC engine 111 of the memory controller 110 can be configured to detect or correct errors in data read from the memory device 120. For example, due to the physical characteristics of the memory device 120 or various external factors, errors can occur in the data stored in the memory device 120. The ECC engine 111 can generate ECC data by performing an ECC encoding operation on the user data to be stored in the memory device 120. The ECC data can be stored in the memory device 120 together with the user data. The ECC engine 111 can detect and correct errors included in the data read from the memory device 120 by performing an ECC decoding operation on the read data and the ECC data corresponding to the read data.

[0014] In some example embodiments, the ECC engine 111 can detect and correct errors in the data based on a soft decision decoding scheme. Alternatively, the ECC engine 111 can correct errors by using coding modulation such as low density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic code (RSC), trellis-coded modulation (TCM), or block coded modulation (BCM), or various other schemes.

[0015] In some example embodiments, errors that occur in the memory device 120 can be attributed to various factors. As an example, when the characteristics of the memory cells of the memory device 120 deteriorate, errors can occur during a programming operation. Alternatively, errors can occur due to various factors such as read interference, write interference, and temperature changes.

[0016] The memory controller 110 according to some example embodiments of the present disclosure may retrieve and manage the error positions of data stored in the memory device 120. For example, the error position manager 112 of the memory controller 100 may retrieve the error positions of data stored in the memory device 120. Specifically, in the case where the data to be stored in the memory device 120 corresponds to the bit string "11110000" and the actual data stored in the memory device 120 (e.g., data including an error) corresponds to the bit string "11110001", the error position manager 112 may retrieve the position where the error occurs in the bit string (e.g., the LSB position).

[0017] Hereinafter, the term "error position information EPI" is used to describe example embodiments of the present disclosure. The error position information EPI may be information indicating the error positions in the data stored in the memory device 120 (e.g., the positions of the error bits among the bits of the bit string corresponding to the stored data). Alternatively, the error position information EPI may be information indicating the positions of the memory cells where errors occur. That is, the positions of the memory cells where errors occur or the positions of their bit values may be retrieved based on the error position information EPI.

[0018] The error position information EPI retrieved by the error position manager 112 may be stored in the memory device 120. The memory controller 110 may improve the reliability of the data by refining the data read from the memory device 120 based on the error position information EPI stored in the memory device 120. For example, in the case where the data read from the memory device 120 includes multiple errors, the errors may not be corrected by the ECC engine 111. In this case, the memory controller 110 may refine the read data based on the error position information EPI stored in the memory device 120, and may generate refined data. In this case, the refined data may include errors, and the number of the errors is less than the number of the read data. Thus, the refined data may include errors that can be corrected by the ECC engine 111. This may mean that the memory controller 110 can improve the reliability of the data without increasing the burden on the error correction ability of the ECC engine 111. The operation of the error position manager 112 according to some example embodiments of the present disclosure will be described in detail with reference to the following drawings.

[0019] FIG. 2 is a diagram showing a first memory block among multiple memory blocks included in the memory device shown in FIG. 1. In some example embodiments, the memory device 120 of FIG. 1 may be a flash memory device including multiple memory blocks.

[0020] The memory block of the three-dimensional structure will be described with reference to FIG. 2, but the present disclosure is not limited thereto. The memory block according to the present disclosure may have a two-dimensional memory block structure. The first memory block BLK1 will be described with reference to FIG. 2, but the present disclosure is not limited thereto. The remaining memory blocks may be structurally similar to the first memory block BLK1 to be described with reference to FIG. 2.

[0021] In some example embodiments, the first memory block BLK1 to be described with reference to FIG. 2 may correspond to a physical erasure unit of the memory device 120. However, the present disclosure is not limited thereto. For example, the erasure unit may be a page unit, a word line unit, a sub-block unit, or the like.

[0022] Referring to FIG. 2, the first memory block BLK1 may include a plurality of cell strings CS11, cell strings CS12, cell strings CS21, and cell strings CS22. The plurality of cell strings CS11, cell strings CS12, cell strings CS21, and cell strings CS22 may be configured in a column direction and a row direction to form columns and rows.

[0023] Each of the plurality of cell strings CS11, cell strings CS12, cell strings CS21, and cell strings CS22 includes a plurality of cell transistors. For example, each of the cell strings CS11, cell strings CS12, cell strings CS21, and cell strings CS22 may include a string select transistor SSTa and a string select transistor SSTb, a plurality of memory cells MC1 to memory cells MC8, a ground select transistor GSTa and a ground select transistor GSTb, and dummy memory cells DMC1 and dummy memory cells DMC2. In some example embodiments, each of the plurality of cell transistors included in the cell strings CS11, cell strings CS12, cell strings CS21, and cell strings CS22 may be a charge trap flash (CTF) memory cell.

[0024] In each cell string, the plurality of memory cells MC1 to memory cells MC8 are connected in series and stacked in a direction perpendicular to the plane defined by the column direction and the row direction (i.e., in the height direction). In each cell string, the string select transistor SSTa and the string select transistor SSTb are connected in series and inserted between the bit line BL1 or the bit line BL2 and the plurality of memory cells MC1 to memory cells MC8. The ground select transistor GSTa and the ground select transistor GSTb are connected in series and inserted between the plurality of memory cells MC1 to memory cells MC8 and the common source line CSL.

[0025] In some example embodiments, in each cell string, the first dummy memory cell DMC1 can be inserted between a plurality of memory cells MC1 to MC8 and the ground selection transistors GSTa and GSTb. In some example embodiments, the second dummy memory cell DMC2 can be inserted between a plurality of memory cells MC1 to MC8 and the string selection transistors SSTa and SSTb.

[0026] The ground selection transistors GSTa and GSTb of the cell strings CS11, CS12, CS21, and CS22 can be commonly connected by a ground selection line GSL. In some example embodiments, the ground selection transistors on the same column can be connected to the same ground selection line, and the ground selection transistors on different columns can be connected to different ground selection lines. For example, the first ground selection transistor GSTa of the cell strings CS11 and CS12 on the first column can be connected to the first ground selection line, and the first ground selection transistor GSTa of the cell strings CS21 and CS22 on the second column can be connected to the second ground selection line.

[0027] In some example embodiments, although not shown in FIG. 2, the ground selection transistors provided at the same height from the substrate (not shown) can be connected to the same ground selection line, and the ground selection transistors provided at different heights from the substrate can be connected to different ground selection lines.

[0028] The memory cells or the ground selection transistors GSTa and GSTb at the same height from the substrate are commonly connected to the same word line, and the memory cells at different heights from the substrate are connected to different word lines. For example, the memory cells MC1 to MC8 of the cell strings CS11, CS12, CS21, and CS22 can be connected to the first word line WL1 to the eighth word line WL8.

[0029] Among the first string selection transistors SSTa at the same height, the string selection transistors belonging to the same column are connected to the same string selection line, and the string selection transistors belonging to different columns are connected to different string selection lines. For example, the first string selection transistor SSTa of the cell strings CS11 and CS12 on the first column can be commonly connected to the string selection line SSL1a, and the first string selection transistor SSTa of the cell strings CS21 and CS22 on the second column can be commonly connected to the string selection line SSL2a.

[0030] Similarly, among the second string selection transistors SSTb of the same height, the second string selection transistors belonging to the same column are connected to the same string selection line, and the second string selection transistors on different columns are connected to different string selection lines. For example, the second string selection transistors SSTb of the unit strings CS11 and CS12 on the first column are commonly connected to the string selection line SSL1b, and the second string selection transistors SSTb of the unit strings CS21 and CS22 on the second column can be commonly connected to the string selection line SSL2b.

[0031] In some exemplary embodiments, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to different dummy word lines. For example, the first dummy memory cell DMC1 is connected to the first dummy word line DWL1, and the second dummy memory cell DMC2 is connected to the second dummy word line DWL2.

[0032] In some exemplary embodiments, the first memory block BLK1 shown in FIG. 2 is only an example. The number of unit strings can be increased or decreased, and the number of columns and the number of rows of the unit strings can be increased or decreased depending on the number of unit strings. In addition, the number of unit transistors (e.g., GST, MC, DMC, and SST) in the first memory block BLK1 can be increased or decreased, and the height of the first memory block BLK1 can be increased or decreased depending on the number of unit transistors. In addition, the number of lines (e.g., GSL, WL, DWL, and SSL) connected to the unit transistors can be increased or decreased depending on the number of unit transistors.

[0033] FIG. 3 is a diagram showing the threshold voltage distribution of the memory cells of FIG. 2. Hereinafter, for describing the exemplary embodiments of the present disclosure, it is assumed that each of the memory cells in the memory device 120 is a quad level cell (QLC) configured to store 4-bit data. However, the present disclosure is not limited thereto. For example, each memory cell can be a single level cell (SLC) storing one bit, or a multi-level cell (MLC), a triple level cell (TLC), or a quad level cell (QLC) storing n-bit data (n is a natural number greater than 1).

[0034] Referring to FIGS. 2 and 3, each of memory cells MC1 to MC8 in the first memory block BLK1 can be programmed to have an erased state "E" and one of a first programmed state P1 to a fifteenth programmed state P15. Whether the memory cells MC1 to MC8 are normally programmed can be verified by using a first verification voltage VF1 to a fifteenth verification voltage VF15.

[0035] In some exemplary embodiments, even though whether the memory cells MC1 to MC8 are normally programmed is determined by using a first verification voltage VF1 to a fifteenth verification voltage VF15, errors can still occur between adjacent programmed states due to the physical characteristics of the memory cells MC1 to MC8 or insufficient margins between the programmed states. Alternatively, the threshold voltages of the memory cells MC1 to MC8 can be variable due to various external factors associated with the memory cells MC1 to MC8; in this case, errors can occur in the data stored in the memory cells MC1 to MC8. In the case where the errors in the data stored in the memory cells MC1 to MC8 exceed the error correction capability of the ECC engine 111, the reliability of the data stored in the memory cells MC1 to MC8 cannot be guaranteed.

[0036] According to some exemplary embodiments of the present disclosure, since the error position information EPI indicating the error positions of the data stored in the memory cells MC1 to MC8 is separately managed, the errors in the data stored in the memory cells MC1 to MC8 can be partially refined, and the errors in the refined data may not exceed the error correction capability of the ECC engine 111. Therefore, the reliability of the memory system 100 can be improved.

[0037] FIG. 4 is a flowchart showing the operation of the memory controller of FIG. 1. Referring to FIGS. 1 and 3, in operation S111, the memory controller 110 can perform a programming operation to store data in the memory device 120. In some exemplary embodiments, the memory controller 110 can perform the programming operation in units of pages or word lines. For example, the memory controller 110 can send a program command, a first address, and write data to the memory device 120. The memory device 120 can store the write data in the memory cells connected to the word line corresponding to the first address in response to the program command.

[0038] In operation S112, the memory controller 110 may retrieve error position information EPI via a read operation. For example, after performing a program operation in operation S111, the memory controller 110 may read the stored data from the memory device 120. In this case, the data read from the memory device 120 may include errors attributable to the physical characteristics of the memory device 120. The error position manager 112 of the memory controller 110 may retrieve error position information EPI based on the error in the read data (e.g., information about the position of the bit string where the error occurs, or information about the position of the memory cell where the error occurs). In some exemplary embodiments, operation S112 may be performed via at least one read operation. For example, the memory controller 110 may send a read command and a first address to the memory device 120. The memory device 120 may read the data stored in the memory cells connected to the word line corresponding to the first address in response to the read command and may send the read data to the memory controller 110.

[0039] In some exemplary embodiments, operation S112, i.e., the read operation or the error position information retrieval operation, may be performed immediately after performing the program operation in operation S111. Alternatively, operation S112, i.e., the read operation or the error position information retrieval operation, may be performed after a predetermined time has elapsed after the time of the program operation performed in operation S111. Alternatively, operation S112, i.e., the read operation or the error position information retrieval operation, may be performed after performing the program operation of operation S111 up to a predetermined unit (e.g., a memory block unit or a sub-block unit). Operation S112, i.e., the read operation or the error position information retrieval operation, will be described in detail with reference to the following diagrams.

[0040] In operation S113, the memory controller 110 may collect the error position information EPI. In some exemplary embodiments, the memory controller 110 may collect the error position information EPI corresponding to the data of a given unit. For example, one error position information EPI may correspond to one page of data or one word line of data. The memory controller 110 may collect multiple error position information EPIs corresponding to the data of a memory block unit or a sub-block unit.

[0041] In operation S114, the memory controller 110 may store the collected error position information EPI in the memory device 120. In some example embodiments, the error position information EPI may be stored in another area of the memory device 120, which is different from the area storing data (e.g., user data). For example, the memory controller 110 may send a program command, a second address, and the collected error position information EPI to the memory device 120. The memory device 120 may store the collected error position information EPI in a memory cell connected to a word line corresponding to the second address. In some example embodiments, the first address described in operation S111 and the second address described in operation S114 may be different addresses, and the word lines corresponding to the first address and the second address may be different from each other.

[0042] In some example embodiments, the memory cells of the memory device 120 may perform TLC operations. That is, the user data stored in the memory device 120 may be stored in the memory cells performing TLC operations. In contrast, the collected error position information EPI may be stored in the memory cells performing SLC or MLC operations. The area for storing the error position information EPI will be described in detail with reference to the following diagrams.

[0043] As described above, after storing data in the memory device 120, the memory controller 110 may retrieve the error position information EPI associated with the data stored in the memory device 120 and may store the retrieved error position information EPI in the memory device 120.

[0044] In operation S121, the memory controller 110 may perform a first read operation to read data from the memory device 120. In operation S122, the memory controller 110 may perform a first ECC decoding on the read data. In operation S123, the memory controller 110 may determine whether an uncorrectable error exists.

[0045] For example, the ECC engine 111 of the memory controller 110 may detect and correct errors in the data read from the memory device 120. When the error in the data read from the memory device 120 exceeds the error correction capability of the ECC engine 111, the error cannot be corrected. In this case, the memory controller 110 may determine that an uncorrectable error exists.

[0046] When it is determined that there is an uncorrectable error, in operation S124, the memory controller 110 may perform a second read operation to read error position information EPI from the memory device 120. In some example embodiments, the error position information EPI may correspond to the data read via the first read operation in operation S121. In some example embodiments, the second read operation in operation S124 may be different from the first read operation in operation S121. That is, the first read operation and the second read operation may be performed based on different addresses.

[0047] In operation S125, the memory controller 110 may refine the read data based on the error position information EPI. For example, the error position manager 112 of the memory controller 110 may determine the position of the bit string where the error occurs or the position of the memory cell where the error occurs based on the error position information EPI. The error position manager 112 may generate refined data by inverting the bit values in the read data that correspond to the error position information. That is, the refined data may be data containing errors, and the number of errors is less than the number of the original read data.

[0048] In some example embodiments, the error position manager 112 may be configured to refine at least one of the original read data, soft decision data, or hard decision data. Example embodiments associated with how to refine data will be described in detail with reference to the following diagrams.

[0049] In operation S126, the memory controller 110 may perform a second ECC decoding on the refined data. In operation S127, the memory controller 110 may output the corrected data.

[0050] In some example embodiments, since the error level of the refined data is lower than the error level of the original read data, even if the first ECC decoding fails, the second ECC decoding may still succeed (e.g., the error can be corrected). That is, the overall reliability of the memory system 100 can be improved.

[0051] As described above, according to some example embodiments of the present disclosure, after programming the data in the memory device 120, the memory controller 110 may retrieve the error position information associated with the first programmed data and may store the error position information in the memory device 120. Subsequently, the memory controller 110 may refine the error (or a part of the error) of the first data read from the memory device 120 based on the error position information stored in the memory device 120 and may perform ECC decoding on the refined data, and thus the reliability of the first data can be improved.

[0052] Figures 5 to 7 are diagrams for depicting the operation of the error position manager of FIG. 1. The operation of extracting error position information EPI (for example, operation S112 of FIG. 4) will be described with reference to FIGS. 5 to 7. To simplify the diagrams and facilitate the description, only the components required for extracting the error position information EPI are shown and the remaining components are omitted.

[0053] First, referring to FIGS. 1 and 5, the error position manager 112 of the memory controller 110 can generate error position information EPI by comparing the original data with the read data. For example, the memory controller 110 can program the first data DT1 in the memory device 120 (operation ① in FIG. 5). In this case, the first data DT1 can be the bit string "10011001", and the actual data actually stored in the memory device 120 (hereinafter referred to as "the first stored data DT1_s") can be the bit string "10001001". That is, even if the first data DT1 of "10011001" is programmed in the memory device 120, the first stored device data DT1_s stored in the memory device 120 can still have the bit string "10001001" (for example, the fifth bit of the LSB is in error).

[0054] The error position manager 112 of the memory controller 110 can read the first stored data DT1_s stored in the memory device 120 (operation ② in FIG. 5). The error position manager 112 can generate error data ER by comparing the first data DT1 (for example, the original data) with the first stored data DT1_s (for example, the read data containing errors) (operation ③ in FIG. 5). For example, in the case where the first data DT1 (for example, the original data) is "10011001" and the first stored data DT1_s (for example, the data containing errors) is "10001001", the error data ER can be "00010000", indicating that the value of the fifth bit of the LSB corresponds to an error.

[0055] The error position manager 112 can generate error position information EPI based on the error data ER. For example, in some exemplary embodiments of FIG. 5, the generated error data ER can be "00010000", indicating that the value of the fifth bit of the LSB corresponds to an error. In this case, the error position information EPI can be implemented by a binary code (for example, "101") indicating that the value of the fifth bit of the LSB corresponds to an error. That is, the error position information EPI can be a value indicating the position of the bit in the bit string constituting the data where an error occurs; in this case, the magnitude value of the error position information EPI can be different from the magnitude value of the corresponding data.

[0056] In an exemplary embodiment illustrated by FIG. 5, 3 bits of data may be required to express an error position with respect to 8 bits of data. In some exemplary embodiments, the memory controller 110 may perform a programming operation and a read operation of the memory device 120 in a page unit. In this case, the error position information EPI corresponding to one page may have a magnitude of 2 bytes. The numerical values described above are examples for easily describing some exemplary embodiments of the present disclosure, and the present disclosure is not limited thereto.

[0057] Next, referring to FIGS. 1 and 6, the error position manager 112 of the memory controller 110 may generate error position information EPI via a unit counting scheme using multiple read operations.

[0058] For example, as shown in FIG. 6, to distinguish the thirteenth programmed state P13 from the fourteenth programmed state P14, the memory controller 110 may perform multiple read operations by using multiple read voltages R1, read voltage R2, read voltage R3, and read voltage R4. Via the multiple read operations using the multiple read voltages R1, read voltage R2, read voltage R3, and read voltage R4, the memory controller 110 may classify the memory cells of the fourteenth programmed state P14 into memory cells of a first region "A", memory cells of a second region "B", memory cells of a third region "C", and memory cells of a fourth region "D".

[0059] The memory cells of the first region "A" may be memory cells having a very strong error. For example, the memory cells of the first region "A" are memory cells programmed to have the fourteenth programmed state P14. However, since the threshold voltage of the memory cells of the first region "A" is relatively lower than the value of the valley line of the thirteenth programmed state P13 and the fourteenth programmed state P14, the probability that the memory cells of the first region "A" are determined to have the thirteenth programmed state P13 (for example, the probability that the memory cells of the first region "A" are determined to be in error) is high. As described above, the probability that the memory cells of the second region "B", the third region "C", and the fourth region "D" are determined to be in error may also be high.

[0060] In some example embodiments, in memory cells of a first region "A", a second region "B", a third region "C", and a fourth region "D" having a threshold voltage lower than the valley line value of the thirteenth programmed state P13 and the fourteenth programmed state P14, as the difference between the threshold voltage of the memory cell and the valley value increases, the error probability of the memory cell can become higher. That is, the error probability of the memory cells in the third region "C" can be higher than the error probability of the memory cells in the fourth region "D"; the error probability of the memory cells in the second region "B" can be higher than the error probability of the memory cells in the third region "C"; the error probability of the memory cells in the first region "A" can be higher than the error probability of the memory cells in the second region "B". That is, a high error probability means the probability that an error state immediately after a programming operation continues to stay at the error.

[0061] As described above, the error location manager 112 of the memory controller 110 according to some example embodiments of the present disclosure can generate error location information EPI based on memory cells belonging to the first region "A" having the highest error probability. That is, the error location information EPI can indicate the positions of the bits in the bit string of the data that are stored in the memory cells belonging to the first region "A" having the highest error probability.

[0062] For the sake of simplicity of the drawings and convenience of description, the error probability corresponding to the threshold voltage distribution of the thirteenth programmed state P13 and the fourteenth programmed state P14 will be described with reference to FIG. 6. For example, the errors described above can occur at the tails of the threshold voltage distributions of other programmed states. The memory controller 110 can read multiple read data by performing multiple read operations based on multiple read voltages for each of the multiple programmed states. The error location manager 112 can generate error location information EPI according to each programmed state based on the multiple read data via a scheme similar to the above scheme.

[0063] Next, referring to FIGS. 1 and 7, the error location manager 112 of the memory controller 110 can generate error location information EPI based on the ECC decoding result of the ECC engine 111.

[0064] For example, the ECC engine 111 may include an ECC encoder 112a and an ECC decoder 112b. The ECC encoder 112a may perform ECC encoding on the first data DT1 for storage in the memory device 120 to generate ECC data DT_ECC. The ECC data DT_ECC may be stored in the memory device 120 together with the first data DT1. The ECC decoder 112b may perform ECC decoding based on the first stored data DT1_s and the ECC data DT_ECC read from the memory device 120. Errors in the first stored data DT1_s may be detected and corrected via ECC decoding.

[0065] In this case, the error location manager 112 may receive error data ER regarding the detected error from the ECC decoder 112b of the ECC engine 111. The error location manager 112 may generate error location information EPI based on the error data ER.

[0066] In some example embodiments, the error location information EPI is information indicating the location where the corresponding data has an error or the location of the memory cell where the error occurs. That is, it can be understood that the error location information EPI of the present disclosure is a component significantly different from the ECC data or the parity bits generated by the ECC engine 111.

[0067] As described above, the error location manager 112 of the memory controller 110 may be configured to generate error location information by extracting the error location of the data stored in the memory device 120 via various schemes. In some example embodiments, the error location information EPI may be information directly indicating the location of the error occurring in the data stored in the memory device 120, the location of the bit where the error occurs, or the location of the memory cell where the error occurs, and may be a component different from the ECC data or the parity data used to correct data errors.

[0068] FIG. 8 is a block diagram showing the memory device of FIG. 1. FIG. 9 is a diagram for depicting the error location information extraction operation of the memory device of FIG. 8. In some example embodiments described with reference to FIGS. 5 to 7, the error location information EPI may be extracted depending on the operation and control of the memory controller 110. However, the present disclosure is not limited thereto. For example, the error location information EPI may be extracted in the memory device 120 and the memory controller 110 may be configured to collect and manage the error location information EPI extracted by the memory device 120.

[0069] Referring to FIGS. 1, 8, and 9, the memory device 120 may include a memory cell array 121, an address decoder 122, control logic and a voltage generation circuit (hereinafter referred to as "control logic circuit") 123, a page buffer circuit 124, and an input / output circuit 125.

[0070] The memory cell array 121 may include a plurality of memory blocks. The structure of each of the plurality of memory blocks may be similar to the structure of the first memory block BLK1 described with reference to FIG. 2.

[0071] The address decoder 122 may be connected to the memory cell array 121 via a string select line SSL, a word line WL, and a ground select line GSL. The address decoder 122 may receive an address ADDR from the memory controller 110 and decode the address ADDR. The address decoder 122 may control the voltages of the string select line SSL, the word line WL, and the ground select line GSL based on the decoding result.

[0072] The control logic circuit 123 may generate various operating voltages necessary for the operation of the memory device 120. For example, the various operating voltages may include a plurality of programming voltages, a plurality of verification voltages, a plurality of pass voltages, a plurality of select read voltages, a plurality of non-select read voltages, a plurality of erase voltages, and similar voltages. The control logic circuit 123 may receive a command CMD and control logic CTRL from the memory controller 110, and may control the components of the memory device 120 based on the received signals.

[0073] The page buffer circuit 124 may be connected to the memory cell array 121 via a bit line BL. The page buffer circuit 124 may temporarily store data read from the memory cell array 121 or data to be stored in the memory cell array 121. For example, the page buffer circuit 124 may read data from the memory cell array 121 via the bit line BL or may store data in the memory cell array 121 via the bit line BL.

[0074] The input / output circuit 125 may exchange data "DATA" with the memory controller 110. The input / output circuit 125 may provide the data "DATA" received from the memory controller 110 to the page buffer circuit 124 via a data line DL, or may receive the data "DATA" to be transmitted to the memory controller 110 from the page buffer circuit 124 via the data line DL.

[0075] In some example embodiments, the memory device 120 may further include an error position information extractor 126. The error position information extractor 126 may be configured to extract error position information EPI that indicates an error position of data stored in the memory cell array 121.

[0076] For example, as shown in FIG. 9, under the control of the memory controller 110, the memory device 120 may program the first data DT1 (operation ① in FIG. 9) at the fifth word line WL5 (or in the memory cells of the fifth word line WL5) of the first memory block BLK1 of the memory cell array 121. In this case, as described above, the first stored data DT1_s programmed at the fifth word line WL5 may include an error.

[0077] After completing the programming operation associated with the first data DT1, the memory device 120 may read the first stored data DT1_s from the fifth word line WL5 (or from the memory cells of the fifth word line WL5). The error position information extractor 126 of the memory device 120 may generate error data ER by comparing the first stored data DT1_s with the first data DT1. The error position information extractor 126 may generate error position information EPI based on the error data ER. The operation of the error position information extractor 126 is similar to the operation of the error position manager 112 described with reference to FIG. 5, and thus additional description will be omitted to avoid redundancy.

[0078] As described above, after performing a programming operation for each page or word line, the memory device 120 may extract error position information EPI by reading the programmed data and comparing the read data with the original data.

[0079] In some example embodiments of FIGS. 8 and 9, a configuration in which the memory device 120 further includes an error position information extractor 126 is described, but the present disclosure is not limited thereto. For example, the memory device 120 may perform a comparison operation (e.g., an XOR operation) on the first data DT1 and the first stored data DT1_s by using the page buffer circuit 124, and may extract error position information EPI based on the result of the comparison operation.

[0080] In some example embodiments of FIGS. 8 and 9, a configuration in which the memory device 120 extracts error position information EPI by comparing original data with stored data is described, but the present disclosure is not limited thereto. For example, the memory device 120 may repeatedly perform a read operation on the first stored data DT1_s by using multiple read voltages. The memory device 120 may detect the positions of memory cells (e.g., degraded memory cells) belonging to a tail region of a threshold voltage distribution of each programmed state (refer to FIG. 6). The memory device 120 may generate error position information EPI based on the detected positions of the memory cells.

[0081] In some example embodiments, the error position information EPI generated by the memory device 120 may be provided to the memory controller 110 via various schemes. For example, the memory device 120 may perform a programming operation in response to a programming command received from the memory controller 110. After completing the programming operation, the memory controller 110 may check whether the programming operation of the memory device 120 is completed via a status read operation. In some example embodiments, the error position information EPI may be provided from the memory device 120 to the memory controller 110 via a status read operation for checking whether the programming operation of the memory device 120 is completed. Alternatively, the memory device 120 may generate the error position information EPI in response to an explicit request (or a separate command) from the memory controller 110 and may provide the error position information EPI to the memory controller 110.

[0082] As described above, the error position information EPI may be generated by the memory controller 110 or the memory device 120. The above operations of extracting the error position information EPI are examples for easily describing example embodiments of the present disclosure, and the present disclosure is not limited thereto.

[0083] FIGS. 10A to 10D are diagrams for depicting error position extraction time points according to some example embodiments of the present disclosure. In some example embodiments, the error position information EPI may indicate an error position of programmed data in the memory device 120 or a position corresponding to an error memory cell. The error position information EPI may be extracted immediately after the data is programmed, after a given time has elapsed from the time point when the data is programmed, or after performing the programming operation up to a specific cell.

[0084] In some example embodiments, the time point when data is programmed can be identified via status information read from the memory device 120. For example, the memory controller 110 can transfer a program command, an address, and data to the memory device 120 for the purpose of programming data in the memory device 120, and the memory device 120 can perform a program operation in response to the program command. When the program operation of the memory device 120 is completed, the memory controller 110 can transfer a status read command to the memory device 120, and the memory device 120 can transfer information regarding whether the program operation is completed as status information. Via the status read operation described above, the memory controller 110 can check whether the program operation of the memory device 120 is completed.

[0085] Hereinafter, in order to easily describe the time point of extracting error position information EPI, it is assumed that the memory controller 110 programs data in the memory device 120 and extracts error position information EPI from the memory device 120. However, the present disclosure is not limited thereto. For example, the operation of extracting error position information EPI can be automatically performed in the memory device 120 or can be performed in the memory device 120 under the control of the memory controller 110. Hereinafter, the error position information extraction operation can be performed based on at least one of the operation methods described with reference to FIGS. 1 to 9.

[0086] For example, referring to FIGS. 1, 2, 10A, 10B, 10C, and 10D, the memory device 120 can perform a program operation in units of word lines under the control of the memory controller 110. For example, under the control of the memory controller 110, the memory device 120 can sequentially perform program operations on the first word line WL1 to the eighth word line WL8 of the first memory block BLK1. In this case, the memory device 120 can perform the program operation in the order from the uppermost word line to the lowermost word line (e.g., WL8 → WL7 → WL6 → WL5 → WL4 → WL3 → WL2 → WL1). In some example embodiments, the programming sequence of the word lines can be controlled by the memory controller 110 based on the physical characteristics of the memory device 120, and it is understood that the present disclosure is not limited to the shown programming sequence.

[0087] First, the memory controller 110 can repeatedly perform a programming operation and an error position information extraction operation in units of word lines. For example, as shown in FIG. 10A, the memory controller 110 can perform a programming operation on the eighth word line WL8 of the first memory block BLK1 (refer to operation [1] in FIG. 10A). Subsequently, the memory controller 110 can perform an error position information extraction operation on the eighth word line WL8 of the first memory block BLK1 (refer to operation [2] in FIG. 10A). Next, the memory controller 110 can perform a programming operation on the seventh word line WL7 (refer to operation [3] in FIG. 10A). Subsequently, the memory controller 110 can perform an error position information extraction operation on the seventh word line WL7 (refer to operation [4] in FIG. 10A).

[0088] Similarly, the memory controller 110 can perform a pair of programming operations and error position information extraction operations (hereinafter referred to as operation pair ([x], [y])) on each of the sixth word line WL6 to the first word line WL1, that is, can sequentially perform operation pair ([5], [6]), operation pair ([7], [8]), operation pair ([9],

[10] ), operation pair (

[11] ,

[12] ), operation pair (

[13] ,

[14] ), and operation pair (

[15] ,

[16] ) on the sixth word line WL6 to the first word line WL1. That is, when the memory controller 110 performs a programming operation and an error position information extraction operation in units of word lines, the memory controller 110 can immediately perform an error position information extraction operation on the target word line after performing a programming operation on the target word line.

[0089] Alternatively, when the memory controller 110 repeatedly performs the program operation and the error position information extraction operation in units of word lines, the memory controller 110 may perform the error position information extraction operation on the target word line after performing the program operation on the adjacent word line of the target word line. For example, as shown in FIG. 10B, the memory controller 110 may perform a program operation on the eighth word line WL8 (refer to operation [1] in FIG. 10B). Then, the memory controller 110 may perform a program operation on the seventh word line WL7 (refer to operation [2] in FIG. 10B). Then, the memory controller 110 may perform an error position information extraction operation on the eighth word line WL8 (refer to operation [3] in FIG. 10B). Subsequently, the memory controller 110 may perform a program operation on the sixth word line WL6 (refer to operation [4] in FIG. 10B). Subsequently, the memory controller 110 may perform an error position information extraction operation on the seventh word line WL7 (refer to operation [5] in FIG. 10B). Similarly, with respect to each of the fifth word line WL5 to the first word line WL1, the memory controller 110 may perform a program operation (refer to operation [6], operation [8], operation

[10] , operation

[12] , or operation

[14] in FIG. 10B), and may perform an error position information extraction operation after completing the program operation on the adjacent word line (refer to operation [7], operation [9], operation

[11] , operation

[13] , operation

[15] , or operation

[16] in FIG. 10B).

[0090] As described above, when the memory controller 110 alternately performs the program operation and the error position information extraction operation in units of word lines, the error position information extraction operation may be performed at various time points: immediately after completing the program operation, after a given time has elapsed from the time point of completing the program operation, and after completing the program operation on the adjacent word line.

[0091] Alternatively, the memory controller 110 may perform an error location information extraction operation after executing a program operation up to a given unit. For example, as shown in FIG. 10C, the memory controller 110 may perform a program operation on the eighth word line WL8 to the fifth word line WL5 of the first memory block BLK1 (refer to operation [1] in FIG. 10C). In some example embodiments, the memory controller 110 may perform a program operation on the eighth word line WL8 to the fifth word line WL5 in units of pages or word lines. Then, the memory controller 110 may perform an error location information extraction operation on the eighth word line WL8 to the fifth word line WL5 (refer to operation [2] in FIG. 10C). In some example embodiments, the memory controller 110 may perform an error location information extraction operation on the eighth word line WL8 to the fifth word line WL5 in units of pages or word lines. Similarly, the memory controller 110 may perform a program operation on the fourth word line WL4 to the first word line WL1 (refer to operation [3] in FIG. 10C) and may then perform an error location information extraction operation on the fourth word line WL4 to the first word line WL1 (refer to operation [4] in FIG. 10C).

[0092] In some example embodiments, the word line region or sub-block including the eighth word line WL8 to the fifth word line WL5 may be different from the word line region or sub-block including the fourth word line WL4 to the first word line WL1. That is, the memory controller 110 may repeatedly perform a program operation and an error location information extraction operation in units of word line regions, sub-blocks, or word lines, and determine in advance the number of word line regions, sub-blocks, or word lines.

[0093] Alternatively, the memory controller 110 may perform an error location information extraction operation after performing a program operation in units of memory blocks. For example, as shown in FIG. 10D, the memory controller 110 may perform a program operation on the first memory block BLK1 (refer to operation [1] in FIG. 10D). In some example embodiments, the program operation associated with the first memory block BLK1 may be performed in units of word lines. Subsequently, the memory controller 110 may perform an error location information extraction operation on the first memory block BLK1 (refer to operation [2] in FIG. 10D). In some example embodiments, the error location information extraction operation associated with the first memory block BLK1 may be performed in units of word lines.

[0094] FIGS. 11A to 11D are diagrams for describing operations of programming error location information in a memory device. For the sake of brevity of the diagrams and convenience of description, components unnecessary for the error location information EPI in the programmed memory device 120 are omitted.

[0095] In the following, for ease of description, this specification will give an example of extracting error position information EPI in units of memory blocks, but the present disclosure is not limited thereto. For example, similar to some exemplary embodiments described with reference to FIGS. 10A to 10D, error position information EPI can be extracted at various time points in units of word lines or pages.

[0096] As described with reference to FIGS. 10A to 10D, the memory controller 110 can instantaneously extract error position information EPI associated with data stored in the memory device 120 at various operating points. In some exemplary embodiments, the extracted error position information EPI can be collected by a given unit. For example, one page of data stored in the memory device 120 can be 8 kilobytes. 2-byte information may be required to express the position of an error occurring in the 8KB data. A page (e.g., a page of 8KB size) can contain error position information EPI associated with 4K errors, and the error position information EPI associated with the 4K errors can be programmed in the memory device 120 via a program operation. That is, the memory controller 110 can collect error position information EPI associated with multiple errors up to a given size included in multiple pages or multiple word lines and can program the collected error position information EPI in the memory device 120.

[0097] Specifically, as shown in FIG. 11A, the memory controller 110 can perform a program operation on the eighth word line WL8 to the first word line WL1 of the first memory block BLK1 and can perform an error position information extraction operation. The error position information EPI associated with the first memory block BLK1 can be collected by the memory controller 110. The collected error position information EPI can be programmed at the first dummy word line DWL1 or the second dummy word line DWL2 of the first memory block BLK1.

[0098] In some exemplary embodiments, as described with reference to FIG. 2, the first memory block BLK1 can include a first dummy memory cell DMC1 and a second dummy memory cell DMC2 connected to the first dummy word line DWL1 and the second dummy word line DWL2. In some exemplary embodiments, the first dummy memory cell DMC1 and the second dummy memory cell DMC2 can be memory cells that are not used to store user data and can be provided for the reliability of the first memory block BLK1. According to some exemplary embodiments of the present disclosure, the error position information EPI can be programmed in the first dummy memory cell DMC1 and the second dummy memory cell DMC2.

[0099] Alternatively, as shown in FIG. 11B, the memory controller 110 may program the error position information EPI at the edge word lines (e.g., the eighth word line WL8 and the first word line WL1) of the first memory block BLK1. In some example embodiments, among the word lines WL1 to WL8 included in the first memory block BLK1, the eighth word line WL8 that is physically closest to the bit line BL may be the uppermost word line, and the first word line WL1 that is physically closest to the common source line CSL among the word lines WL1 to WL8 may be the lowermost word line. To improve the reliability of the data stored in the first memory block BLK1, each of the memory cells connected to the uppermost word line and the lowermost word line may be configured to store a relatively small number of bits depending on the physical characteristics of the first memory block BLK1. For example, the memory cells included in the first memory block BLK1 may operate as TLC. In this case, the memory cells connected to the uppermost word line and the lowermost word line among the memory cells of the first memory block BLK1 may operate as SLC or MLC.

[0100] In this case, the memory controller 110 may program the user data at the seventh word line WL7 to the second word line WL2 of the first memory block BLK1, and may program the error position information EPI at the eighth word line WL8 or the first word line WL1.

[0101] That is, as described above, the memory controller 110 may program the error position information EPI of a specific memory block at the dummy word line of the specific memory block or at the uppermost word line and the lowermost word line of the specific memory block. In some example embodiments, the number of bits in each of the memory cells in which the error position information EPI is programmed may be less than the number of bits in each of the memory cells in which the user data is programmed.

[0102] Alternatively, as shown in FIG. 11C, the memory controller 110 may program the first error position information EPI1 of the first memory block BLK1 at the uppermost word line WL8 of a second memory block BLK2 different from the first memory block BLK1. In some example embodiments, the second memory block BLK2 may be a memory block allocated after the first memory block BLK1. Although not shown in FIG. 11C, the second error position information EPI2 of the second memory block BLK2 may be programmed at the uppermost word line of any other memory block allocated after the second memory block BLK2. In some example embodiments, the uppermost word line in FIG. 11C may be replaced by the lowermost word line (e.g., WL1) or a dummy word line.

[0103] Alternatively, as shown in FIG. 11D, the memory controller 110 may retrieve and collect first error position information EPI1, second error position information EPI2, and third error position information EPI3 of the first memory block BLK1, the second memory block BLK2, and the third memory block BLK3. The memory controller 110 may program the first error position information EPI1, the second error position information EPI2, and the third error position information EPI3 at a separate memory block BLKa. In some example embodiments, the memory cells of the first memory block BLK1, the second memory block BLK2, and the third memory block BLK3 may operate as TLC, and the memory cells of the separate memory block BLKa may operate as SLC.

[0104] As described with reference to FIGS. 11A to 11D, the memory controller 110 may collect multiple error position information EPIs and may program the multiple error position information EPIs collected at a specific area of the memory device 120 accordingly. In this case, one error position information EPI may be information indicating the position of an error occurring at the page unit or data of a given size. That is, the size of one error position information EPI may be smaller than the size of one page. The multiple error position information EPIs may have the same size as one page or may have the same size as the programming unit of the memory device 120.

[0105] In some example embodiments, the memory controller 110 may compress the multiple error position information EPIs and may program the compressed data in the memory device 120. In this case, the amount of error position information EPI stored in the memory device 120 by using the same number of memory cells may be increased. Alternatively, via the ECC encoder 112a of the ECC engine 111, the memory controller 110 may compress the error position information EPI by generating a parity related to the error position information EPI.

[0106] FIG. 12 is a diagram for describing the read operation of FIG. 4. In some example embodiments, the memory controller 110 may store the error position information EPI regarding the data stored in the memory device 120 in the memory device 120 based on some example embodiments described above. The memory controller 110 may perform a read operation or an ECC decoding operation by using the error position information EPI.

[0107] For example, as shown in FIG. 12, the memory controller 110 may read the first stored data DT1_s and the error position information EPI from the memory device 120. In some example embodiments, the first read operation for reading the first stored data DT1_s and the second read operation for reading the error position information EPI may be different from each other. For example, the memory controller 110 may read the first stored data DT1_s from the memory device 120 by transmitting a first address and a read command to the memory device 120, and may read the error position information EPI from the memory device 120 by transmitting a second address and a read command to the memory device 120.

[0108] The error position manager 112 of the memory controller 110 may generate refined data DT_rf based on the first stored data DT1_s and the error position information EPI. For example, as described above, the error position information EPI may indicate the position of an error included in the first stored data DT1_s. That is, the error position manager 112 may identify the error position of the first stored data DT1_s based on the error position information EPI, and may generate the refined data DT_rf by inverting the bit value corresponding to the error position information EPI (e.g., 0 → 1 or 1 → 0). In some example embodiments, the refined data DT_rf may include a relatively smaller number of errors compared to the first stored data DT1_s. The ECC engine 111 of the memory controller 110 may perform ECC decoding based on the refined data DT_rf and may generate corrected data DT_cor.

[0109] In some example embodiments, in a case where the ECC engine 111 of the memory controller 110 cannot correct an error of the first stored data DT1_s via an ECC decoding operation associated with the first stored data DT1_s, the error correction operation described with reference to FIG. 12 may be performed. That is, since a part of the error of the first stored data DT1_s is refined based on the error position information EPI, the error included in the refined data DT_rf may be corrected by the ECC engine 111. Therefore, the reliability of the memory system is improved.

[0110] In some example embodiments, the ECC engine 111 may correct errors by using coding modulation such as low density parity check (LDPC) codes, Bose - Chaudhuri - Hocquenghem (BCH) codes, turbo codes, Reed - Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis - coded modulation (TCM), or block - coded modulation (BCM), or various other schemes. [

[0111] ]FIG. 13 and FIG. 14 are diagrams for describing operations for generating refined data. For simplicity of the diagrams and convenience of description, components that are not necessary for the error location manager 112 of the memory controller 110 to generate the refined data DT_rf are omitted. However, the present disclosure is not limited thereto. For example, the operations for generating the refined data DT_rf to be described with reference to FIGS. 13 and 14 may be performed after the first ECC decoding by the memory controller 110 fails. [

[0112] ]In some example embodiments, the refined data DT_rf may be generated by inverting bits among the following data that correspond to the error position information EPI: hard decision data, soft decision data, or target data read from the memory device 120. [

[0113] ]Referring to FIGS. 1, 13, and 14, due to various factors, an error may additionally occur in the first stored data DT1_s stored in the memory device 120. In this case, the first stored data DT1_s' including the additional error may be maintained in the memory device 120. For example, the original data stored in the memory device 120 may have a bit string "10011001". The first stored data DT1_s actually stored in the memory device 120 may have a bit string "10001001". In this case, the fifth bit from the LSB may be an error, and the error position information EPI may have a value "101" indicating the fifth position from the LSB. After storing the first stored data DT1_s, an error may occur in the second bit from the LSB due to various factors. In this case, the first stored data DT1_s' including the additional error may have a bit string "10001011". [

[0114] ]In some example embodiments, the memory controller 110 may correct a part of an error in the hard decision data or the target data read from the memory device 120 based on the error position information EPI. [

[0115] ]For example, as shown in FIG. 13, the memory controller 110 may read the first stored data DT1_s' from the memory device 120. The memory controller 110 may read the error position information EPI corresponding to the first stored data DT1_s' from the memory device 120. In some example embodiments, the read operation for reading the first stored data DT1_s' and the read operation for reading the error position information EPI may be different from each other.

[0116] The error location manager 112 of the memory controller 110 may generate error data ER based on error location information EPI. The error data ER may have a bit string "00010000" indicating that the fifth bit from the LSB is in error. The error location manager 112 may generate refined first data DT1_rf by comparing the first stored data DT1_s' with the error data ER (e.g., performing an exclusive OR operation on the first stored data DT1_s' and the error data ER). In this case, the refined first data DT1_rf may have a bit string "10011011". That is, in the case of the refined first data DT1_rf, compared with the original data, the error corresponding to the position of the error location information EPI can be corrected.

[0117] In some example embodiments, in the case of the refined first data DT1_rf, the error can be corrected via an ECC decoding operation of the ECC engine 111 in the memory controller 110. For example, assume that the ECC engine 111 is capable of correcting a 1-bit error. In this case, since the first stored data DT1_s' contains a 2-bit error, the error of the first stored data DT1_s' may not be corrected by the ECC engine 111. In contrast, since the refined first data DT1_rf contains a 1-bit error, the error of the refined first data DT1_rf can be corrected by the ECC engine 111. That is, the memory controller 110 may generate refined data by correcting a part of the error of the data read from the memory device 120 based on the error location information EPI corresponding to the read data, and may perform ECC decoding based on the refined data, and thus can ensure the reliability of the data.

[0118] In some example embodiments, the memory controller 110 may change the value of at least one of the bits of the soft decision data read from the memory device 120 based on the error location information EPI. For example, as shown in FIG. 14, via a soft decision read operation, the memory controller 110 may read a plurality of soft decision data DT1_SD associated with the first stored data DT1_s' from the memory device 120. In some example embodiments, the soft decision read operation may include repeatedly performing a read operation on the same word line or the same page by using a plurality of read voltages, so as to generate a plurality of soft decision data DT1_SD.

[0119] The memory controller 110 can read the error position information EPI from the memory device 120. The error position manager 112 of the memory controller 110 can generate error data ER based on the error position information EPI. The error position manager 112 can refine at least one of the multiple soft decision data DT1_SD based on the error data ER, and can generate refined soft decision data DT1_SD_rf. The refined soft decision data DT1_SD_rf can be provided to the ECC engine 111, and the ECC engine 111 can perform soft decision decoding based on the refined soft decision data DT1_SD_rf.

[0120] FIG. 15 is a block diagram of a host storage system 1000 according to an example embodiment. Referring to FIG. 15, the host storage system 1000 can include a host 1100 and a storage device 1200. In addition, the storage device 1200 can include a storage controller 1210 and an NVM 1220. According to an example embodiment, the host 1100 can include a host controller 1110 and a host memory 1120. The host memory 1120 can act as a buffer memory configured to temporarily store data to be transmitted to the storage device 1200 or data received from the storage device 1200.

[0121] The storage device 1200 can include a storage medium configured to store data in response to requests from the host 1100. As an example, the storage device 1200 can include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 1200 is an SSD, the storage device 1200 can be a device compliant with the NVMe standard. When the storage device 1200 is an embedded memory or an external memory, the storage device 1200 can be a device compliant with the UFS standard or the eMMC standard. Each of the host 1100 and the storage device 1200 can generate and transmit packets according to the standard protocol adopted.

[0122] When the NVM 1220 of the storage device 1200 includes flash memory, the flash memory can include a 12D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 1200 can include various other types of NVM. For example, the storage device 1200 can include magnetic RAM (MRAM), spin torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FRAM), PRAM, RRAM, and various other types of memory.

[0123] According to an embodiment, the host controller 1110 and the host memory 1120 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 1110 and the host memory 1120 may be integrated in the same semiconductor chip. As an example, the host controller 1110 may be any one of a plurality of modules included in an application processor (AP). The AP may be implemented as a System on Chip (SoC). In addition, the host memory 1120 may be an embedded memory included in the AP or a non-volatile memory (NVM) or a memory module located outside the AP.

[0124] The host controller 1110 may manage an operation of storing data (e.g., write data) in a buffer area of the host memory 1120 in the NVM 1220 or an operation of storing data (e.g., read data) in the NVM 1220 in the buffer area.

[0125] The storage controller 1210 may include a host interface 1211, a memory interface 1212, and a CPU 1213. In addition, the storage controller 1210 may further include a flash translation layer (FTL) 1214, a packet manager 1215, a buffer memory 1216, an error correction code (ECC) engine 1217, and an advanced encryption standard (AES) engine 1218. The storage controller 1210 may further include a working memory (not shown) in which the FTL 1214 is loaded. The CPU 1213 may execute the FTL 1214 to control data write and read operations to / from the NVM 1220.

[0126] The host interface 1211 may transmit a packet to the host 100 and receive a packet from the host 100. A packet transmitted from the host 1100 to the host interface 1211 may include a command or data to be written in the NVM 1220. A packet transmitted from the host interface 1211 to the host 1100 may include a response to a command or data read from the NVM 1220. The memory interface 1212 may transmit data to be written into the NVM 1220 to the NVM 1220 or receive data read from the NVM 1220. The memory interface 1212 may be configured to comply with a standard protocol such as a bi-state trigger or an Open NAND Flash Interface (ONFI).

[0127] The FTL 1214 can perform various functions, such as address mapping operations, wear leveling operations, and garbage collection operations. The address mapping operation can be an operation of converting a logical address received from the host 1100 into a physical address for actually storing data in the NVM 1220. The wear leveling operation can be a technique for preventing excessive degradation of a specific block by uniformly using the blocks of the NVM 1220. As an example, the wear leveling operation can be implemented using a firmware technique that balances the erase counts of physical blocks. The garbage collection operation can be a technique for ensuring the available capacity in the NVM 1220 by copying the valid data of an existing block to a new block and then erasing the existing block.

[0128] The packet manager 1215 can generate packets according to the protocol of the interface negotiated with the host 1100, or parse various types of information from the packets received from the host 100. In addition, the buffer memory 1216 can temporarily store data to be written into the NVM 1220 or data to be read from the NVM 1220. Although the buffer memory 1216 can be a component included in the storage controller 1210, the buffer memory 1216 can be located outside the storage controller 1210.

[0129] The ECC engine 1217 can perform error detection and correction operations on the read data read from the NVM 1220. More specifically, the ECC engine 1217 can generate parity bits for the write data to be written into the NVM 1220, and the generated parity bits can be stored in the NVM 1220 together with the write data. During the period of reading data from the NVM 1220, the ECC engine 1217 can correct the errors in the read data by using the parity bits read from the NVM 1220 and the read data, and output the error-corrected read data.

[0130] The AES engine 1218 can perform at least one of an encryption operation and a decryption operation on the data input to the storage controller 1210 by using a symmetric key algorithm.

[0131] In some example embodiments, the storage controller 1210 can extract error position information EPI about the data stored in the non-volatile memory device 1220 based on the operation methods described with reference to FIGS. 1 to 14, can store the extracted error position information EPI in the non-volatile memory device 1220, and can refine the data read from the non-volatile memory device 1220 by using the error position information EPI.

[0132] In some example embodiments, in the storage controller 1210, the area in which the error position information EPI is stored can be managed by the flash translation layer 1214.

[0133] FIG. 16 is a diagram of a system 2000 of an application storage device according to some example embodiments. The system 2000 of FIG. 16 may be substantially a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a medical device, or an Internet of Things (IoT) device. However, the system 2000 of FIG. 16 is not necessarily limited to a mobile system and may be a PC, a laptop, a server, a media player, or an automotive device (e.g., a navigation device).

[0134] Referring to FIG. 16, the system 2000 may include a main processor 2100, memories (e.g., memory 2200a and memory 2200b), and storage devices (e.g., storage device 2300a and storage device 2300b). Additionally, the system 2000 may include at least one of an image capture device 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power supply device 2470, and a connection interface 2480.

[0135] The main processor 2100 may control all operations of the system 2000, and more specifically, the operations of other components included in the system 2000. The main processor 2100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0136] The main processor 2100 may include at least one CPU core 2110, and further include a controller 2120 configured to control the memory 2200a and the memory 2200b and / or the storage device 2300a and the storage device 2300b. In some example embodiments, the main processor 2100 may further include an accelerator 2130, which is a dedicated circuit for high-speed data operations, such as artificial intelligence (AI) data operations. The accelerator 2130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and is implemented as a chip physically separated from other components of the main processor 2100.

[0137] Memory 2200a and memory 2200b can be used as the main memory devices of system 2000. Although each of memory 2200a and memory 2200b may include volatile memory, such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memory 2200a and memory 2200b may include non-volatile memory, such as flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM). Memory 2200a and memory 2200b may be implemented in the same package as main processor 2100.

[0138] Storage devices 2300a and 2300b can serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than memory 2200a and memory 2200b. Storage devices 2300a and 2300b may respectively include storage controllers (STRG CTRL) 2310a and 2310b configured to store data under the control of storage controllers 2310a and 2310b, and non-volatile memory (Non-Volatile Memory; NVM) 2320a and non-volatile memory 2320b. Although NVM 2320a and NVM 2320b may include flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, NVM 2320a and NVM 2320b may include other types of NVM, such as PRAM and / or RRAM.

[0139] The storage devices 2300a and 2300b can be physically separated from the main processor 2100 and be included in the system 2000 or implemented in the same package as the main processor 2100. Additionally, the storage devices 2300a and 2300b can be of the type of solid-state device (SSD) or memory card, and be detachably combined with other components of the system 200 via an interface (such as the connection interface 2480 to be described below). The storage devices 2300a and 2300b can be devices that apply standard protocols, such as universal flash storage (UFS), embedded multi-media (eMMC), or non-volatile memory express (NVMe), but are not limited thereto.

[0140] In some example embodiments, the storage devices 2300a and 2300b can be the memory systems or storage devices described with reference to FIGS. 2 to 25. The storage devices 2300a and 2300b can operate based on the operation methods described with reference to FIGS. 2 to 25.

[0141] The image capture device 2410 can capture still images or moving images. The image capture device 2410 can include a camera, a camcorder, and / or a webcam.

[0142] The user input device 2420 can receive various types of data input by the user of the system 2000, and includes a touchpad, a keypad, a keyboard, a mouse, and / or a microphone.

[0143] The sensor 2430 can detect various types of physical quantities that can be obtained from outside the system 2000, and convert the detected physical quantities into electrical signals. The sensor 2430 can include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0144] The communication device 2440 can transmit and receive signals between other devices outside the system 2000 according to various communication protocols. The communication device 2440 can include an antenna, a transceiver, and / or a modem.

[0145] The display 2450 and the speaker 2460 can serve as output devices configured to output visual information and auditory information to the user of the system 2000, respectively.

[0146] The power supply device 2470 can appropriately convert the power from a battery (not shown) embedded in the system 2000 and / or an external power supply, and supply the converted power to each of the components of the system 2000.

[0147] The connection interface 2480 can provide a connection between the system 2000 and an external device that is connected to the system 2000 and capable of transmitting data to and receiving data from the system 2000. The connection interface 2480 can be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE 2394, universal serial bus (USB) interface, secure digital (SD) card interface, multi-media card (MMC) interface, eMMC interface, UFS interface, embedded UFS (eUFS) interface, and compact flash (CF) card interface.

[0148] FIG. 17 is a diagram of a data center 3000 that applies a memory device according to some example embodiments. Referring to FIG. 17, the data center 3000 can be a device that collects various types of data fragments and provides services and is referred to as a data storage center. The data center 3000 can be a system for operating a search engine and a database, and can be a computing system used by a company such as a bank or a government agency. The data center 3000 can include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m can be differently selected according to the example embodiments. The number of application servers 3100 to 3100n can be different from the number of storage servers 3200 to 3200m.

[0149] The application server 3100 or the storage server 3200 may include at least one of a processor 3110 and a processor 3210, and a memory 3120 and a memory 3220. Hereinafter, the storage server 3200 will be described as an example. The processor 3210 may control all operations of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded in the memory 3220. The memory 3220 may be a double-data-rate synchronous DRAM (DDR SDRAM), a high-bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, and / or a non-volatile DIMM (NVMDIMM). In some example embodiments, the number of the processor 3210 and the memory 3220 included in the storage server 3200 may be selected differently. In some example embodiments, the processor 3210 and the memory 3220 may provide a processor-memory pair. In some example embodiments, the number of the processor 3210 may be different from the number of the memory 3220. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. In some example embodiments, the application server 3100 may not include a storage device 3150. The storage server 3200 may include at least one storage device 3250. The number of the storage devices 3250 included in the storage server 3200 may be selected differently according to some example embodiments.

[0150] The application servers 3100 to 3100n may communicate with the storage servers 3200 to 3200m via a network 3300. The network 3300 may be implemented by using a fiber channel (FC) or Ethernet. In this case, the FC may be a medium for relatively high-speed data transmission and use an optical switch with high performance and high availability. The storage servers 3200 to 3200m may be provided as a file storage, a block storage, or an object storage according to the access method of the network 3300.

[0151] In some example embodiments, network 3300 may be a storage-exclusive network such as a storage area network (SAN). For example, the SAN may be a Fibre Channel SAN (FC-SAN) using a Fibre Channel (FC) network and implemented according to the Fibre Channel Protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN using a Transmission Control Protocol (TCP) / IP network and implemented according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In some example embodiments, network 3300 may be a general network, such as a TCP / IP network. For example, network 3300 may be implemented according to protocols such as Fibre Channel over Ethernet (FCoE), network attached storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0152] Hereinafter, application server 3100 and storage server 3200 will be mainly described. The description of application server 3100 may be applicable to another application server 3100n, and the description of storage server 3200 may be applicable to another storage server 3200m.

[0153] Application server 3100 may store data requested by a user or client for storage in one of storage servers 3200 to 3200m via network 3300. In addition, application server 3100 may obtain data requested by a user or client for reading from one of storage servers 3200 to 3200m via network 3300. For example, application server 3100 may be implemented as a web server or a database management system (DBMS).

[0154] The application server 3100 can access the memory 3120n or the storage device 3150n included in another application server 3100n via the network 3300. Alternatively, the application server 3100 can access the memory 3220 to the memory 3220m or the storage device 3250 to the storage device 3250m included in the storage servers 3200 to the storage servers 3200m via the network 3300. Therefore, the application server 3100 can perform various operations on the data stored in the application servers 3100 to the application servers 3100n and / or the storage servers 3200 to the storage servers 3200m. For example, the application server 3100 can execute instructions for moving data or copying data between the application servers 3100 to the application servers 3100n and / or the storage servers 3200 to the storage servers 3200m. In this case, the data can be moved from the storage devices 3250 to the storage devices 3250m of the storage servers 3200 to the storage servers 3200m to the memories 3120 to the memories 3120n of the application servers 3100 to the application servers 3100n directly or via the memories 3220 to the memories 3220m of the storage servers 3200 to the storage servers 3200m. The data moved via the network 3300 can be data encrypted for security or privacy.

[0155] Now, the storage server 3200 will be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented using a direct attached storage (DAS) scheme, where the storage device 3250 is directly connected to a dedicated cable. For example, the interface 3254 can be implemented by using various interface schemes, such as ATA, SATA, e - SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and / or CF card interface.

[0156] The storage server 3200 can further include a switch 3230 and a network interconnect (NIC) 3240. The switch 3230 can selectively connect the processor 3210 to the storage device 3250, or selectively connect the NIC 3240 to the storage device 3250 under the control of the processor 3210.

[0157] In some example embodiments, the NIC 3240 may include a network interface card and a network adapter. The NIC 3240 may be connected to the network 3300 via a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to the processor 3210 and / or the switch 3230 via the host bus interface. The host bus interface may be implemented as one of the examples described above for the interface 3254. In some example embodiments, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0158] Among the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may transmit commands to the storage devices 3150 to 3150n and the storage devices 3250 to 3250m or the memories 3120 to 3120n and the memories 3220 to 3220m and program or read data. In this case, the data may be data whose errors are corrected by an ECC engine. The data may be data that performs a data bus inversion (DBI) operation or a data masking (DM) operation, and may include cyclic redundancy code (CRC) information. The data may be data encrypted for security or privacy.

[0159] Storage devices 3150 to 3150n and storage devices 3250 to 3250m can transmit control signals and command / address signals to NAND flash memory devices 3252 to 3252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 3252 to 3252m, a read enable (RE) signal can be input as a data output control signal, and thus data can be output to the DQ bus. A data strobe signal DQS can be generated using the RE signal. Command and address signals can be latched in the page buffer depending on the rising edge or falling edge of a write enable (WE) signal. Controller 3251 can control all operations of storage device 3250. In some example embodiments, controller 3251 can include SRAM. Controller 3251 can write data to NAND flash memory device 3252 in response to a write command, or read data from NAND flash memory device 3252 in response to a read command. For example, write commands and / or read commands can be provided from processor 3210 of storage server 3200, processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. DRAM 3253 can temporarily store (e.g., buffer) data to be written to NAND flash memory device 3252 or data read from NAND flash memory device 3252. Additionally, DRAM 3253 can store metadata. Here, the metadata can be user data or data generated by controller 3251 to manage NAND flash memory device 3252. Storage device 3250 can include a secure element (SE) for security or privacy.

[0160] In some example embodiments, each of storage devices 3150 to 3150n and storage devices 3250 and 3250m can be the storage device described with reference to FIGS. 1 to 16, and can be configured to manage error location information based on the operation methods described with reference to FIGS. 1 to 16.

[0161] Memory controller 110, EPI manager 112, ECC engine 111, memory device 120, memory system 100, ECC decoder 112b, ECC encoder 112a, EPI management 112, memory cell array 121, logic control / voltage generation circuit 123, page buffer circuit 124, EPI extractor 126, I / O circuit 125, system 1000, storage device 1200, memory device 110, system 2000, main processor 2100, memories (e.g., memory 2200a and memory 2200b) and storage devices (e.g., storage device 2300a and storage device 2300b), image capture device 2410, user input device 2420, sensor 2430, communication device 2440, display 2450, speaker 2460, power supply 2470, and connection interface 2480, data center 3000, subcomponents or other circuits discussed herein) may include hardware including logic circuits; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0162] According to the present disclosure, the memory controller may retrieve error location information about data stored in the memory device and may store the retrieved error location information in the memory device. The memory controller may refine an error in reading data by using the error location information stored in the memory device and may perform an error correction operation on the refined data. In this case, the ability to correct errors in the data may be improved, and thus an operation method of the memory controller configured to control the memory device with improved reliability is provided.

[0163] When the present disclosure has been described with reference to the exemplary embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Brief Description of the Drawings

[0009] The above and other objects and features of the present disclosure will become more apparent by describing in detail examples thereof with reference to the accompanying drawings. FIG. 1 is a block diagram showing a memory system according to some example embodiments of the present disclosure. FIG. 2 is a diagram showing a first memory block of a plurality of memory blocks included in the memory device of FIG. 1. FIG. 3 is a diagram showing a threshold voltage distribution of the memory cells of FIG. 2. FIG. 4 is a flowchart showing the operation of the memory controller of FIG. 1. FIGS. 5 to 7 are diagrams for depicting the operation of the error position manager of FIG. 1. FIG. 8 is a block diagram showing the memory device of FIG. 1. FIG. 9 is a diagram for depicting the error position information extraction operation of the memory device of FIG. 8. FIGS. 10A to 10D are diagrams for depicting the error position extraction time points according to some example embodiments of the present disclosure. FIGS. 11A to 11D are diagrams for describing the operation of programming error position information in the memory device. FIG. 12 is a diagram for describing the read operation of FIG. 4. FIGS. 13 and 14 are diagrams for describing the operation of generating refined data. FIG. 15 is a diagram showing a system to which a memory system according to some example embodiments of the present disclosure is applied. FIG. 16 is a diagram showing a system to which a memory system according to some example embodiments of the present disclosure is applied. FIG. 17 is a diagram showing a data sensor of a memory device to which some example embodiments of the present disclosure are applied.

Claims

1. A method for operating a memory controller configured to control a memory device, the method comprising: The written data is stored in the first region of the memory device; The method involves: retrieving first error location information indicating the location of at least one error in data stored in the first region; storing the first error location information in a second region of the memory device; reading read data from the first region of the memory device; reading the first error location information from the second region of the memory device; refining the read data based on the first error location information to generate refined data; performing soft decision decoding based on the refined data to generate corrected data; and outputting the corrected data.

2. The method of operation as described in claim 1, wherein the acquisition of the first error location information comprises: reading data from the first region; comparing the read data with the written data to generate first error data; and generating the first error location information based on the first error data.

3. The method of operation as described in claim 1, wherein the acquisition of the first error location information comprises: reading a plurality of read data from the first region based on a plurality of read voltages; and generating the first error location information based on the plurality of read data.

4. The method of operation as described in claim 1, wherein the acquisition of the first error location information comprises: reading data from the first region; performing the soft decision decoding based on the read data to detect errors in the read data; and generating the first error location information based on the detected errors.

5. The method of operation as described in claim 1, wherein the retrieval of the first error location information is performed immediately after storing the written data in the first region of the memory device.

6. The method of operation as described in claim 1, wherein after a predetermined time has elapsed since the storage of the data written into the first region of the memory device, the retrieval of the first error location information is performed.

7. The method of operation as described in claim 1, wherein the first region corresponds to a first character line of a first memory block of the memory device, and wherein the retrieval of the first error location information is performed after completing a program operation associated with a character line adjacent to the first character line among a plurality of character lines of the first memory block.

8. The method of operation as described in claim 1, wherein the first region corresponds to a first character line of a first memory block of the memory device, and wherein the retrieval of the first error location information is performed after program operations associated with a plurality of character lines of the first memory block are completed.

9. The method of operation as described in claim 1, wherein the first region corresponds to a first character line of a first memory block of the memory device, wherein the second region corresponds to a second character line of the first memory block of the memory device, and wherein the second character line is the uppermost character line or the lowermost character line of the first memory block.

10. The method of operation as described in claim 9, wherein each of the memory cells connected to the first character line stores n bits, where n is a natural number greater than 2, and wherein each of the memory cells connected to the second character line stores m bits, where m is a natural number less than n.

11. The method of operation as described in claim 1, wherein the first region corresponds to a first character line of a first memory block of the memory device, and wherein the second region corresponds to a second character line of a second memory block of the memory device.

12. A method of operating a memory controller configured to control a memory device, the method comprising: The first program command, the first address, and the first write data are transmitted to the memory device, wherein the first address corresponds to the first character line of the memory device; The first read command and the first address are transmitted to the memory device to receive first read data from the memory device; the first read data is compared with the first write data to retrieve first error location information about the location of at least one error contained in the first read data; The second program command, the second address, and the first error location information are transmitted to the memory device, wherein the second address corresponds to the second character line of the memory device, and the second character line is different from the first character line of the memory device.

13. The operating method as described in claim 12 further includes: After the first program command, the first address, and the first write data transmission to the memory device, a status read command is transmitted to the memory device to receive status information from the memory device, wherein, based on the completion of the status information instruction program, the first read command and the transmission of the first address to the memory device are executed immediately after receiving the status information to receive the first read data from the memory device.

14. The operating method as described in claim 12 further includes: After the transmission of the first program command, the first address, and the first write data to the memory device, a third program command, a third address, and a second write data are transmitted to the memory device, wherein after the transmission of the third program command, the third address, and the second write data to the memory device, the first read command and the transmission of the first address to the memory device are executed to receive the first read data from the memory device.

15. The method of operation as described in claim 14, wherein the first character line and the second character line are contained in a first memory block of the memory device, wherein the third address corresponds to a third character line of the first memory block of the memory device, and wherein the first character line and the third character line are adjacent character lines, and the second character line is the uppermost or lowermost character line of the first memory block.

16. The operating method as described in claim 12 further includes: The second read command and the first address are transmitted to the memory device to receive the second read data from the memory device; The third read command and the second address are transmitted to the memory device to receive the first error location information from the memory device; the error of the second read data is refined based on the first error location information to generate refined data; and soft decision decoding is performed on the refined data to output corrected data.

17. A method of operating a memory controller configured to control a memory device, the method comprising: A first read operation is performed on a first region of the memory device to read first read data; Based on the error in the first read data, without correction via a first error correction operation for the first read data, perform multiple second read operations on the first region of the memory device to read multiple soft decision data; perform a second read operation on the second region of the memory device to read error location information; refine at least one of the multiple soft decision data based on the error location information to generate multiple refined soft decision data; and perform a second error correction operation on the multiple refined soft decision data to output corrected data.

18. The method of operation as described in claim 17, wherein the error location information indicates the location of at least one error contained in data stored in the first region of the memory device.

19. The operating method as described in claim 17 further includes: Prior to the execution of the first read operation, a first programming operation is performed on the first region of the memory device to store the first write data; Perform a third read operation on the first region of the memory device to read second read data; generate the error location information based on the second read data and the first write data; and perform a second program operation on the second region of the memory device to store the error location information.

20. The operating method as described in claim 17 further includes: Prior to the execution of the first read operation, a first programming operation is performed on the first region of the memory device to store the first write data; Perform a status read operation on the memory device to receive the result of the first program operation and the error location information; And perform a second programming operation on the second region of the memory device to store the error location information.

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