Timing controller, driving method thereof, and display apparatus including timing controller

Abstract

The timing controller generates a second clock using a first clock, generates test pulses using the second clock, and generates multiple test clocks by latching the test pulses. The timing controller determines whether the clock signal is generated correctly by using the number of rising edges and falling edges included in the period of the test pulses. The rising edges are the rising edges of the multiple test clocks, and the falling edges are the falling edges of the multiple test clocks.

Description

[Technical Field]

[0001] The general system of various embodiments relates to a timing controller, a method for driving the timing controller, a display device including the timing controller, and a method for driving the display device. [Previous Technology]

[0002] Typically, liquid crystal display panels (LCD panels) are widely used in display devices used to realize flat panel displays. Such display devices include a timing controller, a source driver, and a display panel. Display panels are being developed to achieve high resolution. To support the high resolution of the display panel, the timing controller and source driver need to be configured to transmit data via a high-speed interface.

[0003] For a high-speed interface between the timing controller and the source driver, protocols based on delay-locked loop (DLL) or phase-locked loop (PLL) can be used. A delay-locked loop-based protocol can be understood as having a source driver that can recover the format of received data packets based on the delay-locked loop, and a phase-locked loop-based protocol can be understood as having a source driver that can recover the format of received data packets based on the phase-locked loop.

[0004] In conventional technology, timing controllers and memory are manufactured as multi-chip packages (MCPs) by stacking them on the same substrate and combining them into a single package. Therefore, the problem is that the proper operation of the timing controller's IP (intellectual property) cannot be checked before the timing controller and memory are packaged.

[0005] Furthermore, the problem is that the packaging process is still performed even when the timing controller IP is abnormal, thus producing defective chips. [Summary of the Invention]

[0006] Various embodiments relate to timing controllers, methods for driving timing controllers, display devices including timing controllers, and methods for driving display devices, which can determine the normal operation of the timing controller's IP before the MCP process.

[0007] Furthermore, various embodiments relate to timing controllers, methods for driving timing controllers, display devices including timing controllers, and methods for driving display devices. They are able to identify abnormal timing controllers before the packaging process and avoid performing the packaging process on abnormal timing controllers, thereby reducing packaging costs.

[0008] In an embodiment, the timing controller may be configured to generate a clock signal by using an external first clock, wherein the timing controller generates a second clock by using the first clock, generates a test pulse by using the second clock, and generates a plurality of test clocks by latching the test pulse, wherein the timing controller determines whether the clock signal is generated normally by using the number of a plurality of rising edges included in the period of the test pulse and the number of a plurality of falling edges included in the period of the test pulse, and wherein the plurality of rising edges are rising edges of a plurality of test clocks, and the plurality of falling edges are falling edges of a plurality of test clocks.

[0009] Therefore, the timing controller according to the embodiment provides the effect of being able to determine the normal operation of the timing controller before the MCP process. Furthermore, the timing controller according to the embodiment provides the effect of being able to identify abnormal timing controllers before the packaging process and thus reducing packaging costs by not performing the packaging process on abnormal timing controllers.

[0010] In an embodiment, a method for driving a timing controller, the timing controller being configured to generate a clock signal using an external first clock, the method may include: generating a second clock using the first clock, and generating a test pulse using the second clock; generating a plurality of test clocks by latching the test pulse; and determining whether the clock signal is generated normally by using the number of a plurality of rising edges included in the period of the test pulse and the number of a plurality of falling edges included in the period of the test pulse, wherein the plurality of rising edges are rising edges of the plurality of test clocks, and the plurality of falling edges are falling edges of the plurality of test clocks.

[0011] Therefore, the method for driving a timing controller according to the embodiment provides the effect of being able to determine the normal operation of the timing controller before the MCP process. Furthermore, the method for driving a timing controller according to the embodiment provides the effect of being able to identify abnormal timing controllers before the packaging process and thus reducing packaging costs by not performing the packaging process on the abnormal timing controllers.

[0012] In an embodiment, the display device may include a timing controller configured to generate a clock signal using an external first clock, wherein the timing controller generates a second clock using the first clock, generates a test pulse using the second clock, and generates a plurality of test clocks by latching the test pulse, wherein the timing controller determines whether the clock signal is generated normally by using the number of a plurality of rising edges included in the period of the test pulse and the number of a plurality of falling edges included in the period of the test pulse, and wherein the plurality of rising edges are rising edges of a plurality of test clocks, and the plurality of falling edges are falling edges of a plurality of test clocks.

[0013] Therefore, the display device according to the embodiment provides the effect of being able to determine the normal operation of the timing controller before the MCP process. Furthermore, the display device according to the embodiment provides the effect of being able to identify abnormal timing controllers before the packaging process and thus reduce packaging costs by not performing the packaging process on the abnormal timing controllers.

[0014] In an embodiment, the timing controller may be configured to generate a clock signal, wherein the timing controller generates a test pulse by using an external clock and generates a test clock by using the test pulse, and wherein the timing controller determines whether the clock signal is generated normally by using the period of the test pulse and the edge of the test clock.

[0015] Therefore, the method for driving a display device according to the embodiment provides the effect of being able to determine the normal operation of the timing controller before the MCP process. Furthermore, the method for driving a display device according to the embodiment provides the effect of being able to identify abnormal timing controllers before the packaging process and thus reducing packaging costs by not performing the packaging process on the abnormal timing controllers.

[0016] The timing controller, the method for driving the timing controller, the display device including the timing controller, and the method for driving the display device according to the embodiments provide the effect of being able to determine the normal operation of the timing controller before the MCP process.

[0017] Furthermore, the timing controller, the method for driving the timing controller, the display device including the timing controller, and the method for driving the display device according to the embodiments provide the effect of being able to identify abnormal timing controllers before the packaging process without performing the packaging process on the abnormal timing controllers, thereby reducing packaging costs.

Implementation Method

[0024] The following description will now be given in detail with reference to the accompanying drawings and exemplary embodiments disclosed herein. Identical or similar elements may be provided with the same or similar reference numerals, and repeated descriptions thereof will be omitted.

[0025] In the following description, the display device according to the embodiment will be described with reference to FIG1.

[0026] FIG1 is a diagram showing a display device according to an embodiment.

[0027] The display device 1 according to the embodiment may include a panel 10, a timing controller 20, a memory 30, a gate driver 40, a data driver 50, and a power supply.

[0028] Panel 10 includes multiple gate lines GL1 to GLn and multiple data lines DL1 to DLm arranged to intersect each other and define multiple pixel regions, as well as multiple pixels PX. The multiple gate lines GL1 to GLn may be arranged in a horizontal direction, and the multiple data lines DL1 to DLm may be arranged in a vertical direction. However, the implementation is not limited to this. Panel 10 may be a liquid crystal display (LCD) panel. Panel 10 may display images by means of light emission from the pixels PX, wherein the corresponding gate lines and corresponding data lines of the multiple gate lines GL1 to GLn and the multiple data lines DL1 to DLm are connected to the pixels PX.

[0029] Each of the plurality of pixels PX can be configured with red, green, blue, and white sub-pixels. In an embodiment, each sub-pixel can be formed repeatedly in the column direction, or it can be formed in the form of a 2×2 matrix. The red, green, blue, and white sub-pixels can be formed with the same area ratio, but they can also be formed with different area ratios.

[0030] The timing controller 20 can receive timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock MCLK, as well as image data (hereinafter referred to as data) DATA input from an external host (not shown). The timing controller 20 can generate a clock signal CLK using the clock MCLK. The timing controller 20 can generate an internal clock using the clock MCLK. The timing controller 20 can generate test pulses using the internal clock. The timing controller 20 can generate multiple test clocks by latching test pulses according to a predetermined phase. For example, the timing controller 20 can generate multiple test clocks as DLL clocks by latching test pulses. The timing controller 20 can sample each of the multiple test clocks as a first voltage level or a second voltage level during the high voltage level period of the test pulse. The timing controller 20 can determine whether the generation of the clock signal CLK is normal based on the sampling results. A detailed method used by the timing controller 20 to determine whether the generated clock signal CLK is normal will be described later.

[0031] The timing controller 20 can convert data DATA according to the data signal format used by the data driver 50 and output the converted image data RGB. To control the gate driver 40 and the data driver 50, the timing controller 20 can receive timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock MCLK, generate various control signals, and output the generated control signals to the data driver 50 and the gate driver 40. For example, to control the gate driver 40, the timing controller 20 can generate a gate control signal GCS including a gate start pulse, a gate shift clock, and a gate output enable signal. The gate start pulse controls the start timing of the operation of the gate driver IC of the gate driver 40. The gate shift clock, as a clock signal commonly input to the gate driver IC, controls the shift timing of the scan signal (gate pulse). The gate output enable signal specifies the timing information of the gate driver IC.

[0032] Furthermore, in order to control the data driver 50, the timing controller 20 generates a data control signal DCS including a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the source driver IC that configures the data driver 50. The source sampling clock is a clock signal that controls the sampling timing of the data in each of the source driver ICs. The source output enable signal controls the output timing of the data driver 50. Since the source start pulse and source sampling clock may be omitted when the image data RGB input to the data driver 50 is transmitted according to the mini-LVDS (Low Voltage Differential Transmission) interface standard, this embodiment is not limited to this.

[0033] The timing controller 20 can use the clock MCLK to generate a clock signal CLK. For example, the timing controller 20 may include a clock divider and can generate the clock signal CLK by reducing the frequency of the clock MCLK.

[0034] The timing controller 20 can write data DATA to the memory 30 via the data line DTL. The timing controller 20 can read the written data DATA via the data line DTL. To compensate for the delay time that occurs between the timing controller 20 and the memory 30, the timing controller 20 generates a clock signal CLK and latches the clock signal CLK with a predetermined phase difference according to the operating frequency of the memory 30. The detailed method for the timing controller 20 to compensate for the delay time will be described later.

[0035] Data DATA can be written to memory 30 via data line DTL according to the memory control signal MCS. Data DATA written to memory 30 can be read via data line DTL according to the memory control signal MCS. Memory 30 can be DDR SDRAM (double data rate synchronous dynamic random access memory), but the implementation is not limited to this.

[0036] The gate driver 40 includes a shift register that sequentially generates scan signals, i.e., gate signals for enable voltage levels, according to the gate control signal GCS of the timing controller 20. The gate driver 40 can generate scan signals for enable voltage levels, causing corresponding pixels PX among a plurality of pixels PX to emit light. The gate driver 40 may be disposed on one side of the panel 10, for example, on the left side of the panel 10. However, the implementation is not limited to this, and the gate driver 40 may be disposed on the left and right sides of the panel 10 facing each other. The gate driver 40 may include a plurality of gate driver integrated circuits (ICs) (not shown). The gate driver 40 may be implemented in the form of a tape-and-reel package in which the gate driver ICs are mounted. However, the implementation is not limited to this, and the gate driver ICs may be directly mounted to the panel 10.

[0037] The data driver 50 converts the image data signal from the timing controller 20 into an analog source signal and outputs the analog source signal to the panel 10. Specifically, the data driver 50 may respond to the data control signal DCS of the timing controller 20 by outputting the analog source signal to each of the multiple data lines DL1 to DLm. The data driver 50 may be disposed on one side of the panel 10, such as the top side of the panel 10. However, the implementation is not limited to this, and the data driver 50 may be disposed on one side and another side of the panel 10, such as the top and bottom sides, facing each other. The data driver 50 may include multiple source driver ICs (not shown) that convert the image data RGB transmitted from the timing controller 20 into an analog source signal and output the analog source signal to the panel 10.

[0038] The data driver 50 may be implemented in the form of a tape-and-reel package in which an active driver IC is mounted, but the implementation is not limited thereto.

[0039] Hereinafter, a method for compensating for delay time occurring between memory and timing controller according to an embodiment will be described with reference to FIG2 and FIG3.

[0040] Figure 2 is a diagram showing the signal path formed between the timing controller and the memory according to an embodiment.

[0041] Figure 3 is a diagram showing image data corresponding to the clock according to an embodiment.

[0042] Referring to Figure 2, the timing controller 20 can generate a memory control signal MCS, causing data DATA to be written to memory 30 and read from memory 30. To write image data RGB to and read image data RGB from memory 30, the timing controller 20 can reset or calibrate the clock during the initial operation of memory 30. The timing controller 20 can transmit the memory control signal MCS via the command line CML. The timing controller 20 can use the memory control signal MCS to write data DATA to memory 30 and read the written data DATA from memory 30. The memory control signal MCS can include DDR SDRAM standard commands, including CK, CKN, CKE, RAS, CAS, WE, ADDRESS, and Bank Address. Data buses and data bus strobes can also be transmitted via the data line DTL.

[0043] A path Ro can be formed through which the memory control signal MCS is transmitted and the data DATA is transmitted to the timing controller 20. From the time when the memory control signal MCS is transmitted to the time when the data DATA is transmitted to the timing controller 20, a delay time can occur during the movement of the signal according to the path Ro.

[0044] The timing controller 20 can set the effective window time WT of the image data RGB according to the operating frequency of the memory 30 and the number of bits of the data line DL. The timing controller 20 can set the window time WT by taking into account the operating characteristics of the memory 30 and the skew of the data lines of the memory 30 (dq of DDR). The timing controller 20 can set the clock latch interval P so that the image data RGB is stably applied to the corresponding data line DL during the window time WT. The timing controller 20 can latch the clock signal CLK into multiple clocks CLK1 to CLKm according to the clock latch interval P. The multiple latched clocks CLK1 to CLKm can correspond to multiple data lines DL1 to DLm.

[0045] For example, referring to FIG3, when the operating frequency of memory 30 is 200MHz and the number of bits of data line DL is 16 or 32, timing controller 20 can set the window time WT to 1ns. When transmitting image data RGB corresponding to the fifth data line DL5 among multiple data lines DL1 to DLm, in order to stably write the image data RGB to pixel PX, the image data RGB should be written corresponding to three clock cycles CLK4, CLK5, and CLK6. Therefore, timing controller 20 can set the clock latch interval P to 0.3125ns, so that the image data RGB is stably latched during the window time WT. Timing controller 20 can latch the clock signal CLK into 16 clock cycles CLK1 to CLK16 according to the clock latch interval P.

[0046] Therefore, the timing controller 20 can compensate for the delay time that occurs in the path Ro by latching the clock signal CLK into 16 clocks CLK1 to CLK16.

[0047] In the following, a detailed method for determining whether the generated clock is normal will be described in detail with reference to FIG4 and FIG5.

[0048] Figure 4 is a block diagram showing the configuration of a timing controller according to an embodiment.

[0049] Figure 5 is a timing diagram showing the operation timing of the memory controller according to an embodiment.

[0050] Referring to FIG4, the timing controller 20 may include a data processor 210 and a memory controller 220. However, the configuration of the timing controller 20 is not limited thereto, and may additionally include various elements for the panel 10.

[0051] The data processor 210 can generate image data RGB by using data DATA.

[0052] The memory controller 220 can generate a memory control signal MCS, causing data DATA to be written to the memory 30, and the written data DATA to be read via the data line DTL. The memory controller 220 can transmit the memory control signal MCS to the memory 30. The memory control signal MCS can include write commands and read commands. The memory controller 220 can readjust the memory 30 by correcting the data line skew of the memory 30 or resetting the memory 30.

[0053] The memory controller 220 can use the clock MCLK to generate an internal clock CLK_I. The memory controller 220 can use the clock MCLK to generate a test pulse TP. The memory controller 220 can generate multiple test clocks CLK_T by latching the clock MCLK. For example, the memory controller 220 can generate multiple test clocks CLK_T into a DLL clock by latching the clock MCLK.

[0054] The memory controller 220 can be set to a period corresponding to a predetermined voltage level in the test pulse TP.

[0055] In multiple test clock cycles CLK_T, the memory controller 220 can identify rising edges included in the setting cycle as a first voltage level and rising edges not included in the setting cycle as a second voltage level. In multiple test clock cycles CLK_T, the memory controller 220 can identify falling edges included in the setting cycle as a first voltage level and falling edges not included in the setting cycle as a second voltage level. The memory controller 220 can determine whether the generation operation of the clock signal CLK is normal by using the number of rising edges and falling edges corresponding to the first voltage level and the number of rising edges and falling edges corresponding to the second voltage level.

[0056] Referring to Figures 4 and 5, the memory controller 220 may include a clock generation circuit 221 and a link circuit 222.

[0057] The clock generation circuit 221 can generate a clock signal CLK using the internal clock CLK_I. The clock generation circuit 221 can measure the period of the internal clock CLK_I. The clock generation circuit 221 can set a portion of the period of the internal clock CLK_I as a phase difference. The clock generation circuit 221 can generate 16 test clocks CLK_T by latching the clock signal CLK according to the set phase difference.

[0058] For example, the clock generation circuit 221 can measure the period of the internal clock CLK_I between a first time point T1 and a second time point T2. The clock generation circuit 221 can set 1 / 16 of the period of the internal clock CLK_I as the phase difference. The clock generation circuit 221 can generate the first test clock CLK_T1 to the sixteenth test clock CLK_T16 by latching the clock signal CLK according to the phase difference. The first test clock CLK_T1 has the same phase as the test pulse TP. The clock generation circuit 221 can be implemented using a delay-locked loop (DLL) circuit.

[0059] Link circuit 222 can generate a memory control signal MCS. During a write operation, link circuit 222 generates the memory control signal MCS, causing data DATA to be written to memory 30. During a read operation, link circuit 222 generates the memory control signal MCS, causing data DATA written to memory 30 to be read. Link circuit 222 can transmit the memory control signal MCS via command line CML. Link circuit 222 can generate a test pulse TP using an internal clock CLK_I. Link circuit 222 can sample each of the multiple test clocks CLK_T as a first voltage level or a second voltage level during the high-voltage level period of the test pulse TP. Timing controller 20 can determine whether the generation of clock signal CLK is normal based on the sampling results.

[0060] The link circuit 222 may include an internal clock generator 2221 and a tester 2222.

[0061] The internal clock generator 2221 can generate the internal clock CLK_I by dividing the clock MCLK by 2.

[0062] The tester 2222 can generate a test pulse TP using an internal clock CLK_I. The tester 2222 can generate a test pulse TP corresponding to the period of the internal clock CLK_I. For example, the tester 2222 can measure the period of the internal clock CLK_I between a first time point T1 and a second time point T2, and can generate a test pulse TP corresponding to the period between the first time point T1 and the second time point T2. The test pulse TP can have an amplitude of a high voltage level H between the first time point T1 and the second time point T2. The test pulse TP can also have an amplitude of a low voltage level L at a time different from the time between the first time point T1 and the second time point T2.

[0063] The tester 2222 can identify the rising edge included in the high voltage level period Pp corresponding to the high voltage level H of the test pulse TP in the first test clock CLK_T1 to the sixteenth test clock CLK_T16 as the first voltage level. The high voltage level period Pp is the time between the first time point T1 and the second time point T2. The tester 2222 can identify the rising edge of the high voltage level period Pp not included in the first test clock CLK_T1 to the sixteenth test clock CLK_T16 as the second voltage level. The tester 2222 can identify the falling edge of the high voltage level period Pp included in the first test clock CLK_T1 to the sixteenth test clock CLK_T16 as the first voltage level. The tester 2222 can identify the falling edge of the high voltage level period Pp not included in the first test clock CLK_T1 to the sixteenth test clock CLK_T16 as the second voltage level. Tester 2222 can generate a first count by adding the number of rising edges corresponding to the first voltage level to the number of falling edges corresponding to the first voltage level. Tester 2222 can generate a second count by adding the number of rising edges corresponding to the second voltage level to the number of falling edges corresponding to the second voltage level.

[0064] The tester 2222 can compare the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level. The tester 2222 can compare the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level. The tester 2222 can compare a first count and a second count. The tester 2222 can compare the sum of the first count and the second count with a preset threshold.

[0065] When the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, the first count and the second count are the same, and the sum of the first count and the second count is the same as the preset threshold, the tester 2222 can determine that the clock generation circuit 221 is operating normally.

[0066] For example, the tester 2222 can sample eight rising edges r1 to r8 included in the high voltage level period Pp. The tester 2222 can identify the eight rising edges r1 to r8 as the first voltage level. The tester 2222 can sample eight falling edges f1 to f8 not included in the high voltage level period Pp. The tester 2222 can identify the eight falling edges f1 to f8 as the second voltage level. When the number of rising edges with the first voltage level and the number of falling edges with the first voltage level are both 8, the number of rising edges with the second voltage level and the number of falling edges with the second voltage level are both 8, and the first count and the second count are both 16, the tester 2222 can determine that the clock generation circuit 221 is operating normally.

[0067] Therefore, the normal operation of the timing controller 20 can be determined before the MCP process. The timing controller 20 can check whether an abnormal clock is generated before the packaging process. Therefore, by not performing the packaging process on an abnormal timing controller that generates an abnormal clock, packaging costs can be reduced.

[0068] Hereinafter, a method for driving a display device according to an embodiment will be described with reference to FIG6.

[0069] FIG6 is a flowchart illustrating a method for driving a display device according to an embodiment.

[0070] In step S10, the timing controller 20 generates an internal clock CLK_I by dividing the clock MCLK by 2. The timing controller 20 uses the internal clock CLK_I to generate a clock signal CLK. The clock generation circuit 221 measures the period of the internal clock CLK_I. The timing controller 20 can generate a test pulse TP corresponding to the period of the internal clock CLK_I. For example, the timing controller 20 measures the period of the internal clock CLK_I between a first time point T1 and a second time point T2, and generates a test pulse TP corresponding to the period between the first time point T1 and the second time point T2.

[0071] In step S20, the clock generation circuit 221 of the timing controller 20 can set a portion of the period of the internal clock CLK_I as a phase difference. The clock generation circuit 221 generates 16 test clocks CLK_T by latching the clock signal CLK according to the set phase difference.

[0072] For example, the timing controller 20 can measure the period of the internal clock CLK_I between the first time point T1 and the second time point T2. The timing controller 20 can set 1 / 16 of the period of the internal clock CLK_I as the phase difference. The clock generation circuit 221 generates the first test clock CLK_T1 to the sixteenth test clock CLK_T16 by latching the clock signal CLK according to the phase difference.

[0073] In step S30, the timing controller 20 determines whether the sum of the first count and the second count is the same as the threshold.

[0074] In detail, the timing controller 20 identifies rising edges in the high-voltage level periods Pp of the test pulse TP, which are included in the first test clock CLK_T1 to the sixteenth test clock CLK_T16, as a first voltage level. The timing controller 20 identifies rising edges in the first test clock CLK_T1 to the sixteenth test clock CLK_T16 that are not included in the high-voltage level periods Pp as a second voltage level. The timing controller 20 identifies falling edges in the first test clock CLK_T1 to the sixteenth test clock CLK_T16 that are not included in the high-voltage level periods Pp as a first voltage level. The timing controller 20 generates a first count by adding the number of rising edges and the number of falling edges corresponding to the first voltage level. The timing controller 20 generates a second count by adding the number of rising edges and the number of falling edges corresponding to the second voltage level.

[0075] The timing controller 20 determines whether the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same. The timing controller 20 determines whether the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same. The timing controller 20 determines whether the first count and the second count are the same.

[0076] In step S40, when the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, the first count and the second count are the same, and the sum of the first count and the second count is the same as the preset threshold, the timing controller 20 determines that the clock generation circuit 221 is operating normally.

[0077] Therefore, the normal operation of the timing controller 20 can be determined before the MCP process. The timing controller 20 can check for abnormal clocks before the packaging process. Therefore, by not performing the packaging process on a timing controller that generates abnormal clocks, packaging costs can be reduced.

[0078] For ease of explanation, the clock signal CLK and the test clock CLK_T have been described above as separate components. However, the implementation is not limited to this, and the clock signal CLK can be the same clock as the test clock CLK_T. [Simplified Explanation of the Diagram]

[0018] FIG1 is a diagram showing the configuration of a display device according to an embodiment.

[0019] Figure 2 is a diagram showing the path between the timing controller and the memory according to an embodiment.

[0020] Figure 3 is a diagram showing the windowing time of image data transferred from memory according to an embodiment.

[0021] Figure 4 is a block diagram showing the configuration of a timing controller according to an embodiment.

[0022] Figure 5 is a timing diagram showing the operation timing of the memory controller according to an embodiment.

[0023] FIG6 is a flowchart illustrating a method for driving a display device according to an embodiment.

Claims

1. A timing controller configured to generate a clock signal using an external first clock, wherein, The timing controller is configured to: generate a second clock using the first clock, generate a test pulse using the second clock, generate a plurality of test clocks by latching the test pulses; determine whether the clock signal is generated normally by using the number of a plurality of rising edges included in the period of the test pulses and the number of a plurality of falling edges included in the period of the test pulses, wherein the plurality of rising edges are rising edges of the plurality of test clocks, and the plurality of falling edges are falling edges of the plurality of test clocks.

2. The timing controller according to claim 1, wherein, The timing controller is further configured to: generate the test pulse, such that the test pulse has a high voltage level corresponding to the period of the second clock, generate the plurality of test clocks as delay-locked loop clocks by latching the test pulse, and the period of the second clock is between a first time point and a second time point.

3. The timing controller according to claim 2, wherein, The timing controller is further configured to: identify a rising edge included in the high voltage level period of the test pulse among the plurality of rising edges as a first voltage level, and identify a rising edge not included in the high voltage level period among the plurality of rising edges as a second voltage level; and identify a falling edge included in the high voltage level period among the plurality of falling edges as the first voltage level, and identify a falling edge not included in the high voltage level period among the plurality of falling edges as the second voltage level.

4. The timing controller according to claim 3, wherein, The timing controller is further configured to determine that the clock signal is generated normally when the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, and the first count and the second count are the same, wherein the first count is the sum of the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level, and the second count is the sum of the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level.

5. The timing controller according to claim 3, wherein, The timing controller is configured to determine that the clock signal is being generated normally when the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, and the sum of the first count and the second count is the same as a preset threshold; wherein the first count is the sum of the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level, and the second count is the sum of the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level.

6. A method for driving a timing controller, the timing controller being configured to generate a clock signal using an external first clock, the method comprising: A second clock is generated using the first clock, and a test pulse is generated using the second clock. Multiple test clocks are generated by latching the test pulses; And determine whether the clock signal is generated normally by using the number of multiple rising edges included in the period of the test pulse and the number of multiple falling edges included in the period of the test pulse; wherein the multiple rising edges are the rising edges of the multiple test clocks, and the multiple falling edges are the falling edges of the multiple test clocks.

7. The method according to request item 6, wherein, Generating the test pulse includes: generating the test pulse such that the test pulse has a high voltage level corresponding to the period of the second clock, wherein generating the plurality of test clocks includes: generating the plurality of test clocks as delay-locked loop clocks by latching the test pulses, and wherein the period of the second clock is between a first time point and a second time point.

8. The method according to claim 7 further includes: The rising edge included in the high voltage level period of the test pulse among the plurality of rising edges is identified as a first voltage level; the rising edge not included in the high voltage level period among the plurality of rising edges is identified as a second voltage level; the falling edge included in the high voltage level period among the plurality of falling edges is identified as the first voltage level; and the falling edge not included in the high voltage level period among the plurality of falling edges is identified as the second voltage level.

9. The method according to request item 8, wherein, Determining whether the clock signal is generated normally includes: when the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, and the first count and the second count are the same, the clock signal is determined to be generated normally, wherein the first count is the sum of the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level, and the second count is the sum of the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level.

10. The method according to claim 8, wherein determining whether the clock signal is generated normally includes: When the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, and the sum of the first count and the second count is the same as a preset threshold, it is determined that the clock signal is generated normally, wherein the first count is the sum of the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level, and the second count is the sum of the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level.

11. A display device comprising a timing controller configured to generate a clock signal using an external first clock, wherein, The timing controller is configured to generate a second clock using the first clock, generate a test pulse using the second clock, and generate a plurality of test clocks by latching the test pulses. The timing controller is configured to determine whether a clock signal is generated correctly by using the number of multiple rising edges included in the period of the test pulse and the number of multiple falling edges included in the period of the test pulse. The multiple rising edges are rising edges of the plurality of test clocks, and the multiple falling edges are falling edges of the plurality of test clocks.

12. The display device according to claim 11, wherein: The timing controller is configured to generate the test pulse, such that the test pulse has a high voltage level corresponding to the period of the second clock, and generates the plurality of test clocks as delay-locked loop clocks by latching the test pulse, and the period of the second clock is between a first time point and a second time point.

13. The display device according to claim 12, wherein: The timing controller is configured to identify a rising edge included in the high voltage level period of the test pulse as a first voltage level, and a rising edge not included in the high voltage level period as a second voltage level; and the timing controller is configured to identify a falling edge included in the high voltage level period as the first voltage level, and a falling edge not included in the high voltage level period as the second voltage level.

14. The display device according to claim 13, wherein: When the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, and the first count and the second count are the same, the timing controller is configured to determine that the clock signal is generated normally, and the first count is the sum of the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level, and the second count is the sum of the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level.

15. The display device according to claim 13, wherein: When the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level are the same, the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level are the same, and the sum of the first count and the second count is the same as a preset threshold, the timing controller is configured to determine that the clock signal is generated normally, and the first count is the sum of the number of rising edges corresponding to the first voltage level and the number of falling edges corresponding to the first voltage level, and the second count is the sum of the number of rising edges corresponding to the second voltage level and the number of falling edges corresponding to the second voltage level.

16. A timing controller configured to generate a clock signal, wherein, The timing controller is configured to generate a test pulse using an external clock and to generate a test clock using the test pulse, wherein the timing controller is configured to determine whether the clock signal is generated normally by using the period of the test pulse and the edges of the test clock, wherein: the timing controller is configured to generate the test clock as a delay-locked loop clock by latching the test pulse, and is configured to determine whether the clock signal is generated normally by using the number of rising edges and the number of falling edges included in the period of the test pulse, wherein the rising edge is the rising edge of the test clock and the falling edge is the falling edge of the test clock.

17. The timing controller according to claim 16, wherein: The timing controller is configured to generate an internal clock using the external clock and to generate the test pulse, such that the test pulse has a high voltage level corresponding to the period of the internal clock, and the period of the internal clock is between a first time point and a second time point.

18. The timing controller according to claim 17, wherein, The timing controller is configured to sample the rising edge and the falling edge included in the high voltage level period of the test pulse as a first voltage level, and to sample the rising edge and the falling edge not included in the high voltage level period as a second voltage level.

19. The timing controller according to claim 18, wherein, When the number of rising and falling edges corresponding to the first voltage level and the number of rising and falling edges corresponding to the second voltage level are the same, the timing controller is configured to determine that the clock signal is generated normally.

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