Semiconductor package

Abstract

A semiconductor package is provided in which a first insulating layer includes a first recess spaced apart from a first pad in a first direction, and a second insulating layer includes a second recess spaced apart from a second pad in the first direction and overlapping at least a portion of the first recess in a second direction perpendicular to the first direction to provide an air gap together with the first recess. The semiconductor package further includes a first bonding surface and a second bonding surface, the first bonding surface being defined on one side of the air gap adjacent to the first and second pads by a first insulating layer and a second insulating layer in contact with each other, and the second bonding surface being defined on the other side of the air gap opposite to the first side by a first insulating layer and a second insulating layer in contact with each other.

Description

Technical Field

[0001] [Cross - reference to Related Applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2021 - 0154537, filed with the Korean Intellectual Property Office on November 11, 2021. The entire disclosure of the Korean patent application is incorporated herein by reference.

[0003] Embodiments of the present disclosure relate to a semiconductor package and a method for manufacturing the semiconductor package.

Background Art

[0004] As the demand for high - capacity, thin, and small electronic products increases, various types of semiconductor packages are being developed. Recently, as a method of integrating more components (e.g., semiconductor chips) into a package structure, a direct bonding technique for bonding semiconductor chips without using an adhesive film (e.g., a non - conductive film (NCF)) or connection bumps (e.g., solder balls) has been developed.

Summary of the Invention

[0005] According to an aspect of the present disclosure, there is provided a semiconductor package having improved reliability and a method for manufacturing the semiconductor package.

[0006] According to an embodiment of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor die, including a first substrate, a first pad, and a first insulating layer, the first pad being located above the first substrate, and the first insulating layer being located above the first substrate and surrounding the first pad; and a second semiconductor die, located on the first semiconductor die, the second semiconductor die including a second substrate, a second pad, and a second insulating layer, the second pad being located below the second substrate and contacting the first pad, the second insulating layer being located below the second substrate, surrounding the second pad, and contacting the first insulating layer, wherein the first insulating layer includes a first recess spaced apart from the first pad in a first direction, wherein the second insulating layer includes a second recess spaced apart from the second pad in the first direction, the second recess overlapping at least a portion of the first recess in a second direction perpendicular to the first direction, an air gap exists between the first recess and the second recess, and wherein the semiconductor package further includes a first bonding surface defined by the first insulating layer and the second insulating layer contacting each other on a side of the air gap adjacent to the first pad and the second pad, and the semiconductor package further includes a second bonding surface defined by the first insulating layer and the second insulating layer contacting each other on another side of the air gap opposite to the one side.

[0007] According to an embodiment of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor die, including a first substrate, a plurality of first pads, and a first insulating layer, the plurality of first pads being located above the first substrate, the first insulating layer being located above the first substrate and surrounding the plurality of first pads; a second semiconductor die, located on the first semiconductor die, the second semiconductor die including a second substrate, a plurality of second pads, and a second insulating layer, the plurality of second pads being located below the second substrate, the second insulating layer being located below the second substrate and surrounding the plurality of second pads, wherein the first semiconductor die and the second semiconductor die are electrically connected to each other by a pair of first bonding pad structures and second bonding pad structures, the first bonding pad structure and the second bonding pad structure each including one of the plurality of first pads and one of the plurality of second pads, wherein the semiconductor package further includes a first air gap surrounding the first bonding pad structure and a second air gap surrounding the second bonding pad structure, and wherein the semiconductor package further includes: a first bonding surface defined by at least a portion of the first insulating layer and at least a portion of the second insulating layer in contact with each other between the first bonding pad structure and the first air gap and between the second bonding pad structure and the second air gap; and a second bonding surface defined by at least a portion of the first insulating layer and at least a portion of the second insulating layer in contact with each other between the first air gap and the second air gap.

[0008] According to an embodiment of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor die, including a first substrate, a first pad, and a first insulating layer, the first pad being located above the first substrate, the first insulating layer including a first recess surrounding the first pad; and a second semiconductor die, located on the first semiconductor die, the second semiconductor die including a second substrate, a second pad, and a second insulating layer, the second pad being located below the second substrate and in contact with the first pad, the second insulating layer including a second recess surrounding the second pad, wherein the second insulating layer is in contact with the first insulating layer, and wherein side surfaces of each of the first pad and the second pad are completely covered by the first insulating layer and the second insulating layer, respectively.

[0009] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor package is provided. The method includes: preparing a semiconductor wafer, the semiconductor wafer including a preliminary substrate, a circuit layer on a front surface of the preliminary substrate, and a preliminary insulating layer on the circuit layer; forming a front insulating layer including an etching groove by etching at least a part of the preliminary insulating layer; forming a preliminary barrier layer and a preliminary conductive layer on the front insulating layer (including on the etching groove); forming a front pad including a barrier layer and a conductive layer by polishing the preliminary barrier layer and the preliminary conductive layer in a polishing process using a first slurry; and forming a recess spaced apart from the front pad by a predetermined distance by polishing the front insulating layer in a polishing process using a second slurry.

[0010] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor package is provided. The method includes: preparing a semiconductor wafer, the semiconductor wafer including a preliminary substrate and a plurality of through electrodes disposed in the preliminary substrate; forming a substrate having a rear surface by removing a part of the preliminary substrate, the plurality of through electrodes protruding from the rear surface; forming a preliminary protective layer and a preliminary buffer layer on the rear surface of the substrate on the plurality of through electrodes; forming a flat surface exposing the plurality of through electrodes by planarizing the preliminary protective layer and the preliminary buffer layer; forming a preliminary insulating layer on the flat surface; forming a rear insulating layer including an etching groove by etching at least a part of the preliminary insulating layer; forming a preliminary barrier layer and a preliminary conductive layer on the rear insulating layer (including on the etching groove); forming a rear pad including a barrier layer and a conductive layer by polishing the preliminary barrier layer and the preliminary conductive layer in a polishing process using a first slurry; and forming a recess spaced apart from the rear pad by a predetermined distance by polishing the rear insulating layer in a polishing process using a second slurry.

[0011] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor package is provided. The method includes: preparing a semiconductor wafer including a plurality of rear pads and a rear insulating layer surrounding the plurality of rear pads, the rear insulating layer including a first recess spaced apart from the plurality of rear pads; preparing a plurality of second semiconductor wafers including a plurality of front pads and a front insulating layer surrounding the plurality of front pads, the front insulating layer including a second recess spaced apart from the plurality of front pads; forming an air gap between the first recess and the second recess by disposing the plurality of second semiconductor wafers on the semiconductor wafer, the plurality of rear pads contacting the plurality of front pads, and the rear insulating layer contacting the front insulating layer in a remaining portion of the front insulating layer other than the air gap; and bonding the rear insulating layer to the front insulating layer to each other and bonding the plurality of rear pads to the plurality of front pads to each other by performing a thermocompression process.

Embodiment

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0014] It should be understood that when an element or layer is referred to as being "on", "above", "over", "under", "beneath", "below", "connected to" or "coupled to" another element or layer, the element or layer can be directly on, above, over, under, beneath, below, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly above", "directly over", "directly under", "directly beneath", "directly below", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0015] FIG. 1A is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure, FIG. 1B is a partial enlarged view showing part "A" shown in FIG. 1A, FIG. 1C is a partial enlarged view showing part "B" shown in FIG. 1A, and FIGS. 1D and 1E are plan views of FIG. 1C taken along line I-I'.

[0016] Referring to FIG. 1A, the semiconductor package 10 according to an embodiment may include a plurality of semiconductor wafers stacked in a vertical direction (Z-axis direction), such as a first semiconductor wafer 100 and a second semiconductor wafer 200. The upper surface of the first semiconductor wafer 100 and the lower surface of the second semiconductor wafer 200 may be directly bonded and joined together (e.g., hybrid bonding, direct bonding, or similar bonding) without having a connecting member (e.g., a metal bump or a similar connecting member). The first insulating layer 151 and the first pads 152 provided on the upper surface of the first semiconductor wafer 100 may be bonded and joined to the second insulating layer 231 and the second pads 232 provided on the lower surface of the second semiconductor wafer 200. The first semiconductor wafer 100 may be electrically connected to the second semiconductor wafer 200 through a bonding pad structure BP including the first pads 152 and the second pads 232 bonded together.

[0017] Embodiments of the present disclosure may include an air gap AG surrounding the bonding pad structure BP between the first insulating layer 151 and the second insulating layer 231 to trap the gas generated during the thermocompression process and prevent the occurrence of interface delamination or voids. Additionally, the air gap AG may be spaced apart from the bonding pad structure BP by a predetermined distance to form a junction interface (or "bonding surface") of the first insulating layer 151 and the second insulating layer 231 between the bonding pad structure BP and the air gap AG, thereby improving the bonding quality between the first pads 152 and the second pads 232.

[0018] For example, at least a part of the first insulating layer 151 may be located between the side surface of at least one of the first pads 152 and the first recess 151R, and at least a part of the second insulating layer 231 may be located between the side surface of at least one of the second pads 232 and the second recess 231R. In this case, the at least a part of the first insulating layer 151 may contact the at least a part of the second insulating layer. Accordingly, the side surfaces of at least one of the first pads 152 and at least one of the second pads 232 may be completely covered by the first insulating layer 151 and the second insulating layer 231, respectively, and may not be exposed from the first recess 151R and the second recess 231R, respectively. In this case, the "first insulating layer" and the "second insulating layer" may be referred to as the "first upper insulating layer" or the "first rear insulating layer" and the "second lower insulating layer" or the "second front insulating layer" to distinguish the positions of the components in the first semiconductor wafer 100 or the second semiconductor wafer 200. Additionally, the "first pads" and the "second pads" may be referred to as the "first upper pads" or the "first rear pads" and the "second lower pads" or the "second front pads", respectively.

[0019] Hereinafter, the components of the first semiconductor wafer 100 and the second semiconductor wafer 200 will be described in detail with reference to FIGS. 1B to 1E and FIG. 1A.

[0020] The first semiconductor wafer 100 may include a first substrate 110, a first circuit layer 120, a first through electrode 140, a first insulating layer 151, and a first pad 152. The first semiconductor wafer 100 may have a flat upper surface provided by the upper surface of the first insulating layer 151 and the upper surface of the first pad 152. For example, except for the first recess 151R, the upper surface of the first insulating layer 151 may be substantially coplanar with the upper surface of the first pad 152 exposed from the first insulating layer 151.

[0021] The first substrate 110 may be a semiconductor wafer substrate having a front surface FR and a back surface BA opposite to each other. For example, the first substrate 110 may be a semiconductor wafer containing a semiconductor element (such as silicon or germanium) or a compound semiconductor (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). The front surface FR may be an active surface having an impurity-doped active region, and the back surface BA may be a non-active surface positioned opposite to the front surface FR. An insulating protection layer 113 for electrically insulating the first pad 152 from the first substrate 110 may be provided on the back surface BA of the first substrate 110. For example, the insulating protection layer 113 may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer layer 114 (such as a grinding stop layer or a barrier) may be provided on the upper surface of the insulating protection layer 113. For example, the buffer layer 114 may include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0022] The first circuit layer 120 may be disposed on the front surface FR of the first substrate 110 and may include a first wiring structure (not shown) connected to the active region and a first interlayer insulating layer (not shown) surrounding the first wiring structure. A first pad 132 electrically connected to a wiring structure (not shown) may be disposed below the first circuit layer 120. The first pad 132 may be a pad structure electrically connected to a wiring structure (not shown). A connection bump 136 may be disposed below one of the first pads 132. The connection bump 136 may be, for example, a conductive bump structure (including solder balls, copper (Cu) pillars, or similar structures). The first circuit layer 120 may have a structure the same as or similar to the structure of the second circuit layer 220 shown in FIGS. 1B and 1C. Thus, it can be understood that the first wiring structure (not shown) and the first interlayer insulating layer (not shown) have characteristics similar to the second wiring structure 225 and the second interlayer insulating layer 221 of the second circuit layer 220 to be described later. Additionally, referring to the modified example shown in FIG. 7, the structure of the first wiring structure (e.g., the first wiring structure 125 in FIG. 7) and the first interlayer insulating layer (e.g., the first interlayer insulating layer 121 in FIG. 7) of the first circuit layer 120 can be easily understood.

[0023] The first via electrode 140 may pass through the first substrate 110 and the insulating protection layer 113 to electrically connect at least one of the first pads 152 and at least one of the first pads 132. The first via electrode 140 may include a via plug 145 and a side barrier layer 141 surrounding the side surface of the via plug 145. The via plug 145 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed in a plating process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. The side barrier layer 141 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) and may be formed in a plating process, a PVD process, or a CVD process. A side insulating layer (not shown) including an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a similar material (e.g., high aspect ratio process (HARP) oxide) may be formed between the side barrier layer 141 and the first substrate 110.

[0024] The first insulating layer 151 may be disposed on the back surface BA of the first substrate 110. The first insulating layer 151 may include an insulating material capable of bonding and coupling to the second insulating layer 231 in the lower portion of the second semiconductor wafer 200. For example, the first insulating layer 151 may include silicon oxide (SiO) or silicon carbonitride (SiCN). For example, at least a portion of the first insulating layer 151 may be bonded to the second insulating layer 231 to form a bonding surface (e.g., the first bonding surface BS1 and the second bonding surface BS2) for bonding and coupling the first semiconductor wafer 100 and the second semiconductor wafer 200 to each other. Additionally, the first insulating layer 151 may be formed to surround a plurality of first pads 152 (also referred to as "upper pads") disposed on the upper surface of the first insulating layer 151 and may be spaced apart from the plurality of first pads 152 by a predetermined distance to have a plurality of first recesses 151R surrounding the plurality of first pads 152. The plurality of first recesses 151R may be aligned with a plurality of second recesses 231R of the second semiconductor wafer 200 in a vertical direction to form an air gap AG surrounding the bonding pad structure BP. In such a case, the first insulating layer 151 may be referred to as a first upper insulating layer.

[0025] The first pad 152 may be disposed above the back surface BA of the first substrate 110 and may include a first barrier layer 153 and a first conductive layer 155. At least a portion of one of the first pads 152 may be bonded to one of the second pads 232 of the second semiconductor wafer 200 to form a bonding pad structure BP and a bonding surface (the bonding surface BS3 in FIG. 13) for physically and electrically coupling the first semiconductor wafer 100 and the second semiconductor wafer 200. The first barrier layer 153 may be formed to conformally extend between the first conductive layer 155 and the first insulating layer 151 to surround the outer edge of the first conductive layer 155. The first conductive layer 155 and the first barrier layer 153 may include a conductive material. For example, the first conductive layer 155 may include at least one of copper (Cu), nickel (Ni), gold (Au), and silver (Ag), and the first barrier layer 153 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0026] The second semiconductor wafer 200 may be disposed on the first semiconductor wafer 100 and may include a second substrate 210, a second circuit layer 220, a second insulating layer 231, and second pads 232 (also referred to as "second lower pads"). The second semiconductor wafer 200 may have a flat lower surface provided by the lower surface of the second insulating layer 231 and the lower surface of the second pads 232. For example, except for the second recess 231R, the lower surface of the second insulating layer 231 may be substantially coplanar with the lower surface of the second pads 232 exposed from the second insulating layer 231. Since the first semiconductor wafer 100 and the second semiconductor wafer 200 may have substantially the same or similar structures, the same or similar components may be denoted by the same or similar reference numerals and repeated descriptions of the same components will be omitted. For example, it can be understood that, as described above, the second substrate 210 has substantially the same characteristics as the first substrate 110.

[0027] The second circuit layer 220 may be disposed on the front surface or the active surface of the second substrate 210 and may include a second wiring structure 225 connected to the active region and a second interlayer insulating layer 221 surrounding the second wiring structure 225.

[0028] The second interlayer insulating layer 221 may include flowable oxide (FOX), tonen silazen (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PETEOS), fluoride silicate glass (FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or a combination thereof. At least a portion of the second interlayer insulating layer 221 surrounding the second wiring structure 225 may be formed as a low dielectric layer. The second interlayer insulating layer 221 may be formed using a CVD process, a flowable CVD process, or a spin coating process.

[0029] The second wiring structure 225 can be formed in a multilayer structure including vias and wiring patterns, and the vias and wiring patterns include, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier layer (not shown) including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) can be provided between the wiring pattern and / or the via and the second interlayer insulating layer 221. Individual devices 215 constituting an integrated circuit can be provided on the front surface of the second substrate 210. In such a case, the second wiring structure 225 can be electrically connected to the individual devices 215 via an interconnection portion 213 (e.g., a contact plug). The individual devices 215 can include: a field effect transistor (FET), such as a planar FET, a FinFET, or a similar FET; a memory device, such as a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), a parameter random access memory (PRAM), a magnetoresistive random-access memory (MRAM), a ferroelectric random access memory (FeRAM), a resistive random access memory (RRAM), or a similar memory; a logic device, such as an AND gate, an OR gate, a NAND gate, or a similar logic device; or various active components and / or passive components, such as a system large scale integration (LSI), a customer information system (CIS), or a micro-electromechanical system (MEMS).

[0030] The second insulating layer 231 may be disposed under the second substrate 210 or the second circuit layer 220. The second insulating layer 231 may include an insulating material capable of bonding and coupling to the first insulating layer 151 of the first semiconductor wafer 100. For example, the second insulating layer 231 may include silicon oxide (SiO) or silicon carbonitride (SiCN). For example, at least a portion of the second insulating layer 231 may be bonded to the first insulating layer 151 to form a bonding surface (e.g., the first bonding surface BS1 and the second bonding surface BS2) for bonding and coupling the first semiconductor wafer 100 and the second semiconductor wafer 200 to each other. Additionally, the second insulating layer 231 may be formed to surround a plurality of second pads 232 disposed on the lower surface of the second insulating layer 231 and may be spaced apart from the plurality of second pads 232 by a predetermined distance to have a plurality of second recesses 231R surrounding the plurality of second pads 232. The plurality of second recesses 231R may be aligned with the plurality of first recesses 151R of the first semiconductor wafer 100 in a vertical direction to form an air gap AG surrounding the bonding pad structure BP. In this case, the second insulating layer 231 may be referred to as a second lower insulating layer.

[0031] The second pads 232 may be disposed under the second substrate 210 and may include a second barrier layer 233 and a second conductive layer 235. At least a portion of one of the second pads 232 may be bonded to one of the first pads 152 of the first semiconductor wafer 100 to form a bonding pad structure BP and a bonding surface (the bonding surface BS3 in FIG. 13) for physically and electrically coupling the first semiconductor wafer 100 and the second semiconductor wafer 200. The second barrier layer 233 and the second conductive layer 235 may be formed of the same or similar structure and material as the first barrier layer 153 and the first conductive layer 155 described above.

[0032] As described above, the first recesses 151R of the first insulating layer 151 and the second recesses 231R of the second insulating layer 231 may provide an air gap AG surrounding the bonding pad structure BP. The air gap AG may be spaced apart from the bonding pad structure BP by a predetermined distance to improve the quality of the interface between the first semiconductor wafer 100 and the second semiconductor wafer 200 and enhance the reliability of the semiconductor package 10. Hereinafter, the first bonding surface BS1 and the second bonding surface BS2 formed around the bonding pad structure BP and the air gap AG will be described in more detail.

[0033] As shown in FIG. 1B, the semiconductor package 10 of the present embodiment may include at least one pair of first bonding pad structures BP1 and second bonding pad structures BP2 adjacent to each other among a plurality of bonding pad structures BP for electrically connecting the first semiconductor wafer 100 and the second semiconductor wafer 200.

[0034] At least one pair of the first bonding pad structures BP1 and the second bonding pad structures BP2 may be conductive structures in which the plurality of first pads 152 and the plurality of second pads 232 are joined and bonded to each other. In such a case, a first air gap AG1 adjacent to the first bonding pad structure BP1, a second air gap AG2 adjacent to the second bonding pad structure BP2, a plurality of first bonding surfaces BS1 located between the first bonding pad structure BP1 and the first air gap AG1 and between the second bonding pad structure BP2 and the second air gap AG2, and a second bonding surface BS2 located between the first air gap AG1 and the second air gap AG2 may be formed between the at least one pair of the first bonding pad structures BP1 and the second bonding pad structures BP2.

[0035] The first gap AG1 may be spaced apart from the first bonding pad structure BP1 by a predetermined distance to surround the first bonding pad structure BP1. The second gap AG2 may be spaced apart from the second bonding pad structure BP2 by a predetermined distance to surround the second bonding pad structure BP2. The plurality of first bonding surfaces BS1 may be an interface between the first insulating layer 151 (also referred to as the "first upper insulating layer") and the second insulating layer 231 (also referred to as the "second lower insulating layer"), and the interface is joined between the first bonding pad structure BP1 and the first air gap AG1 and between the second bonding pad structure BP2 and the second air gap AG2. The second bonding surface BS2 may be an interface between the first insulating layer 151 and the second insulating layer 231, and the interface is joined between the first air gap AG1 and the second air gap AG2.

[0036] The first air gap AG1 and the second air gap AG2 can trap the gas generated during the bonding period between the first semiconductor wafer 100 and the second semiconductor wafer 200 and can prevent the occurrence of interface delamination or voids. The width W1 of the first air gap AG1 and the width W2 of the second air gap can be respectively about 25% or less than 25% of the distance D (also referred to as the "pad pitch") between the first bonding pad structure BP1 and the second bonding pad structure BP2 (for example, about 5% to about 25%, about 10% to about 25%, or about 15% to about 25%). When the width W1 of the first air gap AG1 and the width W2 of the second air gap are respectively less than about 5% of the distance D, the gas trapping effect may not be significant. When the width W1 of the first air gap AG1 and the width W2 of the second air gap respectively exceed about 25% of the distance D, sufficient bonding force between the first insulating layer 151 and the second insulating layer 231 may not be ensured. The bonding force between the first insulating layer 151 and the second insulating layer 231 can be ensured by the second bonding surface BS2. For example, the length L2 of the second bonding surface BS2 can be equal to or greater than the sum of the width W1 of the first air gap AG1 and the width W2 of the second air gap AG2. The plurality of first bonding surfaces BS1 can be provided to support and fix the first pad 152 and the second pad 232 during the bonding process (for example, the thermocompression process) and to ensure the bonding reliability of the first pad 152 and the second pad 232, and thus the plurality of first bonding surfaces BS1 can be formed to have a length L1 that is relatively shorter than the length of the second bonding surface BS2. For example, each of the plurality of first bonding surfaces BS1 can have a length L1 that is less than the width W1 of the first air gap and the width W2 of the second air gap. In this case, the length L1 of each of the plurality of first bonding surfaces BS1 can refer to the width of the interface between the first insulating layer 151 and the second insulating layer 231 between the bonding pad structure BP and the air gap AG (the width w in FIG. 1D).

[0037] For example, when the distance D (also referred to as the "pad pitch") is about 2 micrometers, the width W1 of the first air gap AG1 and the width W2 of the second air gap AG2 can be respectively in the range of about 0.1 micrometer to about 0.5 micrometers, the length L2 of the second bonding surface BS2 can be in the range of about 1 micrometer to about 1.8 micrometers, and the length L1 of each of the plurality of first bonding surfaces BS1 can be in the range of about 0.1 nanometer to about 100 nanometers. In such a case, since the length L1 of each of the plurality of first bonding surfaces BS1 is significantly smaller than the width W1 of the first air gap AG1 and the width W2 of the second air gap AG2 and smaller than the length L2 of the second bonding surface BS2, the width W1 of the first air gap AG1 and the width W2 of the second air gap AG2 can be determined in the distance D without considering the length L1 of each of the plurality of first bonding surfaces BS1. For example, the length L1 of the first bonding surface BS1 can be modified in various ways considering the size of the first pad 152 or the second pad 232, the process margin, or similar factors, and the embodiments of the present disclosure are not limited to the above values.

[0038] As shown in FIG. 1C, the air gap AG surrounding the bonding pad structure BP can be formed by the first recess 151R and the second recess 231R. For example, the first insulating layer 151 can have a first recess 151R spaced apart from one of the first pads 152 in a first direction (X-axis direction or Y-axis direction), and the second insulating layer 231 can have a second recess 231R that is spaced apart from one of the second pads 232 in the first direction (X-axis direction or Y-axis direction) and overlaps with the first recess 151R in a second direction (Z-axis direction) to provide an air gap AG together with the first recess 151R.

[0039] The first bonding surface BS1 can be formed on a side of the air gap AG adjacent to one of the first pads 152 and one of the second pads 232, and the second bonding surface BS2 can be formed on the other side of the air gap AG opposite to the one side. For example, the first insulating layer 151 and the second insulating layer 231 can be joined between the bonding pad structure BP and the air gap AG to form the first bonding surface BS1 and can be joined on the outside of the air gap AG to form the second bonding surface BS2.

[0040] The shapes of the first recessed portion 151R, the second recessed portion 231R, and the air gap AG are not particularly limited and may have various shapes according to the manufacturing process. For example, the first recessed portion 151R may include a curved surface that is recessed from the first upper surface of the first insulating layer 151 facing the second semiconductor wafer 200 toward the first lower surface opposite to the first upper surface. The second recessed portion 231R may include a curved surface that is recessed from the second lower surface of the second insulating layer 231 facing the first semiconductor wafer 100 toward the second upper surface opposite to the second lower surface.

[0041] The first recessed portion 151R and the second recessed portion 231R (or the air gap AG) may have a predetermined separation distance d from one of the first pads 152 or one of the second pads 232. As described with reference to FIG. 1B, the separation distance d can be used to ensure the bonding reliability between the first pad 152 and the second pad 232, and thus can be formed within various ranges according to the sizes of the first pad 152 and the second pad 232. For example, the separation distance d can be from about 0.1 nm to about 500 nm, from about 0.1 nm to about 400 nm, from about 0.1 nm to about 300 nm, from about 0.1 nm to about 200 nm, from about 0.1 nm to about 100 nm, from about 1 nm to about 100 nm, about 10 nm to about 100 nm, and similar ranges. The separation distance d can be understood to be substantially the same as the length L1 of the first bonding surface BS1 described with reference to FIG. 1B. However, depending on the embodiment, the separation distance d and the length L1 of the first bonding surface BS1 may be different (e.g., the embodiment shown in FIG. 2).

[0042] The first recessed portion 151R and the second recessed portion 231R may be formed to respectively surround one of the first pads 152 and one of the second pads 232 in a plane (e.g., the X-Y plane).

[0043] For example, as shown in FIG. 1D, the air gap AG (or the first recessed portion 151R and the second recessed portion 231R) may be formed to surround at least a part or all of the bonding pad structure BP (or one of the first pads 152 and one of the second pads 232) in a plan view. Additionally, the first bonding surface BS1 may be formed to have a predetermined width w and at least a part or all of the bonding pad structure BP (or one of the first pads 152 and one of the second pads 232) in a plan view. In this case, it can be understood that the width w of the first bonding surface BS1 is similar to the separation distance d shown in FIG. 1C. According to an embodiment, in a manner different from that shown in FIG. 1D (refer to FIG. 1E), the width w of the first bonding surface BS1 may not be constant.

[0044] For example, as shown in FIG. 1E, the first bonding surface BS1' can be formed to have a first width w1 and a second width w2 of different sizes. For example, the first width w1 and the second width w2 can be respectively about 0.1 nm to about 500 nm, about 0.1 nm to about 400 nm, about 0.1 nm to about 300 nm, about 0.1 nm to about 200 nm, about 0.1 nm to about 100 nm, about 1 nm to about 100 nm, about 10 nm to about 100 nm, or similar ranges. The first width w1 and the second width w2 are not limited to the above numerical ranges and can vary depending on the size (width, volume, or similar size) of the first pad 152 or the second pad 232.

[0045] FIG. 2 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure.

[0046] Referring to FIG. 2, in the semiconductor package 10a of the modified example, the length La of the first bonding surface BS1 can be different from the separation distance d1 of the first recess 151R and the separation distance d2 of the second recess 231R, respectively. For example, one of the first recess 151R and the first pad 152 can be spaced apart by the separation distance d1, one of the second recess 231R and the second pad 232 can be spaced apart by the separation distance d2, and the first bonding surface BS1 can have a length La that is respectively shorter than the separation distance d1 and the separation distance d2. The length La of the first bonding surface BS1 can refer to the length of the interface between the first insulating layer 151 and the second insulating layer 231 that respectively falls within the separation distance d1 and the separation distance d2. For example, the difference between the length La of the first bonding surface BS1 and each of the separation distance d1 of the first recess 151R and the separation distance d2 of the second recess 231R can be determined by the misalignment between one of the first pad 152 and one of the second pads 232. This modified example is not limited to the misalignment shown in the figure. For example, even when there is a size difference between the first pad 152 and the second pad 232 (for example, the width of the first pad 152 in the horizontal direction (X-axis direction) is wider than the width of the second pad 232 in the horizontal direction (X-axis direction)), this modified example may also occur.

[0047] FIG. 3 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure.

[0048] Referring to FIG. 3, the semiconductor package 10b of the modified example may have a heterojunction structure, in which different materials are joined to the interface between the first insulating layer 151 and the second insulating layer 231. For example, the second insulating layer 231 may include a lower insulating layer 231b in direct contact with the first insulating layer 151 and an upper insulating layer 231a disposed on the lower insulating layer 231b. To improve the bonding force between the first insulating layer 151 and the second insulating layer 231, the lower insulating layer 231b may include an insulating material different from the insulating material of the first insulating layer 151. For example, the first insulating layer 151 may include silicon oxide (SiO), and the lower insulating layer 231b of the second insulating layer 231 may include silicon carbonitride (SiCN). In this case, the depth dp of the second recess 231R may be equal to or less than the thickness t of the lower insulating layer 231b. For example, the thickness t of the lower insulating layer 231b may be in the range of about 0.1 micrometer to about 2 micrometers.

[0049] FIG. 4 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure.

[0050] Referring to FIG. 4, the semiconductor package 10c of the modified example may include a first insulating layer 151 and / or a second insulating layer 231, and the first insulating layer 151 and / or the second insulating layer 231 includes a plurality of insulating layers. For example, the second insulating layer 231 may include a lower insulating layer 231b in direct contact with the first insulating layer 151 and an upper insulating layer 231a disposed on the lower insulating layer 231b, and the lower insulating layer 231b may include a first lower insulating layer 231b1 and a second lower insulating layer 231b2. The second lower insulating layer 231b2 may contain an insulating material different from that of the first insulating layer 151. For example, the first insulating layer 151 may contain silicon oxide (SiO), and the second lower insulating layer 231b2 may contain silicon carbonitride (SiCN). In addition, the first lower insulating layer 231b1 may contain the same or different material as the second lower insulating layer 231b2. For example, the first lower insulating layer 231b1 may contain silicon oxide (SiO) or silicon carbonitride (SiCN). Even in this modified example, the depth dp of the second recess 231R may still be equal to or less than the thickness t1 of the second lower insulating layer 231b2 located at the lowermost side. For example, the second recess 231R may be formed within the thickness t1 of the second lower insulating layer 231b2, thereby forming an interface between the second lower insulating layer 231b2 and the first insulating layer 151, and thus the interface reliability between the first lower insulating layer 231b1 and the second lower insulating layer 231b2 can be ensured. Compared with the number of insulating layers shown in the figure, the lower insulating layer 231b may include a larger number of insulating layers. In addition, according to the modified example, the first insulating layer 151 may also include a plurality of insulating layers.

[0051] FIG. 5 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure.

[0052] Referring to FIG. 5, the semiconductor package 10d of the modified example may include slots (e.g., a first slot g1 and a second slot g2) formed in the bonding pad structure BP. For example, the first pad 152 may include a first conductive layer 155 and a first barrier layer 153 surrounding the side surface of the first conductive layer 155, and the second pad 232 may include a second conductive layer 235 in contact with at least a portion of the first conductive layer 155 and a second barrier layer 233 surrounding the side surface of the second conductive layer 235. In such a case, the first conductive layer 155 may have a first slot g1 exposing at least a portion of the first barrier layer 153, and the second conductive layer 235 may have a second slot g2 exposing at least a portion of the second barrier layer 233. For example, at least a portion of the inner wall of the first barrier layer 153 and at least a portion of the inner wall of the second barrier layer 233 may be exposed from the first conductive layer 155 and the second conductive layer 235 through the first slot g1 and the second slot g2, respectively. The outer walls of the first barrier layer 153 and the second barrier layer 233 may be covered by the first insulating layer 151 and the second insulating layer 231, respectively, and may not be exposed to the air gap AG. The first slot g1 and the slot g2 may respectively ensure an expansion space for the first conductive layer 155 and the second conductive layer 235 to more stably bond the first pad 152 and the second pad 232 fixed by the first bonding surface BS1 during the bonding and coupling of the first pad 152 and the second pad 232.

[0053] FIG. 6 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure.

[0054] Referring to FIG. 6, the semiconductor package 10e of the modified example may include a first recess 151R and a second recess 231R formed by a photolithography process and an etching process. For example, the first recess 151R may include a first flat surface recessed from a first upper surface of the first insulating layer 151 facing the second semiconductor wafer 200 toward a first lower surface S1 opposite to the first upper surface, and the second recess 231R may include a second flat surface recessed from a second lower surface of the second insulating layer 231 facing the first semiconductor wafer 100 toward a second upper surface S2 opposite to the second lower surface. In this modified example, compared with the case where the first recess 151R and the second recess 231R are formed using a planarization process (e.g., a chemical mechanical polishing (CMP) process), the separation distance between the first recess 151R and the second recess 231R and the length of the first bonding surface BS1 can be easily adjusted.

[0055] FIG. 7 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure.

[0056] Referring to FIG. 7, in the semiconductor package 10f of the modified example, the second semiconductor wafer 200 may be stacked on the first circuit layer 120 of the first semiconductor wafer 100. For example, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be arranged such that the first front surface FR1 faces the second front surface FR2. The first circuit layer 120, the first front insulating layer 131, and the first pads 132 (also referred to as "first front pads") may be disposed on the first front surface FR1 of the first semiconductor wafer 100, and the second circuit layer 220, the second insulating layer 231 (also referred to as "second front insulating layer"), and the second pads 232 (also referred to as "second front pads") may be disposed on the second front surface FR2 of the second semiconductor wafer 200. The first circuit layer 120 may include a first wiring structure 125 electrically connected to the respective devices 115 via the interconnection portions 112 and a first interlayer insulating layer 121 surrounding the first wiring structure 125. Since the first circuit layer 120 has substantially the same characteristics as the second circuit layer 220 described above, a repeated description thereof will be omitted. The first pad 132 may include a barrier layer 133 and a conductive layer 135. The barrier layer 133 and the conductive layer 135 may be formed of the same or similar materials as the first barrier layer 153 and the first conductive layer 155 described above.

[0057] In the present modified example, the first front insulating layer 131 may have a first recess 131R that provides an air gap AG together with the second recess 231R. The first recess 131R may be spaced apart from one of the first pads 132 by a predetermined distance, and a first bonding surface BS1 may be formed between the first recess 131R and one of the first pads 132. In this case, it can be understood that one of the first insulating layer 151 (or the first upper insulating layer) and the first pad 152 is disposed opposite to one of the first front insulating layer 131 and the first pad 132, and the first insulating layer 151 does not include a recess. Additionally, it can be understood that the second insulating layer 231 and the second pads 232 may also be referred to as "second lower insulating layer" and "second lower pads" (or "second front pads"), respectively. For example, the present modified example may have the same or similar characteristics as those described with reference to FIGS. 1A to 6, except that the first semiconductor wafer 100 shown in FIG. 1A is vertically inverted and bonded to the second semiconductor wafer 200.

[0058] FIG. 8 is a cross-sectional view showing a semiconductor package 10A according to an embodiment of the present disclosure.

[0059] Referring to FIG. 8, since the semiconductor package 10A according to the embodiment has the same or similar characteristics as those described with reference to FIGS. 1A to 7, except that it includes a plurality of second semiconductor wafers 200A, 200B, 200C, and 200D stacked on the first semiconductor wafer 100 in the vertical direction (Z-axis direction) and a molding member 160, a repeated description thereof will be omitted.

[0060] A junction interface may be formed between the plurality of second semiconductor wafers 200A, 200B, 200C, and 200D. In the junction interface, the second rear insulating layer 251 and the second insulating layer 231 (also referred to as the "second front insulating layer") are joined together, and the second rear pad 252 and the second pad 232 (also referred to as the "second front pad") are joined together. The plurality of second semiconductor wafers 200A, 200B, 200C, and 200D may be electrically connected to each other through an upper bonding pad structure BPb. One of the second rear pads 252 and one of the second pads 232 are joined and bonded to the upper bonding pad structure BPb. Among the plurality of second semiconductor wafers 200A, 200B, 200C, and 200D, the lowermost second semiconductor wafer 200A may be electrically connected to the first semiconductor wafer 100 through a lower bonding pad structure BPa. One of the second pads 232 and one of the first pads 152 (also referred to as the "first rear pad") of the first semiconductor wafer 100 are joined and bonded to the lower bonding pad structure BPa. In addition, a plurality of air gaps AG may be formed to surround the lower bonding pad structure BPa and the upper bonding pad structure BPb. The plurality of air gaps AG may be formed at a predetermined distance from the lower bonding pad structure BPa or the upper bonding pad structure BPb.

[0061] The plurality of second semiconductor wafers 200A, 200B, 200C, and 200D may have the same or similar structure as the second semiconductor wafer 200 described with reference to FIGS. 1A to 7, except that they further include second vias 240 for forming mutual electrical connection paths. The uppermost second semiconductor wafer 200D may not include the second vias 240 and may have a relatively large thickness. According to the embodiment, more or fewer semiconductor wafers may be stacked on the first semiconductor wafer 100 compared to the number of semiconductor wafers shown in the drawings. For example, three or fewer or five or more semiconductor wafers may be stacked on the first semiconductor wafer 100.

[0062] For example, the first semiconductor chip 100 may be a buffer chip or a control chip including a plurality of logic devices and / or a plurality of memory devices. The first semiconductor chip 100 may transmit signals from the plurality of second semiconductor chips 200A, 200B, 200C, and 200D stacked on the first semiconductor chip 100 to the outside and may also transmit signals and power from the outside to the plurality of second semiconductor chips 200A, 200B, 200C, and 200D. The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may be memory chips including volatile memory devices (such as DRAM or SRAM) or non-volatile memory devices (such as PRAM, MRAM, FeRAM, or RRAM). In this case, the semiconductor package 10A of the present embodiment can be used for high bandwidth memory (HBM) products, electro data processing (EDP) products, or similar products.

[0063] The molding member 160 may be disposed on the first semiconductor chip 100 and may seal at least a part of each of the plurality of second semiconductor chips 200A, 200B, 200C, and 200D. The molding member 160 may be formed to expose the upper surface of the uppermost second semiconductor chip 200D. According to an embodiment, the molding member 160 may be formed to cover the upper surface of the uppermost second semiconductor chip 200D. The molding member 160 may include, for example, an epoxy mold compound (EMC), but the material of the molding member 160 is not particularly limited.

[0064] FIG. 9A is a plan view showing a semiconductor package 10B according to an embodiment of the present disclosure, and FIG. 9B is a cross-sectional view of FIG. 9A taken along line II-II'.

[0065] Referring to FIGS. 9A and 9B, a semiconductor package 10B according to an embodiment may include a package substrate 600, an interposer substrate 700, and at least one package structure PS. Additionally, the semiconductor package 10B may further include a processor chip 800 (or a logic chip) disposed adjacent to the package structure PS on the interposer substrate 700. The package structure PS is shown in the form of the semiconductor package 10A shown in FIG. 8, but is not limited thereto and may have the same or similar characteristics as the semiconductor packages 10, 10a, 10b, 10c, 10d, 10e, and 10f.

[0066] The packaging substrate 600 can be a support substrate with an interposer substrate 700, a processor chip 800, and a packaging structure PS mounted thereon, and can be a substrate for semiconductor packaging, including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a flexible printed circuit board, or a similar substrate. The packaging substrate 600 can include lower pads 612 disposed on the lower surface of the body, upper pads 611 disposed on the upper surface of the body, and a wiring circuit 613 that electrically connects the lower pads 612 and the upper pads 611. Depending on the type of the substrate, the body of the packaging substrate 600 can include different materials. For example, when the packaging substrate 600 is a printed circuit board, the packaging substrate 600 can have a form in which wiring layers are additionally stacked on one or both surfaces of a body copper clad laminate or a copper clad laminate. The lower pads 612, the upper pads 611, and the wiring circuit 613 can form an electrical path connecting the lower surface and the upper surface of the packaging substrate 600. External connection bumps 620 connected to the lower pads 612 can be disposed on the lower surface of the packaging substrate 600. The external connection bumps 620 can include, for example, solder balls.

[0067] The interposer substrate 700 can include a substrate 701, a lower protective layer 703, lower pads 705, an interconnect structure 710, conductive bumps 720, and vias 730. The packaging structure PS and the processor chip 800 can be stacked on the packaging substrate 600 via the interposer substrate 700. The interposer substrate 700 can electrically connect the packaging structure PS and the processor chip 800 to each other.

[0068] The substrate 701 can be formed of any one of, for example, a silicon substrate, an organic material substrate, a plastic substrate, and a glass substrate. When the substrate 701 is a silicon substrate, the interposer substrate 700 can be referred to as a silicon interposer. When the substrate 701 is an organic material substrate, the interposer substrate 700 can be referred to as a panel interposer.

[0069] The lower protective layer 703 can be disposed on the lower surface of the substrate 701, and the lower pads 705 can be disposed on the lower surface of the lower protective layer 703. The lower pads 705 can be connected to the vias 730. The packaging structure PS and the processor chip 800 can be electrically connected to the packaging substrate 600 via the conductive bumps 720 disposed on the lower pads 705.

[0070] The interconnection structure 710 may be disposed on the upper surface of the substrate 701 and may include an interlayer insulating layer 711 and a wiring structure 712. The wiring structure 712 may be provided as a single-layer wiring structure or a multi-layer wiring structure. When the interconnection structure 710 has a multi-layer wiring structure, the wiring patterns of different layers may be connected to each other via contact vias. An upper pad 704 connected to the wiring structure 712 may be disposed on the interconnection structure 710. The packaging structure PS and the processor chip 800 may be connected to the upper pad 704 via the connection bumps 136.

[0071] The through hole 730 may extend from the upper surface to the lower surface of the substrate 701 to penetrate the substrate 701. For example, the through hole 730 may extend into the interconnection structure 710 to be electrically connected to the wiring of the interconnection structure 710. When the substrate 701 is formed of silicon, the through hole 730 may be referred to as a through-silicon via (TSV). According to an embodiment, the interposer substrate 700 may include only the interconnection structure therein, but may not include the through hole.

[0072] The interposer substrate 700 may be used for the purpose of converting or transmitting input electrical signals between the packaging substrate 600 and the packaging structure PS or the processor chip 800. Therefore, the interposer substrate 700 may not include components such as active components, passive components, or similar components. According to an embodiment, the interconnection structure 710 may be disposed below the substrate 701.

[0073] The conductive bumps 720 may be disposed on the lower surface of the interposer substrate 700 and may be electrically connected to the interconnection structure 710. The interposer substrate 700 may be mounted on the packaging substrate 600 via the conductive bumps 720. For example, some of the lower pads 705 for power or ground among the plurality of lower pads 705 may be integrated together and may be connected to the conductive bumps 720, such that the number of the lower pads 705 is greater than the number of the conductive bumps 720.

[0074] The processor chip 800 (or logic chip) may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application specific integrated circuit (ASIC), or a similar device. Depending on the type of integrated circuit included in the processor chip 800, the semiconductor package 10B may be referred to as a server-oriented semiconductor package or a mobile-oriented semiconductor package. According to an embodiment, more or fewer processor chips 800 and / or package structures PS mounted on the interposer substrate 700 may be provided than the number shown in the figures.

[0075] FIG. 10A is a plan view showing a semiconductor package 10C according to an embodiment of the present disclosure, and FIG. 10B is a cross-sectional view of FIG. 10A taken along line III-III'.

[0076] Referring to FIGS. 10A and 10B, a semiconductor package 10C according to an embodiment may include a plurality of second semiconductor chips 200a, 200b, and 200c disposed on a first semiconductor chip 100 in a horizontal direction. In the present embodiment, the plurality of second semiconductor chips 200a, 200b, and 200c (also referred to as "chiplets") may include chiplets constituting a multi-chip module (MCM). For example, the second semiconductor chips 200a, 200b, and 200c may be mounted on the first semiconductor chip 100. According to an embodiment, the second semiconductor chips 200a, 200b, and 200c may be electrically connected to each other via a first wiring structure 125 (e.g., a wiring circuit) of the first semiconductor chip 100. As described with reference to FIGS. 1A to 7, a bonding pad structure BP and a plurality of air gaps AG may be formed between the first semiconductor chip 100 and the second semiconductor chips 200a, 200b, and 200c. The plurality of air gaps AG may be spaced apart from the bonding pad structure BP by a predetermined distance to improve the interface quality between the first pad 152 and the second pad 232.

[0077] The first semiconductor wafer 100 may include an active interposer serving as an I / O wafer. For example, the first semiconductor wafer 100 may include I / O devices, DC / DC converters, sensors, test circuits, or similar devices therein. Since the first semiconductor wafer 100 may include components similar to those of the interposer substrate 700 shown in FIG. 9B, a duplicate description thereof will be omitted. In the drawings, the first semiconductor wafer 100 is shown in the form of a silicon interposer substrate, but the substrate applicable to this embodiment is not limited thereto. The first semiconductor wafer 100 may be mounted on the package substrate 600.

[0078] The second semiconductor wafers 200a, 200b, and 200c may include CPUs, GPUs, FPGAs, or similar devices. The second semiconductor wafers 200a, 200b, and 200c may be formed of different wafers. For example, the second semiconductor wafer 200a may be a GPU wafer, the second semiconductor wafer 200b may be a CPU wafer, and the second semiconductor wafer 200c may be an FPGA wafer. According to an embodiment, the second semiconductor wafers 200a, 200b, and 200c may be formed of the same type of wafers. For example, all of the second semiconductor wafers 200a, 200b, and 200c may include GPU wafers. The number of dies disposed on the first semiconductor wafer 100 is not particularly limited, and for example, two or less than two or four or more than four dies may be mounted on the first semiconductor wafer 100. In such a case, a die or die technology may refer to a semiconductor wafer manufactured separately according to the size and function of the device or to a manufacturing technology of such a semiconductor wafer.

[0079] FIGS. 11A to 11H are cross-sectional views showing a manufacturing process for forming recesses on the back surface of a semiconductor wafer. FIGS. 11A to 11H show a part of the manufacturing process of the first semiconductor wafer 100 shown in FIG. 1A according to the process sequence.

[0080] Referring to FIG. 11A, a first semiconductor wafer WF1 may be prepared, the first semiconductor wafer WF1 including a first preliminary substrate 110p and a plurality of first vias 140 disposed in the first preliminary substrate 110p.

[0081] The first semiconductor wafer WF1 can be temporarily supported on the first carrier substrate C1 by a junction material layer RL (such as glue). The first semiconductor wafer WF1 may include components for a plurality of semiconductor wafers (or "first semiconductor wafers"). Specifically, it may include a first circuit layer 120 formed on the active surface of the first preliminary substrate 110p and a plurality of first through electrodes 140 connected to the wiring structure of the first circuit layer 120. The plurality of first through electrodes 140 may be formed before or during the formation of the first circuit layer 120, but may not be formed to completely penetrate the first preliminary substrate 110p. Additionally, connection bumps 136 buried in the junction material layer RL may be provided below the first semiconductor wafer WF1.

[0082] Referring to FIG. 11B, a portion of the first preliminary substrate 110p can be removed to form a first substrate 110 having a back surface 110BS, and the plurality of first through electrodes 140 protrude from the back surface 110BS.

[0083] The first substrate 110 having a desired thickness can be formed by applying a grinding process to the upper surface (non-active surface) of the first preliminary substrate 110p. The grinding process can be performed by a grinding process such as a CMP process, an etch-back process, or a combination thereof. For example, the grinding process can be performed to reduce the first preliminary substrate 110p to a predetermined thickness, and an etch-back process with appropriate conditions can be applied to sufficiently expose the first through electrodes 140.

[0084] Referring to FIG. 11C, a preliminary protective layer 113p and a preliminary buffer layer 114p can be formed to cover the upper ends 140T of the plurality of first through electrodes 140 protruding from the back surface 110BS of the first substrate 110. The preliminary protective layer 113p can be formed of silicon oxide, and the preliminary buffer layer 114p can be formed of silicon nitride or silicon oxynitride. The preliminary protective layer 113p and the preliminary buffer layer 114p can be formed using a PVD process or a CVD process. Subsequently, the preliminary protective layer 113p and the preliminary buffer layer 114p can be planarized (e.g., ground) to expose the first through electrodes 140. By the planarization process, the preliminary protective layer 113p and the preliminary buffer layer 114p can be removed to reach a predetermined line GL. Additionally, a portion of the upper ends 140T of the first through electrodes 140 can also be removed.

[0085] Referring to FIG. 11D, the first semiconductor wafer WF1 may have a flat surface FS, and the protective layer 113, the buffer layer 114, and the plurality of first vias 140 are exposed from the flat surface FS. As described above, since the upper end portion 140T of the first via 140 may be partially removed by a planarization process, a part of the via plug 145 may be exposed via the flat surface FS.

[0086] Referring to FIG. 11E, a first insulating layer 151 (also referred to as a "back insulating layer") including a first etching groove ER1 may be formed on the flat surface of the first semiconductor wafer WF1 (the flat surface FS shown in FIG. 11D).

[0087] The first etching groove ER1 may be formed by etching at least a part of a preliminary insulating layer formed on the insulating protective layer 113 and the buffer layer 114. The preliminary insulating layer may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN) and may be formed using a PVD or CVD process. The first etching groove ER1 may be formed using, for example, an etching process (e.g., a reactive-ion etching (RIE) process using a photoresist (not shown)).

[0088] Referring to FIG. 11F, a first preliminary barrier layer 153p and a first preliminary conductive layer 155p may be formed on the surface of the first insulating layer 151 and in the first etching groove ER1.

[0089] The first preliminary barrier layer 153p may be conformally formed along the surface of the first insulating layer 151. The first preliminary conductive layer 155p may be formed on the first preliminary barrier layer 153p and may fill the first etching groove ER1. The first preliminary barrier layer 153p and the first preliminary conductive layer 155p may be formed using a plating process, a PVD process, or a CVD process. For example, the first preliminary barrier layer 153p may include titanium (Ti) or titanium nitride (TiN), and the first preliminary conductive layer 155p may include copper (Cu). A seed layer (not shown) including a material the same as that of the first preliminary conductive layer 155p may be formed between the first preliminary barrier layer 153p and the first preliminary conductive layer 155p.

[0090] Referring to FIG. 11G, a first pad 152 (also referred to as a "back pad") including a first barrier layer 153 and a first conductive layer 155 may be formed by polishing the first preliminary barrier layer 153p and the first preliminary conductive layer 155p.

[0091] A part of the first preliminary barrier layer 153p and a part of the first preliminary conductive layer 155p can be removed in the grinding process to form at least one of the first pads 152 including the first barrier layer 153 and the first conductive layer 155. The grinding process can be performed using, for example, a CMP process using a first slurry. The first slurry can have a grinding selectivity with respect to the first preliminary barrier layer 153p, the first preliminary conductive layer 155p, and the first insulating layer 151. For example, a third recess 152R can be formed on the upper surface of one of the first pads 152, and the third recess 152R is recessed from the upper surface 151S of the first insulating layer 151 that has been planarized by the grinding process. The third recess 152R can provide an expansion space for the first conductive layer 155 in a subsequent bonding process of one of the first pads 152.

[0092] Referring to FIG. 11H, the first insulating layer 151 can be ground to form a first recess 151R spaced apart from the one of the first pads 152 by a predetermined distance.

[0093] The grinding process can be performed using, for example, a CMP process using a second slurry. The second slurry can have a grinding selectivity with respect to the first barrier layer 153, the first conductive layer 155, and the first insulating layer 151. For example, the grinding rate of the first insulating layer 151 with respect to the second slurry can be higher than the grinding rates of the first barrier layer 153 and the first conductive layer 155 with respect to the second slurry. Therefore, the first recess 151R that is recessed in the downward direction can be formed on the upper surface 151S of the first insulating layer 151.

[0094] FIGS. 12A to 12D are cross-sectional views showing a manufacturing process for forming a recess on the front surface of a semiconductor wafer. FIGS. 12A to 12D show a part of the manufacturing process of the second semiconductor wafer 200 shown in FIG. 1A according to the manufacturing sequence.

[0095] Referring to FIG. 12A, a second insulating layer 231 including a second etching groove ER2 can be formed on the second semiconductor wafer WF2.

[0096] The second semiconductor wafer WF2 may include a second preliminary substrate 210p, a second circuit layer 220 disposed on the front surface of the second preliminary substrate 210p, and a second insulating layer 231 disposed on the second circuit layer 220. The second semiconductor wafer WF2 may be supported by a second carrier substrate C2 and temporarily bonded to the second carrier substrate C2. The second etching groove ER2 may be formed by etching at least a portion of the preliminary insulating layer formed on the second circuit layer 220. The preliminary insulating layer may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN) and may be formed using a PVD or CVD process. The second etching groove ER2 may be formed using, for example, an etching process (e.g., a reactive ion etching (RIE) process using a photoresist (not shown)).

[0097] Referring to FIG. 12B, a second preliminary barrier layer 233p and a second preliminary conductive layer 235p may be formed on the surface of the second insulating layer 231 and in the second etching groove ER2.

[0098] The second preliminary barrier layer 233p may be conformally formed along the surface of the second insulating layer 231. The second preliminary conductive layer 235p may be formed on the second preliminary barrier layer 233p and may fill the second etching groove ER2. The second preliminary barrier layer 233p and the second preliminary conductive layer 235p may be formed using a plating process, a PVD process, or a CVD process. For example, the second preliminary barrier layer 233p may include titanium (Ti) or titanium nitride (TiN), and the second preliminary conductive layer 235p may include copper (Cu). A seed layer (not shown) including a material the same as that of the second preliminary conductive layer 235p may be formed between the second preliminary barrier layer 233p and the second preliminary conductive layer 235p.

[0099] Referring to FIG. 12C, a second pad 232 including a second barrier layer 233 and a second conductive layer 235 may be formed by polishing the second preliminary barrier layer 233p and the second preliminary conductive layer 235p.

[0100] A part of the second preliminary conductive layer 235p and a part of the second preliminary barrier layer 233p can be removed during the grinding process to form a second pad 232 including a second conductive layer 235 and a second barrier layer 233. The grinding process can be performed using, for example, a CMP process using a first slurry. The first slurry can have a grinding selectivity with respect to the second preliminary barrier layer 233p, the second preliminary conductive layer 235p, and the second insulating layer 231. For example, the grinding rate of the second insulating layer 231 with respect to the first slurry can be lower than the grinding rates of the second preliminary barrier layer 233p and the second preliminary conductive layer 235p with respect to the first slurry. For example, a fourth recess 232R can be formed on the upper surface of one of the second pads 232, and the fourth recess 232R is recessed from the upper surface 231S of the second insulating layer 231 that has been planarized by the grinding process. The fourth recess 232R can provide an expansion space for the second conductive layer 235 during a subsequent bonding process of one of the second pads 232.

[0101] Referring to FIG. 12D, the second insulating layer 231 can be ground to form a second recess 231R spaced apart from one of the second pads 232 by a predetermined distance.

[0102] The grinding process can be performed using, for example, a CMP process using a second slurry. The second slurry can have a grinding selectivity with respect to the second barrier layer 233, the second conductive layer 235, and the second insulating layer 231. For example, the grinding rate of the second insulating layer 231 with respect to the second slurry can be higher than the grinding rates of the second barrier layer 233 and the second conductive layer 235 with respect to the second slurry. For example, a second recess 231R that is recessed in the downward direction of the second insulating layer 231 can be formed on the upper surface 231S of the second insulating layer 231. Thereafter, a plurality of semiconductor wafers 200 (or "second semiconductor wafers") having a desired thickness can be formed by grinding the back surface of the second preliminary substrate 210p.

[0103] FIG. 13 is a cross-sectional view showing a manufacturing process of the semiconductor package 10 shown in FIG. 1A.

[0104] Referring to FIG. 13, first, a semiconductor wafer WF provided for a plurality of first semiconductor wafers 100 can be prepared. The semiconductor wafer WF can be formed by the manufacturing process shown in FIGS. 11A to 11H. The semiconductor wafer WF can include a plurality of first pads 152 (also referred to as "rear pads") and a first insulating layer 151 surrounding the plurality of first pads 152. The first insulating layer 151 can include a plurality of first recesses 151R spaced apart from the plurality of first pads 152. The semiconductor wafer WF can be supported on a temporary carrier CW by a bonding material layer RL.

[0105] Next, a plurality of second semiconductor wafers 200 may be prepared. The plurality of second semiconductor wafers 200 may be formed by the manufacturing process shown in FIGS. 12A to 12D. The plurality of second semiconductor wafers 200 may include a plurality of second pads 232 and a second insulating layer 231 surrounding the plurality of second pads 232. The second insulating layer 231 may include a plurality of second recesses 231R spaced apart from the plurality of second pads 232. The semiconductor wafer WF and the plurality of second semiconductor wafers 200 may not be provided sequentially, but may be formed by independent manufacturing processes.

[0106] Next, the plurality of second semiconductor wafers 200 may be disposed on the semiconductor wafer WF. The plurality of second semiconductor wafers 200 may be disposed on the plurality of first semiconductor wafers 100 of the semiconductor wafer WF using, for example, a pick-and-place device. The plurality of second semiconductor wafers 200 may be aligned with the plurality of first semiconductor wafers 100 such that an air gap AG is formed between the first recess 151R and the second recess 231R. Accordingly, the plurality of first pads 152 may be in contact with the plurality of second pads 232, and the first insulating layer 151 may be in contact with the second insulating layer 231 in the remaining portion except for the air gap AG.

[0107] Next, a thermal compression process may be performed to bond the first insulating layer 151 and the second insulating layer 231 that are joined to each other and to bond the plurality of first pads 152 and the plurality of second pads 232 that are joined to each other. The thermal compression process may be performed such that the first insulating layer 151 and the second insulating layer 231 are first bonded and then the plurality of first pads 152 and the plurality of second pads 232 are bonded. For example, in the thermal compression process, the first insulating layer 151 and the second insulating layer 231 may be bonded in a hot atmosphere having a temperature of about 100 degrees Celsius to about 200 degrees Celsius, and the plurality of first pads 152 and the plurality of second pads 232 may be bonded in a hot atmosphere having a temperature of about 200 degrees Celsius to about 300 degrees Celsius. The temperature range of the hot atmosphere is not limited to the above range (about 100 degrees Celsius to about 300 degrees Celsius) and may be changed in various ways. During the thermal compression process, the third recesses 152R of the plurality of first pads 152 and the fourth recesses 232R of the plurality of second pads 232 may be expanded to form a third bonding surface BS3 between the plurality of first pads 152 and the plurality of second pads 232. According to an embodiment of the present disclosure, since the first bonding surface BS1 may be formed before the third bonding surface BS3 is formed, the bonding area or the expanded area of one of the first pads 152 and one of the second pads 232 may be restricted by the first insulating layer 151 and the second insulating layer 231. Therefore, the quality of the bonding interface (the third bonding surface BS3) between one of the first pads 152 and one of the second pads 232 may be improved, and the reliability of the bonded pad structure BP may be ensured.

[0108] According to an embodiment of the present disclosure, a semiconductor package and a method of manufacturing the semiconductor package may be provided. The semiconductor package has improved reliability by introducing an air gap spaced apart from the bonded pad structure and implements a semiconductor wafer stack having an excellent quality bonding interface.

[0109] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure.

Brief Description of the Drawings

[0012] Referring to the following detailed description in conjunction with the accompanying drawings, the above and other aspects, features, and advantages of the embodiments of the present disclosure will be more clearly understood. In the accompanying drawings, FIG. 1A is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. FIG. 1B is a partial enlarged view showing part "A" shown in FIG. 1A. FIG. 1C is a partial enlarged view showing part "B" shown in FIG. 1A. FIG. 1D is a first plan view of FIG. 1C taken along line I-I'. FIG. 1E is a second plan view of FIG. 1C taken along line I-I'. FIG. 2 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure. FIG. 3 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure. FIG. 4 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure. FIG. 5 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure. FIG. 6 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure. FIG. 7 is a partial enlarged view showing a modified example of a semiconductor package according to an embodiment of the present disclosure. FIG. 8 is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. FIG. 9A is a plan view showing a semiconductor package according to an embodiment of the present disclosure. FIG. 9B is a cross-sectional view of FIG. 9A taken along line II-II'. FIG. 10A is a plan view showing a semiconductor package according to an embodiment of the present disclosure. FIG. 10B is a cross-sectional view of FIG. 10A taken along line III-III'. FIG. 11A is a first cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 11B is a second cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 11C is a third cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 11D is a fourth cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 11E is a fifth cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 11F is a sixth cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 11G is a seventh cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 11H is an eighth cross-sectional view showing a manufacturing process for forming a recess on the back surface of a semiconductor wafer. FIG. 12A is a first cross-sectional view showing a manufacturing process for forming a recess on the front surface of a semiconductor wafer. FIG. 12B is a second cross-sectional view showing a manufacturing process for forming a recess on the front surface of a semiconductor wafer. FIG. 12C is a third cross-sectional view showing a manufacturing process for forming a recess on the front surface of a semiconductor wafer. FIG. 12D is a fourth cross-sectional view showing a manufacturing process for forming a recess on the front surface of a semiconductor wafer. FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor package shown in FIG. 1A.

Claims

1. A semiconductor package, comprising: A first semiconductor wafer includes a first substrate, a first pad, and a first insulating layer, the first pad being located above the first substrate and the first insulating layer being located above the first substrate and surrounding the first pad; and a second semiconductor wafer is located on the first semiconductor wafer, the second semiconductor wafer including a second substrate, a second pad, and a second insulating layer, the second pad being located below the second substrate and contacting the first pad, the second insulating layer being located below the second substrate, surrounding the second pad, and contacting the first insulating layer, wherein the first insulating layer includes a first recess spaced apart from the first pad in a first direction, wherein the second insulating layer includes a second recess spaced apart from the second pad in the first direction, the second recess overlapping at least a portion of the first recess in a second direction perpendicular to the first direction, an air gap existing between the first recess and the second recess, and wherein the semiconductor package further includes: a first bonding surface defined on one side of the air gap adjacent to the first pad and the second pad by the first insulating layer and the second insulating layer in contact with each other; and a second bonding surface defined on the other side of the air gap opposite to the one side by the first insulating layer and the second insulating layer in contact with each other.

2. The semiconductor package of claim 1, wherein the first recess and the first pad are spaced apart from each other by a first distance in the first direction, wherein the second recess and the second pad are spaced apart from each other by a second distance in the first direction, and wherein the length of the first bonding surface in the first direction is equal to or shorter than each of the first distance and the second distance.

3. The semiconductor package as claimed in claim 2, wherein each of the first distance and the second distance is in the range of 0.1 nanometers to 500 nanometers.

4. The semiconductor package of claim 1, wherein each of the first recess and the second recess surrounds each of the first pad and the second pad in a plane.

5. The semiconductor package as claimed in claim 4, wherein each of the first recess and the second recess completely surrounds each of the first pad and the second pad.

6. The semiconductor package of claim 1, wherein the first recess includes a curved surface recessed from a first upper surface of the first insulating layer facing the second semiconductor wafer toward a first lower surface of the first insulating layer opposite to the first upper surface, and wherein the second recess includes a curved surface recessed from a second lower surface of the second insulating layer facing the first semiconductor wafer toward a second upper surface of the second insulating layer opposite to the second lower surface.

7. The semiconductor package of claim 1, wherein the first recess includes a first flat surface recessed from a first upper surface of the first insulating layer facing the second semiconductor wafer toward a first lower surface of the first insulating layer opposite to the first upper surface, and wherein the second recess includes a second flat surface recessed from a second lower surface of the second insulating layer facing the first semiconductor wafer toward a second upper surface of the second insulating layer opposite to the second lower surface.

8. The semiconductor package of claim 1, wherein the second insulating layer includes a lower insulating layer in direct contact with the first insulating layer and an upper insulating layer located on the lower insulating layer, wherein the lower insulating layer comprises an insulating material different from the insulating material of the first insulating layer.

9. The semiconductor package of claim 8, wherein the first insulating layer comprises silicon oxide (SiO) and wherein the lower insulating layer of the second insulating layer comprises silicon carbonitride (SiCN).

10. The semiconductor package of claim 8, wherein the depth of the second recess is equal to or less than the thickness of the lower insulating layer.

11. The semiconductor package of claim 1, wherein the first pad includes a first conductive layer and a first barrier layer surrounding a side surface of the first conductive layer, and wherein the second pad includes a second conductive layer in contact with at least a portion of the first conductive layer and further includes a second barrier layer surrounding a side surface of the second conductive layer.

12. The semiconductor package of claim 11, wherein the first conductive layer includes a first trench exposing at least a portion of the first barrier layer, and wherein the second conductive layer includes a second trench exposing at least a portion of the second barrier layer.

13. The semiconductor package of claim 1, wherein the first semiconductor wafer further includes a first circuit layer, a lower pad and a first through electrode, the first circuit layer being located below the first substrate, the lower pad being located below the first circuit layer, and the first through electrode passing through the first substrate and electrically connected to the first pad and the lower pad.

14. A semiconductor package, comprising: A first semiconductor wafer includes a first substrate, a plurality of first pads, and a first insulating layer, wherein the plurality of first pads are located above the first substrate, and the first insulating layer is located above the first substrate and surrounds the plurality of first pads; and a second semiconductor wafer is located on the first semiconductor wafer, the second semiconductor wafer including a second substrate, a plurality of second pads, and a second insulating layer, wherein the plurality of second pads are located below the second substrate, and the second insulating layer is located below the second substrate and surrounds the plurality of second pads, wherein the first semiconductor wafer and the second semiconductor wafer are electrically connected to each other by a pair of first bonding pad structures and second bonding pad structures, each of the first bonding pad structure and the second bonding pad structure including one of the plurality of first pads and one of the plurality of second pads, wherein the semiconductor package further includes a first air gap surrounding the first bonding pad structure and a second air gap surrounding the second bonding pad structure, and wherein the semiconductor package further includes: A first bonding surface is defined between the first bonding pad structure and the first air gap, and between the second bonding pad structure and the second air gap, by at least a portion of the first insulating layer and at least a portion of the second insulating layer that are in contact with each other; and a second bonding surface is defined between the first air gap and the second air gap by at least a portion of the first insulating layer and at least a portion of the second insulating layer that are in contact with each other.

15. The semiconductor package of claim 14, wherein the length of each of the first bonding surfaces is less than the width of each of the first air gap and the second air gap.

16. The semiconductor package of claim 15, wherein the width of each of the first air gap and the second air gap is 5% to 25% of the spacing between the first bonding pad structure and the second bonding pad structure.

17. The semiconductor package of claim 14, wherein the length of the second bonding surface is equal to or greater than the sum of the width of the first air gap and the width of the second air gap.

18. A semiconductor package, comprising: A first semiconductor wafer includes a first substrate, a first pad, and a first insulating layer, the first pad being located above the first substrate, and the first insulating layer including a first recess surrounding the first pad; and a second semiconductor wafer located on the first semiconductor wafer, the second semiconductor wafer including a second substrate, a second pad, and a second insulating layer, the second pad being located below the second substrate and contacting the first pad, the second insulating layer including a second recess surrounding the second pad, wherein the second insulating layer contacts the first insulating layer, and wherein the side surfaces of each of the first pad and the second pad are completely covered by the first insulating layer and the second insulating layer, respectively, wherein at least a portion of the first insulating layer is located between the side surface of the first pad and the first recess, and wherein at least a portion of the second insulating layer is located between the side surface of the second pad and the second recess.

19. The semiconductor package of claim 18, wherein the portion of the first insulating layer is in contact with the portion of the second insulating layer.

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