Semiconductor devices

Abstract

A semiconductor device capable of miniaturization or hyper-integration is provided. The semiconductor device includes a transistor. The transistor includes an oxide, a first conductor and a second conductor on the oxide, a first insulator on the first and second conductors, a second insulator within an opening included in the first insulator, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. The opening includes a region overlapping with the oxide. The third conductor includes a region overlapping with the oxide across the second, third, and fourth insulators. The second insulator is in contact with the top surface of the oxide and the sidewall of the opening. The thickness of the second insulator is smaller than the thickness of the third insulator. The fourth insulator is less permeable to oxygen than the third insulator. In a cross-section along the channel length of the transistor, the width of the third conductor is 3 nm or more and 15 nm or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a method for manufacturing a metal oxide. Furthermore, one embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Furthermore, one embodiment of the present invention relates to a method for manufacturing a semiconductor device. Furthermore, one embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing units, or memory devices are also embodiments of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting equipment, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-described technical field. One embodiment of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. Prior Technology

[0004] In recent years, semiconductor devices have been developed, with LSIs, CPUs, and memory chips being the main components used in them. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory chips) formed by processing semiconductor wafers to create a chip, and which has electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards (e.g., printed circuit boards) and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. Among other materials, oxide semiconductors have also garnered interest.

[0007] Furthermore, it is known that the leakage current of oxide semiconductor transistors is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of oxide semiconductor transistors. Additionally, Patent Document 2 discloses a memory device that utilizes the low leakage current characteristic of oxide semiconductor transistors to achieve long-term retention of stored content.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices incorporating integrated circuits.

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 Summary of the Invention

[0010] One objective of one embodiment of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Another objective of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with small transistor electrical characteristic non-uniformity. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with high reliability. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with large on-state current. Furthermore, one objective of one embodiment of the present invention is to provide a low-power semiconductor device.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not need to achieve all of the above objectives. Note that objectives other than those described above can be derived from the description in the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes: an oxide; a first conductor and a second conductor on the oxide; a first insulator having an opening on the first and second conductors; a second insulator within the opening of the first insulator; a third insulator on the second insulator; a fourth insulator on the third insulator; and a third conductor on the fourth insulator. The opening of the first insulator includes a region overlapping with the oxide. The third conductor, separated by the second, third, and fourth insulators, includes a region overlapping with the oxide. The second insulator includes a region contacting the top surface of the oxide and the sidewall of the opening of the first insulator. The second insulator includes a region whose thickness is smaller than that of the third insulator. The fourth insulator is less permeable to oxygen compared to the third insulator. In a cross-section along the channel length of the transistor, the third conductor includes a region with a width of 3 nm or more and 15 nm or less.

[0013] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes: an oxide; a first conductor and a second conductor on the oxide; a first insulator having an opening on the first and second conductors; a second insulator within the opening of the first insulator; a third insulator on the second insulator; a fourth insulator on the third insulator; and a third conductor on the fourth insulator. The opening of the first insulator includes a region overlapping with the oxide. The third conductor, separated by the second, third, and fourth insulators, includes a region overlapping with the oxide. The second insulator includes a region in contact with the top surface of the oxide and the sidewall of the opening of the first insulator. The second insulator includes a region whose thickness is smaller than that of the third insulator. The fourth insulator is less permeable to oxygen compared to the third insulator. In a cross-section along the channel length direction of the transistor, the third conductor includes a region with a width of 3 nm or more and 15 nm or less. In a cross-section along the channel length direction of the transistor, the distance between the lower end of the first conductor and the lower end of the second conductor is 10 nm or more and less than 40 nm.

[0014] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes: an oxide; a first conductor and a second conductor on the oxide; a first insulator having an opening on the first conductor and the second conductor; a second insulator within the opening of the first insulator; a third insulator on the second insulator; a fourth insulator on the third insulator; a third conductor on the fourth insulator; and a fifth insulator. The opening of the first insulator includes a region overlapping with the oxide. The third conductor includes a region overlapping with the oxide across the second, third, and fourth insulators. The second insulator includes a region in contact with the top surface of the oxide and the sidewall of the opening of the first insulator. The second insulator includes a region whose thickness is smaller than that of the third insulator. The fourth insulator is less permeable to oxygen compared to the third insulator. In a cross-section along the channel length of the transistor, the third conductor includes a region with a width of 3 nm or more and 15 nm or less. A fifth insulator is disposed between the first conductor and the second conductor and the first insulator. The fifth insulator includes an opening that overlaps with the opening of the first insulator. The fifth insulator is less permeable to oxygen than the third insulator. The fifth insulator includes a region that contacts the sidewalls of the oxide, the sidewalls of the first conductor, and the sidewalls of the second conductor. The second insulator includes a region that contacts the sidewall of the opening of the fifth insulator. The oxide comprises indium, zinc, and one or more selected from gallium, aluminum, and tin. The oxide is crystalline, and the c-axis of the crystal is substantially perpendicular to the surface of the oxide or the surface in which it is formed.

[0015] In the aforementioned semiconductor device, preferably, the third conductor is a stack of the fourth conductor and the fifth conductor on the fourth conductor, and the first conductor, the second conductor, and the fifth conductor all contain metal and nitrogen.

[0016] In the aforementioned semiconductor device, preferably, the transistor includes a first layer and a second layer, the first layer being located between a first conductor and a second insulator, the second layer being located between a second conductor and a second insulator, the length of the channel in the first layer being smaller than its width, the length of the channel in the second layer being smaller than its width, and both the first layer and the second layer containing metal and oxygen.

[0017] In the aforementioned semiconductor device, preferably, the bottom surface of the third conductor includes a flat region, and the width is the width of the flat region.

[0018] In the aforementioned semiconductor device, preferably, the third conductor has an arc-shaped bottom surface with its curvature center located within the third conductor, and its width is the width of the region where a straight line including the curvature center and parallel to the bottom surface of the oxide overlaps with the third conductor.

[0019] In the aforementioned semiconductor device, preferably, the oxide includes a region in which the thickness of the region of the oxide overlapping with the third conductor is smaller than the thickness of the region of the oxide overlapping with the first conductor.

[0020] In the aforementioned semiconductor device, it is preferable that the cutoff frequency of the transistor is above 100 GHz at room temperature.

[0021] According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Additionally, according to one embodiment of the present invention, a semiconductor device with small transistor electrical characteristic non-uniformity can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Additionally, according to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. Furthermore, according to one embodiment of the present invention, a low-power semiconductor device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all the above-described effects. Note that effects other than those described above can be learned and derived from the description in the specification, drawings, claims, etc. Simple Explanation of the Diagram

[0023] [Figure 1A] is a top view of a semiconductor device according to an embodiment of the present invention. [Figures 1B] to [Figure 1D] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 2A] and [Figure 2B] are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 3] is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figures 4A to 4F are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 5A] and [Figure 5B] are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 6A] is a top view of a semiconductor device according to an embodiment of the present invention. [Figures 6B] to [Figure 6D] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 7A] is a top view of a semiconductor device according to an embodiment of the present invention. [Figures 7B] to [Figure 7D] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 8A] is a top view of a semiconductor device according to an embodiment of the present invention. [Figures 8B] to [Figure 8D] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 9A] is a top view of a semiconductor device according to an embodiment of the present invention. [Figures 9B] to [Figure 9D] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Fig. 10A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 10B] to [Fig. 10D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 11A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 11B] to [Fig. 11D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 12A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 12B] to [Fig. 12D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 13A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 13B] to [Fig. 13D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 14A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 14B] to [Fig. 14D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 15A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 15B] to [Fig. 15D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 16A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 16B] to [Fig. 16D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 17A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 17B] to [Fig. 17D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 18A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 18B] to [Fig. 18D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 19A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 19B] to [Fig. 19D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 20A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 20B] to [Fig. 20D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] is a top view illustrating a microwave processing apparatus according to an embodiment of the present invention. [Figure 22] is a cross-sectional schematic diagram illustrating a microwave processing apparatus according to an embodiment of the present invention. [Figure 23] is a cross-sectional schematic diagram illustrating a microwave processing apparatus according to an embodiment of the present invention. [Figure 24] is a schematic diagram illustrating a microwave processing apparatus according to an embodiment of the present invention. [Figure 25A] is a top view of a semiconductor device according to an embodiment of the present invention. [Figure 25B] and [Figure 25C] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 26] is a cross-sectional view showing the structure of a memory device according to an embodiment of the present invention. [Figure 27] is a cross-sectional view showing the structure of a memory device according to an embodiment of the present invention. [Figure 28] is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 29A] and [Figure 29B] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 30] is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 31A] is a block diagram showing a structural example of a memory device according to an embodiment of the present invention. [Figure 31B] is a perspective view showing a structural example of a memory device according to an embodiment of the present invention. Figures 32A to 32H are circuit diagrams illustrating a structural example of a memory device according to an embodiment of the present invention. [Figure 33A] and [Figure 33B] are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 34A] and [Figure 34B] are diagrams illustrating an example of an electronic component. Figures 35A to 35E are schematic diagrams of a memory device according to an embodiment of the present invention. Figures 36A to 36H are diagrams illustrating an electronic device according to one embodiment of the present invention. Figures 37A to 37C are schematic diagrams showing the structure of the prototype transistor. [Figure 38A] and [Figure 38B] are planar SEM images of the tested samples. [Fig. 39A] and [Fig. 39B] are cross-sectional STEM images of the manufactured sample. [Fig. 39C] is a cross-sectional STEM image of the metal oxide. [Fig. 39D] is a localized Fourier transform image. [Figure 40A] and [Figure 40B] show the Id-Vg characteristics of the transistor. [Figure 41] is a plot showing the normal probability distribution of Vth. [Figure 42] is a graph illustrating the size dependence of Vth. [Figure 43A] is a diagram showing the circuit for measuring the off-state current. [Figure 43B] is a diagram showing the temperature dependence of the off-state current. [Figure 44A] is a diagram illustrating the evaluation environment for cutoff frequency measurement. [Figure 44B] is a diagram illustrating the TEG for cutoff frequency measurement. [Figure 45A] and [Figure 45B] are graphs showing the measurement results of the transistor's cutoff frequency. [Figure 46] is a diagram showing the route of the OS transistor. [Figure 47] shows the Id-Vd characteristics of the transistor. [Figure 48A] is a graph showing the measurement results of the transistor's cutoff frequency. [Figure 48B] is a graph showing the measurement results of the transistor's maximum oscillation frequency. Figures 49A to 49D show the Id-Vg characteristics of the transistor. Figures 50A to 50D show the Id-Vg characteristics of the transistor. [Figure 51] is a schematic diagram showing the structure of the prototype. [Figure 52A] and [Figure 52B] show the Id-Vg characteristics of the transistor. Implementation

[0024] The embodiments will now be described with reference to the drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0025] In the drawings, for obvious purposes, sizes, layer thicknesses, or areas are sometimes exaggerated. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples, and the invention is not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or photoresist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, in the drawings, the same element symbols are sometimes used across different drawings to represent the same parts or parts with the same function, omitting redundant descriptions. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without specifically adding element symbols.

[0026] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some components are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines are sometimes omitted.

[0027] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the process sequence or stacking order. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present invention.

[0028] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate configuration and to illustrate the positional relationships of components with reference to diagrams. Furthermore, the positional relationships of components may be appropriately changed depending on the orientation of each component being described. Therefore, the use of terms not limited to those described in the specification may be modified as appropriate.

[0029] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, connection relationships other than those shown in the drawings or text are disclosed in the drawings or text, not limited to those specified therein. Here, X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0030] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel-forming region (hereinafter also referred to as a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), through which current can flow between the source and drain. Note that in this specification, the channel-forming region refers to the region through which current primarily flows.

[0031] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0032] Note that channel length, for example, refers to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the conducting state) and gate electrode in a top view of the transistor, or between the source (source region or source electrode) and drain (drain region or drain electrode) in the channel-forming region. Furthermore, the channel length in a transistor is not necessarily the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, channel length refers to any value, maximum value, minimum value, or average value in the channel-forming region.

[0033] Channel width, for example, refers to the length of the channel-forming region perpendicular to the channel length direction within the overlapping area of ​​the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the conducting state) and gate electrode in a top view of the transistor. Furthermore, the channel width in a transistor is not necessarily the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value within the channel-forming region.

[0034] In this specification, depending on the transistor's structure, the actual channel width (hereinafter also referred to as "effective channel width") in the region forming the channel sometimes differs from the channel width shown in the transistor's top view (hereinafter also referred to as "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, sometimes the effective channel width is greater than the apparent channel width, and its effect cannot be ignored. For example, in miniature transistors where the gate electrode covers the side of the semiconductor, sometimes the proportion of the channel formation region formed on the side of the semiconductor is increased. In this case, the effective channel width is greater than the apparent channel width.

[0035] In the aforementioned situations, it can sometimes be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width based on design values, it is necessary to know the assumed shape of the semiconductor beforehand. Therefore, when the shape of the semiconductor is uncertain, it is difficult to accurately measure the effective channel width.

[0036] In this specification, when simply described as "channel width," it sometimes refers to the visual channel width. Alternatively, in this specification, when simply referred to as "channel width," it sometimes refers to the effective channel width. Note that, for example, the values ​​of channel length, channel width, effective channel width, or visual channel width can be determined by analyzing cross-sectional TEM images.

[0037] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density of the semiconductor, a decrease in crystallinity, etc. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to the formation of oxygen vacancies (also known as VO₂) in the oxide semiconductor.

[0038] Note that in this specification, silicon oxynitride refers to a substance with an oxygen content greater than its nitrogen content. Similarly, silicon oxynitride refers to a substance with a nitrogen content greater than its oxygen content. Furthermore, aluminum oxynitride refers to a substance with an oxygen content greater than its nitrogen content. Additionally, hafnium oxynitride refers to a substance with an oxygen content greater than its nitrogen content.

[0039] Note that in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Additionally, "conductor" may be replaced with "conductive film" or "conductive layer". Furthermore, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0040] In this specification, "parallel" refers to a state where the angle formed by two straight lines is between -10° and 10°. Therefore, it also includes a state where the angle is between -5° and 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is between -30° and 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is between 80° and 100°. Therefore, it also includes a state where the angle is between 85° and 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is between 60° and 120°.

[0041] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0042] Note that in this specification, "normally off" means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor with a channel width of 1 μm is less than 1 × 10⁻²⁰ A at room temperature, less than 1 × 10⁻¹⁸ A at 85 °C, or less than 1 × 10⁻¹⁶ A at 125 °C.

[0043] Furthermore, in this instruction manual and other documents, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference between the reference potential and the reference potential; for example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Grounding potential does not necessarily mean 0V. Furthermore, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0044] Furthermore, in this specification and other documents, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", or "[m,n]" are sometimes added to the symbol for identification.

[0045] Note that in this specification, "height consistent or substantially consistent" refers to a structure in which the height from a reference surface (e.g., a flat surface such as a substrate surface) is equal when viewed in cross-section. For example, in the manufacturing process of semiconductor devices, planarization (typically CMP) is sometimes performed to expose the surfaces of one or more layers. In this case, the surface being processed in the CMP process is at the same height from the reference surface. Note that depending on the processing apparatus, processing method, or material of the surface being processed during CMP, the heights of multiple layers may differ. In this specification, "height consistent or substantially consistent" also includes the above-mentioned cases. For example, in the case where there are layers with two heights relative to a reference surface (here referred to as the first layer and the second layer), when the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, it is also referred to as "height consistent or substantially consistent".

[0046] Note that in this specification, "end-to-end overlap or substantially overlap" means that at least a portion of the outlines of stacked layers overlap when viewed from above. For example, this includes cases where the upper and lower layers are processed using the same masking pattern or a portion thereof. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is inside or outside the outline of the lower layer; these cases are also included in "end-to-end overlap or substantially overlap".

[0047] In this specification, the off-state current is sometimes referred to as leakage current. In this specification, the off-state current sometimes refers to the current flowing between the source and drain when the transistor is in the off state.

[0048] Implementation Method 1 In this embodiment, an example of a semiconductor device according to one embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1A to 20D. The semiconductor device according to one embodiment of the present invention includes a transistor.

[0049] <Examples of semiconductor device structures> The structure of the semiconductor device including transistor 200 will be described with reference to FIG1. ​​FIG1A to FIG1D are top views and cross-sectional views of the semiconductor device including transistor 200. FIG1A is a top view of the semiconductor device. FIG1B to FIG1D are cross-sectional views of the semiconductor device. Here, FIG1B is a cross-sectional view along the dotted line A1-A2 in FIG1A, which is also a cross-sectional view along the channel length direction of transistor 200. In addition, FIG1C is a cross-sectional view along the dotted line A3-A4 in FIG1A, which is also a cross-sectional view along the channel width direction of transistor 200. In addition, FIG1D is a cross-sectional view along the dotted line A5-A6 in FIG1A. Note that in the top view of FIG1A, some components are omitted for clarity.

[0050] A semiconductor device according to one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 285 on the insulator 283 and the insulator 274. Insulators 212, 214, 280, 282, 283, 285, 274, and 285 are used as interlayer films. Furthermore, it includes conductors 240a and 240b electrically connected to the transistor 200 and used as plugs. Additionally, it includes an insulator 241a in contact with the side of conductor 240a and an insulator 241b in contact with the side of conductor 240b. Additionally, a conductor 246a, electrically connected to the conductor 240a and used for wiring, is provided on the insulator 285 and the conductor 240a, and a conductor 246b, electrically connected to the conductor 240b and used for wiring, is provided on the insulator 285 and the conductor 240b. Furthermore, the insulator 283 is in contact with a portion of the top surface of the insulator 214, the side surface of the insulator 280, and the side and top surfaces of the insulator 282.

[0051] An insulator 241a is disposed in contact with the inner wall of the openings of insulators 280, 282, 283, and 285, and a conductor 240a is disposed in contact with the side of insulator 241a. Similarly, an insulator 241b is disposed in contact with the inner wall of the openings of insulators 280, 282, 283, and 285, and a conductor 240b is disposed in contact with the side of insulator 241b. Furthermore, both insulators 241a and 241b have a structure in which a first insulator is disposed in contact with the inner wall of the openings and a second insulator is disposed inside it. Additionally, conductor 240a has a structure in which a first conductor is disposed in contact with the side of insulator 241a and a second conductor is disposed inside it. Similarly, conductor 240b has a structure in which a first conductor is disposed in contact with the side of insulator 241b and a second conductor is disposed inside it. Here, the top surface height of conductor 240a can be approximately the same as the top surface height of insulator 285 in the region overlapping conductor 246a. Similarly, the top surface height of conductor 240b can be approximately the same as the top surface height of insulator 285 in the region overlapping conductor 246b.

[0052] Furthermore, in transistor 200, each of insulators 241a and 241b has a first insulator and a second insulator stacked on top of it, but the present invention is not limited thereto. For example, insulators 241a and 241b may also have a single-layer structure or a stacked structure of three or more layers. Furthermore, in transistor 200, each of conductors 240a and 240b has a first conductor and a second conductor stacked on top of it, but the present invention is not limited thereto. For example, conductors 240a and 240b may also have a single-layer structure or a stacked structure of three or more layers. Furthermore, when the structure has a stacked structure, sometimes ordinal numbers are assigned according to the order of formation for distinction.

[0053] [Transistor 200] As shown in Figures 1A to 1D, the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a and 205b) disposed in the insulator 216, an insulator 222 on the insulator 216 and conductors 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and a conductor 271a on the oxide 230b. 42b, insulator 271b on conductor 242b, insulator 252 on oxide 230b, insulator 250 on insulator 252, insulator 254 on insulator 250, conductor 260 (conductor 260a and conductor 260b) located on insulator 254 and overlapping a portion of oxide 230b, and insulator 275 disposed on insulator 222, insulator 224, oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 271a and insulator 271b. Here, as shown in Figures 1B and 1C, insulator 252 is in contact with at least a portion of the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and top surface of oxide 230b, the side surfaces of conductors 242a and 242b, the side surfaces of insulators 271a and 271b, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. Furthermore, the top surface of conductor 260 is arranged such that its height is approximately the same as the height of the uppermost part of insulator 254, the uppermost part of insulator 250, the uppermost part of insulator 252, and the top surface of insulator 280. Additionally, insulator 282 is in contact with at least a portion of the top surfaces of conductors 260, 252, 250, 254, and 280.

[0054] Hereinafter, oxides 230a and 230b are sometimes collectively referred to as oxide 230. Additionally, conductors 242a and 242b are sometimes collectively referred to as conductor 242. Furthermore, insulators 271a and 271b are sometimes collectively referred to as insulator 271.

[0055] An opening reaching the oxide 230b is provided in insulators 280 and 275. That is, this opening can be said to include a region overlapping with the oxide 230b. Furthermore, insulator 275 can be said to include an opening overlapping with the opening included in insulator 280. Insulators 252, 250, 254, and conductor 260 are provided within this opening. That is, conductor 260 includes a region overlapping with oxide 230b across insulators 252, 250, and 254. Furthermore, in the channel length direction of transistor 200, conductors 260, 252, 250, and 254 are provided between insulators 271a and 242a and between insulators 271b and 242b. Insulator 254 has a region contacting the side surface of conductor 260 and a region contacting the bottom surface of conductor 260.

[0056] Oxide 230 preferably includes oxide 230a on insulator 224 and oxide 230b on oxide 230a. When oxide 230a is included below oxide 230b, the diffusion of impurities from the structure formed below oxide 230a to oxide 230b can be suppressed.

[0057] Note that in transistor 200, oxide 230 has a two-layer stacked structure of oxide 230a and oxide 230b, but the present invention is not limited thereto. For example, oxide 230 may have a single-layer or three-layer stacked structure of oxide 230b, or it may have a structure in which oxide 230a and oxide 230b are stacked separately.

[0058] Conductor 260 is used as the first gate electrode (also called the top gate electrode), and conductor 205 is used as the second gate electrode (also called the back gate electrode). Furthermore, insulators 252, 250, and 254 are used as the first gate insulators, and insulators 222 and 224 are used as the second gate insulators. Note that the gate insulators are sometimes referred to as gate insulating layers or gate insulating films. Additionally, conductor 242a is used as one of the source and drain electrodes, and conductor 242b is used as the other. Furthermore, at least a portion of the region of oxide 230 overlapping with conductor 260 is used as a channel forming region.

[0059] Here, Figure 2A shows an enlarged view of the area near the channel formation region in Figure 1B. Since oxide 230b is supplied with oxygen, the channel formation region is formed in the region between conductor 242a and conductor 242b. Therefore, as shown in Figure 2A, oxide 230b includes region 230bc, which serves as the channel formation region of transistor 200, and regions 230ba and 230bb, which are disposed in a manner that sandwiches region 230bc and serve as source or drain regions. At least a portion of region 230bc overlaps with conductor 260. In other words, region 230bc is disposed in the region between conductor 242a and conductor 242b. Region 230ba overlaps with conductor 242a, and region 230bb overlaps with conductor 242b.

[0060] Compared to regions 230ba and 230bb, region 230bc has fewer oxygen vacancies or lower impurity concentrations, making it a high-resistivity region with low carrier concentration, thus it is used as a channel-forming region. Therefore, region 230bc can be considered a type I (essential) or essentially type I region.

[0061] Furthermore, regions 230ba and 230bb, which are used as source or drain regions, are characterized by increased carrier concentration due to a high number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in lower resistance. In other words, regions 230ba and 230bb are n-type regions with higher carrier concentration and lower resistance than region 230bc.

[0062] Here, the carrier concentration in region 230bc, used as the channel forming region, is preferably below 1×10¹⁸ cm⁻³, more preferably below 1×10¹⁷ cm⁻³, further preferably below 1×10¹⁶ cm⁻³, more preferably below 1×10¹³ cm⁻³, and even more preferably below 1×10¹² cm⁻³. There is no particular limitation on the lower limit of the carrier concentration in region 230bc, used as the channel forming region; for example, it can be set to 1×10⁻⁹ cm⁻³.

[0063] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, with a carrier concentration equal to or lower than that of region 230ba and region 230bb, but equal to or higher than that of region 230bc. In other words, this region is used as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region is sometimes equal to or lower than that of region 230ba and region 230bb, but equal to or higher than that of region 230bc. Additionally, the oxygen vacancies in this junction region are sometimes equal to or less than those in region 230ba and region 230bb, but equal to or more than those in region 230bc.

[0064] Note that Figure 2A shows an example of regions 230ba, 230bb, and 230bc formed in oxide 230b, but the invention is not limited thereto. For example, the above-mentioned regions can also be formed in oxide 230b and oxide 230a.

[0065] In oxide 230, it is sometimes difficult to clearly observe the boundaries of each region. The concentrations of metallic elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to vary in stages according to each region; they can vary gradually within each region. That is, the closer to the channel formation region, the lower the concentration of metallic elements and impurity elements such as hydrogen and nitrogen should be.

[0066] Preferably, in transistor 200, a metal oxide (hereinafter, sometimes referred to as oxide semiconductor) to be used as a semiconductor is used in oxide 230 (oxide 230a, oxide 230b) that includes the channel forming region.

[0067] The band gap of the metal oxide used as a semiconductor is preferably 2 eV or higher, and more preferably 2.5 eV or higher. By using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced.

[0068] For example, oxide 230 is preferably an In-M-Zn oxide containing indium, element M, and zinc (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may also be used as oxide 230.

[0069] Oxide 230 is preferably a stacked structure having multiple oxide layers with different chemical compositions. For example, the ratio of the number of atoms of element M, the main metal element, in the metal oxide used for oxide 230a is preferably greater than the ratio of the number of atoms of element M, the main metal element, in the metal oxide used for oxide 230b. Furthermore, the ratio of the number of atoms of In to element M in the metal oxide used for oxide 230a is preferably greater than the ratio of the number of atoms of In to element M in the metal oxide used for oxide 230b. By employing such a structure, the diffusion of impurities and oxygen from the structure formed beneath oxide 230a to oxide 230b can be suppressed.

[0070] Preferably, the ratio of In atoms to M atoms in the metal oxide used for oxide 230b is greater than that in the metal oxide used for oxide 230a. By employing this structure, the transistor 200 can achieve high on-state current and high frequency characteristics.

[0071] Furthermore, oxides 230a and 230b contain common elements as their main components in addition to oxygen, which can reduce the defect state density at the interface between oxides 230a and 230b. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can achieve high on-state current and high-frequency characteristics.

[0072] Specifically, as oxide 230a, a metal oxide with an In:M:Zn ratio of 1:3:4 or similar, or an In:M:Zn ratio of 1:1:0.5 or similar, can be used. Furthermore, as oxide 230b, a metal oxide with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:2 or similar, or an In:M:Zn ratio of 4:2:3 or similar, can be used. Note that "similar" includes a range of ±30% of the desired atomic ratio. Furthermore, gallium is preferably used as element M. Additionally, when a monolayer of oxide 230b is provided as oxide 230, a metal oxide suitable for oxide 230a can also be used as oxide 230b.

[0073] Furthermore, when depositing metal oxides by sputtering, the aforementioned atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but can also be the atomic ratio of the sputtering target used for depositing the metal oxide.

[0074] Oxide 230b is preferably crystalline. In particular, it is preferred to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0075] CAAC-OS possesses a highly crystalline, dense structure and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating CAAC-OS after its formation at a temperature that prevents polymorphism (e.g., above 400°C and below 600°C), a more crystalline, dense structure can be achieved. Thus, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen within it can be further reduced.

[0076] Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of a decrease in electron mobility due to grain boundaries. Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides with CAAC-OS demonstrate high heat resistance and reliability.

[0077] Furthermore, when a crystalline oxide such as CAAC-OS is used as oxide 230b, oxygen extraction from oxide 230b at the source or drain electrode can be suppressed. Therefore, even with heat treatment, oxygen extraction from oxide 230b can be reduced, and the transistor 200 remains stable at high temperatures (so-called thermal budget) during the process.

[0078] In transistors using oxide semiconductors, the electrical properties are prone to variation and can sometimes reduce reliability if impurities and oxygen vacancies are present in the channel-forming region of the oxide semiconductor. Furthermore, hydrogen near oxygen vacancies can form defects (hereinafter sometimes referred to as VOH) that allow hydrogen to enter the oxygen vacancy, potentially generating electrons that can become carriers. Therefore, when oxygen vacancies are present in the channel-forming region of the oxide semiconductor, the transistor exhibits always-on characteristics (the characteristic that current flows through the transistor even without a voltage applied to the gate electrode). Thus, it is preferable to minimize impurities, oxygen vacancies, and VOH in the channel-forming region of the oxide semiconductor. In other words, it is preferable to reduce the carrier concentration in the channel-forming region of the oxide semiconductor and to essentially or substantially reduce it to I-type.

[0079] In contrast, by performing heat treatment with an insulator containing oxygen that is removed by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulator, thereby reducing oxygen vacancies and VOH. Note that when too much oxygen is supplied to the source or drain region, it may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, when the amount of oxygen supplied to the source or drain region is uneven within the substrate surface, the characteristics of the semiconductor device, including the transistor, become uneven. In addition, when the oxygen supplied from the insulator to the oxide semiconductor diffuses to conductors such as the gate electrode, source electrode, and drain electrode, these conductors may sometimes be oxidized, resulting in a loss of conductivity, thus negatively impacting the electrical characteristics and reliability of the transistor.

[0080] Therefore, preferably, in the oxide semiconductor, the carrier concentration of region 230bc, which is used as the channel forming region, is reduced and is i-typened or substantially i-typened. On the other hand, preferably, the carrier concentration of regions 230ba and 230bb, which are used as the source or drain regions, is high and is n-typened. In other words, it is preferable to reduce oxygen vacancies and V OH in region 230bc of the oxide semiconductor and to prevent excessive oxygen supply to regions 230ba and 230bb. Furthermore, it is preferable to employ a structure that suppresses the oxidation of conductors 260, 242a, and 242b.

[0081] In this embodiment, the semiconductor device has a structure that efficiently supplies oxygen to region 230bc and suppresses oxidation of conductors 242a, 242b and 260.

[0082] To supply oxygen to region 230bc, it is preferable to use an oxygen-permeable insulator as insulator 250. Furthermore, it is preferable to use an insulator containing excess oxygen as insulator 280. By employing this structure, the oxygen contained in insulator 280 can be supplied to region 230bc via insulator 250.

[0083] Furthermore, in order to suppress the oxidation of conductors 242a, 242b, and 260, it is preferable to provide an insulator with the function of suppressing oxygen diffusion near each of conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, such insulators are, for example, insulators 252, 254, and 275.

[0084] The insulator 252 preferably has oxygen-barrier properties. The insulator 252 is disposed between the insulator 250 and the conductor 242a, and between the insulator 250 and the conductor 242b. Therefore, oxygen contained in the insulator 250 can be prevented from diffusing to the conductors 242a and 242b, thereby suppressing the oxidation of the conductors 242a and 242b. Alternatively, the amount of oxygen contained in the insulator that diffuses to the conductors 242a and 242b is reduced, thereby allowing for the thinning of the layers formed on the sides of the conductors 242a and 242b (corresponding to layers 244a and 244b described later). Furthermore, the insulator 252 is disposed between the insulator 250 and the oxide 230b. Therefore, during heat treatment, oxygen detachment from region 230bc of the oxide 230b can be suppressed.

[0085] Note that the thickness of insulator 252 is preferably thinner. For example, insulator 252 preferably includes a region whose thickness is smaller than that of insulator 250. Insulator 250 includes a region that contacts the top surface of oxide 230b. By reducing the thickness of insulator 252, oxygen contained in insulator 250 can be supplied to region 230bc of oxide 230b and excess oxygen supply in insulator 250 can be suppressed. Furthermore, insulator 252 is disposed between insulator 280 and insulator 250 and includes a region that contacts the sidewall of the opening included in insulator 280. By reducing the thickness of insulator 252, oxygen contained in insulator 280 can be supplied to insulator 250 and excess oxygen supply in insulator 280 can be suppressed.

[0086] The insulator 254 preferably has oxygen-barrier properties. The insulator 254 is disposed between the insulator 250 and the conductor 260. Therefore, it can prevent oxygen contained in the insulator 250 from diffusing into the conductor 260 and inhibit the oxidation of the conductor 260. Note that the insulator 254 should be at least less permeable to oxygen than the insulator 250.

[0087] Preferably, insulator 275 is an insulator that inhibits oxygen permeation. Insulator 275 is disposed between insulator 280 and conductors 242a and 242b. By employing this structure, the diffusion of oxygen contained in insulator 280 to conductors 242a and 242b can be suppressed. Therefore, the oxidation of conductors 242a and 242b caused by oxygen contained in insulator 280, which would increase resistivity and reduce current, can be prevented. Note that insulator 275 should be at least less permeable to oxygen than insulator 250.

[0088] By employing the above structure, region 230bc, which is used as the channel forming region, can be i-shaped or substantially i-shaped, and regions 230ba and 230bb, which are used as the source or drain regions, can be n-shaped, thus providing a semiconductor device with excellent electrical characteristics. Furthermore, by employing the above structure, even when the semiconductor device is miniaturized or highly integrated, it can still possess good electrical characteristics. For example, even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, or 7 nm or less but 2 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can still be obtained. Note that the gate length will be explained later.

[0089] Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be increased. When the gate length is within the aforementioned range, for example at room temperature, the transistor's cutoff frequency can be above 50 GHz or 100 GHz.

[0090] Note that conductors 242a, 242b, and 260 are preferably made of conductive materials that are not easily oxidized or have the function of inhibiting oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This helps to suppress the decrease in conductivity of conductors 242a, 242b, and 260. When conductive materials containing metals and nitrogen are used as conductors 242a, 242b, and 260, conductors 242a, 242b, and 260 contain at least metals and nitrogen.

[0091] Any one or more of conductors 242a, 242b, and 260 may have a stacked structure. For example, when conductors 242a and 242b have a stacked structure, the layer in contact with oxide 230b is preferably a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion. Furthermore, for example, as shown in FIG1B, when conductor 260 has a stacked structure of conductors 260a and 260b, conductor 260a may be a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion.

[0092] As oxide 230b, it is preferable to use an oxide with crystallinity such as CAAC-OS. As this oxide, it is preferable to use the aforementioned metal oxides suitable for oxide 230. Particularly preferred are metal oxides containing indium, zinc, and one or more selected from gallium, aluminum, and tin. Furthermore, CAAC-OS is a crystalline oxide with the c-axis of the crystals substantially perpendicular to the surface of the oxide or the surface to which it is formed. This can suppress oxygen extraction from oxide 230b by conductor 242a or conductor 242b. Furthermore, it can suppress the decrease in conductivity of conductor 242a and conductor 242b.

[0093] The insulator 282 disposed on the insulator 280 is preferably formed by a method that allows oxygen to be added to the insulator 280. Thus, the insulator 280 can contain an excess of oxygen.

[0094] In this embodiment, the semiconductor device, in addition to the structure described above, also has a structure for suppressing hydrogen ingress into the transistor 200. For example, an insulator with the function of suppressing hydrogen diffusion is provided in a manner that covers the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, insulator 212 and insulator 283.

[0095] As the insulator 212, it is preferable to use an insulator that has the function of suppressing hydrogen diffusion. Thus, hydrogen diffusion from below the insulator 212 can be suppressed from the transistor 200.

[0096] As the insulator 283, it is preferable to use an insulator that has the function of suppressing hydrogen diffusion. This can suppress hydrogen diffusion from the top of the insulator 283 onto the transistor 200. Furthermore, hydrogen diffusion transistor 200 contained in the insulator 274 can be suppressed.

[0097] Figure 3 shows an enlarged view of the area near the channel formation region in Figure 1B. The solid arrows in Figure 3 indicate the diffusion of oxygen. Furthermore, the dashed arrows in Figure 3 indicate the diffusion of hydrogen. By employing the above structure, oxygen can be efficiently supplied to region 230bc while suppressing the oxidation of conductors 242a, 242b, and 260. Furthermore, hydrogen incorporation into transistor 200 can be suppressed.

[0098] Here, the gate length mentioned above is explained.

[0099] Figure 4A shows an enlarged view of the area near the channel formation region in Figure 1B. Figure 4A is a cross-sectional view of the transistor 200 along the channel length direction. As described above, insulators 252, 250, and 254 are used as the first gate insulator.

[0100] Hereafter, insulators 252, 250, and 254 are sometimes collectively referred to as insulator 256. In this case, insulator 256 includes insulator 252, insulator 250 on insulator 252, and insulator 254 on insulator 250. Furthermore, insulator 256 is used as the first gate insulator.

[0101] Figure 4B shows a cross-sectional view with insulator 256 replaced by insulator 252, insulator 250, and insulator 254 included in Figure 4A. Furthermore, a single-layer conductor 260 is shown in Figure 4B for simplification. Note that, as described above, conductor 260 may have a stacked structure of conductors 260a and 260b, or a stacked structure of three or more layers.

[0102] The width Lg shown in Figures 4A and 4B is the width of the bottom surface of the conductor 260 in the region overlapping with oxide 230b in the cross-section along the channel length direction. Hereafter, the bottom surface of the conductor 260 in the region overlapping with oxide 230b in the cross-section along the channel length direction will sometimes be simply referred to as the bottom surface of the conductor 260 in the region overlapping with oxide 230b. That is, the bottom surface of the conductor 260 in the region overlapping with oxide 230b described later can sometimes be referred to as the bottom surface of the conductor 260 in the region overlapping with oxide 230b in the cross-section along the channel length direction.

[0103] The gate length is the length of the gate electrode in the direction within the carrier movement channel forming region when the transistor is operating, and is the width of the bottom surface of the gate electrode in a top view of the transistor. In this specification, the gate length is the width of the bottom surface of the conductor 260 in the region overlapping with oxide 230b in a cross-section along the channel length direction. That is, the gate length is the width Lg shown in Figures 4A and 4B. Note that the conductor 260 is disposed inside the openings included in insulators 275 and 280. Furthermore, the sidewalls of the openings are perpendicular to or inclined to the substrate surface. In particular, when the angle formed between the sidewalls of the openings and the substrate surface is 90° or less, the minimum width of the conductor 260 in the region overlapping with oxide 230b is the width Lg. Therefore, in a cross-section along the channel length direction, the conductor 260 can also be said to include a region of width Lg.

[0104] Preferably, the bottom surface of the conductor 260 in the region overlapping with oxide 230b has a flat region. As shown in Figures 4A and 4B, when the bottom surface of the conductor 260 in the region overlapping with oxide 230b has a flat region, the width Lg is the width of that flat region. By having a flat region on the bottom surface of the conductor 260 in the region overlapping with oxide 230b, an electric field can be uniformly generated in the channel forming region of oxide 230.

[0105] Figures 4A and 4B show a structure where the bottom surface of the conductor 260 in the region overlapping with oxide 230b has a flat area; however, the invention is not limited to this. In a cross-section along the channel length, the bottom surface of the conductor 260 in the region overlapping with oxide 230b may also have a curve.

[0106] Figure 4C shows a modified example of the transistor 200 shown in Figure 4B. Figure 4C is a cross-sectional view of the transistor 200 along its channel length. For example, as shown in Figure 4C, the bottom surface of the conductor 260 in the region overlapping with oxide 230b may also include a flat region and a curved region. Note that the curved regions are located at the ends of both sides of the bottom surface. Here, the point where the curve on the conductor 242a side of the bottom surface contacts the side surface of the conductor 242a side of the conductor 260 is point Qa. Furthermore, the point where the curve on the conductor 242b side of the bottom surface contacts the side surface of the conductor 242b side of the conductor 260 is point Qb. In this structure, the width Lg is the length of the line segment connecting points Qa and Qb.

[0107] Figure 4D shows a modified example of the transistor 200 shown in Figure 4B. Figure 4D is a cross-sectional view of the transistor 200 along its channel length. For example, as shown in Figure 4D, the conductor 260 can also have an arc-shaped bottom surface. Note that this arc is an arc with the center of curvature P located within the conductor 260 and a radius r. In this structure, the width Lg is the width of the area in the cross-section along the channel length that overlaps with the conductor 260 by a straight line including the center of curvature P and parallel to the bottom surface of the oxide 230b. In other words, the width Lg is twice the radius r. Note that the straight line represented by the dashed line in Figure 4D is a straight line including the center of curvature P and parallel to the bottom surface of the oxide 230b.

[0108] Note that in the bottom shape of the conductor 260 shown in Figure 4D, when the radius r is large (e.g., when the radius r is larger than the channel length), the distance from the curvature center P to the channel forming region of the oxide 230b also increases. In this case, the gate length of this shape can also be the width Lg shown in Figure 4C. That is, the width Lg can also be calculated based on the shape of the bottom surface of the conductor 260 shown in Figure 4D, which determines points Qa and Qb.

[0109] In the bottom surface shape of the conductor 260 shown in Figure 4C, determining points Qa and Qb can sometimes be difficult. In this case, the gate length of this shape can also be the width Lg shown in Figure 4D. That is, the width Lg can also be calculated based on the curvature center P determined by the bottom surface shape of the conductor 260 shown in Figure 4C.

[0110] The above explains the gate length. Next, the channel length will be explained.

[0111] As shown in Figures 4A to 4D, the distance between the lower end of conductor 242a and the lower end of conductor 242b is distance L. Distance L corresponds to the channel length of transistor 200.

[0112] In the above structure, the channel length is set according to the material used for the conductor 260, the gate length, and the material and thickness used for the first gate insulator. When the gate length is within any of the above ranges, the channel length can be, for example, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less and 10 nm or more, 15 nm or more, or 20 nm or more.

[0113] When openings are formed in insulators 280 and 275, the upper part of oxide 230b in the region overlapping with the opening is sometimes removed, as will be explained in detail later. In this case, as shown in FIG4E, the thickness of the region of oxide 230b overlapping with conductor 260 is thinner than the thickness of the region of oxide 230b overlapping with conductor 242a. Note that the transistor 200 shown in FIG4E is a modified example of the transistor 200 shown in FIG4B. FIG4E is a cross-sectional view of the transistor 200 along the channel length direction.

[0114] Here, the difference Lt is the thickness of the region where oxide 230b overlaps with conductor 260 and the thickness of the region where oxide 230b overlaps with conductor 242a (see Figure 4E). If the difference Lt is small, the distance L can be considered as the channel length.

[0115] Furthermore, as described above, when forming a thinner insulator 252, as shown in FIG4F, a layer 244a is sometimes formed between the conductor 242a and the insulator 256. Similarly, a layer 244b is sometimes formed between the conductor 242b and the insulator 256. In other words, the transistor 200 sometimes includes a layer 244a located between the conductor 242a and the insulator 256 and a layer 244b located between the conductor 242b and the insulator 256. Note that the transistor 200 shown in FIG4F is a modified example of the transistor 200 shown in FIG4E. FIG4F is a cross-sectional view of the transistor 200 along the channel length direction.

[0116] Layers 244a and 244b are formed by oxidation of the side surfaces of conductors 242a and 242b, respectively. Therefore, layer 244a contains the elements and oxygen present in conductor 242a. Furthermore, layer 244b contains the elements and oxygen present in conductor 242b. For example, when both conductors 242a and 242b contain a metal and nitrogen, layers 244a and 244b also contain that metal and oxygen.

[0117] The conductivity of layer 244a is lower than that of conductor 242a. Furthermore, the conductivity of layer 244b is lower than that of conductor 242b. Therefore, when transistor 200 has layers 244a and 244b, the distance between the lower end of conductor 242a and the lower end of conductor 242b can be defined as distance L, and distance L can be considered as the channel length. In other words, by forming layers 244a and 244b, the channel length can be increased. Therefore, the source-drain breakdown voltage of transistor 200 can be improved to achieve a transistor with high reliability.

[0118] Note that in the cross-section along the channel length direction, the length of layer 244a along the channel length direction is length Lo (see Figure 4F). Note that the length of layer 244b along the channel length direction is equal to or approximately the same as length Lo. Length Lo is preferably small. For example, length Lo is preferably smaller than width Lg. Specifically, length Lo is preferably 1 nm or more and less than 8 nm, more preferably 2 nm or more and less than 5 nm. By adopting this structure, transistor 200 can obtain good electrical characteristics even if the gate length is within any of the above ranges.

[0119] Therefore, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device capable of miniaturization or high integration can be provided. Additionally, a semiconductor device with good electrical characteristics and capable of miniaturization or high integration can be provided.

[0120] Furthermore, in this embodiment, microwave treatment is performed in an oxygen-containing atmosphere with conductors 242a and 242b disposed on oxide 230b to reduce oxygen vacancies and VOH in region 230bc. Here, microwave treatment refers, for example, to treatment using a device including a power source that generates high-density plasma using microwaves.

[0121] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency signals such as RF (Radio Frequency), thus enabling the oxygen plasma to function. At this time, region 230bc can also be irradiated with high-frequency signals such as microwaves or RF. Through the action of plasma, microwaves, etc., the V OH in region 230bc can be separated into oxygen vacancies and hydrogen. The hydrogen can be removed from region 230bc, and the oxygen vacancies can be filled by oxygen. Therefore, the hydrogen concentration, oxygen vacancies, and V OH in region 230bc can be reduced, thereby lowering the carrier concentration.

[0122] Furthermore, when microwave processing is performed in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not affect regions 230ba and 230bb. Moreover, the effects of oxygen plasma can be reduced by insulators 271 and 280 covering oxide 230b and conductor 242. Therefore, during microwave processing, no reduction of VOH and excessive oxygen supply occur in regions 230ba and 230bb, thus preventing a decrease in carrier concentration.

[0123] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after depositing the insulating film as insulator 252 or after depositing the insulating film as insulator 250. In this way, by performing microwave treatment in an oxygen-containing atmosphere via insulator 252 or insulator 250, oxygen can be efficiently injected into region 230bc. Additionally, by configuring insulator 252 in contact with the side surface of conductor 242 and the surface of region 230bc, unnecessary oxygen injection into region 230bc can be suppressed, thus suppressing oxidation of the side surface of conductor 242. Furthermore, oxidation of the side surface of conductor 242 can be suppressed during the deposition of the insulating film as insulator 250.

[0124] Furthermore, the oxygen injected into region 230bc can be in various forms, including oxygen atoms, oxygen molecules, and oxygen free radicals (also known as O free radicals, which are atoms, molecules, or ions containing unpaired electrons). The oxygen injected into region 230bc can be any one or more of the above-mentioned forms, with oxygen free radicals being particularly preferred. Additionally, the reliability of the transistor 200 is improved because the film quality of insulators 252 and 250 can be enhanced.

[0125] As described above, oxygen vacancies and V OH groups can be selectively removed from region 230bc of the oxide semiconductor, making region 230bc i-type or substantially i-type. Furthermore, excessive oxygen supply to regions 230ba and 230bb, which are used as source or drain regions, can be suppressed, maintaining the state of the n-type region before microwave processing. Therefore, variations in the electrical characteristics of the transistor 200 can be suppressed, thereby suppressing non-uniformity in the electrical characteristics of the transistor 200 within the substrate surface.

[0126] By employing the above structure, a semiconductor device with small transistor characteristic non-uniformity can be provided. Furthermore, a semiconductor device with good reliability can be provided. Additionally, a semiconductor device with excellent electrical characteristics can be provided. Furthermore, a semiconductor device capable of miniaturization or hyper-integration can be provided.

[0127] Furthermore, as shown in Figure 1C, when viewed in cross-section of the channel width of transistor 200, a curved surface may also be present between the side surface and the top surface of oxide 230b. That is, the ends of the side surface and the top surface may also be curved (hereinafter also referred to as circular).

[0128] The radius of curvature of the aforementioned curved surface is preferably greater than 0 nm and less than the thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the aforementioned curved surface. Specifically, the radius of curvature of the aforementioned curved surface is greater than 0 nm and less than 20 nm, preferably more than 1 nm and less than 15 nm, and more preferably more than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the oxide 230b of the insulator 252, insulator 250, insulator 254, and conductor 260 can be improved.

[0129] Furthermore, as shown in Figure 1C, since the insulator 252, formed of aluminum oxide or the like, is provided in contact with the top and side surfaces of the oxide 230, the indium contained in the oxide 230 is sometimes distributed at and near the interface between the oxide 230 and the insulator 252. Therefore, the surface area of ​​the oxide 230 has an atomic ratio close to that of indium oxide or close to that of In-Zn oxide. When the atomic ratio of indium near the surface of the oxide 230, especially oxide 230b, is large, the field-effect mobility of the transistor 200 can be improved.

[0130] At least one of insulators 212, 214, 271, 275, 282, 283, and 285 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen from one side of the substrate or above the transistor 200 to the transistor 200. Therefore, at least one of insulators 212, 214, 271, 275, 282, 283, and 285 is preferably an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Furthermore, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, making it difficult for the aforementioned oxygen to permeate).

[0131] Furthermore, in this specification, "barrier insulating film" refers to an insulating film with barrier properties. In this specification, barrier properties refer to the function of inhibiting the diffusion of the corresponding substance (also known as low permeability). Alternatively, it refers to the function of capturing and fixing the corresponding substance (also known as gettering).

[0132] As insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, as insulators 212, 275, and 283, silicon nitride, which has higher hydrogen blocking properties, is preferably used. Furthermore, as insulators 214, 271, 282, and 285, aluminum oxide or magnesium oxide, which have high hydrogen trapping and fixing performance, is preferably used. Thus, the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through insulators 212 and 214 can be suppressed. Alternatively, the diffusion of impurities such as water and hydrogen from the interlayer insulating film disposed outside the insulator 285 to the transistor 200 side can be suppressed. Alternatively, the diffusion of oxygen contained in the insulator 224 to the substrate side via the insulator 212 and the insulator 214 can be suppressed. Alternatively, the diffusion of oxygen contained in the insulator 280 to the top of the transistor 200 via the insulator 282 can be suppressed. Thus, it is preferable to adopt a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 275, 282, 283 and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0133] Here, insulators 212, 214, 271, 275, 282, 283, and 285 are preferably insulators with an amorphous structure. For example, metal oxides such as AlOx (where x is any number greater than 0) or MgOy (where y is any number greater than 0) are preferred. These amorphous metal oxides sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. By using these amorphous metal oxides as components of the transistor 200 or placing them around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be trapped or fixed. In particular, it is preferable to trap or fix hydrogen contained in the channel-forming regions of the transistor 200. By using metal oxides with amorphous structures as components of the transistor 200 or placing them around the transistor 200, it is possible to manufacture a highly reliable transistor 200 and semiconductor device with good characteristics.

[0134] Furthermore, insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but polycrystalline structures may also be formed in some regions thereon. Additionally, insulators 212, 214, 271, 275, 282, 283, and 285 may also have a multilayer structure with layers of amorphous and polycrystalline structures stacked on top of each other. For example, a stacked structure may also have amorphous layers with polycrystalline layers formed on top of them.

[0135] The deposition of insulators 212, 214, 271, 275, 282, 283, and 285 can be achieved, for example, by sputtering. Sputtering eliminates the need for hydrogen-containing molecules as the deposition gas, thus reducing the hydrogen concentration in insulators 212, 214, 271, 275, 282, 283, and 285. In addition to sputtering, other suitable deposition methods include chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0136] Furthermore, it is sometimes preferable to reduce the resistivity of insulators 212, 275, and 283. For example, by making the resistivity of insulators 212, 275, and 283 approximately 1 × 10¹³ Ωcm, in semiconductor device manufacturing processes using plasma or similar materials, insulators 212, 275, and 283 can sometimes mitigate charge accumulation in conductors 205, 242, 260, or 246. The resistivity of insulators 212, 275, and 283 is preferably 1 × 10¹⁰ Ωcm or higher and 1 × 10¹⁵ Ωcm or lower.

[0137] Furthermore, the dielectric constants of insulators 216, 274, 280, and 285 are preferably lower than that of insulator 214. By using materials with low dielectric constants in the interlayer film, parasitic capacitances generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, fluorinated silicon oxide, carbon-containing silicon oxide, carbon and nitrogen-containing silicon oxide, or porous silicon oxide can be appropriately used as insulators 216, 274, 280, and 285.

[0138] Conductor 205 is arranged to overlap with oxide 230 and conductor 260. Preferably, conductor 205 is disposed in a manner that embeds it within an opening formed in insulator 216. Furthermore, a portion of conductor 205 may sometimes be embedded in insulator 214.

[0139] The conductor 205 includes conductor 205a and conductor 205b. Conductor 205a is disposed in contact with the bottom surface and sidewall of the opening. Conductor 205b is disposed embedded in the recess formed in conductor 205a. Here, the height of the top surface of conductor 205b is approximately the same as the height of the top surface of conductor 205a and the height of the top surface of insulator 216.

[0140] Here, the conductor 205a is preferably a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), and copper atoms. Alternatively, it is preferably a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0141] By using a conductive material that reduces hydrogen diffusion as conductor 205a, impurities such as hydrogen contained in conductor 205b can be prevented from diffusing to oxide 230 through insulators 216 and 224. Furthermore, by using a conductive material that inhibits oxygen diffusion as conductor 205a, oxidation of conductor 205b and a decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, single-layer or multi-layered conductive materials can be used as conductor 205a. For example, titanium nitride can be used as conductor 205a.

[0142] Furthermore, conductor 205b is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, conductor 205b can be made of tungsten.

[0143] Conductor 205 is sometimes used as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential applied to conductor 205 without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be increased, thereby reducing the off-state current. Thus, compared to not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0144] Furthermore, the resistivity of conductor 205 is designed considering the potential applied to conductor 205, and the thickness of conductor 205 is set according to this resistivity. Additionally, the thickness of insulator 216 is approximately the same as that of conductor 205. Here, it is preferable to reduce the thickness of both conductor 205 and insulator 216 within the design limits of conductor 205. By reducing the thickness of insulator 216, the absolute amount of impurities such as hydrogen contained in insulator 216 can be reduced, thus reducing the diffusion of these impurities into oxide 230.

[0145] Furthermore, as shown in FIG1A, the conductor 205 is preferably larger than the region in oxide 230 that does not overlap with conductors 242a and 242b. In particular, as shown in FIG1C, the conductor 205 is preferably a region extending to the outer side of the ends of oxides 230a and 230b in the channel width direction. That is, preferably, the conductor 205 and the conductor 260 overlap with an insulator on the outer side of the side in the channel width direction of oxide 230. With the above structure, a region can be formed around the channel of oxide 230 by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In this specification, the transistor structure in which the electric fields of the first gate and the second gate form a region around the channel is referred to as a surrounded channel (S-channel) structure.

[0146] In this specification, an S-channel transistor refers to a transistor structure in which the electric fields of one and the other of a pair of gate electrodes form a region around the channel. Furthermore, the S-channel structure disclosed in this specification differs from Fin-type and planar structures. By employing the S-channel structure, transistors with improved tolerance to short-channel effects can be realized; in other words, transistors less prone to short-channel effects can be achieved.

[0147] By having the transistor 200 normally off and possessing the aforementioned S-channel structure, a region can be formed around the channel. Therefore, the transistor 200 can also be described as having a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By giving the transistor 200 an S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be incorporated into the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be increased, and thus an increase in the transistor's on-state current or field-effect mobility can be expected.

[0148] Furthermore, as shown in FIG1C, the conductor 205 is extended for use as wiring. However, the present invention is not limited to this, and the conductor used for wiring may also be provided under the conductor 205. In addition, it is not necessary to provide a conductor 205 in each transistor. For example, the conductor 205 may be used in multiple transistors.

[0149] Note that the diagram shows a structure in which conductors 205a and 205b are stacked as conductors 205 in transistor 200, but the present invention is not limited thereto. For example, conductor 205 may have a single-layer structure or a stacked structure of three or more layers.

[0150] Insulators 222 and 224 are used as gate insulators.

[0151] Insulator 222 preferably has the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). Furthermore, insulator 222 preferably has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, compared to insulator 224, insulator 222 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen.

[0152] The insulator 222 is preferably an insulator containing an oxide of one or both of aluminum and hafnium as the insulating material. Preferably, the insulator is aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferred. When the insulator 222 is formed using this material, it serves to suppress the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230 layer. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inner side of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, the reaction between the conductor 205 and the oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

[0153] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the insulator as insulator 222.

[0154] Furthermore, as the insulator 222, insulators containing so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide can be used, either as a single layer or in layers. When miniaturizing and hyper-integrating transistors, problems such as leakage current sometimes occur due to the thin-film nature of the gate insulator. By using a high-k material as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Additionally, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), can sometimes be used as the insulator 222.

[0155] As the insulator 224 in contact with oxide 230, silicon oxide, silicon oxynitride, etc., can be used appropriately.

[0156] Furthermore, in the manufacturing process of transistor 200, heat treatment is preferably performed with the surface of oxide 230 exposed. This heat treatment is preferably performed at a temperature of 100°C or higher and 600°C or lower, more preferably at 350°C or higher and 550°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxide 230, thereby reducing oxygen vacancies. Heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in a nitrogen or inert gas atmosphere, followed by heat treatment in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to fill the detached oxygen. Alternatively, heat treatment can be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas, followed by continuous heat treatment in a nitrogen or inert gas atmosphere.

[0157] By subjecting oxide 230 to oxidation treatment, the oxygen vacancies in oxide 230 can be filled by the supplied oxygen. Furthermore, the hydrogen remaining in oxide 230 reacts with the supplied oxygen to remove the hydrogen in the form of H₂O (dehydration). Thus, the recombination of hydrogen remaining in oxide 230 with oxygen vacancies to form VOH can be inhibited.

[0158] Furthermore, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material; it can also be a multilayer structure made of different materials. Furthermore, insulator 224 may be formed as an island and overlap with oxide 230a. In this case, insulator 275 contacts the side surface of insulator 224 and the top surface of insulator 222. Note that in this specification, "island" refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

[0159] Conductors 242a and 242b are in contact with the top surface of oxide 230b. Conductors 242a and 242b are used as the source electrode or drain electrode of transistor 200, respectively.

[0160] As conductors 242 (conductors 242a and 242b), it is preferred to use nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. In one embodiment of the invention, it is particularly preferred to use nitrides containing tantalum. In addition, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., may also be used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen.

[0161] Note that sometimes hydrogen contained in oxide 230b, etc., diffuses into conductor 242a or conductor 242b. In particular, when a tantalum-containing nitride is used as conductor 242a and conductor 242b, sometimes hydrogen contained in oxide 230b, etc., readily diffuses into conductor 242a or conductor 242b, and this diffused hydrogen bonds with the nitrogen contained in conductor 242a or conductor 242b. That is, sometimes hydrogen contained in oxide 230b, etc., is absorbed by conductor 242a or conductor 242b.

[0162] Furthermore, it is preferable that no curved surface is formed between the side surface and the top surface of the conductor 242. By eliminating this curved surface, as shown in FIG1D, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased. This increases the conductivity of the conductor 242, thereby increasing the on-state current of the transistor 200.

[0163] Furthermore, when heat treatment is performed while the conductor 242a (conductor 242b) is in contact with the oxide 230b, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) sometimes decreases. Additionally, the carrier concentration sometimes increases. Therefore, it is possible to self-align and reduce the resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b).

[0164] Figures 1A to 1D show a single-layer structure for conductor 242, but the present invention is not limited to this and may also employ a stacked structure of two or more layers. For example, as shown in Figure 5B, conductor 242a may be a stacked structure of two layers: conductor 242a1 and conductor 242a2 on conductor 242a1, and conductor 242b1 and conductor 242b2 on conductor 242b1 may be a stacked structure for conductor 242b1. In this case, conductors 242a1 and 242b1 are disposed on the side in contact with oxide 230b.

[0165] Note that conductors 242a1 and 242b1 are sometimes referred to as the lower layer of conductor 242. Additionally, conductors 242a2 and 242b2 are sometimes referred to as the upper layer of conductor 242.

[0166] The lower layers of conductor 242 (conductors 242a1 and 242b1) are preferably made of a conductive material that is not easily oxidized. This suppresses oxidation of the lower layers of conductor 242, preventing a decrease in the conductivity of conductor 242. Furthermore, the lower layers of conductor 242 can also have the characteristic of readily absorbing (extracting) hydrogen. This allows hydrogen from oxide 230 to diffuse into the lower layers of conductor 242, reducing the hydrogen concentration in oxide 230. Therefore, the transistor 200 can possess stable electrical characteristics.

[0167] Furthermore, the upper layer (conductors 242a2 and 242b2) of conductor 242 is preferably made of a conductive material with higher conductivity than the lower layer (conductors 242a1 and 242b1) of conductor 242. In this case, at least a portion of the upper layer of conductor 242 may have regions with higher conductivity than the lower layer of conductor 242. Alternatively, the upper layer of conductor 242 is preferably made of a conductive material with lower resistivity than the lower layer of conductor 242. This allows for the manufacture of a semiconductor device in which wiring delay is suppressed.

[0168] Furthermore, the upper layer of conductor 242 can also have the characteristic of readily absorbing hydrogen. Therefore, the hydrogen absorbed by the lower layer of conductor 242 diffuses back to the upper layer of conductor 242, further reducing the hydrogen concentration in oxide 230. Thus, transistor 200 can possess stable electrical characteristics.

[0169] Here, the lower and upper layers of conductor 242 are preferably made of conductive materials with the same constituent elements but different chemical compositions. This allows the lower and upper layers of conductor 242 to be continuously formed without exposure to the atmospheric environment. By forming a film without exposure to the atmospheric environment, impurities or moisture from the atmosphere can be prevented from adhering to the surface of the lower layer of conductor 242, thereby maintaining the cleanliness of the area near the interface between the lower and upper layers of conductor 242.

[0170] Furthermore, it is preferable that the lower layer of the conductor 242 uses a tantalum-containing nitride with a high ratio of nitrogen atoms to tantalum, while the upper layer of the conductor 242 uses a tantalum-containing nitride with a low ratio of nitrogen atoms to tantalum. For example, as the lower layer of the conductor 242, a tantalum-containing nitride is used with a nitrogen atom ratio to tantalum of 1.0 or more and 2.0 or less, preferably 1.1 or more and 1.8 or less, and more preferably 1.2 or more and 1.5 or less. For example, as the upper layer of the conductor 242, a tantalum-containing nitride is used with a nitrogen atom ratio to tantalum of 0.3 or more and 1.5 or less, preferably 0.5 or more and 1.3 or less, and more preferably 0.6 or more and 1.0 or less.

[0171] Furthermore, by increasing the atomic ratio of nitrogen to tantalum in the tantalum-containing nitride, the oxidation of the tantalum-containing nitride can be suppressed. Additionally, the oxidation resistance of the tantalum-containing nitride can be improved. Oxygen diffusion into the tantalum-containing nitride can be suppressed. Therefore, as the lower layer of the conductor 242, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum. This prevents the formation of an oxide layer between the lower layer of the conductor 242 and the oxide 230, or reduces the thickness of the oxide layer.

[0172] Furthermore, by reducing the atomic ratio of nitrogen to tantalum in the tantalum-containing nitride, the resistivity of the nitride can be reduced. Therefore, as the upper layer of the conductor 242, it is preferable to use a tantalum-containing nitride with a low atomic ratio of nitrogen to tantalum. This allows for the fabrication of a semiconductor device in which wiring delay is suppressed.

[0173] Note that in conductor 242, the boundary between the upper and lower layers can sometimes be difficult to clearly observe. When using a tantalum-containing nitride in conductor 242, the concentrations of tantalum and nitrogen detected in each layer are not limited to varying in stages for each layer, but can also vary gradually in the region between the upper and lower layers (also known as gradation). That is, in conductor 242, the closer the region is to oxide 230, the higher the ratio of nitrogen atoms relative to tantalum. Therefore, the ratio of nitrogen atoms relative to tantalum in the region below conductor 242 is preferably higher than that in the region above conductor 242.

[0174] The film thickness of the lower layer of the conductor 242 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, at least a portion of the lower layer of the conductor 242 may have a region with the aforementioned film thickness. Furthermore, the film thickness of the lower layer of the conductor 242 is preferably thinner than the film thickness of the upper layer of the conductor 242. In this case, at least a portion of the lower layer of the conductor 242 may have a region with a film thickness thinner than the upper layer of the conductor 242.

[0175] In addition, an example is shown here in which conductive materials with the same constituent elements but different chemical compositions are used as the lower layer and the upper layer of the conductor 242, but it is not limited to this. The lower layer and the upper layer of the conductor 242 may also be formed using different conductive materials.

[0176] Note that the structures of the lower and upper layers of conductor 242 are not limited to those described above. For example, one or more of the constituent elements, chemical composition, and deposition conditions of the lower and upper layers of conductor 242 may be different. For example, a tantalum-containing nitride may be used as the lower layer of conductor 242 and a titanium-containing nitride may be used as the upper layer of conductor 242.

[0177] Insulator 271a is in contact with the top surface of conductor 242a, and insulator 271b is in contact with the top surface of conductor 242b. Insulator 271 is preferably used as an insulating film that at least blocks oxygen. Therefore, insulator 271 preferably has the function of inhibiting oxygen diffusion. For example, compared with insulator 280, insulator 271 preferably has a further function of inhibiting oxygen diffusion. For example, silicon nitride, aluminum oxide, and magnesium oxide can be used as insulator 271.

[0178] Insulator 275 is disposed such that it covers insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 271. Specifically, insulator 275 includes regions that contact the sides of oxide 230b, the sides of conductor 242a, and the sides of conductor 242b. Insulator 275 preferably has the function of trapping and fixing hydrogen. In this case, insulator 275 is preferably a silicon nitride or a metal oxide with an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, a laminate of aluminum oxide and silicon nitride on the aluminum oxide can also be used as insulator 275.

[0179] By providing the aforementioned insulators 271 and 275, the conductor 242 can be surrounded by an oxygen-blocking insulator. In other words, the diffusion of oxygen contained in insulators 224 and 280 into the conductor 242 can be suppressed. Therefore, the direct oxidation of the conductor 242 by oxygen contained in insulators 224 and 280, which would otherwise increase resistivity and reduce current, can be prevented.

[0180] Insulator 252 is used as part of the gate insulator. Preferably, an oxygen-barrier insulating film is used as insulator 252. Any insulator suitable for the aforementioned insulator 282 can be used as insulator 252. Preferably, an insulator containing an oxide of one or both of aluminum and hafnium is used as insulator 252. This insulator can be composed of aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc. In this embodiment, aluminum oxide is used as insulator 252. In this case, insulator 252 contains at least oxygen and aluminum.

[0181] As shown in Figure 1C, the insulator 252 is arranged in contact with the top and side surfaces of the oxide 230b, the side surface of the oxide 230a, the side surface of the insulator 224, and the top surface of the insulator 222. That is, in the cross-section along the channel width, the areas where the oxides 230a, 230b, and insulator 224 overlap with the conductor 260 are covered by the insulator 252. Therefore, the oxygen-barrier insulator 252 can prevent oxygen from detaching from the oxides 230a and 230b during heat treatment, etc. This reduces the formation of oxygen vacancies in the oxides 230a and 230b. Consequently, the formation of oxygen vacancies and VOH in region 230bc can be reduced. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0182] Conversely, even if insulators 280 and 250 contain excessive oxygen, the excessive supply of oxygen to oxides 230a and 230b can be suppressed. Therefore, the decrease in the on-state current or field efficiency of transistor 200 caused by excessive oxidation of region 230ba and region 230bb due to region 230bc can be suppressed.

[0183] Furthermore, as shown in Figure 1B, the insulator 252 is disposed in contact with the sides of the conductors 242, 271, 275, and 280. Therefore, oxidation of the sides of the conductor 242, resulting in the formation of an oxide film on those sides, can be reduced. Consequently, the decrease in the on-state current or field-effect mobility of the transistor 200 can be suppressed.

[0184] Furthermore, insulator 252 needs to be disposed together with insulator 254, insulator 250, and conductor 260 in the opening formed in insulator 280, etc. To achieve miniaturization of transistor 200, the thickness of insulator 252 is preferably small. The thickness of insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and less than 3.0 nm. In this case, at least a portion of insulator 252 is a region having the above-mentioned thickness. Additionally, the thickness of insulator 252 is preferably smaller than the thickness of insulator 250. In this case, at least a portion of insulator 252 is a region with a thickness smaller than that of insulator 250.

[0185] To deposit a thin layer of insulator 252 as described above, it is preferable to deposit insulator 252 using the ALD method. ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react the precursors and reactants, and PEALD (Plasma Enhanced ALD) which uses reactants excited by plasma. In the PEALD method, deposition can be performed at lower temperatures by using plasma, so it is sometimes preferred.

[0186] Furthermore, the ALD method can deposit atoms layer by layer, thereby achieving the advantages of depositing very thin films, depositing structures with high aspect ratios, depositing with fewer defects such as pinholes, depositing with excellent coverage, and depositing at low temperatures. Therefore, it is possible to deposit the insulator 252 with the aforementioned relatively small thickness and high coverage on the sides of openings formed in the insulator 280, etc.

[0187] The precursors used in the ALD method sometimes contain carbon and other impurities. Therefore, films formed using the ALD method sometimes contain more carbon and other impurities compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0188] Furthermore, by appropriately adjusting the deposition conditions of the insulating film that forms insulator 250, the microwave processing conditions in an oxygen-containing atmosphere, and the oxygen added to insulator 280 due to the deposition of insulator 282, it is sometimes possible to reduce oxygen vacancies and V OH formed in region 230bc, thereby suppressing excessive oxidation of regions 230ba and 230bb. In this case, by adopting a structure without insulator 252, the semiconductor device manufacturing process can be simplified, and productivity can be improved.

[0189] Insulator 250 is used as part of the gate insulator. Insulator 250 is preferably configured to contact the top surface of insulator 252. Insulator 250 can be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. In this case, insulator 250 is an insulator containing at least oxygen and silicon.

[0190] Similar to insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in insulator 250 is reduced. The thickness of insulator 250 is preferably 0.1 nm or more and 20 nm or less, more preferably 0.5 nm or more and 15 nm or less. In particular, for manufacturing microtransistors (e.g., transistors with a gate length of 10 nm or less), the thickness of insulator 250 is preferably 0.5 nm or more and 10 nm or less, more preferably 0.5 nm or more and 5 nm or less. In the above cases, at least a portion of insulator 250 may be a region having the aforementioned thickness.

[0191] In Figures 1A to 1D, the insulator 250 is shown to have a single-layer structure, but the present invention is not limited to this and may also employ a stacked structure of two or more layers. For example, as shown in Figure 2B, the insulator 250 may also have a stacked structure of two layers: insulator 250a and insulator 250b on insulator 250a.

[0192] As shown in Figure 2B, when the insulator 250 has a two-layer stacked structure, it is preferable that the lower insulator 250a is formed using an insulator that allows oxygen to pass through, while the upper insulator 250b is formed using an insulator that has the function of inhibiting oxygen diffusion. By adopting this structure, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the reduction of the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, the oxidation of the conductor 260 caused by oxygen contained in the insulator 250a can be suppressed. For example, the insulator 250a can use the materials described above that can be used for the insulator 250, and the insulator 250b can use an insulator containing an oxide of one or both of aluminum and hafnium. As this insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 250b. At this point, the insulator 250b contains at least oxygen and hafnium. Furthermore, the thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, and even more preferably 1.0 nm or more and 3.0 nm or less. At this point, at least a portion of the insulator 250b is a region having the aforementioned thickness.

[0193] Note that when silicon oxide or silicon oxynitride is used for insulator 250a, insulator 250b can also be formed using an insulating material with a high-k relative permittivity. By employing a stacked structure of insulator 250a and insulator 250b as the gate insulator, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. Therefore, the insulation withstand voltage of insulator 250 can be improved.

[0194] Insulator 254 is used as part of the gate insulator. Preferably, a hydrogen-barrier insulating film is used as insulator 254. This prevents impurities such as hydrogen contained in conductor 260 from diffusing into insulator 250 and oxide 230b. The insulator 254 can be any of the insulators described above that can be used in insulator 283. For example, silicon nitride deposited using the PEALD method can be used as insulator 254. In this case, insulator 254 contains at least nitrogen and silicon.

[0195] In addition, the insulator 254 may also have oxygen-blocking properties. This prevents oxygen contained in the insulator 250 from diffusing into the conductor 260.

[0196] Furthermore, insulator 254 needs to be disposed together with insulator 252, insulator 250, and conductor 260 in the opening formed in insulator 280, etc. To achieve miniaturization of transistor 200, the thickness of insulator 254 is preferably small. The thickness of insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, at least a portion of insulator 254 is a region having the above-mentioned thickness. Additionally, the thickness of insulator 254 is preferably smaller than the thickness of insulator 250. In this case, at least a portion of insulator 254 is a region with a thickness smaller than that of insulator 250.

[0197] Furthermore, as shown in Figure 2B, when the insulator 250 adopts a two-layer stacked structure, by using an insulator such as hafnium oxide, which has the function of suppressing the permeation of impurities such as hydrogen and oxygen, as insulator 250b, insulator 250b can also have the functions of insulator 254. In this case, by adopting a structure without insulator 254, the semiconductor device manufacturing process can be simplified, and productivity can be improved.

[0198] Conductor 260 is used as the first gate electrode of transistor 200. Conductor 260 preferably includes conductor 260a and conductor 260b disposed on conductor 260a. For example, conductor 260a is preferably disposed such that it surrounds the bottom and side surfaces of conductor 260b. Furthermore, as shown in Figures 1B and 1C, the top surface of conductor 260 is substantially aligned with the top surface of insulator 250. Although conductor 260 has a two-layer structure of conductor 260a and conductor 260b in Figures 1B and 1C, it may also have a single-layer structure or a stacked structure of three or more layers.

[0199] As the conductor 260a, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0200] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. For example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be used as conductive materials with the function of inhibiting oxygen diffusion.

[0201] Furthermore, since conductor 260 is also used for wiring, it is preferable to use a conductor with high conductivity. For example, conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main component. In addition, conductor 260b can have a laminated structure, for example, it can have a laminated structure of titanium or titanium nitride with the aforementioned conductive material.

[0202] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner by filling the openings formed in the insulator 280, etc. By forming the conductor 260 in this way, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0203] Furthermore, as shown in Figure 1C, in the channel width direction of the transistor 200, with the bottom surface of the insulator 222 as a reference, the height of the bottom surface of the region where the conductor 260 does not overlap with the oxide 230b is preferably lower than the height of the bottom surface of the oxide 230b. By employing a structure in which the conductor 260, used as a gate electrode, covers the side and top surfaces of the channel forming region of the oxide 230b through the insulator 250, it is easier for the electric field of the conductor 260 to act on the entire channel forming region of the oxide 230b. This improves the on-state current and frequency characteristics of the transistor 200. With the bottom surface of the insulator 222 as a reference, the difference between the height of the bottom surface of the conductor 260 and the bottom surface of the oxide 230b in the region where the oxides 230a and 230b do not overlap with the conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0204] An insulator 280 is disposed on an insulator 275, and an opening is formed in the region where the insulator 250 and the conductor 260 are disposed. Furthermore, the top surface of the insulator 280 may be planarized.

[0205] Preferably, the insulator 280 used as the interlayer film has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between the wirings can be reduced. Insulator 280 is preferably formed, for example, using the same material as insulator 216. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Alternatively, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferred because they readily form regions containing oxygen that has been released upon heating.

[0206] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, silicon oxides such as silicon oxide and silicon oxynitride can be appropriately used as the insulator 280.

[0207] The insulator 282 is preferably a barrier insulating film used to inhibit the diffusion of impurities such as water and hydrogen from above into the insulator 280, and also has the function of capturing impurities such as hydrogen. Furthermore, the insulator 282 is preferably a barrier insulating film used to inhibit oxygen permeation. As the insulator 282, a metal oxide with an amorphous structure, such as aluminum oxide, can be used. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282, which is in contact with the insulator 280 and has the function of capturing impurities such as hydrogen, in the region sandwiched between the insulator 212 and the insulator 283, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, the insulator 282 is preferably made of aluminum oxide with an amorphous structure, because it can sometimes capture or fix hydrogen more effectively. Therefore, a transistor 200 and a semiconductor device with good characteristics and high reliability can be manufactured.

[0208] As the insulator 282, it is preferable to deposit alumina by sputtering, and more preferably, to deposit alumina using an aluminum target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, thereby improving the sputtering rate and film quality. Here, RF (Radio Frequency) power can also be applied to the substrate. The amount of oxygen injected into the underlying layer of the insulator 282 can be controlled according to the magnitude of the RF power applied to the substrate. For example, the lower the RF power, the less oxygen is injected into the underlying layer of the insulator 282, and the oxygen is easily saturated even if the insulator 282 is thin. Conversely, the higher the RF power, the more oxygen is injected into the underlying layer of the insulator 282.

[0209] As for the RF power, it is set to, for example, above 0 W / cm² and below 1.86 W / cm². In other words, the oxygen content can be changed to an amount suitable for the characteristics of the transistor and injected according to the RF power when forming the insulator 282. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected.

[0210] In addition, the RF frequency is preferably above 10MHz. A typical frequency is 13.56MHz. The higher the RF frequency, the less damage it can cause to the substrate.

[0211] In Figures 1A to 1D, the insulator 282 is shown to have a single-layer structure, but the present invention is not limited to this and may also employ a stacked structure of two or more layers. For example, as shown in Figure 5A, the insulator 282 may also employ a two-layer stacked structure of insulator 282a and insulator 282b on insulator 282a.

[0212] Preferably, insulators 282a and 282b are formed using the same material but different methods. For example, when aluminum oxide is deposited as insulator 282 using an aluminum target in an oxygen-containing atmosphere by pulsed DC sputtering, it is preferable that the RF power applied to the substrate when depositing insulator 282a is different from the RF power applied to the substrate when depositing insulator 282b, and more preferably, the RF power applied to the substrate when depositing insulator 282a is lower than the RF power applied to the substrate when depositing insulator 282b. Specifically, insulator 282a is deposited with an RF power applied to the substrate of 0 W / cm² or more and 0.62 W / cm² or less, and insulator 282b is deposited with an RF power applied to the substrate of 1.86 W / cm² or less. More specifically, the RF power applied to the substrate is set to 0 W / cm² for depositing insulator 282a, and the RF power applied to the substrate is set to 0.31 W / cm² for depositing insulator 282b. By adopting this structure, insulator 282 can be made amorphous and the amount of oxygen supplied to insulator 280 can be adjusted.

[0213] Note that the RF power applied to the substrate during insulator deposition 282a can also be higher than the RF power applied to the substrate during insulator deposition 282b. Specifically, the RF power applied to the substrate during insulator deposition 282a is set to 1.86 W / cm² or less, and the RF power applied to the substrate during insulator deposition 282b is set to 0 W / cm² or more but 0.62 W / cm² or less. More specifically, the RF power applied to the substrate during insulator deposition 282a is set to 1.86 W / cm², and the RF power applied to the substrate during insulator deposition 282b is set to 0.62 W / cm². By employing this structure, the amount of oxygen supplied to insulator 280 can be increased.

[0214] Furthermore, the film thickness of insulator 282a is 1 nm or more and 20 nm or less, preferably 1.5 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, and even more preferably 3 nm or more and 8 nm or less. By adopting this structure, insulator 282a can be made amorphous regardless of the RF power. Additionally, by making insulator 282a amorphous, insulator 282b can easily become amorphous, and insulator 282 can also become amorphous.

[0215] The insulators 282a and 282b described above have a laminated structure made of the same material, but the present invention is not limited thereto. Insulators 282a and 282b may also have a laminated structure made of different materials.

[0216] Part of the top surface of insulator 283 is in contact with a portion of the top surface of insulator 214, a side surface of insulator 216, a side surface of insulator 222, a side surface of insulator 275, a side surface of insulator 280, and a side surface and top surface of insulator 282.

[0217] Insulator 283 serves as a barrier insulating film to prevent impurities such as water and hydrogen from diffusing from above into insulator 280. Insulator 283 is disposed on insulator 282. Preferably, silicon-containing nitrides such as silicon nitride or silicon oxynitride are used as insulator 283. For example, silicon nitride deposited by sputtering can be used as insulator 283. By depositing insulator 283 by sputtering, a high-density silicon nitride film can be formed. Furthermore, silicon nitride deposited by PEALD or CVD can also be layered on top of silicon nitride deposited by sputtering as insulator 283.

[0218] Conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Alternatively, conductors 240a and 240b may also have a laminated structure.

[0219] When the conductor 240 is arranged in a multilayer structure, the first conductor disposed near the insulators 285, 283, 282, 280, 275, and 271 is preferably a conductive material that suppresses the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. The conductive material that suppresses the permeation of impurities such as water and hydrogen can be used as a single layer or in multilayers. In addition, it can prevent impurities such as water and hydrogen contained in the layer above the insulator 283 from being mixed into the oxide 230 through the conductors 240a and 240b.

[0220] As insulators 241a and 241b, barrier insulating films suitable for insulators 275 and the like can be used. For example, silicon nitride, aluminum oxide, and silicon oxynitride can be used as insulators 241a and 241b. Because insulators 241a and 241b are disposed in contact with insulators 283, 282, and 271, impurities such as water and hydrogen contained in insulators 280 can be prevented from being mixed into oxide 230 through conductors 240a and 240b. In particular, silicon nitride has high hydrogen barrier properties, so it is preferred. Furthermore, it can prevent oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0221] When insulators 241a and 241b have a laminated structure as shown in FIG1B, it is preferable that an oxygen-barrier insulating film and a hydrogen-barrier insulating film are used in combination as the first insulator that contacts the inner wall of the opening of insulator 280 and the second insulator inside it.

[0222] For example, aluminum oxide deposited using the ALD method can be used as the first insulator, and silicon nitride deposited using the PEALD method can be used as the second insulator. By adopting such a structure, the oxidation of the conductor 240 can be suppressed, and the entry of hydrogen into the conductor 240 can be suppressed.

[0223] Conductors 246 (conductors 246a and 246b) used for wiring can be configured to contact the top surfaces of conductors 240a and 240b. Conductors 246 are preferably made of conductive materials primarily composed of tungsten, copper, or aluminum. Furthermore, the conductor can have a laminated structure, for example, a laminated structure of titanium or titanium nitride with the aforementioned conductive material. Additionally, the conductor can also be formed by embedding it in an opening formed in an insulator.

[0224] Materials Constituting Semiconductor Devices The following describes the constituent materials that can be used in semiconductor devices.

[0225] <<Substrate>> The substrate for forming the transistor 200 can be an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Additionally, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Alternatively, substrates with components mounted on them can be used. Examples of components mounted on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0226] <<Insulators>> As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0227] For example, when miniaturizing and hyper-integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using high-k materials as the gate insulator, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. On the other hand, by using materials with relatively low permittivity in the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0228] Examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0229] Examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide or resin.

[0230] Furthermore, by surrounding a transistor using a metal oxide with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical properties of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride, can be used as insulators that suppress the permeation of impurities such as hydrogen and oxygen.

[0231] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is removed by heating is contacted with the oxide 230, the oxygen vacancies contained in the oxide 230 can be filled.

[0232] <<Conductors>> As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, so they are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicates can also be used.

[0233] Furthermore, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0234] Furthermore, when using oxides in the channel forming region of a transistor, it is preferable to employ a laminated structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material as the conductor used as the gate electrode. In this case, it is preferable to place the oxygen-containing conductive material on one side of the channel forming region. By placing the oxygen-containing conductive material on one side of the channel forming region, oxygen detached from the conductive material can be easily supplied to the channel forming region.

[0235] In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide can also be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide in which the channel is formed can sometimes be captured. Or, hydrogen mixed in from external insulators or the like can sometimes be captured.

[0236] <<Metal Oxides>> As oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that is used as a semiconductor. Hereinafter, a metal oxide that can be used as oxide 230 according to the present invention will be described.

[0237] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Furthermore, it preferably also contains aluminum, gallium, yttrium, tin, etc. Additionally, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0238] This case considers the metal oxide as an In-M-Zn oxide containing indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin. Other elements that can be used with element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. Note that multiple of the above elements can sometimes be combined as element M. In particular, element M is preferably selected from one or more of gallium, aluminum, yttrium, and tin.

[0239] In particular, the semiconductor layer of the transistor is preferably an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO). Alternatively, the semiconductor layer of the transistor can also be an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO). Alternatively, the semiconductor layer can also be an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO).

[0240] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0241] The following is an example of a metal oxide containing indium (In), gallium (Ga), and zinc (Zn). Note that oxides containing indium (In), gallium (Ga), and zinc (Zn) are sometimes referred to as In-Ga-Zn oxides.

[0242] <Classification of Crystal Structures> Examples of crystalline structures for oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.

[0243] X-ray diffraction (XRD) spectroscopy can be used to evaluate the crystal structure of films or substrates. For example, the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) can be used for evaluation. Furthermore, the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement will sometimes be simply referred to as the XRD spectrum.

[0244] For example, the peak shapes of the XRD spectrum of a quartz glass substrate are roughly symmetrical from left to right. On the other hand, the peak shapes of the XRD spectrum of an In-Ga-Zn oxide film with a crystalline structure are not symmetrical from left to right. The asymmetry of the XRD peak shapes indicates the presence of crystals in the film or substrate. In other words, unless the XRD peak shapes are symmetrical from left to right, it cannot be said that the film or substrate is in an amorphous state.

[0245] Furthermore, the crystal structure of the film or substrate can be evaluated using diffraction patterns observed by nano-beam electron diffraction (NBED). For example, the observation of a halo pattern in the diffraction pattern of a quartz glass substrate confirms that the quartz glass is in an amorphous state. Conversely, a spot-like pattern without a halo is observed in the diffraction pattern of an In-Ga-Zn oxide film deposited at room temperature. Therefore, it can be inferred that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state, neither monocrystalline nor polycrystalline nor amorphous, and the conclusion that the In-Ga-Zn oxide is amorphous cannot be drawn.

[0246] <<Structure of Oxide Semiconductors>> Furthermore, when considering the structure of oxide semiconductors, the classification of oxide semiconductors sometimes differs from that described above. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include, for instance, CAAC-OS and nc-OS, as mentioned above. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors, etc.

[0247] Here, we will explain the details of CAAC-OS, nc-OS, and a-like OS.

[0248] [CAAC-OS] CAAC-OS is an oxide semiconductor comprising multiple crystalline regions, whose c-axis is aligned in a specific direction. This specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. Furthermore, a crystalline region is a region exhibiting a periodic atomic arrangement. Note that when atomic arrangement is considered as lattice arrangement, a crystalline region is also a region with a consistent lattice arrangement. Moreover, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and sometimes this region exhibits distortion. Distortion refers to the portion of the lattice arrangement direction that changes between lattice-aligned regions and other lattice-aligned regions within the region where multiple crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor with c-axis alignment but no obvious alignment in the ab-plane direction.

[0249] Furthermore, each of the aforementioned multiple crystalline regions is composed of one or more microcrystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single microcrystal, the maximum diameter of that crystalline region is less than 10 nm. Conversely, when a crystalline region is composed of multiple microcrystals, the maximum diameter of that crystalline region is sometimes around tens of nm.

[0250] Furthermore, in In-Ga-Zn oxides, there is a tendency for CAAC-OS to exhibit a layered crystal structure (also known as a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter, In layers) and layers containing gallium (Ga), zinc (Zn), and oxygen (hereinafter, (Ga,Zn) layers). In addition, indium and gallium can substitute for each other. Therefore, sometimes the (Ga,Zn) layer contains indium. Furthermore, sometimes the In layer contains gallium. Note that sometimes the In layer contains zinc. This layered structure is observed, for example, as a lattice image in high-resolution TEM (Transmission Electron Microscope) images.

[0251] For example, when performing structural analysis on CAAC-OS films using an XRD apparatus, a peak representing c-axis alignment is detected at or near 2θ = 31° in out-of-plane XRD measurements using θ / 2θ scanning. Note that the position (2θ value) of the peak representing c-axis alignment sometimes varies depending on the type and composition of the metallic elements constituting CAAC-OS.

[0252] Furthermore, for example, multiple bright spots (spots) were observed in the electron diffraction pattern of the CAAC-OS film. Additionally, when the spot of the incident electron beam passing through the sample (also known as the direct spot) is taken as the center of symmetry, one spot and other spots were observed at point-symmetrical positions.

[0253] When observing the crystalline region from the aforementioned specific directions, although the lattice arrangement in this region is primarily hexagonal, the unit lattice is not limited to a regular hexagon; there are also cases where it is non-regular hexagonal. Furthermore, in the aforementioned distortions, pentagonal, heptagonal, and other lattice arrangements are sometimes observed. Moreover, no clear grain boundary is observed near the distortion in CAAC-OS. That is, the lattice arrangement distortion inhibits grain boundary formation. This may be because CAAC-OS can accommodate distortion due to the low density of oxygen atoms along the ab plane or changes in the bonding distance between atoms caused by the substitution of metal atoms.

[0254] Furthermore, crystalline structures with clearly defined grain boundaries are called polycrystalline structures. Grain boundaries act as recombination centers, trapping carriers and potentially leading to a decrease in the transistor's on-state current and field-effect mobility. Therefore, CAAC-OS, which lacks clearly defined grain boundaries, is one of the crystalline oxides that provides an excellent crystalline structure for the semiconductor layer of the transistor. Note that a Zn-containing structure is preferred for constructing CAAC-OS. For example, In-Zn oxides and In-Ga-Zn oxides are preferred because they can further suppress grain boundary formation compared to In oxides.

[0255] CAAC-OS is a highly crystalline oxide semiconductor with indistinct grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Furthermore, the crystallinity of oxide semiconductors can sometimes decrease due to impurities or defects; thus, CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Consequently, oxide semiconductors containing CAAC-OS possess high heat resistance and high reliability. Moreover, CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS to include metal oxides (sometimes referred to as OS transistors) in the channel formation region, process flexibility can be expanded.

[0256] [nc-OS] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. In other words, nc-OS possesses tiny crystallinity. Furthermore, for example, these tiny crystallinity sizes are between 1 nm and 10 nm, particularly between 1 nm and 3 nm; these tiny crystallinity sizes are referred to as nanocrystals. Moreover, no regularity in crystallinity orientation is observed between different nanocrystals in nc-OS. Therefore, no alignment is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods. For example, when performing structural analysis on nc-OS films using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when performing electron diffraction (also known as selected area electron diffraction) on nc-OS films using an electron beam with a beam diameter larger than that of nanocrystals (e.g., larger than 50 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also known as nano-beam electron diffraction) is performed on nc-OS films using an electron beam whose beam diameter is close to or smaller than the size of nanocrystals (e.g., more than 1 nm and less than 30 nm), sometimes an electron diffraction pattern of multiple spots is observed in an annular region centered on a direct spot.

[0257] [a-like OS] a-like OS is an oxide semiconductor with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the hydrogen concentration in a-like OS films is higher than that in nc-OS and CAAC-OS films.

[0258] <<Structure of Oxide Semiconductors>> Next, the details of CAC-OS will be explained. Furthermore, CAC-OS is related to material composition.

[0259] [CAC-OS] CAC-OS, for example, refers to a composition in which elements are non-uniformly distributed within a metal oxide, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed within a metal oxide and the regions containing those metal elements are mixed is also referred to as mosaic or patch-like, wherein the size of the region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately.

[0260] Furthermore, CAC-OS refers to a structure in which the material is divided into a first region and a second region, forming a mosaic-like structure, with the first region distributed throughout the film (hereinafter also referred to as cloud-like). In other words, CAC-OS refers to a composite metal oxide having a structure that combines the first and second regions.

[0261] Here, each of the atomic ratios of In, Ga, and Zn, relative to the metal elements constituting the CAC-OS in In-Ga-Zn oxide, is denoted as [In], [Ga], and [Zn]. For example, in the CAC-OS of In-Ga-Zn oxide, a first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. Furthermore, a second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Alternatively, for example, a first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. Furthermore, a second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0262] Specifically, the first region mentioned above is a region whose main component is indium oxide or indium zinc oxide. Furthermore, the second region mentioned above is a region whose main component is gallium oxide or gallium zinc oxide. In other words, the first region can be referred to as a region whose main component is In. Furthermore, the second region can be referred to as a region whose main component is Ga.

[0263] Note that sometimes the clear boundaries between the first region and the second region mentioned above are not observable.

[0264] Furthermore, CAC-OS in In-Ga-Zn oxides refers to a structure in which regions dominated by Ga and regions dominated by In are irregularly arranged in a mosaic pattern within a material containing In, Ga, Zn, and O. Therefore, it can be inferred that CAC-OS has a structure with uneven distribution of metallic elements.

[0265] CAC-OS can be formed, for example, by sputtering without heating the substrate. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gases, and nitrogen gases can be used as the deposition gas. Furthermore, the lower the oxygen gas flow rate in the total flow rate of the deposition gas during deposition, the better. For example, the oxygen gas flow rate in the total flow rate of the deposition gas during deposition should be 0% or more and less than 30%, preferably 0% or more and less than 10%.

[0266] For example, in CAC-OS of In-Ga-Zn oxide, based on the EDX surface analysis (mapping) image obtained by Energy Dispersive X-ray spectroscopy (EDX), a structure with an unevenly distributed and mixed structure of regions with In as the main component (first region) and regions with Ga as the main component (second region) can be identified.

[0267] Here, the first region has higher conductivity than the second region. That is, when carriers flow through the first region, it exhibits the conductivity of a metal oxide. Therefore, when the first region is distributed in a cloud-like manner within the metal oxide, a high field mobility (μ) can be achieved.

[0268] On the other hand, the second region has higher insulation properties than the first region. That is, when the second region is distributed in the metal oxide, it can suppress the off-state current.

[0269] When CAC-OS is used in transistors, the complementary effect of conductivity arising from the first region and insulation arising from the second region enables CAC-OS to possess switching functionality (the function of controlling on / off). In other words, a portion of the CAC-OS material exhibits conductivity while another portion exhibits insulation, resulting in a semiconductor function within the overall material. By separating the conductive and insulating functions, each function can be maximized. Therefore, by using CAC-OS in transistors, high on-state current (Ion), high field-effect mobility (μ), and excellent switching performance can be achieved.

[0270] Furthermore, transistors using CAC-OS exhibit high reliability. Therefore, CAC-OS is best suited for various semiconductor devices, such as display devices.

[0271] Oxide semiconductors possess various structures and properties. In one embodiment of the present invention, the oxide semiconductor may also include two or more of the following: amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0272] <Including oxide semiconductor transistors> Next, the use of the aforementioned oxide semiconductor in transistors will be explained.

[0273] By using the aforementioned oxide semiconductors in transistors, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can be achieved.

[0274] It is preferable to use oxide semiconductors with low carrier concentrations in transistors. For example, the carrier concentration of the oxide semiconductor can be 1×10¹⁷ cm⁻³ or less, preferably 1×10¹⁵ cm⁻³ or less, more preferably 1×10¹³ cm⁻³ or less, further preferably 1×10¹¹ cm⁻³ or less, and even more preferably less than 1×10¹⁰ cm⁻³ and greater than 1×10⁻⁹ cm⁻³. When the purpose is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as high-purity nature or substantially high-purity nature. Furthermore, oxide semiconductors with low carrier concentrations are sometimes referred to as oxide semiconductors with high-purity nature or substantially high-purity nature.

[0275] Because high-purity or essentially high-purity oxide semiconductor films have a low defect state density, they may also have a low trap state density.

[0276] Furthermore, the charge trapped in the trap state of an oxide semiconductor takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical properties of transistors forming channel formation regions in oxide semiconductors with high trap state density are sometimes unstable.

[0277] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical properties of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to elements other than the main components constituting the oxide semiconductor. For example, elements with a concentration less than 0.1 atomic% can be considered impurities.

[0278] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0279] When an oxide semiconductor contains silicon or carbon, one of the elements in Group 14, defect states are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (the concentration measured by secondary ion mass spectrometry) is set, for example, to be 2 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁷ atoms / cm³ or less.

[0280] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states can sometimes be formed, thus creating carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to have always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor, as measured by SIMS, is set to 1 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁶ atoms / cm³ or less.

[0281] When oxide semiconductors contain nitrogen, electrons are generated as carriers, increasing the carrier concentration and making them more susceptible to n-type conversion. As a result, transistors using nitrogen-containing oxide semiconductors tend to have always-on characteristics. Alternatively, when oxide semiconductors contain nitrogen, trapped states sometimes form. Consequently, the electrical properties of the transistors can sometimes be unstable. Therefore, the nitrogen concentration in the oxide semiconductor, measured using SIMS, is set to be below 5 × 10¹⁹ atoms / cm³, preferably below 5 × 10¹⁸ atoms / cm³, more preferably below 1 × 10¹⁸ atoms / cm³, and even more preferably below 5 × 10¹⁷ atoms / cm³.

[0282] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as carriers. Furthermore, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as carriers. Therefore, transistors using oxide semiconductors containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the oxide semiconductor. Specifically, the hydrogen concentration in the oxide semiconductor, as measured by SIMS, is set to be less than 1 × 10²⁰ atoms / cm³, preferably less than 1 × 10¹⁹ atoms / cm³, more preferably less than 5 × 10¹⁸ atoms / cm³, and even more preferably less than 1 × 10¹⁸ atoms / cm³.

[0283] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can be made to have stable electrical characteristics.

[0284] <<Other Semiconductor Materials>> Oxide 230 can be referred to as a semiconductor layer including the channel forming region of transistor 200. Note that the semiconductor material that can be used for this semiconductor layer is not limited to the aforementioned metal oxide. As this semiconductor layer, a semiconductor material with a band gap (a semiconductor material that is not a zero band gap semiconductor) can also be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layered material used as a semiconductor (also called an atomic layer material, a two-dimensional material, etc.). In particular, it is preferable to use a layered material used as a semiconductor as the semiconductor material.

[0285] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure formed by layers of covalent or ionic bonds stacked together by bonds weaker than covalent and ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity, intended for use as a semiconductor, in the channel-forming region, transistors with high on-state current can be provided.

[0286] As layered materials, examples include graphene, silicon, and chalcogenides. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0287] As a semiconductor layer, it is preferable to use transition metal chalcogenides that are used as semiconductors. Examples of transition metal chalcogenides that can be used as semiconductor layers include molybdenum sulfide (typically MoS₂), molybdenum selenide (typically MoSe₂), molybdenum telluride (typically MoTe₂), tungsten sulfide (typically WS₂), tungsten selenide (typically WSe₂), tungsten telluride (typically WTe₂), hafnium sulfide (typically HfS₂), hafnium selenide (typically HfSe₂), zirconium sulfide (typically ZrS₂), and zirconium selenide (typically ZrSe₂).

[0288] <Methods for Manufacturing Semiconductor Devices> Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention shown in Figures 1A to 20D will be described using Figures 10A to 20D.

[0289] In each figure, A is a top view. Additionally, B in each figure is a cross-sectional view along the dashed line A1-A2 in A, which corresponds to a cross-sectional view along the channel length direction of transistor 200. C in each figure is a cross-sectional view along the dashed line A3-A4 in A, which corresponds to a cross-sectional view along the channel width direction of transistor 200. Furthermore, D in each figure is a cross-sectional view along the dashed line A5-A6 in A. For clarity, some components are omitted in the top view of A in each figure.

[0290] The insulating materials used to form insulators, the conductive materials used to form conductors, or the semiconductor materials used to form semiconductors can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD.

[0291] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0292] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0293] By utilizing plasma CVD, high-quality films can be obtained at lower temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece can be reduced. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage these components. On the other hand, since thermal CVD, which does not use plasma, does not produce this type of plasma damage, the yield of semiconductor devices can be improved. Moreover, since plasma damage during deposition is not generated in thermal CVD, films with fewer defects can be obtained.

[0294] As an ALD method, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants that have been excited by plasma.

[0295] CVD and ALD methods differ from sputtering methods that deposit particles released from a target or similar material. Therefore, films formed by CVD and ALD methods are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed by ALD methods have excellent step coverage and thickness uniformity, making ALD suitable for forming films covering surfaces with high aspect ratio openings. However, the deposition rate of ALD is relatively slow, so it is sometimes preferable to combine it with other deposition methods such as CVD, which have faster deposition rates.

[0296] Furthermore, when using CVD, films of arbitrary composition can be deposited by adjusting the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to using multiple deposition chambers because the time required for transmission or pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0297] When using the ALD method, membranes of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, membranes of arbitrary composition can be deposited.

[0298] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 10A to 10D). The insulator 212 is preferably deposited using a sputtering method. By using a sputtering method, which does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. Note that the deposition of the insulator 212 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used.

[0299] In this embodiment, silicon nitride is deposited using a silicon target as the insulator 212 in a nitrogen-containing gas atmosphere via pulsed DC sputtering. By using pulsed DC sputtering, particles generated due to arcing on the target surface can be suppressed, resulting in a more uniform thickness. Furthermore, by using pulsed voltage, the rise and fall during discharge can be more rapid compared to high-frequency voltage. This allows for more efficient power supply to the electrodes, thereby improving the sputtering rate and film quality.

[0300] Furthermore, by using an insulator such as silicon nitride, which does not easily allow impurities such as water and hydrogen to pass through, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Moreover, by using an insulator such as silicon nitride, which does not easily allow copper to pass through, even if a metal such as copper, which easily diffuses, is used as the conductor in the layer below the insulator 212 (not shown), the diffusion of that metal upwards through the insulator 212 can be suppressed.

[0301] Next, insulator 214 is deposited on insulator 212 (see Figures 10A to 10D). Insulator 214 is preferably deposited using a sputtering method. By using a sputtering method, which does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in insulator 214 can be reduced. Note that the deposition of insulator 214 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used.

[0302] In this embodiment, aluminum oxide is deposited using an aluminum target in an oxygen-containing gas atmosphere via pulsed DC sputtering as the insulator 214. Using pulsed DC sputtering allows for more uniform thickness, improving sputtering rate and film quality. RF power can also be applied to the substrate. The amount of oxygen injected into the lower layer of the insulator 214 can be controlled by adjusting the RF power applied to the substrate. The RF power is set to 0 W / cm² or higher and 1.86 W / cm² or lower. In other words, the RF power used during insulator 214 formation can be used to modify the oxygen content to an amount suitable for transistor characteristics before injection. Therefore, an amount of oxygen suitable for improving transistor reliability can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage to the substrate can be caused.

[0303] As the insulator 214, a metal oxide with an amorphous structure, such as aluminum oxide, is preferably used, as it has high hydrogen trapping and fixation performance. This allows hydrogen contained in the insulator 216 to be trapped or fixed, preventing the hydrogen from diffusing into the oxide 230. In particular, the insulator 214 is especially preferably made of amorphous aluminum oxide or aluminum oxide with an amorphous structure, because it can sometimes trap or fix hydrogen more effectively. This allows the manufacture of a transistor 200 and semiconductor device with good properties and high reliability.

[0304] Next, insulator 216 is deposited on insulator 214. Insulator 216 is preferably deposited using a sputtering method. By using sputtering, which does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in insulator 216 can be reduced. Note that the deposition of insulator 216 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used.

[0305] In this embodiment, silicon oxide is deposited using a silicon target in an oxygen-containing atmosphere via pulsed DC sputtering as the insulator 216. By using pulsed DC sputtering, the thickness can be made more uniform, thereby improving the sputtering rate and film quality.

[0306] Insulators 212, 214, and 216 are preferably deposited continuously without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the film, and also reduces hydrogen ingress into the film between deposition processes.

[0307] Next, an opening leading to insulator 214 is formed in insulator 216. The opening may include, for example, a groove or slit. The area where the opening is formed is sometimes referred to as the opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. As insulator 214, it is preferable to select an insulator that serves as an etch stop film when etching insulator 216 to form the groove. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide are preferably used as insulator 214.

[0308] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure in which a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of the same frequency are applied to each of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of different frequencies are applied to each of the parallel planar electrodes can be used. Alternatively, a dry etching apparatus with a high-density plasma source can also be used. For example, as a dry etching apparatus with a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0309] After the opening is formed, a conductive film is deposited to form conductor 205a. This conductive film preferably includes a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of a conductor that inhibits oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. This conductive film can be deposited using sputtering, CVD, MBE, PLD, ALD, and other methods.

[0310] In this embodiment, titanium nitride is deposited as a conductive film serving as conductor 205a. By using the aforementioned metal nitride as the underlying layer of conductor 205b, oxidation of conductor 205b, such as insulator 216, can be suppressed. Furthermore, even if a metal that easily diffuses, such as copper, is used as conductor 205b, diffusion of that metal from conductor 205a to the outside can be prevented.

[0311] Next, a conductive film is deposited to form the conductor 205b. Tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used as this conductive film. The conductive film can be deposited using electroplating, sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, tungsten is deposited as the conductive film.

[0312] Next, the conductive film that becomes conductor 205a and a portion of the conductive film that becomes conductor 205b are removed by CMP treatment, exposing the insulator 216 (see Figures 10A to 10D). As a result, conductors 205a and 205b remain only in the opening. In addition, sometimes a portion of the insulator 216 is removed by this CMP treatment.

[0313] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 11A to 11D). Preferably, the insulator 222 is an insulator containing an oxide of one or both of aluminum and hafnium. Preferably, the insulator containing an oxide of one or both of aluminum and hafnium is aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, hafnium zirconium oxide is preferred. The insulator containing an oxide of one or both of aluminum and hafnium provides barrier properties against oxygen, hydrogen, and water. When the insulator 222 provides barrier properties against hydrogen and water, it can suppress the diffusion of hydrogen and water contained in the surrounding structure of the transistor 200 into the interior of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0314] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method. In particular, a method for forming hafnium oxide with a reduced hydrogen concentration according to an embodiment of the present invention is preferred.

[0315] Next, heat treatment is preferably performed. The heat treatment is performed at a temperature of 250°C or higher and 650°C, preferably 300°C or higher and 500°C, and more preferably 320°C or higher and 450°C. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the proportion of oxygen gas can be set to approximately 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0316] Furthermore, the gas used in the above heat treatment is preferably highly purified. For example, the water content of the gas used in the heat treatment is less than 1 ppb, preferably less than 0.1 ppb, and more preferably less than 0.05 ppb. By using a highly purified gas for heat treatment, the absorption of moisture and the like by the insulator 222 can be prevented as much as possible.

[0317] In this embodiment, as a heat treatment, the insulator 222 is subjected to a process at a nitrogen to oxygen gas flow ratio of 4:1 and a temperature of 400°C for 1 hour. This heat treatment removes impurities such as water and hydrogen contained in the insulator 222. Furthermore, when a hafnium-containing oxide is used as the insulator 222, this heat treatment sometimes crystallizes a portion of the insulator 222. Alternatively, the heat treatment can be performed after the insulator 224 is deposited, or at other times.

[0318] Next, an insulating film 224A is deposited on the insulator 222 (see Figures 11A to 11D). The insulating film 224A can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, a silicon oxide film is deposited as the insulating film 224A using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A comes into contact with the oxide 230a in subsequent processes, it is preferable to reduce the hydrogen concentration in this way.

[0319] Next, oxide films 230A and 230B are sequentially deposited on the insulating film 224A (see Figures 11A to 11D). Preferably, oxide films 230A and 230B are deposited continuously without exposure to the atmospheric environment. By performing the deposition without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide films 230A and 230B, thus keeping the area near the interface between oxide films 230A and 230B clean.

[0320] Oxide films 230A and 230B can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. Depositing oxide films 230A and 230B using the ALD method allows for the formation of films of uniform thickness even in trenches or openings with large aspect ratios, making it preferable. Furthermore, the PEALD method allows for the formation of oxide films 230A and 230B at a lower temperature compared to the thermal ALD method, making it also preferable. In this embodiment, sputtering is used for the deposition of oxide films 230A and 230B.

[0321] For example, when depositing oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and noble gases is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above-mentioned oxide films using sputtering, the aforementioned In-M-Zn oxide target can be used, for example.

[0322] In particular, during the deposition of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulator 224. Therefore, the oxygen content in the sputtering gas can be 70% or more, preferably 80% or more, and more preferably 100%.

[0323] When forming the oxide film 230B using sputtering, an oxygen-excess oxide semiconductor can be formed by deposition under conditions where the oxygen content in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%. Using an oxygen-excess oxide semiconductor as a transistor in the channel formation region can result in higher reliability. Note that one embodiment of the invention is not limited thereto. When forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when deposition is performed under conditions where the oxygen content in the sputtering gas is set to more than 1% and less than 30%, preferably more than 5% and less than 20%. Using an oxygen-deficient oxide semiconductor as a transistor in the channel formation region can result in higher field-effect mobility. Furthermore, by performing deposition while heating the substrate, the crystallinity of the oxide film can be improved.

[0324] In this embodiment, an oxide film 230A is deposited using an oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic number ratio) via sputtering. Furthermore, an oxide film 230B is deposited using an oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic number ratio), an In:Ga:Zn ratio of 1:1:1 (atomic number ratio), an In:Ga:Zn ratio of 1:1:1.2 (atomic number ratio), or an In:Ga:Zn ratio of 1:1:2 (atomic number ratio). The deposition conditions and atomic number ratios for each oxide film can be appropriately selected based on the desired characteristics of oxides 230a and 230b.

[0325] Note that it is preferable to deposit the insulating film 224A, oxide film 230A, and oxide film 230B by sputtering without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This reduces the amount of hydrogen entering the insulating film 224A, oxide film 230A, and oxide film 230B between deposition processes.

[0326] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range that prevents polycrystalline formation in the oxide films 230A and 230B, preferably between 250°C and 650°C, and more preferably between 400°C and 600°C. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the proportion of oxygen gas can be set to approximately 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the released oxygen, heat treatment can be performed in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas.

[0327] Furthermore, the gas used in the above heat treatment is preferably highly purified. For example, the water content of the gas used in the heat treatment is less than 1 ppb, preferably less than 0.1 ppb, and more preferably less than 0.05 ppb. By using a highly purified gas for heat treatment, the absorption of moisture and other substances by the oxide film 230A, oxide film 230B, etc., can be prevented as much as possible.

[0328] In this embodiment, as a heat treatment, a process is performed for 1 hour at a nitrogen to oxygen gas flow ratio of 4:1 and a temperature of 400°C. This oxygen-containing heat treatment reduces impurities such as carbon, water, and hydrogen in the oxide films 230A and 230B. By reducing impurities in the films, the crystallinity of the oxide film 230B is improved, resulting in a denser structure. Therefore, the crystalline regions in the oxide films 230A and 230B can be increased, and the in-plane inhomogeneity of the crystalline regions in the oxide films 230A and 230B can be reduced. Therefore, the in-plane inhomogeneity of the electrical properties of the transistor 200 can be reduced.

[0329] Furthermore, through heat treatment, hydrogen in insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B is transferred to insulator 222 and absorbed by insulator 222. In other words, hydrogen in insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B diffuses into insulator 222. Therefore, although the hydrogen concentration in insulator 222 increases, the hydrogen concentration in insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B all decrease.

[0330] In particular, insulating film 224A is used as the gate insulator of transistor 200, and oxide films 230A and 230B are used as channel forming regions of transistor 200. Therefore, transistor 200 including insulating film 224A, oxide film 230A, and oxide film 230B with reduced hydrogen concentration has excellent reliability and is therefore preferred.

[0331] Next, a conductive film 242A is deposited on the oxide film 230B (see Figures 11A to 11D). The conductive film 242A can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. For example, tantalum nitride can be deposited as the conductive film 242A using sputtering. Furthermore, a heat treatment can be performed before depositing the conductive film 242A. This heat treatment can also be performed under reduced pressure, wherein the conductive film 242A is continuously deposited without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide films 230A and 230B can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is set to 200°C.

[0332] Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 11A to 11D). The insulating film 271A can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. Preferably, the insulating film 271A is an insulating film that inhibits oxygen permeation. For example, aluminum oxide or silicon nitride can be deposited as the insulating film 271A by sputtering. Alternatively, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film can also be deposited as the insulating film 271A by sputtering.

[0333] Preferably, the conductive film 242A and the insulating film 271A are deposited by sputtering in a manner that avoids exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This reduces the amount of hydrogen in the films during deposition of the conductive film 242A and the insulating film 271A, and also reduces hydrogen ingress into the films between deposition processes. Furthermore, when a hard mask is formed on the insulating film 271A, the film serving as the hard mask can also be continuously deposited in a manner that avoids exposure to the atmosphere.

[0334] Next, the insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A are processed into island shapes using photolithography to form insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B (see Figures 12A to 12D). Here, insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B are formed such that at least a portion of them overlaps with conductor 205. Furthermore, the above processing can be performed using dry etching or wet etching. Processing using dry etching is suitable for micro-processing. In addition, the processing of insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A can also be performed under different conditions.

[0335] Note that in photolithography, the photoresist is first exposed using a mask. Next, a developing solution is used to remove or leave the exposed area, forming a photoresist mask. Then, the photoresist mask can be etched to process a conductor, semiconductor, or insulator into the desired shape. For example, the photoresist mask can be formed by exposing the photoresist using a KrF excimer laser, an ArF excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Note that when using electron beams or ion beams, a mask is not required. Furthermore, the photoresist mask can be removed by dry etching (such as ashing), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0336] Furthermore, a hard mask made of an insulator or conductor can also be used under the photoresist mask. When using a hard mask, an insulating film or conductive film serving as the hard mask material can be formed on the conductive film 242A, and a photoresist mask can be formed thereon. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film 242A, etc., can be performed either after removing the photoresist mask or without removing the photoresist mask. In the latter case, the photoresist mask may disappear during etching. The hard mask can be removed by etching after etching the conductive film 242A, etc. On the other hand, it is not necessary to remove the hard mask if the hard mask material does not affect subsequent processes or can be used in subsequent processes. In this embodiment, the insulating layer 271B is used as the hard mask.

[0337] Here, the insulating layer 271B is used as a shield for the conductive layer 242B. As shown in Figures 12B to 12D, the conductive layer 242B does not have a curved surface between its side and top surfaces. Therefore, the ends where the side and top surfaces of conductors 242a and 242b shown in Figures 1B and 1D intersect are angled. When the ends where the side and top surfaces of conductor 242 intersect are angled, the cross-sectional area of ​​conductor 242 increases compared to the case where the ends have curved surfaces. This reduces the resistance of conductor 242, thereby increasing the on-state current of transistor 200.

[0338] Furthermore, as shown in Figures 12B to 12D, the side surface shapes of insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B can also be conical. Note that in this specification, a conical shape refers to a shape in which at least a portion of the side surface of the component is inclined relative to the substrate surface. For example, the angle formed by the inclined side surface and the substrate surface (hereinafter, sometimes referred to as the cone angle) is preferably less than 90°. Insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B are formed, for example, with a cone angle of 60° or more and less than 90°. When the side surface has such a conical shape, the coverage of insulator 275 and the like in subsequent processes is improved, and defects such as voids can be reduced.

[0339] However, it is not limited to this; a structure in which the sides of insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B are substantially perpendicular to the top surface of insulator 222 can also be adopted. By adopting such a structure, a smaller area and higher density can be achieved when multiple transistors 200 are installed.

[0340] Furthermore, sometimes byproducts generated during the above-described etching process form in layers on the sides of insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B. In this case, the layered byproducts form between insulator 224, oxide 230a, oxide 230b, conductive layer 242B, insulating layer 271B, and insulator 275. Therefore, it is preferable to remove the layered byproducts that contact the top surface of insulator 222.

[0341] Next, insulator 275 is deposited covering insulator 224, oxides 230a and 230b, conductive layer 242B, and insulating layer 271B (see Figures 13A to 13D). Preferably, insulator 275 is in close contact with the top surface of insulator 222 and the side surface of insulator 224. Insulator 275 can be deposited using sputtering, CVD, MBE, PLD, ALD, or similar methods. Preferably, insulator 275 is an insulating film that inhibits oxygen permeation. For example, silicon nitride can be deposited as insulator 275 using the ALD method. Alternatively, aluminum oxide can be deposited as insulator 275 by sputtering, and silicon nitride can be deposited thereon using the PEALD method. When insulator 275 has this layered structure, the ability to inhibit the diffusion of impurities such as water and hydrogen, as well as oxygen, is sometimes improved.

[0342] Thus, oxides 230a, oxides 230b, and conductive layer 242B can be covered by insulators 275 and insulating layer 271B, which have the function of inhibiting oxygen diffusion. As a result, oxygen can be prevented from diffusing directly from insulators 280, etc., into insulators 224, oxides 230a, oxides 230b, and conductive layer 242B in subsequent processes.

[0343] Next, an insulating film, forming insulator 280, is deposited on insulator 275. This insulating film can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. For example, a silicon oxide film can be deposited as this insulating film using sputtering. By depositing this insulating film using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in insulator 280 can be reduced. Furthermore, a heat treatment can be performed before depositing this insulating film. This heat treatment can also be performed under reduced pressure, wherein the insulating film is continuously deposited without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of insulator 275 can be removed, and the moisture and hydrogen concentrations in oxides 230a, oxides 230b, and insulator 224 can be reduced. This heat treatment can be performed under the conditions described above.

[0344] Next, by performing CMP treatment on the insulating film that becomes insulator 280, an insulator 280 with a flat top surface is formed (see Figures 13A to 13D). Alternatively, silicon nitride can be deposited on insulator 280, for example, by sputtering, until the silicon nitride reaches insulator 280, and then CMP treatment is performed.

[0345] Next, a portion of insulator 280, a portion of insulator 275, a portion of insulating layer 271B, and a portion of conductive layer 242B are processed to form an opening reaching oxide 230b. This opening is preferably formed in a manner that overlaps with conductor 205. By forming this opening, insulator 271a, insulator 271b, conductor 242a, and conductor 242b are formed (see Figures 14A to 14D).

[0346] Here, as shown in Figures 14B and 14C, the side shapes of insulators 280, 275, 271, and conductor 242 are sometimes conical. Furthermore, the cone angle of insulator 280 is sometimes larger than that of conductor 242. Additionally, although not shown in Figures 14A to 14C, the top of oxide 230b is sometimes removed when forming the aforementioned opening.

[0347] Furthermore, a portion of insulator 280, a portion of insulator 275, a portion of insulating layer 271B, and a portion of conductive layer 242B can be processed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Moreover, this processing can be performed under different conditions. For example, a portion of insulator 280 can be processed using dry etching, a portion of insulator 275 and a portion of insulating layer 271B can be processed using wet etching, and a portion of conductive layer 242B can be processed using dry etching.

[0348] Here, sometimes the following occurs: impurities adhere to the side surface of oxide 230a, the top and side surfaces of oxide 230b, the side surface of conductor 242, and the side surface of insulator 280; or the impurities diffuse into their interiors. Furthermore, a process to remove these impurities can be performed. Additionally, sometimes a damaged area is formed on the surface of oxide 230b due to the aforementioned dry etching. Such damaged areas can also be removed. Examples of such impurities include those caused by the following components: components contained in insulator 280, insulator 275, a portion of insulating layer 271B, and conductive layer 242B; components contained in the components used in the apparatus used to form the aforementioned opening; and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0349] In particular, impurities such as aluminum and silicon can sometimes reduce the crystallinity of oxide 230b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface and vicinity of oxide 230b. Furthermore, it is preferable to reduce the concentration of these impurities. For example, the concentration of aluminum atoms on and near the surface of oxide 230b can be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, further preferably 1.0 atomic% or less, and especially preferably less than 0.3 atomic%.

[0350] Due to impurities such as aluminum and silicon, the density of the crystal structure decreases in regions of low crystallinity of oxide 230b, resulting in the generation of a large amount of V OH, which makes the transistors prone to becoming normally on. Therefore, it is preferable to reduce or remove regions of low crystallinity of oxide 230b.

[0351] In contrast, oxide 230b preferably has a layered CAAC structure. In particular, it is preferable that the lower end of the drain of oxide 230b also has a CAAC structure. Here, in transistor 200, conductor 242a or conductor 242b and its vicinity are used as drains. In other words, oxide 230b near the lower end of conductor 242a (conductor 242b) preferably has a CAAC structure. Thus, by removing the region of low crystallinity of oxide 230b in the drain end that significantly affects the drain withstand voltage, thereby giving it a CAAC structure, variations in the electrical characteristics of transistor 200 can be further suppressed. Furthermore, the reliability of transistor 200 can be further improved.

[0352] To remove impurities and other contaminants that adhere to the surface of oxide 230b during the etching process described above, a washing process is performed. Washing methods include wet washing (also known as wet etching) using a washing solution, plasma treatment using plasma, and washing using heat treatment; combinations of these methods may also be appropriate. Note that this washing process sometimes deepens the aforementioned tank area.

[0353] As a wet washing process, an aqueous solution prepared by diluting ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water, or pure water or carbonated water can be used for washing. Alternatively, ultrasonic washing can be performed using the aforementioned aqueous solution, pure water, or carbonated water. Furthermore, a combination of the above washing methods can be appropriately combined.

[0354] Note that in this specification, the aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and the aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia. Furthermore, the concentration and temperature of the aqueous solution can be appropriately adjusted according to the impurities to be removed and the structure of the semiconductor device being cleaned. The ammonia concentration of the dilute ammonia is set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. Similarly, the hydrogen fluoride concentration of the dilute hydrofluoric acid is set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0355] Furthermore, for ultrasonic cleaning, a frequency of 200 kHz or higher is preferred, and a frequency of 900 kHz or higher is even more preferable. By using this frequency, damage to oxides such as 230b can be reduced.

[0356] Furthermore, the above washing process can be performed multiple times, or the washing solution can be changed for each washing process. For example, the first washing process can use dilute hydrofluoric acid or dilute ammonia, and the second washing process can use pure water or carbonated water.

[0357] In this embodiment, a wet wash is performed using dilute ammonia water as the washing treatment described above. This washing treatment removes impurities adhering to the surface of oxides 230a and 230b, or those diffused into their interior. Furthermore, it improves the crystallinity of oxide 230b.

[0358] Heat treatment can also be performed after the etching or washing described above. The heat treatment should be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment should be performed in an atmosphere containing nitrogen, an inert gas, or an oxidizing gas containing 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby reducing oxygen vacancies. Furthermore, the crystallinity of oxide 230b can be improved by performing the above heat treatment. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0359] Next, an insulating film 252A is deposited (see Figures 15A to 15D). The insulating film 252A can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. Preferably, the insulating film 252A is deposited using the ALD method. As mentioned above, the insulating film 252A is preferably deposited thinly, and thickness non-uniformity needs to be minimized. For this purpose, the ALD method is a deposition method that alternately introduces precursors and reactants (e.g., oxidants). Since the film thickness can be adjusted according to the number of cycles, the thickness can be precisely adjusted. Furthermore, as shown in Figures 15B and 15C, the insulating film 252A needs to be deposited with high coverage on the bottom and side surfaces of the openings formed in the insulator 280, etc. In particular, the insulating film 252A needs to be deposited with high coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since each atomic layer can be deposited on the bottom and sides of the opening, an insulating film 252A can be deposited in the opening with high coverage.

[0360] In addition, when depositing the insulating film 252A using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidants. By using ozone (O3) and oxygen (O2), which do not contain hydrogen, as oxidants, the amount of hydrogen diffusing into the oxide 230b can be reduced.

[0361] In this embodiment, aluminum oxide is deposited as the insulating film 252A by thermal ALD.

[0362] Next, an insulating film 250A is deposited (see Figures 15A to 15D). Here, heat treatment can also be performed before depositing the insulating film 250A, and preferably, this heat treatment is performed under reduced pressure to continuously deposit the insulating film 250A without exposure to the atmosphere. Furthermore, this heat treatment is preferably performed in an oxygen-containing atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in oxides 230a and 230b can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0363] The insulating film 250A can be deposited using methods such as sputtering, CVD, PECVD, MBE, PLD, and ALD. Preferably, the insulating film 250A is deposited using a deposition method that reduces or removes hydrogen atoms. This reduces the hydrogen concentration of the insulating film 250A. In subsequent processes, the insulating film 250A becomes an insulator 250a separated from the oxide 230b by a thinner insulator 252, thus further reducing the hydrogen concentration.

[0364] In this embodiment, silicon oxynitride is deposited as the insulating film 250A by PECVD.

[0365] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere. Furthermore, in this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower.

[0366] The dotted lines shown in Figures 15B to 15D represent high frequencies such as microwaves and RF, oxygen plasma, or oxygen free radicals. Microwave processing is preferably performed using a microwave processing apparatus that includes a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is set to 300 MHz or higher and 300 GHz or lower, preferably 2.4 GHz or higher and 2.5 GHz or lower, for example, 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave processing apparatus is 1000 W or higher and 10000 W or lower, preferably 2000 W or higher and 5000 W or lower. In addition, the microwave processing apparatus may also include a power supply for applying RF to one side of the substrate. Furthermore, by applying RF to one side of the substrate, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide 230b.

[0367] Furthermore, the aforementioned microwave treatment is preferably performed under reduced pressure, with a pressure of 10 Pa or more and 1000 Pa or less, preferably 300 Pa or more and 700 Pa or less. Additionally, the treatment temperature is 750 °C or less, preferably 500 °C or less, for example, around 250 °C. Alternatively, heat treatment can be performed continuously after oxygen plasma treatment without exposure to the atmosphere. For example, the treatment temperature can be 100 °C or more and 750 °C or less, preferably 300 °C or more and 500 °C or less.

[0368] Alternatively, for example, the microwave treatment described above can be performed using oxygen and argon gases. Here, the oxygen flow rate ratio (O₂ / (O₂+Ar)) is greater than 0% and less than 100%, preferably greater than 0% and less than 50%, more preferably more than 10% and less than 40%, and even more preferably more than 10% and less than 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. Furthermore, by preventing the introduction of excessive oxygen into the treatment chamber during microwave treatment, excessive reduction in carrier concentration in regions 230ba and 230bb can be prevented.

[0369] As shown in Figures 15B to 15D, by performing microwave treatment in an oxygen-containing atmosphere, oxygen gas plasma can be plasmaized using microwaves or high frequencies such as RF, and this oxygen plasma can act on the region between conductors 242a and 242b of oxide 230b. At this time, region 230bc can also be irradiated with microwaves or high frequencies such as RF. In other words, microwaves or RF, oxygen plasma, etc., can act on region 230bc as shown in Figure 2A. Through the action of plasma, microwaves, etc., the V OH in region 230bc can be separated, removing hydrogen from region 230bc. In other words, the V OH contained in region 230bc can be reduced. Therefore, the oxygen vacancies and V OH in region 230bc can be reduced, thereby lowering the carrier concentration. Furthermore, by supplying oxygen free radicals generated in the aforementioned oxygen plasma or oxygen contained in insulator 250 to the oxygen vacancies formed in region 230bc, the oxygen vacancies in region 230bc can be further reduced, thereby lowering the carrier concentration.

[0370] On the other hand, conductors 242a and 242b are provided in regions 230ba and 230bb as shown in FIG. 2A. Here, conductor 242 is preferably used as a shielding film to protect against the effects of microwaves, RF and other high frequencies or oxygen plasmas during microwave processing in an oxygen-containing atmosphere. Thus, conductor 242 preferably has the function of shielding electromagnetic waves of 300 MHz and above and 300 GHz and below, for example, 2.4 GHz and above and 2.5 GHz and below.

[0371] As shown in Figures 15B to 15D, conductors 242a and 242b shield against the effects of high frequencies such as microwaves or RF, and oxygen plasma, thus preventing their influence on regions 230ba and 230bb. Therefore, microwave treatment in regions 230ba and 230bb does not result in a decrease in VOH or excessive oxygen supply, thereby preventing a decrease in carrier concentration.

[0372] Furthermore, an oxygen-barrier insulator 252 is provided in contact with the sides of conductors 242a and 242b. Therefore, the formation of an oxide film on the sides of conductors 242a and 242b due to microwave processing can be suppressed.

[0373] The reliability of transistor 200 is improved because the film quality of insulator 252 and insulator 250a can be improved.

[0374] As described above, oxygen vacancies and V OH groups can be selectively removed from region 230bc of the oxide semiconductor, making region 230bc type I or substantially type I. Furthermore, excessive oxygen supply to regions 230ba and 230bb, which are used as source or drain regions, can be suppressed to maintain conductivity. Therefore, variations in the electrical characteristics of the transistor 200 can be suppressed, thereby suppressing non-uniformity in the electrical characteristics of the transistor 200 within the substrate surface.

[0375] Furthermore, in microwave processing, thermal energy is sometimes directly transferred to oxide 230b due to the electromagnetic interaction between microwaves and molecules in oxide 230b. Sometimes, this thermal energy heats oxide 230b. This heat treatment is sometimes referred to as microwave annealing. By performing microwave processing in an oxygen-containing atmosphere, effects equivalent to oxygen annealing can sometimes be obtained. Additionally, it can be considered that when oxide 230b contains hydrogen, the aforementioned thermal energy is transferred to the hydrogen in oxide 230b, and the activated hydrogen is released from oxide 230b.

[0376] The microwave treatment described above can also be performed after the deposition of insulating film 252A. Alternatively, microwave treatment can be performed after the deposition of insulating film 252A without performing microwave treatment after the deposition of insulating film 250A.

[0377] Furthermore, when the insulator 250 adopts the two-layer stacked structure shown in FIG. 2B, an insulating film as insulator 250b can be deposited after the aforementioned insulating film 250A is deposited. The insulating film as insulator 250b can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods. Preferably, the insulating film as insulator 250b is formed using an insulator that has the function of suppressing oxygen diffusion. By adopting this structure, the diffusion of oxygen contained in insulator 250a to conductor 260 can be suppressed. In other words, the reduction of the amount of oxygen supplied to oxide 230 can be suppressed. In addition, the oxidation of conductor 260 caused by oxygen contained in insulator 250a can be suppressed. The insulating film as insulator 250b can be made of the same material as insulator 222. For example, hafnium oxide can be deposited as the insulating film as insulator 250b using thermal ALD.

[0378] Note that when the insulator 250 has the two-layer stacked structure shown in FIG. 2B, the above-described microwave treatment can also be performed after the deposition of the insulating film 250A (refer to FIG. 15A to 15D). Alternatively, microwave treatment can be performed after the deposition of the insulating film that will become the insulator 250b, without performing microwave treatment after the deposition of the insulating film 250A.

[0379] Alternatively, heat treatment can be performed under reduced pressure after microwave treatment following the deposition of insulating films 252A and 250A, and after the deposition of the insulating film that becomes insulator 250b. This treatment efficiently removes hydrogen from insulating films 252A, 250A, the insulating film that becomes insulator 250b, oxide 230b, and oxide 230a. Furthermore, some hydrogen may sometimes be attracted by conductors 242 (conductors 242a and 242b). Furthermore, the step of performing heat treatment under reduced pressure after microwave treatment can be repeated. Repeated heat treatment further efficiently removes hydrogen from insulating films 252A, 250A, the insulating film that becomes insulator 250b, oxide 230b, and oxide 230a. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower. The microwave treatment described above, i.e., microwave annealing, can also be used as this heat treatment. This heat treatment may be omitted when the oxide 230b is sufficiently heated by microwave annealing.

[0380] Furthermore, by altering the film quality of insulating films 252A, 250A, and 250b (which become insulators) through microwave treatment, the diffusion of hydrogen, water, impurities, etc., can be suppressed. This suppresses the diffusion of hydrogen, water, impurities, etc., through insulator 252 to oxides 230b, oxides 230a, etc., caused by post-processing such as deposition of the conductive film that becomes conductor 260 or post-treatment such as heat treatment.

[0381] Next, an insulating film 254A is deposited (see Figures 16A to 16D). The insulating film 254A can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. Similar to the insulating film 252A, the insulating film 254A is preferably deposited using the ALD method. By using the ALD method, a thinner insulating film 254A can be deposited with high coverage. In this embodiment, silicon nitride is deposited as the insulating film 254A using the PEALD method.

[0382] Next, conductive films 260a and 260b are deposited sequentially. The conductive films 260a and 260b can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, titanium nitride is deposited as the conductive film 260a using ALD, and tungsten is deposited as the conductive film 260b using CVD.

[0383] Next, insulating films 252A, 250A, 254A, the conductive film that becomes conductor 260a, and the conductive film that becomes conductor 260b are polished using CMP processing until the insulator 280 is exposed, thereby forming insulators 252, 250, 254, and conductors 260a and 260b (see Figures 17A to 17D). Thus, insulator 252 is positioned to cover the opening reaching oxide 230b. Furthermore, conductor 260 is positioned to fill the opening, passing through insulators 252, 250, and 254.

[0384] Next, heat treatment can be performed under the same conditions as described above. In this embodiment, the treatment is carried out at 400°C for 1 hour in a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250 and 280. Furthermore, after the heat treatment described above, the deposition of insulator 282 is carried out continuously without exposure to the atmosphere.

[0385] Next, insulator 282 is formed on insulator 252, insulator 250, insulator 254, conductor 260, and insulator 280 (see Figures 17A to 17D). Insulator 282 can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. Sputtering is preferred for depositing insulator 282. By using sputtering, which does not require the use of hydrogen-containing molecules as deposition gas, the hydrogen concentration in insulator 282 can be reduced.

[0386] In this embodiment, aluminum oxide is deposited using an aluminum target in an oxygen-containing gas atmosphere via pulsed DC sputtering as the insulator 282. Using pulsed DC sputtering allows for more uniform thickness, improving sputtering rate and film quality. Furthermore, the RF power applied to the substrate is set to 1.86 W / cm² or less, preferably 0 W / cm² or more and 0.62 W / cm² or less. Reducing the RF power suppresses the amount of oxygen injected into the insulator 280. Alternatively, an insulator 282 with a two-layer stacked structure can be formed. In this case, the lower layer of the insulator 282 is formed with the RF power applied to the substrate set to 0 W / cm², and the upper layer is formed with the RF power applied to the substrate set to 0.62 W / cm².

[0387] Furthermore, by using sputtering to deposit the insulator 282 in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 during the deposition process. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0388] Next, an etching mask is formed on insulator 282 using photolithography until the top surface of insulator 214 is exposed. This process is applied to a portion of insulator 282, a portion of insulator 280, a portion of insulator 275, a portion of insulator 222, and a portion of insulator 216 (see Figures 18A to 18D). Wet etching can be used for this process, but dry etching is preferred for microfabrication.

[0389] Next, heat treatment may be performed. The heat treatment is preferably performed at a temperature of 250°C or higher and 650°C or lower, more preferably at 350°C or higher and 600°C or lower. Furthermore, this heat treatment is preferably performed at a temperature lower than the heat treatment temperature performed after depositing the oxide film 230B. In addition, the heat treatment is performed in a nitrogen or inert gas atmosphere. By performing this heat treatment, a portion of the oxygen added to the insulator 280 diffuses through the insulator 250 and the like into the oxide 230.

[0390] By performing this heat treatment, oxygen and hydrogen bonded to the oxygen contained in the insulator 280, formed by processing insulators 282, 280, 275, 222, and 216, can be released to the outside from the side of the insulator 280. Note that the hydrogen bonded to the oxygen is released as water. Therefore, unwanted oxygen and hydrogen contained in the insulator 280 can be reduced.

[0391] Furthermore, in the region where the oxide 230 overlaps with the conductor 260, an insulator 252 is provided in contact with the top and side surfaces of the oxide 230. The insulator 252 has oxygen-blocking properties, thus reducing excessive oxygen diffusion into the oxide 230. Therefore, oxygen can be supplied to region 230bc and its vicinity in a way that avoids excessive oxygen supply. This reduces oxygen vacancies and VOHs formed in region 230bc while suppressing oxidation of the side surfaces of the conductor 242 due to excessive oxygen. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0392] On the other hand, when high-density integration of transistor 200 is achieved, the volume of insulator 280 relative to the volume of a single transistor 200 may be too small. In this case, the amount of oxygen diffusing into oxide 230 during the aforementioned heat treatment is significantly less. When oxide 230 is heated in contact with an oxide insulator (e.g., insulator 250, etc.) with a relatively low oxygen content, oxygen constituting oxide 230 may detach. However, in the transistor 200 shown in this embodiment, an insulator 252 is provided in the region where oxide 230 overlaps with conductor 260, in contact with the top and side surfaces of oxide 230. Because insulator 252 has oxygen-blocking properties, oxygen detachment from oxide 230 can be reduced during the aforementioned heat treatment. As a result, oxygen vacancies and V OH formed in region 230bc can be reduced. Therefore, the electrical characteristics and reliability of transistor 200 can be improved.

[0393] As described above, in the semiconductor device according to this embodiment, a transistor with good electrical characteristics and high reliability can be formed whether the oxygen supplied by the insulator 280 is high or low. Therefore, a semiconductor device in which the non-uniformity of the electrical characteristics of the transistor 200 in the substrate surface is suppressed can be provided.

[0394] Next, insulator 283 is formed on insulator 282 (see Figures 19A to 19D). Insulator 283 can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods. Sputtering is preferred for depositing insulator 283. By using sputtering, which does not require the use of hydrogen-containing molecules as deposition gases, the hydrogen concentration in insulator 283 can be reduced. Furthermore, insulator 283 can also have a multilayer structure. For example, silicon nitride can be deposited by sputtering, and then silicon nitride can be deposited on top of the silicon nitride using ALD. By using highly barrier insulator 283 and insulator 214 to surround transistor 200, moisture and hydrogen can be prevented from entering from the outside.

[0395] Next, an insulating film that will become insulator 274 is formed on insulator 283. This insulating film can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, silicon oxide is deposited as the insulating film using CVD.

[0396] Next, the insulating film that will become the insulator 274 is polished by CMP treatment until the insulator 283 is exposed, so as to flatten the top surface of the insulating film and form the insulator 274 (see Figures 19A to 19D). Sometimes a portion of the top surface of the insulator 283 is removed by this CMP treatment.

[0397] Next, insulator 285 is formed on insulator 274 and insulator 283 (see Figures 20A to 20D). Insulator 285 can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. Sputtering is preferred for depositing insulator 285. By using sputtering, which does not require the use of hydrogen-containing molecules as deposition gas, the hydrogen concentration in insulator 285 can be reduced.

[0398] In this embodiment, silicon oxide is deposited as insulator 285 by sputtering.

[0399] Next, an opening leading to the conductor 242 is formed in insulators 271, 275, 280, 282, 283, and 285 (see Figures 20A and 20B). This opening can be formed using photolithography. Note that in Figure 20A, the opening is circular in top view, but it is not limited to this. For example, in top view, the opening can also have a roughly circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape with rounded corners.

[0400] Next, an insulating film is deposited to form insulators 241a and 241b, and the insulating film is anisotropically etched to form insulators 241a and 241b (see Figure 20B). This insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or similar methods. Preferably, an insulating film with oxygen-suppressing properties is used. For example, it is preferable to deposit an alumina film using the ALD method and then deposit a silicon nitride film on it using the PEALD method. Silicon nitride has high hydrogen barrier properties, so it is preferred.

[0401] Furthermore, anisotropic etching of the insulating film that forms insulators 241a and 241b can be performed, for example, by dry etching. By providing insulators 241a and 241b on the sidewalls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed subsequently can be prevented. In addition, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the conductors 240a and 240b.

[0402] Next, conductive films 240a and 240b are formed. Preferably, the conductive film has a multilayer structure containing a conductor that inhibits the permeation of impurities such as water and hydrogen. For example, it may have a multilayer structure of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive film can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0403] Next, by performing a CMP process, a portion of the conductive film that forms conductors 240a and 240b is removed, exposing the top surface of insulator 285. As a result, the conductive film remains only in the opening, thereby forming conductors 240a and 240b with flat top surfaces (see Figures 20A to 20D). Note that sometimes a portion of the top surface of insulator 285 is removed due to this CMP process.

[0404] Next, conductive films are deposited to form conductors 246a and 246b. These conductive films can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD.

[0405] Next, the conductive films that become conductors 246a and 246b are processed using photolithography to form conductor 246a, which contacts the top surface of conductor 240a, and conductor 246b, which contacts the top surface of conductor 240b. At this time, a portion of the insulator 285 in the area where conductors 246a and 246b do not overlap with the insulator 285 is sometimes removed.

[0406] By means of the above-described process, a semiconductor device including the transistor 200 shown in Figures 1A to 1D can be manufactured. As shown in Figures 10A to 20D, the transistor 200 can be manufactured by means of the semiconductor device manufacturing method shown in this embodiment.

[0407] Microwave Processing Device The following describes a microwave processing apparatus that can be used in the manufacturing method of the above-described semiconductor device.

[0408] First, the structure of a manufacturing apparatus with less impurity contamination during the manufacturing of semiconductor devices will be described with reference to Figures 21 to 24.

[0409] Figure 21 schematically shows a top view of a monolithic multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes: an atmospheric-side substrate supply chamber 2701 equipped with a cassette 2761 for storing substrates and an alignment machine 2762 for aligning substrates; an atmospheric-side substrate transfer chamber 2702 for transferring substrates from the atmospheric-side substrate supply chamber 2701; a load locking chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to depressurization or from depressurization to atmospheric pressure; an unloading locking chamber 2703b for unloading substrates and switching the pressure inside the chamber from depressurization to atmospheric pressure or from atmospheric pressure to depressurization; a transfer chamber 2704 for transferring substrates in a vacuum; processing chambers 2706a, 2706b, 2706c; and 2706d.

[0410] In addition, the atmospheric side substrate transfer chamber 2702 is connected to the load locking chamber 2703a and the unloading locking chamber 2703b, the load locking chamber 2703a and the unloading locking chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the processing chambers 2706a, 2706b, 2706c and 2706d.

[0411] A gate valve GV is installed at the connection between the chambers, thereby allowing each chamber, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transfer chamber 2702, to be independently maintained in a vacuum state. A transfer robot 2763a is installed in the atmospheric substrate transfer chamber 2702, and a transfer robot 2763b is installed in the transfer chamber 2704. By using the transfer robots 2763a and 2763b, substrates can be transferred within the manufacturing apparatus 2700.

[0412] The back pressure (total pressure) of the transfer chamber 2704 and each processing chamber is, for example, 1×10⁻⁴ Pa or less, preferably 3×10⁻⁵ Pa or less, and even more preferably 1×10⁻⁵ Pa or less. The partial pressure of gas molecules (atoms) in the transfer chamber 2704 and each processing chamber with a mass charge ratio (m / z) of 18 is, for example, 3×10⁻⁵ Pa or less, preferably 1×10⁻⁵ Pa or less, and even more preferably 3×10⁻⁶ Pa or less. Furthermore, the partial pressure of gas molecules (atoms) in the transfer chamber 2704 and each processing chamber with an m / z of 28 is, for example, 3×10⁻⁵ Pa or less, preferably 1×10⁻⁵ Pa or less, and even more preferably 3×10⁻⁶ Pa or less. The partial pressure of gas molecules (atoms) in the transfer chamber 2704 and each processing chamber with an m / z of 44 is, for example, 3×10⁻⁵ Pa or less, preferably 1×10⁻⁵ Pa or less, and even more preferably 3×10⁻⁶ Pa or less.

[0413] The total pressure and partial pressure in transfer chamber 2704 and each processing chamber can be measured using an ionization vacuum gauge, mass analyzer, etc.

[0414] Furthermore, the transfer chamber 2704 and each processing chamber are preferably structures with minimal external or internal leakage. For example, the leakage rate of the transfer chamber 2704 is less than 1×10⁻⁰ Pa / min, preferably less than 5×10⁻¹ Pa / min. Similarly, the leakage rate of each processing chamber is less than 1×10⁻¹ Pa / min, preferably less than 5×10⁻² Pa / min.

[0415] The leakage rate can be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, mass analyzer, etc. For example, it can be derived from the total pressure 10 minutes after evacuation begins using a vacuum pump such as a turbomolecular pump, and the total pressure 10 minutes after the valve is closed. Note that the total pressure 10 minutes after evacuation begins can be the average of multiple measurements of that total pressure.

[0416] The leakage rate depends on both external and internal leakage. External leakage refers to the inflow of gas from the outside of the vacuum system due to tiny holes or poor sealing. Internal leakage is caused by leaks from valves or other baffles within the vacuum system, or by the release of gas from internal components. To keep the leakage rate below these values, measures need to be taken to address both external and internal leakage.

[0417] For example, it is preferable to use metal gaskets to seal the opening and closing parts of the transfer chamber 2704 and each processing chamber. The metal gaskets are preferably made of metal coated with iron fluoride, alumina, or chromium oxide. Metal gaskets have a higher tightness than O-rings, thus reducing external leakage. By using passivated metals such as iron fluoride, alumina, or chromium oxide, the release of gases containing impurities from the metal gaskets can be suppressed, thereby reducing internal leakage.

[0418] As components constituting the manufacturing apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain few released gases and impurities, are used. Alternatively, alloys containing iron, chromium, and nickel can be coated with the aforementioned metals that contain few released gases and impurities. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and easy to process. Here, by reducing the surface roughness of the component through polishing or other methods to reduce the surface area, the released gases can be reduced.

[0419] Alternatively, ferric fluoride, alumina, chromium oxide, etc., can be used to cover the components of the manufacturing apparatus 2700.

[0420] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when a viewing window made of quartz or the like is provided, in order to suppress the release of gas, the surface of the viewing window is preferably covered with a thin layer of iron fluoride, aluminum oxide or chromium oxide.

[0421] Although the deposits present in the transfer chamber 2704 and each processing chamber adhere to the inner walls and do not affect the pressure of the transfer chamber 2704 and each processing chamber, these deposits become the cause of gas release during venting of the transfer chamber 2704 and each processing chamber. Therefore, although the leakage rate is not related to the venting speed, it is very important to use a pump with high venting capacity to remove the deposits present in the transfer chamber 2704 and each processing chamber as much as possible and to vent them in advance. To promote the removal of deposits, the transfer chamber 2704 and each processing chamber can also be baked. By baking, the removal speed of deposits can be increased by about 10 times. Baking can be carried out at a temperature of 100°C or higher and 450°C or lower. At this time, by removing deposits while introducing inert gas into the transfer chamber 2704 and each processing chamber, the removal speed of water and other substances that are not easily removed by venting alone can be further improved. In addition, by heating the introduced inert gas at a temperature similar to the baking temperature, the removal speed of deposits can be further improved. Here, a noble gas is preferred as the inert gas.

[0422] Furthermore, it is preferable to increase the pressure in the transfer chamber 2704 and each processing chamber by introducing heated noble gases or oxygen, and then exhaust the transfer chamber 2704 and each processing chamber again after a certain period of time. The introduction of heated gas can remove deposits from the transfer chamber 2704 and each processing chamber, thereby reducing impurities present in the transfer chamber 2704 and each processing chamber. Effectively, this process should be repeated at least twice and no more than 30 times, preferably at least five times and no more than 15 times. Specifically, by introducing inert gases or oxygen at temperatures of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each processing chamber is set to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, more preferably 5 Pa to 100 Pa, and the pressure is maintained for at least one minute to 300 minutes, preferably 5 minutes to 120 minutes. Then, exhaust air from the transfer chamber 2704 and each processing chamber for at least 5 minutes and no more than 300 minutes, preferably at least 10 minutes and no more than 120 minutes.

[0423] Next, the cross-sectional schematic diagram shown in Figure 22 will be used to describe the processing chambers 2706b and 2706c.

[0424] Processing chambers 2706b and 2706c are, for example, processing chambers capable of performing microwave processing on the object being processed. Note that the only difference between processing chambers 2706b and 2706c is the atmosphere during microwave processing. Since the other structures of processing chambers 2706b and 2706c are the same, they will be described together below.

[0425] Processing chambers 2706b and 2706c include a slotted antenna plate 2808, a dielectric plate 2809, a substrate support 2812, and an exhaust port 2819. Furthermore, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided externally to processing chambers 2706b and 2706c.

[0426] A high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slotted antenna plate 2808 via a waveguide 2807. The slotted antenna plate 2808 is grounded in contact with a dielectric plate 2809. Furthermore, a gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is introduced into processing chambers 2706b and 2706c via a gas pipe 2806 passing through the mode converter 2805, waveguide 2807, and dielectric plate 2809. Additionally, a vacuum pump 2817 functions to discharge gas from processing chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. Finally, a high-frequency power supply 2816 is connected to a substrate support 2812 via a matching adapter 2815.

[0427] The substrate holder 2812 has the function of holding the substrate 2811. For example, the substrate holder 2812 has the function of electrostatically or mechanically chuckling the substrate 2811. In addition, the substrate holder 2812 has the function of electrodes that are powered by a high-frequency power supply 2816. Furthermore, the substrate holder 2812 includes a heating mechanism 2813 inside and has the function of heating the substrate 2811.

[0428] As the vacuum pump 2817, various types of pumps can be used, such as drying pumps, mechanical booster pumps, ion pumps, titanium sublimation pumps, cryogenic pumps, or turbomolecular pumps. Furthermore, in addition to the vacuum pump 2817, cryogenic cold traps can also be used. The use of both cryogenic pumps and cryogenic cold traps allows for efficient water removal, which is particularly advantageous.

[0429] As the heating mechanism 2813, a heating mechanism that uses a resistance heating element or the like for heating can be used. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a gas to be heated can also be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA uses a high-temperature gas for heat treatment. An inert gas is used as the gas.

[0430] Furthermore, the gas supply source 2801 can be connected to the purifier via a mass flow controller. Preferably, the gas used has a dew point below -80°C, and more preferably below -100°C. For example, oxygen gas, nitrogen gas, and noble gases (such as argon) can be used.

[0431] For example, silicon oxide (quartz), aluminum oxide, or yttrium oxide can be used as the dielectric substrate 2809. Furthermore, other protective layers can be formed on the surface of the dielectric substrate 2809. These protective layers can be made of materials such as magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric substrate 2809 is exposed to a particularly high-density area of ​​the high-density plasma 2810 (described later), damage can be mitigated by providing a protective layer. As a result, the increase of particles during processing can be suppressed.

[0432] The high-frequency generator 2803 has the function of generating microwaves, for example, at frequencies above 0.3 GHz and below 3.0 GHz, above 0.7 GHz and below 1.1 GHz, or above 2.2 GHz and below 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. In the mode converter 2805, the transmitted TE-mode microwaves are converted to TEM-mode microwaves. Then, the microwaves are transmitted to a slotted antenna plate 2808 via a waveguide 2807. Multiple slots are provided in the slotted antenna plate 2808, through which microwaves pass and through a dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 includes ions and free radicals depending on the type of gas supplied from the gas supply source 2801. For example, the high-density plasma 2810 includes oxygen free radicals, etc.

[0433] At this time, the quality of films on substrate 2811 can be improved by utilizing the ions and free radicals generated in the high-density plasma 2810. Furthermore, it is sometimes preferable to apply a bias voltage to one side of substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56MHz or 27.12MHz can be used as the high-frequency power supply 2816. By applying a bias voltage to one side of the substrate, ions in the high-density plasma 2810 can efficiently reach the depth of openings in films on substrate 2811.

[0434] For example, by introducing oxygen from gas supply source 2801, oxygen free radical treatment using high-density plasma 2810 can be carried out in treatment chamber 2706b or treatment chamber 2706c.

[0435] Next, the cross-sectional schematic diagram shown in Figure 23 will be used to describe the processing chambers 2706a and 2706d.

[0436] Processing chambers 2706a and 2706d are, for example, processing chambers capable of irradiating the processed object with electromagnetic waves. Note that the only difference between processing chambers 2706a and 2706d is the type of electromagnetic wave. Since most of the other structures of processing chambers 2706a and 2706d are the same, they will be described together below.

[0437] Processing chambers 2706a and 2706d include one or more lamps 2820, a substrate support 2825, a gas inlet 2823, and an exhaust outlet 2830. Furthermore, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the processing chambers 2706a and 2706d.

[0438] A gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. A vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. A lamp 2820 is disposed opposite to a substrate support 2825. The substrate support 2825 has the function of holding the substrate 2824. Furthermore, the substrate support 2825 includes a heating mechanism 2826 inside and has the function of heating the substrate 2824.

[0439] As for lamp 2820, for example, a light source that can emit electromagnetic waves such as visible light or ultraviolet light can be used. For example, a light source that can emit electromagnetic waves with peak values ​​in the wavelength regions of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm can be used.

[0440] For example, as lamp 2820, light sources such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps can be used.

[0441] For example, some or all of the electromagnetic waves emitted from the lamp 2820 are drawn into the substrate 2824, thereby improving the quality of films, etc., on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Furthermore, when defects are generated or reduced, or impurities are removed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed, etc., efficiently.

[0442] Alternatively, for example, electromagnetic waves emitted from lamp 2820 can be used to heat the substrate support 2825, thereby heating the substrate 2824. In this case, it is not necessary to include a heating mechanism 2826 inside the substrate support 2825.

[0443] Vacuum pump 2828 can be referred to the description of vacuum pump 2817. Furthermore, heating mechanism 2826 can be referred to the description of heating mechanism 2813. Furthermore, gas supply source 2821 can be referred to the description of gas supply source 2801.

[0444] The microwave processing apparatus that can be used in this embodiment is not limited to the microwave processing apparatus described above, and the microwave processing apparatus 2900 shown in FIG. 24 can be used. The microwave processing apparatus 2900 includes a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. In addition, the microwave processing apparatus 2900 includes a substrate support 2902 inside the quartz tube 2901 to support multiple substrates (2811_1 to 2811_n, where n is an integer of 2 or more). In addition, the microwave processing apparatus 2900 may also include a heating unit 2903 on the outside of the quartz tube 2901.

[0445] Microwaves generated by a high-frequency generator 2803 are irradiated onto a substrate disposed within a quartz tube 2901 via a waveguide 2804. A vacuum pump 2817, connected to an exhaust port 2819 via a valve 2818, can adjust the pressure inside the quartz tube 2901. Additionally, a gas supply source 2801, connected to a gas pipe 2806 via a valve 2802, can introduce a desired gas into the quartz tube 2901. Furthermore, a heating unit 2903 can heat multiple substrates within the quartz tube 2901 to a desired temperature. Alternatively, the heating unit 2903 can heat the gas supplied from the gas supply source 2801. The microwave processing apparatus 2900 allows for simultaneous heat treatment and microwave treatment of multiple substrates. Alternatively, microwave treatment can be performed after heating multiple substrates. Alternatively, heat treatment can be performed after microwave treatment of multiple substrates.

[0446] Substrates 2811_1 to 2811_n can all be used as processing substrates for forming semiconductor devices or memory devices, or a portion of substrates 2811_1 to 2811_n can be used as dummy substrates. For example, substrates 2811_1 and 2811_n can be used as dummy substrates, and substrates 2811_2 to 2811_n-1 can be used as processing substrates. Alternatively, substrates 2811_1, 2811_2, 2811_n-1, and 2811_n can be used as dummy substrates, and substrates 2811_3 to 2811_n-2 can be used as processing substrates. By using dummy substrates, multiple processing substrates can be processed uniformly during microwave processing or heat processing, thereby reducing non-uniformity between processing substrates, which is preferable. For example, by placing the dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804, direct exposure of the processing substrate to microwaves can be suppressed, which is preferable.

[0447] By using the above-mentioned manufacturing apparatus, impurities can be prevented from entering the processed material and the membrane quality can be improved.

[0448] <Examples of variations of semiconductor devices> Hereinafter, an example of a semiconductor device according to an embodiment of the present invention will be described using Figures 6A to 9D.

[0449] In each figure, A is a top view of the semiconductor device. In each figure, B is a cross-sectional view along the dashed line A1-A2 in figure A. In each figure, C is a cross-sectional view along the dashed line A3-A4 in figure A. In each figure, D is a cross-sectional view along the dashed line A5-A6 in figure A. For clarity, some components are omitted in the top view of figure A.

[0450] Note that in the semiconductor devices shown by A to D in each figure, the same element symbols are added to structures having the same function as the components constituting the semiconductor device shown in the <Structure Examples of Semiconductor Devices>. Note that the materials constituting the semiconductor devices in this section may be the materials described in detail in the <Structure Examples of Semiconductor Devices>.

[0451] <Example 1 of a variation of a semiconductor device> The semiconductor devices shown in Figures 6A to 6D are variations of the semiconductor devices shown in Figures 1A to 1D. The difference between the semiconductor devices shown in Figures 6A to 6D and those shown in Figures 1A to 1D is that each of insulators 271 and 283 has a two-layer stacked structure.

[0452] Insulator 271a includes insulator 271a1 and insulator 271a2 on insulator 271a1. Insulator 271b includes insulator 271b1 and insulator 271b2 on insulator 271b1.

[0453] Insulators 271a1 and 271b1 are preferably used as insulating films that at least block oxygen. Therefore, insulators 271a1 and 271b1 preferably have the function of inhibiting oxygen diffusion. This prevents oxygen contained in insulator 280 from diffusing to conductors 242a and 242b. Thus, it can suppress the oxidation of conductors 242a and 242b caused by oxygen contained in insulator 280, which would increase resistivity and reduce on-state current.

[0454] Insulators 271a2 and 271b2 are used as protective layers to retain insulators 271a1 and 271b1. When removing the hard mask after processing the conductive films (which will become conductors 242a and 242b) and the oxide film (which will become oxide 230b) into island shapes, there is a concern that the insulating layers of insulators 271a1 and 271b1 may be removed. Therefore, by providing insulating layers of insulators 271a2 and 271b2 between the hard mask and the insulating layers of insulators 271a1 and 271b1, the insulating layers of insulators 271a1 and 271b1 can be retained. For example, when tungsten is used as the hard mask, silicon oxide or the like is preferred as the insulators 271a2 and 271b2.

[0455] Insulator 283 includes insulator 283a and insulator 283b on insulator 283a. Insulators 283a and 283b are preferably formed using the same material but different methods. For example, silicon nitride is preferably deposited as insulator 283a using sputtering and silicon nitride is deposited as insulator 283b using ALD. By using sputtering, which does not require the use of hydrogen-containing molecules as deposition gas, the hydrogen concentration in insulator 282a can be reduced. Furthermore, in cases where pinholes or breaks are formed in the film deposited by sputtering, a film with excellent coverage, deposited by ALD, can be used to fill and overlap the pinholes or breaks.

[0456] Note that, as shown in Figure 6B, sometimes a portion of the top surface of insulator 283b is removed. Furthermore, it is sometimes difficult to clearly detect the boundaries between insulators 283a and 283b.

[0457] Insulators 283a and 283b are not limited to a laminated structure made of the same material, but may also have a laminated structure made of different materials.

[0458] <Example 2 of a modified semiconductor device> The semiconductor devices shown in Figures 7A to 7D are variations of the semiconductor devices shown in Figures 1A to 1D. The difference between the semiconductor devices shown in Figures 7A to 7D and those shown in Figures 1A to 1D is that the insulator 282 is not provided. Therefore, in the semiconductor devices shown in Figures 7A to 7D, the insulator 283 is in contact with the top surface of the conductor 260, the top surface of the insulator 280, the uppermost part of the insulator 254, the uppermost part of the insulator 250, and the uppermost part of the insulator 252.

[0459] For example, when a large amount of oxygen can be supplied to the oxide 230 using microwave processing as shown in FIG15, the oxygen supply to the insulator 280 can be substantially shaped even without the insulator 282. In this case, as shown in FIG7A to FIG7D, by adopting a structure without the insulator 282, the semiconductor device manufacturing process can be simplified, and productivity can be improved.

[0460] <Example 3 of a variation of a semiconductor device> The semiconductor devices shown in Figures 8A to 8D are variations of the semiconductor devices shown in Figures 1A to 1D. The difference between the semiconductor devices shown in Figures 8A to 8D and those shown in Figures 1A to 1D is the presence of oxide 243 (oxide 243a, oxide 243b). Oxide 243a is disposed between oxide 230b and conductor 242a, and oxide 243b is disposed between oxide 230b and conductor 242b. Preferably, oxide 243a is in contact with the top surface of oxide 230b and the bottom surface of conductor 242a. Similarly, oxide 243b is preferably in contact with the top surface of oxide 230b and the bottom surface of conductor 242b.

[0461] Oxide 243 preferably has the function of suppressing oxygen permeation. By distributing oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which is used as the source electrode or drain electrode, and oxide 230b, the resistance between the conductor 242 and oxide 230b is reduced, which is preferable. By adopting such a structure, the electrical characteristics, field-effect mobility, and reliability of transistor 200 can sometimes be improved.

[0462] Metal oxides containing element M can also be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin are preferably used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Furthermore, gallium oxide can also be used as oxide 243. Additionally, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the ratio of In atoms to element M atoms in the metal oxide used for oxide 243 is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. Furthermore, oxide 243 is preferably crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be appropriately suppressed. For example, when oxide 243 has a hexagonal crystal structure, the release of oxygen from oxide 230 can sometimes be suppressed.

[0463] <Example 4 of a Semiconductor Device> The semiconductor devices shown in Figures 9A to 9D are variations of the semiconductor devices shown in Figures 1A to 1D. The difference between the semiconductor devices shown in Figures 9A to 9D and those shown in Figures 1A to 1D is that a portion of the top surface of insulator 283 is in contact with that of insulator 212. Therefore, transistor 200 is disposed in the region sealed by insulator 283 and insulator 212. With this structure, hydrogen contained outside the sealed region can be suppressed from mixing into the sealed region. Furthermore, in the transistor 200 shown in Figures 9A to 9D, insulator 212 and insulator 283 have a single-layer structure, but the present invention is not limited to this. For example, insulator 212 and insulator 283 may also each have a stacked structure of two or more layers.

[0464] OS transistors, such as the 200, exhibit minimal changes in electrical properties due to radiation exposure; that is, they possess high radiation tolerance. Therefore, they can be appropriately used even in environments where radiation exposure is possible. For example, OS transistors can be appropriately used in situations where they can be used in outer space. Specifically, OS transistors can be used as transistors constituting semiconductor devices installed in space shuttles, satellites, or space probes. Examples of radiation include X-rays and neutron radiation. Furthermore, outer space refers, for example, to a region at an altitude of 100 km or higher; however, outer space as described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0465] Alternatively, for example, OS transistors can be used as transistors constituting semiconductor devices in working robots installed in nuclear power plants and radioactive waste treatment or disposal sites. In particular, they can be suitably used as transistors constituting semiconductor devices installed in remote operating robots used for remote operations such as reactor facility decommissioning, removal of nuclear fuel or fuel debris, and field investigations in spaces with high levels of radioactive material.

[0466] <Application Examples of Semiconductor Devices> Hereinafter, an example of a semiconductor device according to an embodiment of the present invention will be described using FIG25.

[0467] Figure 25A shows a top view of the semiconductor device 500. In Figure 25A, the direction parallel to the channel length direction of the transistor 200 is the x-axis, and the direction perpendicular to the x-axis is the y-axis. Additionally, Figure 25B is a cross-sectional view along the dotted line A1-A2 in Figure 25A, which corresponds to a cross-sectional view along the channel length direction of the transistor 200. Figure 25C is a cross-sectional view along the dotted line A3-A4 in Figure 25A, which corresponds to a cross-sectional view of the opening region 400 and its vicinity. Note that some components are omitted in the top view of Figure 25A for clarity.

[0468] Note that in the semiconductor devices shown in Figures 25A to 25C, the same element symbols are added to structures having the same function as the components constituting the semiconductor devices shown in the <Structural Examples of Semiconductor Devices>. Note that the materials constituting the semiconductor devices in this section may be the materials detailed in the <Structural Examples of Semiconductor Devices>.

[0469] The semiconductor device 500 shown in Figures 25A to 25C is a variation of the semiconductor device shown in Figures 1A to 1D. The difference between the semiconductor device 500 shown in Figures 25A to 25C and the semiconductor device shown in Figures 1A to 1D is that the insulators 282 and 280 have opening regions 400. Furthermore, the difference from the semiconductor device shown in Figures 1A to 1D is that a sealing portion 265 is formed around a plurality of transistors 200.

[0470] The semiconductor device 500 includes a plurality of transistors 200 arranged in a matrix and a plurality of opening regions 400. Additionally, a plurality of conductors 260, serving as gate electrodes of the transistors 200, are provided extending in the y-axis direction. The opening regions 400 are formed in regions that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed surrounding the plurality of transistors 200, the plurality of conductors 260, and the plurality of opening regions 400. Note that the number, arrangement, and size of the transistors 200, conductors 260, and opening regions 400 are not limited to the structure shown in FIG. 25, and can be appropriately set according to the design of the semiconductor device 500.

[0471] As shown in Figures 25B and 25C, the sealing portion 265 is arranged around the plurality of transistors 200, insulators 216, 222, 275, 280, and 282. In other words, the insulator 283 is arranged to cover the insulators 216, 222, 275, 280, and 282. Furthermore, in the sealing portion 265, the top surface of the insulator 283 contacts the top surface of the insulator 214. Additionally, above the sealing portion 265, an insulator 274 is provided between the insulators 283 and 285. The height of the top surface of the insulator 274 is approximately the same as the height of the topmost part of the insulator 283. Furthermore, the same insulator as the insulator 280 can be used as the insulator 274.

[0472] By employing such a structure, multiple transistors 200 can be surrounded by insulators 283, 214, and 212. Here, one or more of insulators 283, 214, and 212 are preferably used as hydrogen-barrier insulating films. This prevents hydrogen outside the area of ​​the sealing portion 265 from entering the area of ​​the sealing portion 265.

[0473] As shown in Figure 25C, in the opening region 400, the insulator 282 has an opening. Alternatively, in the opening region 400, the insulator 280 may also have a groove that overlaps with the opening of the insulator 282. The depth of the groove in the insulator 280 is sufficient to expose the top surface of the insulator 275; for example, it can be approximately 1 / 4 to 1 / 2 of the maximum thickness of the insulator 280.

[0474] Furthermore, as shown in Figure 25C, the insulator 283 contacts the side surface of the insulator 282, the side surface of the insulator 280, and the top surface of the insulator 280 on the inner side of the opening region 400. Additionally, in the opening region 400, sometimes a portion of the insulator 274 is formed by embedding into a recess formed in the insulator 283. In this case, the height of the top surface of the insulator 274 formed in the opening region 400 is sometimes approximately the same as the height of the uppermost part of the insulator 283.

[0475] By performing heat treatment with the opening region 400 formed and the insulator 280 exposed at the opening of the insulator 282, a portion of the oxygen contained in the insulator 280 can diffuse to the outside from the opening region 400 while oxygen is supplied to the oxide 230. Thus, a sufficient amount of oxygen can be supplied from the insulator 280, which contains oxygen that has been released by heating, to the region in the oxide semiconductor layer that serves as the channel formation region and its vicinity, while preventing excessive oxygen supply.

[0476] At this point, the hydrogen contained in insulator 280 can be bonded to oxygen and released to the outside through opening region 400. The hydrogen bonded to oxygen is released as water. Therefore, the amount of hydrogen contained in insulator 280 can be reduced, and the entry of hydrogen contained in insulator 280 into oxide 230 can be reduced.

[0477] Furthermore, in Figure 25A, the top-view opening region 400 is generally rectangular in shape, but the present invention is not limited to this. For example, the top-view opening region 400 may also be rectangular, elliptical, circular, rhomboid, or a combination of these shapes. Additionally, the area and spacing of the opening regions 400 can be appropriately set according to the design of the semiconductor device including the transistors 200. For example, in regions with low transistor density, the area of ​​the opening regions 400 can be increased or the spacing of the opening regions 400 can be decreased. Conversely, in regions with high transistor density, the area of ​​the opening regions 400 can be decreased or the spacing of the opening regions 400 can be increased.

[0478] According to one embodiment of the present invention, a novel transistor can be provided. According to one embodiment of the present invention, a semiconductor device with small non-uniformity in transistor characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high field-effect mobility can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good frequency characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or hyper-integration can be provided. Furthermore, according to one embodiment of the present invention, a low-power semiconductor device can be provided.

[0479] The structures, methods, etc. shown in this embodiment can be appropriately combined with other embodiments and other examples described in this specification.

[0480] Implementation Method 2 In this embodiment, an embodiment of the semiconductor device will be described with reference to Figures 26 to 30.

[0481] [Memory Device 1] Figure 26 illustrates an example of a semiconductor device (memory device) according to an embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, a transistor 200 is disposed above a transistor 300, and a capacitor 100 is disposed above both the transistor 300 and the transistor 200. Furthermore, the transistor 200 described in the above embodiment can be used as the transistor 200.

[0482] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200 has a low off-state current, its use in memory devices allows for long-term retention of stored content. In other words, since no update operation is required or the update frequency is extremely low, the power consumption of the memory device can be significantly reduced.

[0483] In the semiconductor device shown in Figure 26, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Additionally, the other of the gate of transistor 300 and the source and drain of transistor 200 is electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0484] Furthermore, by arranging the memory devices shown in Figure 26 in a matrix configuration, a memory cell array can be formed.

[0485] <Transistor 300> Transistor 300 is disposed on substrate 311 and includes: a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b used as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0486] In the transistor 300 shown in FIG. 26, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. The conductor 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also referred to as a FIN-type transistor. Furthermore, an insulator used to form a shield for the convex portion may be provided in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0487] Note that the structure of transistor 300 shown in Figure 26 is only an example and is not limited to the above structure. Appropriate transistors can be used according to the circuit structure or driving method.

[0488] <Capacitor 100> A capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 283 shown in the above embodiment.

[0489] Alternatively, conductors 112 and 110 may be formed simultaneously on conductor 240. Furthermore, conductor 112 may be used as a plug or wiring for electrical connection with capacitor 100, transistor 200, or transistor 300.

[0490] In Figure 26, conductors 112 and 110 have a single-layer structure, but are not limited to this structure and may also have a stacked structure of two or more layers. For example, a conductor with high density between the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0491] In addition, the insulator 130 may be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride, etc., and may be provided in a stacked or single layer.

[0492] For example, the insulator 130 is preferably a multilayer structure using materials with high insulating stress resistance, such as silicon oxynitride, and materials with high dielectric constant (high-k). By adopting this structure, the capacitor 100 can include an insulator with high dielectric constant (high-k) to ensure sufficient capacitance, and can include an insulator with high insulating stress resistance to improve insulating stress resistance, thereby suppressing electrostatic damage to the capacitor 100.

[0493] Note that high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0494] On the other hand, materials with high insulation and stress resistance (materials with relatively low permittivity) include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0495] <Wiring Layer> Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductors that function as plugs or wiring, the same symbol is sometimes used to represent multiple structures. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be a single component. That is, a portion of a conductor is sometimes used as wiring, and a portion of a conductor is sometimes used as a plug.

[0496] For example, on transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to capacitor 100 or transistor 200, are embedded within insulators 320, 322, 324, and 326. Additionally, conductors 328 and 330 are used as plugs or wiring.

[0497] Furthermore, the insulator used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of insulator 322, planarization can also be achieved by planarization treatment using chemical mechanical polishing (CMP) or the like.

[0498] Alternatively, a wiring layer can be provided on the insulator 326 and the conductor 330. For example, in FIG26, insulators 350, 352, and 354 are stacked sequentially. Furthermore, a conductor 356 is formed in insulators 350, 352, and 354. The conductor 356 is used as a plug or wiring.

[0499] Similarly, conductors 218 and conductors constituting transistor 200 (conductor 205) are filled in insulators 210, 212, 214, and 216. Furthermore, conductor 218 is used as a plug or wiring for electrical connection with capacitor 100 or transistor 300. Additionally, insulator 150 is provided on conductor 120 and insulator 130.

[0500] Here, similar to the insulator 241 shown in the above embodiment, the insulator 217 is provided in contact with the side of the conductor 218 used as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. The conductor 205 can be formed in parallel with the conductor 218, so sometimes the insulator 217 is formed in contact with the side of the conductor 205.

[0501] As the insulator 217, insulators such as silicon nitride, aluminum oxide, or silicon oxynitride can be used. Insulator 217 is disposed in contact with insulators 210, 212, 214, and 222, thus preventing impurities such as water and hydrogen from entering oxide 230 from insulators 210 or 216 via conductor 218. Silicon nitride, in particular, has high hydrogen barrier properties, making it preferred. Furthermore, it prevents oxygen contained in insulators 210 or 216 from being absorbed by conductor 218.

[0502] Insulator 217 can be formed using the same method as insulator 241. For example, silicon nitride can be deposited using the PEALD method, and anisotropic etching can be used to form the opening reaching conductor 356.

[0503] As insulators that can be used as interlayer films, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0504] For example, by using a material with a low relative permittivity in the insulator used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material based on the function of the insulator.

[0505] For example, insulators 150, 210, 352, and 354 are preferably insulators with low relative permittivity. For example, the insulator is preferably composed of silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resin. Alternatively, the insulator is preferably a laminated structure comprising silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with resin, a laminated structure with thermal stability and low relative permittivity can be achieved. Examples of resins include polyesters, polyolefins, polyamides (nylon, aromatic polyamides, etc.), polyimides, polycarbonates, or acrylic resins.

[0506] Furthermore, by using an insulator that suppresses the permeation of impurities such as hydrogen and oxygen around a transistor using an oxide semiconductor, the electrical properties of the transistor can be stabilized. Therefore, insulators 214, 212, and 350, etc., can be insulators that suppress the permeation of impurities such as hydrogen and oxygen.

[0507] As an insulator that suppresses impurities such as hydrogen and oxygen permeation, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in layers. Specifically, as an insulator that suppresses impurities such as hydrogen and oxygen permeation, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as silicon oxynitride and silicon nitride, can be used.

[0508] As a conductor suitable for wiring and plugs, materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium can be used. Additionally, semiconductors with high conductivity, such as polycrystalline silicon containing impurities like phosphorus, and silicides such as nickel silicates can also be used.

[0509] For example, conductors 328, 330, 356, 218, and 112 can be made of conductive materials such as metallic materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above-mentioned materials, either in a single layer or in layers. Preferably, high-melting-point materials such as tungsten or molybdenum, which possess both heat resistance and conductivity, are used; tungsten is particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0510] <Wires or connectors with oxide semiconductor layers> Note that when an oxide semiconductor is used in transistor 200, an insulator with an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a barrier insulator between the insulator with the excess oxygen region and the conductor provided in the insulator with the excess oxygen region.

[0511] For example, in Figure 26, it is preferable to provide an insulator 241 between an insulator 280 having excess oxygen and a conductor 240. By providing insulator 241 in contact with insulators 222, 282 and 283, the transistor 200 can have a structure sealed by a barrier insulator.

[0512] In other words, by providing insulator 241, the absorption of excess oxygen in insulator 280 by conductor 240 can be suppressed. Furthermore, by having insulator 241, the diffusion of hydrogen as an impurity through conductor 240 to transistor 200 can be suppressed.

[0513] Furthermore, as the insulator 241, it is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide are preferred. In particular, silicon nitride has high hydrogen barrier properties, so it is preferred. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can also be used.

[0514] Furthermore, as shown in the above embodiments, the transistor 200 may also employ a structure sealed by insulators 212, 214, 282, and 283. By employing the above structure, the mixing of hydrogen contained in insulators 274, 150, etc., into insulator 280, etc., can be reduced.

[0515] Here, conductor 240 penetrates insulators 283 and 282, conductor 218 penetrates insulators 214 and 212, and as described above, insulator 241 is disposed in contact with conductor 240, and insulator 217 is disposed in contact with conductor 218. This reduces the amount of hydrogen mixed into the interior of insulators 212, 214, 282, and 283 by conductors 240 and 218. Thus, the transistor 200 can be sealed by insulators 212, 214, 282, 283, 241, and 217, reducing the ingress of impurities such as hydrogen contained in insulators 274 from the outside.

[0516] <cut line> The following describes the dicing lines (sometimes called dividing lines, separation lines, or cut-off lines) used when dividing a large-area substrate into multiple semiconductor devices in wafer shape by dividing each semiconductor element. As a dicing method, for example, sometimes grooves (dicing lines) for separating semiconductor elements are first formed in the substrate, and then the substrate is cut off at the dicing lines to obtain multiple semiconductor devices that have been separated (divided).

[0517] Here, for example, as shown in FIG26, it is preferable to design the insulator 283 and the insulator 214 to overlap the cutting line. That is, openings are provided in the insulators 282, 280, 275, 222 and 216 near the area that forms the cutting line at the edge of the memory cell including the plurality of transistors 200.

[0518] In other words, in the openings provided in insulators 282, 280, 275, 222 and 216, insulator 214 is in contact with insulator 283.

[0519] Furthermore, openings can be formed in insulators 282, 280, 275, 222, 216, and 214, for example. With this structure, insulator 212 and insulator 283 are in contact within the openings provided in insulators 282, 280, 275, 222, 216, and 214. In this case, insulators 212 and 283 can be formed using the same material and the same method. Using the same material and the same method to form insulators 212 and 283 improves the tightness of the seal. For example, silicon nitride is preferred.

[0520] By employing this structure, the transistor 200 can be surrounded by insulators 212, 214, 282, and 283. At least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water. Therefore, even if the substrate is divided into multiple wafers according to the circuit region where each semiconductor element shown in this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from being mixed in from the side direction of the cut substrate and to prevent such impurities from diffusing into the transistor 200.

[0521] Furthermore, by employing this structure, excess oxygen in the insulator 280 can be prevented from diffusing to the outside. Therefore, excess oxygen in the insulator 280 is efficiently supplied to the oxide forming the channel in the transistor 200. This oxygen reduces oxygen vacancies in the oxide forming the channel in the transistor 200. Consequently, the oxide forming the channel in the transistor 200 can become an oxide semiconductor with low defect state density and stable characteristics. In other words, reliability can be improved while suppressing variations in the electrical characteristics of the transistor 200.

[0522] Note that the capacitor 100 in the memory device shown in FIG26 is planar, but the memory device shown in this embodiment is not limited to this. For example, as shown in FIG27, the capacitor 100 may also be cylindrical. The structure below the insulator 150 of the memory device shown in FIG27 is the same as that of the semiconductor device shown in FIG26.

[0523] The capacitor 100 shown in FIG27 includes an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, a conductor 125 on the insulator 145, and a conductor 125 on the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulator 150 and the insulator 142.

[0524] Conductor 115 is used as the lower electrode of capacitor 100, conductor 125 is used as the upper electrode of capacitor 100, and insulator 145 is used as the dielectric of capacitor 100. Capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other by a dielectric material not only on the bottom surface but also on the side surfaces within the openings of insulators 150 and 142, thus increasing the electrostatic capacitance per unit area. The deeper the opening, the greater the electrostatic capacitance of capacitor 100. Therefore, by increasing the electrostatic capacitance per unit area of ​​capacitor 100, miniaturization or hyper-integration of semiconductor devices can be promoted.

[0525] As insulator 152, an insulator that can be used as insulator 280 can be used. In addition, as insulator 142, it is preferable to use an insulator that is used as an etch stop layer when forming the opening of insulator 150 and can be used as insulator 214.

[0526] The openings formed in insulators 150 and 142 can have a rectangular shape, a polygon other than a rectangular shape, a polygon with rounded corners, or a circular shape such as an ellipse when viewed from above. Preferably, the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. By adopting this structure, the area occupied by the semiconductor device, including the capacitor 100 and the transistor 200, can be reduced.

[0527] The conductor 115 is disposed in contact with openings formed in the insulators 142 and 150. Preferably, the top surface of the conductor 115 is substantially aligned with the top surface of the insulator 142. Furthermore, the bottom surface of the conductor 115 contacts the conductor 110 through an opening in the insulator 130. The conductor 115 is preferably deposited using an ALD or CVD method; for example, a conductor suitable for conductor 205 can be used.

[0528] The insulator 145 is configured to cover both the conductor 115 and the insulator 142. For example, the insulator 145 is preferably deposited using an ALD or CVD method. The insulator 145 can be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride, etc., and can be a multilayer or single-layer structure. For example, an insulating film sequentially stacked with zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 145.

[0529] Furthermore, the insulator 145 is preferably made of a material with high insulating stress resistance, such as silicon oxynitride, or a material with a high dielectric constant (high-k). Alternatively, a laminated structure of a material with high insulating stress resistance and a material with a high dielectric constant (high-k) can also be used.

[0530] Note that high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the electrostatic capacitance of capacitor 100 can be sufficiently ensured even if the insulator 145 is thickened. By thickening the insulator 145, leakage current generated between conductors 115 and 125 can be suppressed.

[0531] On the other hand, materials with high insulation stress resistance include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen added, porous silicon oxide, and resins. For example, an insulating film consisting of silicon nitride (SiN x) deposited by the PEALD method, silicon oxide (SiO x) deposited by the PEALD method, and silicon nitride (SiN x) deposited by the PEALD method can be used in sequence. Alternatively, an insulating film consisting of zirconium oxide, silicon oxide deposited by the ALD method, and zirconium oxide in sequence can be used. By using such an insulator with high insulation stress resistance, the insulation stress resistance is increased, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0532] Conductor 125 is disposed in such a way that it fills the openings formed in insulator 142 and insulator 150. Furthermore, conductor 125 is electrically connected to wiring 1005 via conductor 140 and conductor 153. Conductor 125 is preferably deposited by an ALD or CVD method, for example, a conductor suitable for conductor 205 can be used.

[0533] Furthermore, conductor 153 is disposed on insulator 154 and covered by insulator 156. Conductor 153 may be a conductor that can be used for conductor 112, and insulator 156 may be an insulator that can be used for insulator 152. Here, conductor 153 is in contact with the top surface of conductor 140 and is used as a terminal of capacitor 100, transistor 200, or transistor 300.

[0534] [Memory Device 2] Figure 28 shows an example of a semiconductor device (memory device) according to one embodiment of the present invention.

[0535] <Examples of memory device structures> Figure 28 is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Figure 28 includes a capacitor 292 in addition to the transistor 200 shown in Figures 1A to 1D. Figure 28 is a cross-sectional view corresponding to the channel length direction of the transistor 200.

[0536] The capacitor 292 includes a conductor 242b, an insulator 271b disposed on the conductor 242b, an insulator 275 disposed in contact with the top surface, side surface, and side surface of the insulator 271b, and a conductor 294 disposed on the insulator 275. That is, the capacitor 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. Furthermore, one of the pair of electrodes included in the capacitor 292, namely the conductor 242b, can also serve as the source electrode of a transistor. Additionally, the dielectric layer included in the capacitor 292 can also serve as a protective layer disposed in the transistor, namely, insulators 271 and 275. Therefore, the manufacturing process of the capacitor 292 can also utilize a portion of the transistor manufacturing process, thus resulting in a high-yield semiconductor device. Furthermore, one of the pairs of electrodes included in the capacitor element 292, namely the conductor 242b, also serves as the source electrode of the transistor, thus reducing the area on which the transistor and capacitor element are arranged.

[0537] Furthermore, as conductor 294, a material suitable for conductor 242 can be used, for example.

[0538] <Examples of variations of memory devices> The following description uses Figures 29A, 29B, and 30 to illustrate an example of a semiconductor device including a transistor 200 and a capacitor 292 according to an embodiment of the present invention, which differs from the semiconductor device shown in the above-described <Structure Examples of Memory Devices>. Note that in the semiconductor devices shown in Figures 29A, 29B, and 30, structures having the same function as those constituting the semiconductor device shown in the above-described embodiment and <Structure Examples of Memory Devices> (refer to Figure 28) are given the same reference numerals. Furthermore, in this section, the materials used to construct the transistor 200 and the capacitor 292 may be the materials described in detail in the above-described embodiment and <Structure Examples of Memory Devices>. Although the memory device shown in Figure 28 is used in Figures 29A, 29B, and 30, the invention is not limited thereto.

[0539] <<Example 1 of a variation of memory devices>> Hereinafter, an example of a semiconductor device 600 including transistors 200a, 200b, capacitor 292a, and capacitor 292b according to an embodiment of the present invention will be described using FIG29A.

[0540] Figure 29A is a cross-sectional view along the channel length of a semiconductor device 600 including transistors 200a and 200b, capacitor element 292a and capacitor element 292b. Here, capacitor element 292a includes: a conductor 242a; an insulator 271a on the conductor 242a; an insulator 275 in contact with the top surface, side surface, and side surface of the insulator 271a; and a conductor 294a on the insulator 275. Similarly, capacitor element 292b includes: a conductor 242b; an insulator 271b on the conductor 242b; an insulator 275 in contact with the top surface, side surface, and side surface of the insulator 271b; and a conductor 294b on the insulator 275.

[0541] As shown in Figure 29A, the semiconductor device 600 has an axially symmetric structure with the dashed line A3-A4 as the axis of symmetry. The conductor 242c serves as one of the source and drain electrodes of transistor 200a and transistor 200b. Furthermore, an insulator 271c is disposed on the conductor 242c. Additionally, the conductor 240, used as a connector, connects the conductor 246, used as wiring, to transistors 200a and 200b. Thus, by employing the above structure as the connection relationship between two transistors, two capacitors, wiring, and a connector, a semiconductor device capable of miniaturization or hyper-integration can be provided.

[0542] The structure and effects of transistors 200a and 200b, capacitors 292a and 292b can be seen in the example of the semiconductor device shown in Figure 28.

[0543] <<Example 2 of a variation of memory devices>> The above examples of the structure of a semiconductor device show transistors 200a and 200b, capacitors 292a and 292b, but the semiconductor device shown in this embodiment is not limited to this. For example, as shown in FIG29B, a structure in which a semiconductor device 600 and a semiconductor device having the same structure as the semiconductor device 600 are connected by a capacitor section can also be used. In this specification, the semiconductor device including transistors 200a and 200b, capacitors 292a and 292b is referred to as a unit. The structure of transistors 200a and 200b, capacitors 292a and 292b can be referred to in the above description of transistors 200a and 200b, capacitors 292a and 292b.

[0544] Figure 29B is a cross-sectional view of a semiconductor device 600 including transistors 200a and 200b, capacitors 292a and 292b, and a unit having the same structure as the semiconductor device 600 connected by a capacitor section.

[0545] As shown in Figure 29B, the conductor 294b, which serves as an electrode of the capacitor 292b included in the semiconductor device 600, also serves as an electrode of the capacitor included in the semiconductor device 601, which has the same structure as the semiconductor device 600. Furthermore, although not shown, the conductor 294a, which serves as an electrode of the capacitor 292a included in the semiconductor device 600, also serves as an electrode of the capacitor of the adjacent semiconductor device on the left side of the semiconductor device 600, that is, in the A1 direction of Figure 29B. Furthermore, the cells on the right side of the semiconductor device 601, that is, in the A2 direction of Figure 29B, also have the same structure. In other words, a cell array (also referred to as a memory device layer) can be formed. By adopting the above-described cell array structure, the spacing between adjacent cells can be reduced, thereby reducing the projected area of ​​the cell array and achieving high integration. Furthermore, by arranging the cell array structure shown in Figure 29B in a matrix shape, a matrix-shaped cell array can be formed.

[0546] As described above, by forming transistors 200a, 200b, capacitors 292a and 292b with the structure shown in this embodiment, the area of ​​the cells can be reduced, thereby enabling miniaturization or high integration of semiconductor devices including cell arrays.

[0547] Furthermore, in addition to arranging the aforementioned unit arrays in a planar shape, the unit arrays can also be stacked. Figure 30 shows a cross-sectional view of the structure of a unit array 610 with n stacked layers. As shown in Figure 30, by stacking multiple unit arrays (unit array 610_1 to unit array 610_n), the units can be integrated without increasing the area occupied by the unit arrays. That is, a 3D unit array can be constructed.

[0548] The structures, methods, etc. shown in this embodiment can be appropriately combined with other embodiments and other examples described in this specification.

[0549] Implementation Method 3 In this embodiment, referring to FIGS. 31A, 31B, and 32A to 32H, a memory device (hereinafter sometimes referred to as an OS memory device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to an embodiment of the present invention will be described. An OS memory device is a memory device that includes at least a capacitor and an OS transistor controlling the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely low, an OS memory device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0550] <Example of memory device structure> Figure 31A shows an example of the structure of an OS memory device. The memory device 1400 includes peripheral circuitry 1411 and a memory cell array 1470. The peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0551] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to be accessed.

[0552] The memory device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit ...

Claims

1. A semiconductor device including a transistor, wherein, The transistor includes: an oxide; a first conductor and a second conductor on the oxide; a first insulator with an opening on the first conductor and the second conductor; a second insulator within the opening of the first insulator; a third insulator on the second insulator; a fourth insulator on the third insulator; a third conductor on the fourth insulator; and a fifth insulator. The opening of the first insulator includes a region overlapping with the oxide. The third conductor includes a region overlapping with the oxide, separated by the second, third, and fourth insulators. The second insulator includes a region contacting the top surface of the oxide and the sidewall of the opening of the first insulator. The second insulator includes a region with a thickness smaller than that of the third insulator. The fourth insulator is less permeable to oxygen compared to the third insulator. In a cross-section along the channel length of the transistor, the third conductor includes a region with a width of 3 nm or more and 15 nm or less. The fifth insulator is disposed between the first conductor and the second conductor and the first insulator. The fifth insulator includes an opening overlapping the opening of the first insulator. The fifth insulator is less permeable to oxygen than the third insulator. The fifth insulator includes a region that contacts the side of the oxide, the side of the first conductor, and the side of the second conductor. The second insulator includes a region that contacts the sidewall of the opening in the fifth insulator.

2. A semiconductor device including a transistor, wherein, The transistor includes: an oxide; a first conductor and a second conductor on the oxide; a first insulator with an opening on the first conductor and the second conductor; a second insulator within the opening of the first insulator; a third insulator on the second insulator; a fourth insulator on the third insulator; a third conductor on the fourth insulator; and a fifth insulator. The opening of the first insulator includes a region overlapping with the oxide. The third conductor includes a region overlapping with the oxide, separated by the second, third, and fourth insulators. The second insulator includes a region contacting the top surface of the oxide and the sidewall of the opening of the first insulator. The second insulator includes a region with a thickness smaller than that of the third insulator. The fourth insulator is less permeable to oxygen compared to the third insulator. In a cross-section along the channel length of the transistor, the third conductor includes a region with a width of 3 nm or more and 15 nm or less. The fifth insulator is disposed between the first conductor and the second conductor and the first insulator. The fifth insulator includes an opening overlapping the opening of the first insulator. The fifth insulator is less permeable to oxygen than the third insulator. The fifth insulator includes a region that contacts the side surface of the oxide, the side surface of the first conductor, and the side surface of the second conductor. The second insulator includes a region that contacts the sidewall of the opening of the fifth insulator. Furthermore, in the cross-section along the channel length of the transistor, the distance between the lower end of the first conductor and the lower end of the second conductor is 10 nm or more and less than 40 nm.

3. A semiconductor device including a transistor, wherein, The transistor includes: an oxide; a first conductor and a second conductor on the oxide; a first insulator with an opening on the first conductor and the second conductor; a second insulator within the opening of the first insulator; a third insulator on the second insulator; a fourth insulator on the third insulator; a third conductor on the fourth insulator; and a fifth insulator. The opening of the first insulator includes a region overlapping with the oxide. The third conductor includes a region overlapping with the oxide, separated by the second, third, and fourth insulators. The second insulator includes a region contacting the top surface of the oxide and the sidewall of the opening of the first insulator. The second insulator includes a region with a thickness smaller than that of the third insulator. The fourth insulator is less permeable to oxygen compared to the third insulator. In a cross-section along the channel length of the transistor, the third conductor includes a region with a width of 3 nm or more and 15 nm or less. The fifth insulator is disposed between the first conductor and the second conductor and the first insulator. The fifth insulator includes an opening overlapping the opening of the first insulator. The fifth insulator is less permeable to oxygen than the third insulator. The fifth insulator includes regions that contact the sidewalls of the oxide, the sidewalls of the first conductor, and the sidewalls of the second conductor. The second insulator includes regions that contact the sidewalls of the openings in the fifth insulator. The oxide contains indium, zinc, and one or more selected from gallium, aluminum, and tin. The oxide is crystalline, and the c-axis of the crystal is substantially perpendicular to the surface of the oxide or the surface to which it is formed.

4. A semiconductor device as claimed in any one of claims 1 to 3, wherein the third conductor is a stack of a fourth conductor and a fifth conductor on the fourth conductor, and the first conductor, the second conductor and the fifth conductor all comprise a metal and nitrogen.

5. The semiconductor device of claim 4, wherein the transistor includes a first layer and a second layer, the first layer being located between the first conductor and the second insulator, the second layer being located between the second conductor and the second insulator, the length of the channel in the first layer being smaller than the width, the length of the channel in the second layer being smaller than the width, and both the first layer and the second layer containing the metal and oxygen.

6. A semiconductor device as claimed in any one of claims 1 to 3, wherein the bottom surface of the third conductor includes a flat region, and the width is the width of the flat region.

7. A semiconductor device according to any one of claims 1 to 3, wherein the third conductor has an arc-shaped bottom surface with the center of curvature located within the third conductor, and the width is the width of the region where a straight line including the center of curvature and parallel to the bottom surface of the oxide overlaps with the third conductor.

8. A semiconductor device according to any one of claims 1 to 3, wherein the oxide includes a region in which the thickness of the region of the oxide overlapping with the third conductor is smaller than the thickness of the region of the oxide overlapping with the first conductor.

9. A semiconductor device as claimed in any of claims 1 to 3, wherein the cutoff frequency of the transistor is 100 GHz or higher at room temperature.

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