Semiconductor package

Abstract

The semiconductor package includes: a first semiconductor wafer including a first semiconductor layer, a first through electrode penetrating the first semiconductor layer, a first bonding pad connected to the first through electrode, and a first insulating bonding layer; and a second semiconductor wafer located on the first semiconductor wafer and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer and a second insulating layer located on the first insulating layer, the first insulating layer and the first insulating bonding layer form a bonding interface, the first insulating layer includes a second insulating material different from the first insulating material, and the second insulating layer includes a third insulating material different from the second insulating material.

Description

Technical Field

[0001] [Cross - reference to Related Applications]

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0135183, filed with the Korean Intellectual Property Office on October 12, 2021, the disclosure of which is incorporated herein by reference in its entirety.

[0003] The inventive concept relates to a semiconductor package and a method of manufacturing the same.

Background Art

[0004] In accordance with the trend of miniaturization and high performance of semiconductor packages, a package system (system - in - package, SiP) technology has been developed in which multiple semiconductor chips performing different functions are embedded in a single package. In order to form fine wiring connecting semiconductor chips in a single package, technologies such as forming through - silicon vias (TSVs) and bonding semiconductor chips to each other via bonding pads have been utilized.

Summary of the Invention

[0005] Aspects of the inventive concept provide a semiconductor package and a method of manufacturing the same with improved reliability.

[0006] According to an aspect of the inventive concept, a semiconductor package includes: a first semiconductor chip including a first semiconductor layer, a first through - electrode, a first bonding pad, and a first insulating bonding layer, the first through - electrode penetrating the first semiconductor layer in a vertical direction, the first bonding pad being connected to the first through - electrode, and the first insulating bonding layer being located on a side surface of the first bonding pad; and a second semiconductor chip disposed on the first semiconductor chip and including a second semiconductor layer, a second bonding pad, and a second insulating bonding layer, the second bonding pad being located under the second semiconductor layer and bonded to the first bonding pad, and the second insulating bonding layer being located on a side surface of the second bonding pad and bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer and a second insulating layer located on the first insulating layer, the first insulating layer forms a bonding interface with the first insulating bonding layer, the first insulating layer includes a second insulating material different from the first insulating material, and the second insulating layer includes a third insulating material different from the second insulating material.

[0007] According to an aspect of the inventive concept, a semiconductor package includes a first structure and a second structure located on the first structure, wherein the first structure includes: a first semiconductor layer including a first front surface and an opposite first rear surface; a first device layer located on the first front surface of the first semiconductor layer and including a first interconnection layer; a first through electrode penetrating the first semiconductor layer and connected to the first interconnection layer of the first device layer; and a first bonding structure including a first bonding pad and a first insulating bonding layer located on a side surface of the first bonding pad, the first bonding pad being located on the first rear surface of the first semiconductor layer and connected to the first through electrode, and the second structure includes: a second semiconductor layer having a second front surface and an opposite second rear surface; a second device layer located on the second front surface of the second semiconductor layer and including a second interconnection layer; and a second bonding structure including a second bonding pad and a second insulating bonding layer, the second bonding pad being located under the second device layer and bonded to and in direct contact with the first bonding pad, the second insulating bonding layer being in direct contact with and bonded to the first insulating bonding layer, wherein the first bonding pad and the second bonding pad that are bonded to each other to form a part of the bonding interface form an asymmetric structure in which at least one of the width and thickness of the first bonding pad and the second bonding pad is different, and the first insulating bonding layer and the second insulating bonding layer that are bonded to each other to form a part of the bonding interface include different materials.

[0008] According to an aspect of the inventive concept, a semiconductor package includes a first structure and a second structure located on the first structure, wherein the second structure includes a plurality of semiconductor wafers stacked on the first structure, and each of the plurality of semiconductor wafers of the second structure includes: a semiconductor layer; a through electrode penetrating the semiconductor layer in a vertical direction; a device layer connected to a first end of the through electrode; a rear bonding structure connected to an opposite second end of the through electrode; and a front bonding structure located under the device layer, wherein among the plurality of semiconductor wafers of the second structure, the rear bonding structure of a lower semiconductor wafer is directly bonded to and stacked on the front bonding structure of an upper semiconductor wafer, and the outermost insulating layers of the front bonding structure and the rear bonding structure include different materials.

[0009] According to an aspect of the inventive concept, a method of manufacturing a semiconductor package includes: forming a first structure including a first semiconductor layer, a first through electrode penetrating the first semiconductor layer in a vertical direction, a first bonding pad connected to the first through electrode, and a first insulating bonding layer on a side surface of the first bonding pad; forming a second structure including a second semiconductor layer, a second bonding pad under the second semiconductor layer, and a second insulating bonding layer on a side surface of the second bonding pad; and bonding the first structure to the second structure such that the first bonding pad directly contacts the second bonding pad and the first insulating bonding layer directly contacts the second insulating bonding layer, wherein the first insulating bonding layer and the second insulating bonding layer that are bonded to each other to form a part of the bonding interface are formed of different materials.

Embodiments

[0011] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0012] FIG. 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept.

[0013] FIG. 2 is a partially enlarged view showing a semiconductor package according to an embodiment of the inventive concept. FIG. 2 is an enlarged view of region "A" of FIG. 1.

[0014] Referring to FIGS. 1 and 2, a semiconductor package 1000 according to an exemplary embodiment may include a first semiconductor wafer 100 and second semiconductor wafers 200A, 200B, 200C, and 200D. The second semiconductor wafers 200A, 200B, 200C, and 200D may be stacked in a vertical direction (Z-axis direction). According to an embodiment, the number of the second semiconductor wafers 200A, 200B, 200C, and 200D may be greater than or less than the number shown in the drawings. For example, the semiconductor package according to the inventive concept may include three or less than three or five or more than five second semiconductor wafers.

[0015] The first semiconductor wafer 100 and the second semiconductor wafers 200A, 200B, 200C, and 200D stacked in the vertical direction (Z-axis direction) can be electrically connected via the first through electrode 130 and the second through electrode 230. The first semiconductor wafer 100 and the second semiconductor wafers 200A, 200B, 200C, and 200D can have a structure (e.g., hybrid bonding, direct bonding, etc.) in which elements exposed on the upper and lower surfaces of each of the semiconductor wafers are directly bonded without separate connecting members (e.g., metal pillars, solder bumps, etc.). Dielectric-to-dielectric bonding and copper-to-copper bonding can be formed at the interface between the first semiconductor wafer 100 and the lowermost second semiconductor wafer 200A among the second semiconductor wafers 200A, 200B, 200C, and 200D, and dielectric-to-dielectric bonding and copper-to-copper bonding can also be formed at the interfaces between the second semiconductor wafers 200A, 200B, 200C, and 200D.

[0016] As shown in FIG. 2, the post-insulation bonding layer 221 and the post-bonding pad 225 of the lower second semiconductor wafer 200A can be bonded to the pre-insulation bonding layer 211 and the pre-bonding pad 215 of the upper second semiconductor wafer 200B. According to an embodiment of the inventive concept, the post-insulation bonding layer 221 and the pre-insulation bonding layer 211 to be bonded to each other can be formed of different materials to increase the bonding strength of the dielectric-to-dielectric bonding between the insulation bonding layers forming the bonding interface IF. The post-insulation bonding layer 221 and the pre-insulation bonding layer 211 can be formed of different materials among silicon oxide, silicon nitride, silicon carbonitride, and silicon carbon oxynitride. According to an embodiment of the inventive concept, it has been experimentally verified that when the bonding structure is formed by an annealing process at a low temperature (e.g., a temperature of about 200° C. or less than 200° C.), the strength of the dielectric-to-dielectric bonding in the case of bonding between heterogeneous insulation bonding layers is higher than that in the case of bonding between homogeneous insulation bonding layers (e.g., bonding between silicon oxides or bonding between silicon carbonitrides).

[0017] Meanwhile, the rear insulating bonding layer 221 and the front insulating bonding layer 211 can be formed under different process conditions (e.g., different deposition temperatures). For example, the rear insulating bonding layer 221 can be formed at a temperature lower than the formation temperature of the front insulating bonding layer 211. The rear insulating bonding layer 221 can be formed of silicon oxide in a deposition process at a relatively low temperature (e.g., within a temperature range of about 150°C to about 200°C), and the front insulating bonding layer 211 can be formed in a deposition process at a relatively high temperature (e.g., within a temperature range of about 350°C to about 400°C). By forming the insulating bonding layer under relatively low-temperature deposition process conditions, the thermal history of the integrated circuit can be reduced to improve the reliability of the semiconductor package, and materials for low-temperature processes can be used, which will broaden the material selection. Meanwhile, the rear insulating bonding layer 221 can have a porous structure with more pores inside than the front insulating bonding layer 211, and in this case, the bonding surface of the rear insulating bonding layer 221 before bonding can have surface roughness, thereby improving the bonding strength between the insulating bonding layers.

[0018] According to an embodiment of the inventive concept, the rear insulating bonding layer 221 can include a plurality of rear insulating layers 221a, 221b, and 221c, and the front insulating bonding layer 211 can include a plurality of front insulating layers 211a and 211b. Among the plurality of rear insulating layers 221a, 221b, and 221c, the first rear insulating layer 221a can cover or surround the side surfaces of the second semiconductor layer 201 and the second through structure 230, the second rear insulating layer 221b can be disposed on the first rear insulating layer 221a and can be spaced apart from the side surface of the second through structure 230, and the third rear insulating layer 221c can have an opening such that the rear bonding pad 225 can be connected to the second through electrode 232. The plurality of front insulating layers 211a and 211b can include a first front insulating layer 211a and a second front insulating layer 211b located on the first front insulating layer 211a, and the second front insulating layer 211b can include one or more insulating layers. As shown in the enlarged view on the left side of FIG. 2, the second front insulating layer 211b can include a plurality of insulating layers formed of the same material, but the boundaries of the plurality of insulating layers are separated according to the process conditions. The third rear insulating layer 221c, which is the outermost or uppermost insulating layer among the plurality of rear insulating layers 221a, 221b, and 221c, and the first front insulating layer 211a, which is the outermost or lowermost insulating layer among the plurality of front insulating layers 211a and 211b, can be in direct contact to form at least a part of the bonding interface IF.

[0019] The first front insulating layer 211a may be formed of, for example, silicon carbonitride and may be oxidized to silicon carbonitride oxide while being bonded to the third back insulating layer 221c. Accordingly, an insulating layer including silicon oxide as a first insulating material may be disposed under the bonding interface IF, and a first insulating layer including silicon carbonitride oxide as a second insulating material and a second insulating layer including silicon carbonitride as a third insulating material may be disposed above the bonding interface IF.

[0020] In FIG. 2, the peripheral region of the bonding interface between the second semiconductor wafers 200A, 200B, 200C, and 200D bonded to each other vertically is enlarged, but the inventive concept may also be equally applied to the peripheral region of the bonding interface in which the first semiconductor wafer 100 of FIG. 1 is bonded to the lowermost second semiconductor wafer 200A among the second semiconductor wafers 200A, 200B, 200C, and 200D. For example, the back insulating layer 121 of the first back structure 120 of the first semiconductor wafer 100 may be formed of an insulating material different from the insulating material of the front insulating bonding layer 211 of the lowermost second semiconductor wafer 200A.

[0021] Hereinafter, the components of the semiconductor package 1000 according to the exemplary embodiments will be described in detail.

[0022] The first semiconductor wafer 100 may include a first semiconductor layer 101, a first device layer 110, a first back structure 120, and a first through structure 130. The first semiconductor wafer 100 may be a buffer wafer or a control wafer including a plurality of logic devices and / or memory devices in the first device layer 110. The first semiconductor wafer 100 may transmit signals from the second semiconductor wafers 200A, 200B, 200C, and 200D stacked thereon to the outside, and may also transmit signals and power from the outside to the second semiconductor wafers 200A, 200B, 200C, and 200D. The first device layer 110 may include a first integrated circuit disposed on the front surface of the first semiconductor layer 101 facing the first device layer 110. The first integrated circuit may include a circuit (e.g., an input / output (I / O) circuit and the like) for transmitting an address command or a control command so that the second semiconductor wafers 200A, 200B, 200C, and 200D can store or output data. For example, the integrated circuit may perform both a logic function and a memory function via logic elements and memory elements. However, according to an embodiment, the first integrated circuit may include only logic elements to perform only a logic function.

[0023] The first semiconductor layer 101 may include, for example, semiconductor elements such as silicon (Si) or germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first semiconductor layer 101 may have a silicon on insulator (SOI) structure. The first semiconductor layer 101 may include an active region, such as an impurity-doped well or an impurity-doped structure. The first semiconductor layer 101 may include various device isolation structures, such as a shallow trench isolation (STI) structure. The first semiconductor layer 101 may have an active surface and a non-active surface positioned opposite to the active surface, and the active surface has an active region.

[0024] The first device layer 110 may be disposed on the lower surface (e.g., the active surface) of the first semiconductor layer 101 and may include various types of individual devices. The individual devices may be disposed in the active region of the first semiconductor layer 101 and may include various active devices and / or passive devices. The first device layer 110 may include a first interlayer insulating layer 111 and a first interconnecting layer 112. The first interlayer insulating layer 111 covers the individual devices, and the first interconnecting layer 112 connects the individual devices to each other, connects the individual devices to the active region of the first semiconductor layer 101, or connects the individual devices to the connection bumps 140. The first interlayer insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate (TEOS). The first interlayer insulating layer 111 may include multiple layers. The first interconnecting layer 112 may include, for example, a metal material, including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or titanium (Ti), or an alloy thereof. The first interconnecting layer 112 may have a multilayer structure including interconnecting patterns and vias. An insulating protection film for electrically separating the first interconnecting layer 112 from the first semiconductor layer 101 may be disposed between the first device layer 110 and the first semiconductor layer 101.

[0025] The connection bumps 140 may be disposed under the first device layer 110. In addition to the bumps for communicating with the second semiconductor wafers 200A, 200B, 200C, and 200D, the connection bumps 140 may also include bumps for communicating with an external device (e.g., "800" in FIG. 9). The connection bumps 140 may include, for example, a low melting point metal or an alloy including tin (Sn) (e.g., Sn - Ag - Cu). The connection bumps 140 may include, for example, solder balls. Each of the connection bumps 140 may have a platform shape, a spherical shape, or a pin shape. Each of the connection bumps 140 may be formed as a multilayer or a single layer.

[0026] The first back structure 120 may be disposed on the upper surface (e.g., the non-active surface) of the first semiconductor layer 101. The first back structure 120 may include a first bonding pad 125 connected to the first through electrode 132 and a first insulating bonding layer 121 located on the side surface of the first bonding pad 125. The first bonding pad 125 and the first insulating bonding layer 121 may be directly bonded to the lowermost second semiconductor wafer 200A among the second semiconductor wafers 200A, 200B, 200C, and 200D. The first insulating bonding layer 121 may be formed of any one of silicon oxide, silicon nitride, silicon carbonitride, and silicon carbon oxynitride. The first insulating bonding layer 121 may include an insulating material different from the insulating material of the second front insulating layer 211 of the second semiconductor wafer 200.

[0027] The first through structure 130 may penetrate the first semiconductor layer 101 in the vertical direction (Z-axis direction) and provide an electrical path connecting the first interconnection layer 112 and the first bonding pad 125 to each other. The first through structure 130 may include a first spacer 131 and a first through electrode 132. The first through electrode 132 may include a conductive plug and a barrier layer surrounding the conductive plug, which is similar to the structure of the second through electrode 232 in FIG. 2, and thus the following description of the second through electrode 232 will be referred to.

[0028] The second semiconductor wafers 200A, 200B, 200C, and 200D may be disposed on the first semiconductor wafer 100 and each include a second semiconductor layer 201, a second device layer 209, a second front structure 210, a second back structure 220, and a second through structure 230. Since the second semiconductor wafers 200A, 200B, 200C, and 200D may have substantially the same or similar structures, hereinafter, the lowermost second semiconductor wafer 200A will be mainly described, and for simplicity, the reference numerals of the same components and the redundant descriptions may be omitted. However, different from the other second semiconductor wafers 200A, 200B, and 200C, the second semiconductor wafer 200D disposed on the uppermost layer may not include the second through structure 230. In addition, the second semiconductor layer 201, the second device layer 209, and the second through structure 230 have the same or similar characteristics as the first semiconductor layer 101, the first device layer 110, and the first through structure 130 of the first semiconductor wafer 100, and thus the repeated description thereof may be omitted for simplicity.

[0029] The second semiconductor layer 201 may include a material the same as or similar to that of the first semiconductor layer 101. The second semiconductor layer 201 may have a smaller size (e.g., width) than the first semiconductor layer 101, but is not limited thereto.

[0030] The second device layer 209 may include a second interlayer insulating layer 205, a second interconnect layer 206, an interconnect pad 207, a transistor 202, and a device isolation layer 204. The interconnect pad 207 may be connected to a plug or via 206P of the second interconnect layer 206 and may have a thickness greater than the thickness of the interconnect pattern 206L of the second interconnect layer 206. The second interconnect layer 206 and the interconnect pad 207 may include a metal material, including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti) or an alloy thereof. The interconnect pad 207 may be formed of a metal material different from the metal material of the second interconnect layer 206.

[0031] The second device layer 209 may include a second integrated circuit, and the second integrated circuit includes transistors 202 disposed on the front surface (e.g., the active surface) of the second semiconductor layer 201 facing the second device layer 209. The second integrated circuit may include a memory device that stores or outputs data based on address commands and control commands received from the first semiconductor wafer 100. For example, the memory device may include volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM), or non-volatile memory devices such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). In such a case, the semiconductor package according to an embodiment of the inventive concept may be used for high bandwidth memory (HBM) products, electro data processing (EDP) products, or similar products.

[0032] As shown in FIG. 2, each of the transistors 202 may include a gate electrode 202g, a gate dielectric layer 202d, and an impurity region 202a. The impurity region 202a may be, for example, a doped well or a doped structure. The impurity region 202a may be used as, for example, a source region or a drain region of the transistor 202. The gate dielectric layer 202d may be disposed between the gate electrode 202g and the active region of the second semiconductor layer 201. The active region may be defined by device isolation layers 204 in the second semiconductor layer 201. The device isolation layers 204 may be formed by a shallow trench isolation (STI) process. Gate spacers 203 are disposed on both sides of the gate electrode 202g, and the gate spacers 203 may electrically insulate the gate electrode 202g from the impurity region 202a. The transistor 202 may be electrically connected to the second through electrode 232 and the second front pad 215 via the second interconnection layer 206. For example, the impurity region 202a may be connected to the second interconnection layer 206 to be electrically connected to the second through electrode 232. The second interlayer insulating layer 205 may at least partially cover or surround the transistor 202 and the second interconnection layer 206. The second interlayer insulating layer 205 may include silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate (TEOS).

[0033] The second through structure 230 may penetrate the second semiconductor layer 201 in the vertical direction (Z-axis direction) and provide an electrical path for connecting the second front bonding pad 215 to the second back bonding pad 225. The second through structure 230 may include a second spacer 231 and a second through electrode 232. The second spacer 231 may include silicon oxide, silicon oxynitride, silicon nitride, a polymer, or a combination thereof, and may be a single layer or multiple layers. As shown in FIG. 2, the second through electrode 232 may include a conductive plug 232b and a barrier layer 232a surrounding the conductive plug 232b. The barrier layer 232a may include a metal compound, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The conductive plug 232b may include, for example, a metal material such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu).

[0034] The second back structure 220 of the lower second semiconductor wafer 200A may be bonded to the second front structure 210 of the upper second semiconductor wafer 200B. Similarly, the second back structure 220 of the lower second semiconductor wafer 200B may be bonded to the second front structure 210 of the upper second semiconductor wafer 200C. As shown in FIG. 2, since the insulating bonding layers disposed at each bonding interface IF in the vertical direction are formed of different insulating materials, as described above, the bonding strength of dielectric-to-dielectric bonding can be improved.

[0035] The second front bonding pad 215 can be bonded to the second rear bonding pad 225 to form a part of the bonding interface IF. The second front bonding pad 215 and the second rear bonding pad 225 can have an asymmetric structure, in which at least one of the width and thickness of the second front bonding pad 215 and the second rear bonding pad 225 is different from each other. For example, the second rear bonding pad 225 can have a first width W1 and a first thickness T1, while the second front bonding pad 215 can have a second width W2 smaller than the first width W1 and a second thickness T2 greater than the first thickness T1. Since the first width W1 is greater than the second width W2, an alignment margin between the second front bonding pad 215 and the second rear bonding pad 225 can be ensured, and since the second thickness T2 is greater than the first thickness T1, the second front bonding pad 215 and the second rear bonding pad 225 can be stably bonded without creating a gap or empty space between the second front bonding pad 215 and the second rear bonding pad 225 due to the expansion of the metal material (e.g., copper) during bonding. The second front bonding pad 215 and the second rear bonding pad 225 can respectively include a barrier layer 215a and 225a and a conductive layer 215b and 225b. The barrier layers 215a and 225a can contain metal compounds such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The conductive layers 215b and 225b can contain, for example, metal materials such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu).

[0036] Meanwhile, the semiconductor package 1000 according to an exemplary embodiment can further include an encapsulant 500 surrounding the second semiconductor wafers 200A, 200B, 200C, and 200D located on the first semiconductor wafer 100. The encapsulant 500 can be disposed on the first semiconductor wafer 100 and can encapsulate at least a part of each of the second semiconductor wafers 200A, 200B, 200C, and 200D. As shown in FIG. 1, the encapsulant 500 can be formed to expose the upper surface of the uppermost second semiconductor wafer 200D. However, in some embodiments, the encapsulant 500 can be formed to cover the upper surface of the uppermost second semiconductor wafer 200D. The encapsulant 500 can contain, for example, an epoxy mold compound (EMC), but the material of the encapsulant 500 is not particularly limited.

[0037] FIGS. 3 to 8 are enlarged partial views showing a semiconductor package according to an embodiment of the concept of the present invention. FIGS. 3 to 8 are enlarged views of the region corresponding to the region "A" in FIG. 1.

[0038] Referring to FIGS. 3 and 4, in the second front structure 210, the second front insulating layer 211 may include a first insulating layer 211a and a plurality of second insulating layers 211b, and the composition of the insulating material of the plurality of second insulating layers 211b may be different. For example, the second rear insulating layer 221 may contain a first insulating material, the first insulating layer 211a may contain a second insulating material different from the first insulating material, some of the second insulating layers 211b in the second insulating layer 211b may contain a third insulating material different from the second insulating material, and another one of the second insulating layers 211b may contain a fourth insulating material different from the third insulating material. For example, the first insulating material may be silicon oxide, the second insulating material may be silicon oxynitride carbon, the third insulating material may be silicon carbonitride, and the fourth insulating material may be silicon oxide. In FIG. 3, the insulating layer containing the fourth insulating material may be disposed between the insulating layers containing the third insulating material. In FIG. 4, the insulating layer containing the fourth insulating material may be disposed between the insulating layer containing the third insulating material and the first insulating layer 211a. By bonding between the heterogeneous insulating layers located between the layers constituting the second insulating layer 211b, the bonding strength can be further improved.

[0039] Referring to FIG. 5, in the second front structure 210, the second front bonding pad 215 may recess the lower portion of the interconnection pad 207. The second front bonding pad 215 may be received in a groove in the lower portion of the interconnection pad 207. The groove may be a structure formed by partially removing the lower portion of the interconnection pad 207 by an etching process during a process of forming an opening by etching the second front insulating layer 211.

[0040] Referring to FIG. 6, the central axis of the second front bonding pad 215 is shifted or offset from the central axis of the second rear bonding pad 225. Since the second width W2 of the second rear bonding pad 225 is greater than the first width W1 of the second front bonding pad 215, the second front bonding pad 215 and the second rear bonding pad 225 can be stably bonded even if the central axes are shifted from each other.

[0041] Referring to FIG. 7, the second rear structure 220 does not include the second rear bonding pad 225, and the second through electrode 232 of the lower second semiconductor wafer 200A may be in direct contact with the second front bonding pad 215 of the upper second semiconductor wafer 200B. Also in this case, since the second rear insulating layer 221 and the second front insulating layer 211 may contain different insulating materials, dielectric-to-dielectric adhesion can be enhanced.

[0042] Referring to FIG. 8, the second back structure 220 may further include a second back bonding via hole 217 located between the second back bonding pad 225 and the interconnection pad 207. The second back bonding via hole 217 may include a barrier layer 217a and a conductive layer 217b. The second back bonding via hole 217 may have a structure and material similar to those of the barrier layer 225a and the conductive layer 227b of the second back bonding pad 225, and thus, for simplicity, the description thereof is omitted.

[0043] FIG. 9 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept.

[0044] Referring to FIG. 9, a semiconductor package 2000 according to an exemplary embodiment may include a package substrate 600, an interposer substrate 700, and at least one chip structure 1000. In addition, the semiconductor package 2000 may further include a logic chip or a processor chip 800 disposed adjacent to the chip structure 1000 on the interposer substrate 700.

[0045] The packaging substrate 600 may include lower pads 612 disposed on the lower surface of the main body, upper pads 611 disposed on the upper surface of the main body, and a redistribution circuit 613 that electrically connects the lower pads 612 and the upper pads 611 to each other. The packaging substrate 600 may be a support substrate on which an interposer substrate 700, a logic chip 800, and a chip structure 1000 are mounted, and may be a substrate for semiconductor packaging (including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape interconnection board, and similar substrates). Depending on the type of the substrate, the main body of the packaging substrate 600 may include different materials. For example, when the packaging substrate 600 is a PCB, it may be in a form in which an inner connection layer is additionally stacked on one or both sides of a body copper clad laminate or a copper clad laminate. A solder mask layer may be formed on the lower surface and the upper surface of the packaging substrate 600, respectively. The lower pads 612, the upper pads 611, and the redistribution circuit 613 may form an electrical path connecting the lower surface and the upper surface of the packaging substrate 600. The lower pads 612, the upper pads 611, and the redistribution circuit 613 may be formed of at least one or two or more of the following metal materials: copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), or gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C), or an alloy including two or more metals. The redistribution circuit 613 may include a plurality of redistribution layers and vias connecting the plurality of redistribution layers. External connection terminals 620 connected to the lower pads 612 may be disposed on the lower surface of the packaging substrate 600. The external connection terminals 620 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or an alloy thereof.

[0046] The interposer substrate 700 may include a substrate 701, a lower passivation layer 703, lower pads 705, an interconnection structure 710, metal bumps 720, and vias 730. The chip structure 1000 and the processor chip 800 may be stacked on the packaging substrate 600 via the interposer substrate 700. The interposer substrate 700 may electrically connect the chip structure 1000 and the processor chip 800 to each other.

[0047] The substrate 701 can be formed of any one of, for example, a silicon, an organic material, a plastic, and a glass substrate. When the substrate 701 is a silicon substrate, the interposer substrate 700 can be referred to as a silicon interposer. In addition, when the substrate 701 is an organic substrate, the interposer substrate 700 can be referred to as a panel interposer.

[0048] The lower passivation layer 703 can be disposed on the lower surface of the substrate 701, and the lower pads 705 can be disposed on the lower passivation layer 703. The lower pads 705 can be connected to the vias 730. The chip structure 1000 and the processor chip 800 can be electrically connected to the package substrate 600 via the metal bumps 720 disposed on the lower pads 705.

[0049] The interconnect structure 710 can be disposed on the upper surface of the substrate 701, and can include an interlayer insulating layer 711 and single or multiple layers of interconnects 712. When the interconnect structure 710 has a multi-layer interconnect structure, the interconnect patterns of different layers can be connected to each other via contact vias.

[0050] The via 730 can extend from the upper surface of the substrate 701 to the lower surface to penetrate the substrate 701. Additionally, the via 730 can extend into the interconnect structure 710 to be electrically connected to the interconnects of the interconnect structure 710. When the substrate 701 is silicon, the via 730 can be referred to as a TSV. The other structures and materials of the via 730 are the same as those described for the semiconductor package 1000 of FIG. 1. According to an embodiment, the interposer substrate 700 can include only the interconnect structure therein, but may not include vias.

[0051] The interposer substrate 700 can be used to convert or transfer input electrical signals between the package substrate 600 and the chip structure 1000 or the processor chip 800. Thus, the interposer substrate 700 may not include components such as active components or passive components. In addition, according to an embodiment, the interconnect structure 710 can be disposed below the via 730. For example, the positional relationship between the interconnect structure 710 and the via 730 can be relative.

[0052] The metal bumps 720 can be disposed on the lower surface of the interposer substrate 700 and can be electrically connected to the interconnects of the interconnect structure 710. The interposer substrate 700 can be stacked on the package substrate 600 via the metal bumps 720. The metal bumps 720 can be connected to the lower pads 705 via the interconnects of the interconnect structure 710 and the via 730. In one example, some of the lower pads 705 for power or ground can be integrated together and connected to the metal bumps 720 together, such that the number of the lower pads 705 can be more than the number of the metal bumps 720.

[0053] The logic chip or processor chip 800 can be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter (ADC), an application-specific IC (ASIC), and similar components. Depending on the type of devices included in the logic chip 800, the semiconductor package 2000 can be referred to as a server-oriented semiconductor package or a mobile-oriented semiconductor package.

[0054] The chip structure 1000 can have characteristics similar to those of the semiconductor package 1000 described with reference to FIGS. 1 to 8. For example, the chip structure 1000 has a structure in which the first semiconductor chip 100 and the second semiconductor chips 200A, 200B, 200C, and 200D are directly bonded, and the post-bonding pads 225 of the second semiconductor chips 200A, 200B, 200C, and 200D can be directly bonded to the pre-bonding pads 215, and the second post-insulating bonding layer 221 can be formed of an insulating material different from the insulating material of the pre-insulating bonding layer 211.

[0055] Meanwhile, the semiconductor package 2000 can further include an internal encapsulant that covers or surrounds the side surfaces and the upper surface of the chip structure 1000 and the processor chip 800 located on the interposer substrate 700. Additionally, the semiconductor package 2000 can further include an external encapsulant that covers or surrounds the interposer substrate 700 and an internal encapsulant located on the package substrate 600. The external encapsulant and the internal encapsulant can be formed together and thus cannot be distinguished. According to an embodiment, the semiconductor package 2000 can further include a heat sink that covers the chip structure 1000 and the processor chip 800 located on the package substrate 600.

[0056] FIG. 10 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept.

[0057] Referring to FIG. 10, the semiconductor package 3000A may include a first semiconductor wafer 100 and a second semiconductor wafer 200 stacked in a vertical direction. The first semiconductor wafer 100 and the second semiconductor wafer 200 may be coupled by direct bonding without the need for a separate connecting member. Since the first semiconductor wafer 100 has the same structure as the first semiconductor wafer 100 in FIGS. 1 and 2, its description will be omitted for simplicity. However, the first device layer 110 of the first semiconductor wafer 100 may include individual devices, and the individual devices may include: field effect transistors (FETs), such as planar FETs or fin field effect transistors (FinFETs); memory devices, such as flash memories, DRAMs, SRAMs, and electrically erasable programmable read only memories (EEPROMs), PRAMs, MRAMs, FeRAMs, RRAMs, etc.; logic devices, such as AND, OR, NOT; and various active and / or passive components, such as large scale integrated circuits (LSIs), complementary metal oxide semiconductor (CMOS) image sensors (CISs), and micro-electro mechanical systems (MEMSs). The second semiconductor wafer 200 may be configured as a single wafer and may not include a second through structure 230. However, the second semiconductor wafer 200 may have a second semiconductor layer 201 and a second front structure 210 similar to those described above with reference to FIGS. 1 and 2, and the second front structure 210 may be bonded to the first back structure 120 of the first semiconductor wafer 100. In an exemplary embodiment, the second semiconductor wafer 200 may be a chiplet that forms a multi-chip module (MCM), but is not limited thereto.

[0058] FIG. 11 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0059] Referring to FIG. 11, the semiconductor package 3000B may have the same or similar characteristics as those described above with reference to FIG. 10, except that the semiconductor package 3000B further includes a package substrate 300 on which a first semiconductor chip 100 is mounted and an encapsulant 260 that encapsulates the first semiconductor chip 100 and the second semiconductor chip 200 on the package substrate 300.

[0060] As an example, the first semiconductor chip 100 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application specific integrated circuit (ASIC), and similar components. In addition, the second semiconductor chip 200 may include a memory chip, such as DRAM, SRAM, PRAM, MRAM, FeRAM, or RRAM. In this embodiment, the second semiconductor chip 200 has the shape shown in FIG. 10, but may also have a shape similar to the shapes described above with reference to FIGS. 1 to 8. For example, the second semiconductor chip 200 may include a power management IC (PMIC) chip.

[0061] FIG. 12 is a flowchart showing a sequential process of a method for manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0062] FIG. 13 shows a process of bonding a first structure and a second structure to illustrate a method for manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0063] Referring to FIGS. 12 and 13, a first structure 1 including a first bonding structure BS1 is formed (S1), a second structure 2 including a second bonding structure BS2 is formed (S2), and the first structure 1 and the second structure 2 may be bonded such that the first bonding structure BS1 and the second bonding structure BS2 are in direct contact with each other (S3).

[0064] The first bonding structure BS1 may include a first bonding pad BP1 and a first insulating bonding layer BI1 surrounding at least a portion of the side surface of the first bonding pad BP1, and the second bonding structure BS2 may include a second bonding pad BP2 and a second insulating bonding layer BI2 surrounding at least a portion of the side surface of the second bonding pad BP2. The first bonding pad BP1 and the second bonding pad BP2 may be in contact with each other and may be bonded by copper-to-copper bonding. The first insulating bonding layer BI1 and the second insulating bonding layer BI2 may be in contact with each other and may be bonded by dielectric-to-dielectric bonding. The first bonding structure BS1 and the second bonding structure BS2 may be electrically connected to a redistribution layer or a via disposed in each of the first structure 1 and the second structure 2.

[0065] In an exemplary embodiment, the bonding of the first structure 1 and the second structure 2 may be die-to-die bonding, die-to-wafer bonding, or wafer-to-wafer bonding. For example, when each of the first structure 1 and the second structure 2 is a semiconductor wafer, the bonding of the first structure 1 and the second structure 2 may be die-to-die bonding. For example, when the first structure 1 is one of a plurality of semiconductor structures divided by a scribe lane on a semiconductor wafer and the second structure 2 is a semiconductor wafer disposed on each of the plurality of semiconductor structures, the bonding of the first structure 1 and the second structure 2 may be die-to-wafer bonding. For example, when the first structure 1 and the second structure are each one of a plurality of semiconductor structures divided by a scribe lane on a first semiconductor wafer and a second semiconductor wafer, the bonding of the first structure 1 and the second structure 2 may be wafer-to-wafer bonding.

[0066] Hereinafter, a method for manufacturing the first structure 1 and the second structure 2 will be described.

[0067] FIGS. 14A to 14H are cross-sectional views showing a sequential manufacturing process of a semiconductor wafer according to an exemplary embodiment of the inventive concept. FIGS. 14A to 14H show a process from a diced wafer to forming a plurality of semiconductor wafers including a second semiconductor wafer, and FIGS. 14C to 14F are enlarged views of region "B" of FIG. 14B.

[0068] Referring to FIG. 14A, a bonding material layer can be used to temporarily bond the second semiconductor wafer 200W for the plurality of second semiconductor wafers 200 to be supported on the first carrier 10. The second semiconductor wafer 200W can be bonded such that the surface on which the second device layer 209 and the second front structure 210 are formed faces the first carrier 10, and the second semiconductor wafer 200W can be stably supported by an adhesive material layer such as glue during subsequent processes. The second semiconductor wafer 200W can be in a state in which some components of the second semiconductor wafer 200 have been formed. For example, the second semiconductor wafer 200W can include a second device layer 209, a second front structure 210, and a second through structure 230 disposed on one surface of the second semiconductor layer 201. The second through structure 230 can be formed to have a depth that does not completely penetrate the second semiconductor wafer 200W. Referring to FIG. 2, a plurality of second front insulating layers 211 including a plurality of insulating layers can be formed, and the plurality of insulating layers include a material different from the material of the second back insulating layer 221 of the second back structure 220 (for example, silicon carbonitride). The second front pads 215 can be formed by an inlay method in which the second front insulating layer 211 is opened, filled with a conductive material, and the second front insulating layer 211 is subjected to a polishing process.

[0069] The second through structure 230 can be formed by, for example, a via middle structure. However, the structure of the second through structure 230 is not limited thereto, and can be formed as a via first structure or a via last structure. Via first means a structure in which the second through structure 230 is first formed before each device of the second device layer 209 is formed, via middle means a structure in which each device is formed before the second device layer 209 is formed and then the second through structure 230 is formed, and via last means a structure in which the second through structure 230 is formed after all the second device layers 209 are formed.

[0070] Referring to FIG. 14B, the thickness of the second semiconductor wafer 200W can be reduced by performing a polishing process on the upper surface US of the second semiconductor wafer 200W. Accordingly, the upper surface US of the second semiconductor wafer 200W can be formed below the upper end T of the second through-structure 230. When a part of the second semiconductor wafer 200W is removed, the upper end T of the second through-structure 230 can protrude from the upper surface US of the second semiconductor wafer 200W. By the polishing process, the thickness of the second semiconductor wafer 200W can be reduced to a desired thickness of the second semiconductor chip 200. As the polishing process, a grinding process such as a chemical mechanical polishing (CMP) process, an etching-back process, or a combination thereof can be used. For example, a predetermined thickness of the second semiconductor wafer 200W can be reduced by performing a grinding process, and the second through-structure 230 can be sufficiently exposed by applying an etching-back under appropriate conditions.

[0071] FIGS. 14C to 14F are enlarged detailed views showing a process of forming the post-structure 220 in a state where the upper end T of the second through-structure 230 is exposed in FIG. 14B. FIGS. 14C to 14F show a region corresponding to the region "B" in FIG. 14B.

[0072] Referring to FIG. 14C, a first insulating layer 221a can be formed to cover the upper surface and a part of the second through-structure 230 exposed to the second semiconductor chip 200 and extend along the upper surface (non-active surface) of the second semiconductor layer 201. A second insulating layer 221b including a material different from that of the first insulating layer 221a can be formed on the first insulating layer 221a. A sacrificial insulating layer 221' including a material different from that of the second insulating layer 221b can be formed on the second insulating layer 221b. The first insulating layer 221a can be formed of silicon oxide, the second insulating layer 221b can be formed of silicon nitride, and the sacrificial insulating layer 221' can be formed of silicon oxide, but is not limited thereto. Since the upper end T of the second through-structure 230 protrudes from the upper surface US of the second semiconductor layer 201, the first insulating layer 221a, the second insulating layer 221b, and the sacrificial insulating layer 221' can each be curved or stepped along the side surface and the upper surface of the second through-structure 230.

[0073] Referring to FIG. 14D, a part of the first insulating layer 221a, a part of the second insulating layer 221b, and the sacrificial insulating layer 221' protruding onto the second through-structure 230 can be removed by performing a polishing process. By the polishing process, the upper surface of the first insulating layer 131a, the upper surface of the second insulating layer 131b, and the upper surface of the second through-structure 230 can be substantially coplanar.

[0074] Referring to FIG. 14E, a third insulating layer 221c may be formed on the second insulating layer 221b, and the third insulating layer 221c may be patterned to form an opening OP that exposes the upper surface of the second through-structure 230. Accordingly, a back insulating layer 221 including the first insulating layer 221a, the second insulating layer 221b, and the third insulating layer 221c having the opening OP may be formed.

[0075] Referring to FIG. 14F, a barrier layer 225a and a conductive layer 225b may be formed on the second back insulating layer 221 and the second through-structure 230. The barrier layer 225a may substantially conformally cover the inner surface and the bottom surface of the opening OP. The barrier layer 225a may cover the second back insulating layer 221 in the opening OP and extend along the upper surface of the second back insulating layer 221 in the horizontal direction. The barrier layer 225a may serve as a seed layer and a diffusion barrier layer in a plating process for forming the conductive layer 225b. The barrier layer 225a may be formed of at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and copper (Cu). The conductive layer 225b may be formed on the barrier layer 225a.

[0076] Thereafter, a polishing process may be performed until the upper surface of the second back insulating layer 221 of the second back structure 220 is exposed. Accordingly, referring to FIG. 14G, a second back bonding pad 225 including the barrier layer 225a and the conductive layer 225b may be formed.

[0077] Referring to FIG. 14H, the second semiconductor wafer 200W may be cut along the scribe line SL to divide the second semiconductor wafer 200W into a plurality of second semiconductor chips 200. Thereafter, the first carrier 10 may be removed.

[0078] FIGS. 15 to 17 are cross-sectional views showing a process of bonding a semiconductor chip manufactured with reference to FIGS. 14A to 14H to a wafer. FIGS. 15 to 17 show a process of bonding a second semiconductor chip manufactured with reference to FIGS. 14A to 14H to a wafer on which a first semiconductor chip is formed.

[0079] Referring to FIG. 15, first, the first semiconductor wafer 100W of the first semiconductor chip 100 having the first through-structure 130 may be bonded to the second carrier 20 using an adhesive material layer. The first semiconductor wafer 100W may be in a state in which components of the first semiconductor chip 100 are implemented.

[0080] Next, the second semiconductor wafer 200 manufactured by the manufacturing process of FIGS. 14A to 14H can be bonded to the first semiconductor wafer 100W. The second semiconductor wafer 200 can be bonded on the first semiconductor wafer 100W such that the second front structure 210 faces the first semiconductor wafer 100W.

[0081] Referring to FIGS. 16A and 16B, after the first back structure 120 of the first semiconductor wafer 100 and the second front structure 210 of the second semiconductor wafer 200 are bonded to each other, an annealing process (AP) can be performed to obtain a direct bond or a hybrid bond.

[0082] Before bonding the first semiconductor wafer 100 and the second semiconductor wafer 200, an oxygen plasma treatment process can be performed to activate the surfaces of each of the first back insulating layer 121 of the first back structure 120 and the second front insulating layer 211 of the second front structure 210. The annealing process AP can be, for example, a low-temperature annealing process of about 200 °C or less than 200 °C. When the second front insulating layer 211 is formed of silicon carbonitride, a part of the second front insulating layer 211 can be formed as a first insulating layer 211a that is bonded to the first back insulating layer 121 and contains silicon carbonitride oxide when the annealing process (AP) is performed. As described above, since the insulating material constituting the first back insulating layer 121 is different from the insulating material constituting the second front insulating layer 211, the dielectric-to-dielectric bonding force between different insulating layers can be improved.

[0083] Referring to FIG. 17, the second semiconductor wafers 200A, 200B, 200C, and 200D can be stacked in sequence. For the second semiconductor wafers 200A, 200B, 200C, and 200D, the other second semiconductor wafers 200B, 200C, and 200D can be directly bonded or hybrid bonded to the lowermost second semiconductor wafer 200A in a manner similar to the method described above with reference to FIGS. 15 to 16B.

[0084] Thereafter, an encapsulant 500 (e.g., FIG. 1) can be formed on the first semiconductor wafer 100W, a polishing process can be performed on the encapsulant 500, and the encapsulant 500 and the first semiconductor wafer 100W can be cut along the dicing street SL to separate the plurality of semiconductor packages 1000.

[0085] By using different materials to form the lower insulating bonding layer and the upper insulating bonding layer for directly bonding the lower semiconductor wafer and the upper semiconductor wafer, the bonding strength can be improved, thereby providing a semiconductor package with improved reliability and a method for manufacturing the same.

[0086] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the inventive concept defined by the appended claims.

Brief Description of the Drawings

[0010] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept. FIGS. 2 to 8 are enlarged partial views showing a semiconductor package according to an embodiment of the inventive concept. FIG. 9 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept. FIG. 10 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept. FIG. 11 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept. FIG. 12 is a flowchart showing a sequential process of a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. FIG. 13 shows a bonding process of a first structure and a second structure to illustrate a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. FIGS. 14A to 14H are cross-sectional views sequentially showing a sequential process of manufacturing a semiconductor wafer according to an exemplary embodiment of the inventive concept. FIGS. 15 to 17 are cross-sectional views showing a process of bonding a semiconductor wafer to be manufactured with reference to FIGS. 14A to 14H onto a wafer.

Claims

1. A semiconductor package, comprising: A first semiconductor wafer includes a first semiconductor layer, a first through electrode, a first bonding pad, and a first insulating bonding layer, wherein the first through electrode penetrates the first semiconductor layer in a vertical direction, the first bonding pad is connected to the first through electrode, and the first insulating bonding layer is located on a side surface of the first bonding pad; and a second semiconductor wafer is located on the first semiconductor wafer and includes a second semiconductor layer, a second bonding pad, and a second insulating bonding layer, wherein the second bonding pad is located below the second semiconductor layer and bonded to the first bonding pad, and the second insulating bonding layer is located on a side surface of the second bonding pad and bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer and a second insulating layer located on the first insulating layer, the first insulating layer and the first insulating bonding layer form a bonding interface, the first insulating layer includes a second insulating material different from the first insulating material, the second insulating layer includes a third insulating material different from the second insulating material, and wherein the second insulating layer includes a plurality of insulating layers.

2. The semiconductor package as claimed in claim 1, wherein the third insulating material is different from the first insulating material.

3. The semiconductor package of claim 1, wherein the first insulating bonding layer has a porous structure, the porous structure comprising a greater number of pores than the second insulating bonding layer.

4. The semiconductor package of claim 1, wherein the first insulating material is silicon oxide, the second insulating material is silicon carbonitride, and the third insulating material is silicon carbonitride or silicon oxide.

5. The semiconductor package of claim 1, wherein some of the plurality of insulating layers of the second insulating layer contain the third insulating material, and another insulating layer of the plurality of insulating layers of the second insulating layer contains a fourth insulating material different from the third insulating material.

6. The semiconductor package of claim 1, wherein the first bonding pad has a first width and a first thickness, and the second bonding pad has a second width less than the first width and a second thickness greater than the first thickness.

7. The semiconductor package as claimed in claim 1, wherein: The second semiconductor wafer further includes a device layer located between the second semiconductor layer and the second bonding pad, and the device layer includes an interconnect layer, an interlayer insulating layer and an interconnect pad, the interlayer insulating layer being located on a side surface of the interconnect layer, and the interconnect pad electrically connecting the interconnect layer to the second bonding pad.

8. The semiconductor package as claimed in claim 7, wherein the interlayer insulating layer comprises tetraethyl orthosilicate.

9. The semiconductor package of claim 7, wherein the second bonding pad is received in a recess in the lower portion of the interconnect pad.

10. The semiconductor package of claim 1, wherein the central axis of the first bonding pad is offset from the central axis of the second bonding pad in a horizontal direction.

11. The semiconductor package of claim 1, wherein the second semiconductor wafer comprises a plurality of second semiconductor wafers stacked on the first semiconductor wafer in the vertical direction, each of the plurality of second semiconductor wafers comprising a rear insulating bonding layer and a front insulating bonding layer, and the material of the rear insulating bonding layer being different from the material of the front insulating bonding layer.

12. A semiconductor package, comprising: A first structure and a second structure located on the first structure, wherein the first structure includes: a first semiconductor layer including a first front surface and an opposing first rear surface; a first device layer located on the first front surface of the first semiconductor layer and including a first interconnect layer; a first through electrode penetrating the first semiconductor layer and connected to the first interconnect layer of the first device layer; and a first bonding structure including a first bonding pad and a first insulating bonding layer located on a side surface of the first bonding pad, the first bonding pad being located on the first rear surface of the first semiconductor layer and connected to the first through electrode, and the second structure includes: a second semiconductor layer having a second front surface and an opposing second rear surface; a second device layer located on the second front surface of the second semiconductor layer and including a second interconnect layer; and a second bonding structure including a second bonding pad and a second insulating bonding layer, the second bonding pad being located below the second device layer and bonding to and in direct contact with the first bonding pad, the second insulating bonding layer being in direct contact with and bonding to the first insulating bonding layer. The first and second bonding pads, which are joined together to form part of the bonding interface, have an asymmetrical structure in which at least one of the width and thickness of the first and second bonding pads is different, and the first and second insulating bonding layers, which are joined together to form part of the bonding interface, contain different materials.

13. The semiconductor package of claim 12, wherein the first insulating bonding layer comprises a first insulating material, the second insulating bonding layer comprises a first insulating layer and a second insulating layer located on the first insulating layer, the first insulating layer being bonded to the first insulating bonding layer, and the first insulating layer comprising a second insulating material different from the first insulating material.

14. The semiconductor package of claim 13, wherein the second insulating layer comprises a third insulating material different from the second insulating material.

15. The semiconductor package of claim 14, wherein the first insulating material is silicon oxide, the second insulating material is silicon carbonitride, and the third insulating material is silicon carbonitride.

16. A semiconductor package, comprising: A first structure and a second structure located on the first structure, wherein the second structure includes a plurality of semiconductor wafers stacked on the first structure, and each of the plurality of semiconductor wafers of the second structure includes: a semiconductor layer; a through electrode penetrating the semiconductor layer in a vertical direction; a device layer connected to a first end of the through electrode; a rear bonding structure connected to an opposite second end of the through electrode; and a front bonding structure located below the device layer, wherein in the plurality of semiconductor wafers of the second structure, the rear bonding structure of the lower semiconductor wafer is directly bonded to the front bonding structure of the upper semiconductor wafer and stacked on the front bonding structure of the upper semiconductor wafer, the outermost insulating layer of the front bonding structure and the outermost insulating layer of the rear bonding structure contain different materials, and wherein the outermost insulating layer of the front bonding structure includes a first insulating layer containing silicon carbonitride and a second insulating layer containing silicon carbonitride.

17. The semiconductor package of claim 16, wherein the outermost insulating layer of the rear bonding structure comprises silicon oxide, and the silicon oxide of the outermost insulating layer of the rear bonding structure directly contacts the silicon carbonitride of the outermost insulating layer of the front bonding structure.

18. The semiconductor package of claim 16, wherein the device layer comprises: A transistor includes a gate electrode, a gate dielectric layer, and an impurity region, wherein the gate dielectric layer is located between the gate electrode and the semiconductor layer, and the impurity region is located on the semiconductor layer on both sides of the gate electrode; and an interconnect layer electrically connecting the transistor to the through electrode.

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