Systems and methods for fast memory access

Abstract

This paper discloses systems and methods for fast memory access. In one instance, a processor, such as control circuitry in a system-on-a-chip (SoC), is coupled to external memory, such as a Universal File System (UFS) memory (e.g., NAND flash memory) having a partial logic-to-physical (L2P) mapping table stored in the external memory and a local L2P mapping table stored in local memory (e.g., dynamic random access memory (DRAM)). The control circuitry can evaluate the percentage of active entries to inactive entries in the local L2P mapping table. If the number of inactive entries exceeds the number of active entries, the control circuitry can send a read command without accessing the local L2P mapping table.

Description

[Technical Field]

[0001] In general, the technology of this case relates to accessing data stored in NAND flash memory. [Previous Technology]

[0002] Computing devices are ubiquitous in modern society, especially mobile communication devices, which are becoming increasingly common. The popularity of these mobile communication devices is partly driven by the many functions now enabled on them. The increased processing power in these devices means that mobile communication devices have evolved from mere communication tools into sophisticated mobile entertainment centers, thereby enhancing the user experience. Almost every computing device relies on different levels of memory to store data and operating instructions. For example, there may be system memory that accesses NAND flash memory. Since access to NAND flash memory is relatively slow, there may be cache memory associated with the processor, which facilitates address mapping to speed up memory access. Although there are various ways to improve memory access, there always seems to be room for improvement. [Summary of the Invention]

[0003] The embodiments disclosed herein include systems and methods for fast memory access. Specifically, exemplary embodiments of this application envision a processor, such as control circuitry in a system-on-a-chip (SoC), coupled to external memory, such as a universal flash memory (e.g., NAND flash memory) having a partial logic-to-entity (L2P) mapping table stored in external memory and a local L2P mapping table stored in local memory (e.g., dynamic random access memory (DRAM)). The control circuitry can evaluate the percentage of active entries to inactive entries in the local L2P mapping table. If the number of inactive entries exceeds the number of active entries, the control circuitry can send a read command without accessing the local L2P mapping table. By skipping entries in the external memory that the local memory depends on being more recent in time, this can result in faster memory access to the UFS memory, leading to a better user experience.

[0004] In this regard, a System-on-a-Chip (SoC) is disclosed. The SoC includes a memory bus interface configured to be coupled to a UFS memory having an external cache. The external cache includes a portion of the L2P mapping table of the UFS memory. The SoC also includes a local cache, which includes the local L2P mapping table of the UFS memory. The SoC also includes control circuitry coupled to the memory bus interface and the local cache. The control circuitry is configured to determine the activity size of an active portion of the local L2P mapping table in the local cache. The control circuitry is also configured to compare the activity size of the active portion with a threshold.

[0005] In another embodiment, a System-on-a-Chip (SoC) is disclosed. The SoC includes a memory bus interface configured to be coupled to a UFS memory having an external cache. The external cache includes a portion of the L2P mapping table of the UFS memory. The SoC also includes a local cache that includes the local L2P mapping table of the UFS memory. The SoC also includes control circuitry coupled to the memory bus interface and the local cache. The control circuitry is configured to determine the inactivity size of an inactive portion of the local L2P mapping table in the local cache. The control circuitry is also configured to compare the inactivity size of the inactive portion with a threshold.

[0006] In another embodiment, a method for accessing memory from a host is disclosed. The method includes the step of determining the activity size of an active portion of a local L2P mapping table in a local cache associated with the host, relative to an active portion of an L2P mapping table in an external cache in a remote memory device. The method also includes the step of comparing the activity size of the active portion with a threshold.

Implementation Method

[0014] Several exemplary forms of this application are now described with reference to the accompanying drawings. The term “exemplary” as used herein means “serving as an example, instance or illustration.” Any form described herein as “exemplary” is not necessarily to be construed as preferred or superior to other forms.

[0015] The embodiments disclosed herein include systems and methods for fast memory access. Specifically, exemplary embodiments of this application envision a processor, such as control circuitry in a system-on-a-chip (SoC), coupled to external memory, such as a universal flash memory (e.g., NAND flash memory) having a partial logic-to-entity (L2P) mapping table stored in external memory and a local L2P mapping table stored in local memory (e.g., dynamic random access memory (DRAM)). The control circuitry can evaluate the percentage of active entries to inactive entries in the local L2P mapping table. If the number of inactive entries exceeds the number of active entries, the control circuitry can send a read command without accessing the local L2P mapping table. By skipping entries in the external memory that the local memory depends on being more recent in time, this can result in faster memory access to the UFS memory, leading to a better user experience.

[0016] Figure 1 provides a brief overview of a computing device with a host and UFS memory. Figure 2 illustrates a similar computing device with a Host Performance Booster (HPB) enabled and which can implement the exemplary configuration of the present invention. Figure 3 illustrates a scenario where memory calls resulting in cache misses can negatively impact performance, to highlight how the exemplary configuration of the present invention can better improve performance, as illustrated at the beginning of Figure 4.

[0017] In this configuration, FIG1 illustrates a computing device 100 having a System-on-Chip (SoC) 102, which includes a UFS controller 104. The SoC 102 may be a single integrated circuit (IC) having multiple functions, possibly on different layers, for example, possibly using three-dimensional (3D) IC manufacturing technology, and may be a set of stacked dies (e.g., flip-chip arrangement), etc. The SoC 102 may be coupled to a UFS memory 106 via a UFS bus 108. The UFS memory 106 may include NAND memory elements 110 and SRAM memory elements 112. The NAND memory element 110 may store a complete L2P mapping table therein, and this complete L2P mapping table is always up-to-date. The SRAM memory element 112 may include an external cache memory, which includes a partial L2P mapping table with entries corresponding to the most recently (and / or most frequently) accessed logical addresses. Compared to the SRAM memory element 112, the NAND memory element 110 may have a relatively slower read time.

[0018] It should be understood that in use, the UFS controller 104 may generate a read command that initially queries the SRAM memory element 112 to find the physical address. If a portion of the L2P mapping table includes an L2P mapping for the requested address, the UFS memory 106 retrieves the L2P mapping entry from the SRAM memory element 112. The UFS memory 106 then reads a logical block from the NAND memory element 110 and transfers the data to the SoC 102 (see generally the signaling configuration 300 in FIG3). However, if a portion of the L2P mapping table does not include the logical address, the UFS memory 106 receives the read command and reads the physical address from the complete L2P mapping table in the NAND memory element 110. The UFS memory 106 stores the entries from the portion of the L2P mapping table in the SRAM memory element 112. The L2P mapping entry is then retrieved from the SRAM memory element 112. UFS memory 106 then reads logic blocks from NAND memory element 110 and transfers the data to SoC 102 (see signal transmission scenario 310 in Figure 3).

[0019] Although using a cache memory such as that provided in SRAM memory element 112 can speed up access to logic blocks in NAND memory element 110 when there are entries in a partial L2P mapping table, cache misses sometimes occur, resulting in signaling condition 310. The additional time to obtain an address from the complete L2P mapping table in NAND memory element 110 negatively impacts the user experience and may add unacceptable latency to certain operations within computing device 100.

[0020] To improve performance, the industry has turned to the concept of HPB, which moves the complete L2P mapping table into the SoC, as better illustrated in scenarios 320 and 330 of Figures 2 and 3. In this scenario, Figure 2 illustrates a computing device 200 with an SoC 202, which includes a UFS controller 204. The SoC 202 can be coupled to UFS memory 206 via a UFS bus 208. The UFS memory 206 may include NAND memory elements 210 and SRAM memory elements 212. The NAND memory element 210 may store the complete L2P mapping table therein, and this complete L2P mapping table is always up-to-date. The SRAM memory element 212 may include cache memory, which includes a partial L2P mapping table with entries corresponding to the most recently (and / or most frequently) accessed logical addresses. Additionally, the SoC 202 may also include a DRAM element 214, in which the local L2P mapping table is stored. DRAM element 214 acts as cache memory and allows SoC 202 to access physical addresses immediately. Subsequently, SoC 202 can use a read command to send the physical address to UFS memory 206 (see signaling configuration 320 in Figure 3).

[0021] However, sometimes entries in the local L2P mapping table in DRAM element 214 may be outdated or incorrect. For example, sometimes for internal maintenance purposes (e.g., refresh operations, garbage collection, read recycling, read interference, etc.), it is necessary to move data to another physical area of ​​NAND memory element 210. In this case, the local L2P mapping table in DRAM element 214 may be out of sync with the full L2P mapping table in NAND memory element 210. Traditionally, HPB allows UFS memory 206 to send updates to SoC 202. However, this update is periodic, not instantaneous. Therefore, read operations for out-of-sync addresses may also result in cache misses (see signaling scenario 330 in Figure 3). Such cache misses may negatively impact the user experience and / or potentially introduce unacceptable latency to computing device 200.

[0022] Figure 3 provides a comparison of signal transmission scenarios 300, 310, 320, and 330. Signal transmission scenario 300 begins with a read command 302 being issued and sent to UFS memory 106. At 304, UFS memory 106 retrieves an L2P mapping entry from a portion of the L2P mapping table in SRAM memory element 112. At 306, UFS memory 106 reads a logical block from NAND memory element 110 using the logical address from the portion of the L2P mapping table and transfers the data to SoC 102. Although not precisely scaled, the size of 306 indicates that accessing NAND memory element 110 is relatively slower compared to accessing SRAM memory element 112 at 304.

[0023] Signal transmission scenario 310 illustrates a cache miss in computing device 100, and begins with read command 312, which is issued and sent to UFS memory 106. UFS memory 106 checks SRAM memory element 112, finds no mapped entry, and therefore reads the entry from the full L2P mapping table in NAND memory element 110 at 314 and stores the entry in SRAM memory element 112, thus introducing latency. Subsequently, at 316, an address is obtained from SRAM memory element 112. At 318, UFS memory 106 reads a logical block from NAND memory element 110 using a logical address from a portion of the L2P mapping table and transfers the data to SoC 102. The additional latency introduced by the cache miss can be proven unacceptable.

[0024] Signaling state 320 begins with the UFS controller 204 accessing the DRAM element 214, obtaining a logical address from the local L2P mapping table at 322. Subsequently, at 324, a read command with the logical address is sent to the UFS memory 206. At 326, the UFS memory 206 uses the logical address to read a logical block from the NAND memory element 210 and transfers the data to the SoC 202. Using HPB in this manner reduces the latency caused by cache misses in signaling state 310. However, cache misses still occur, as shown in signaling state 330.

[0025] Signal transmission 330 begins with the UFS controller 204 accessing the DRAM element 214, obtaining a logical address from the local L2P mapping table at 332. Subsequently, at 334, a read command with the logical address is sent to the UFS memory 206. However, at 336, the logical address provided in the read command is incorrect, and the UFS device must read the L2P entry from the complete L2P mapping table in the NAND memory element 210. At 338, the UFS memory 206 uses the address from the complete L2P mapping table to read the logical block from the NAND memory element 210 and transfer the data to the SoC 202. Again, such cache misses can introduce unacceptable latency.

[0026] The exemplary state of this case reduces the probability of cache misses, as shown in signaling case 330, by estimating the number of active entries relative to inactive entries in the local L2P mapping table in the local cache (e.g., DRAM). Based on this estimation, the SoC uses only the HPB method when the inactive portion is smaller than the active portion. In essence, when the active portion is larger than the inactive portion, the SoC determines that the address is likely within the active portion and is therefore accurate and up-to-date. Conversely, when the inactive portion is larger than the active portion, the SoC determines that the address is likely within the inactive portion and may be inaccurate or not up-to-date, and therefore should not be used. In this case, using a portion of the L2P mapping table in an external cache (e.g., SRAM) and its possible cache misses is more efficient than using the possible cache misses of the HPB method.

[0027] "Active" is a term defined in the HPB industry and, as used herein, means that an entry in the local L2P map is the same as an entry in a subset of the L2P map. Similarly, "inactive" as used herein means that an entry in the local L2P map does not have an entry in a subset of the L2P map or has a different entry. In an exemplary manner, the UFS memory may proactively (assuming device control mode is enabled) transfer active and inactive addresses or regions to the SoC, for example, after or during maintenance activities (e.g., refresh operations) at the UFS memory. Based on such updates, the SoC may update the local L2P map in the local cache (e.g., DRAM).

[0028] In this embodiment, FIG4 illustrates a computing device 400, which includes a SoC 402 having a UFS host controller or control circuitry 404 therein. The SoC 402 is coupled to a UFS memory 406 via a memory bus 408, which may be a UFS bus. The SoC 402 may include a memory bus interface 408A, which may be a UFS bus interface. Similarly, the UFS memory 406 may include a memory bus interface 408B. The SoC 402 may also include local cache memory, such as DRAM 410, which stores a local L2P mapping table 412 for the UFS memory 406. In one exemplary embodiment, the local L2P mapping table 412 is a complete L2P mapping table with physical addresses for each logical address. In another exemplary embodiment, the local L2P mapping table 412 is a partial L2P mapping table. The presence of DRAM 410 with local L2P mapping table 412 takes into account that the HPB method is possible for read commands to UFS memory 406.

[0029] The UFS memory 406 may include a memory controller 414, external cache memory (e.g., SRAM 416 and NAND memory element 418). The NAND memory element 418 may store a complete L2P mapping table 420 therein, and the complete L2P mapping table 420 is always up-to-date. The SRAM 416 may be or may include external cache memory, which includes a portion of the L2P mapping table 422 of the UFS memory 406, having entries corresponding to logical addresses that are most recently (and / or most frequently) accessed in time.

[0030] As described above, the exemplary embodiment of this invention contemplates determining the active size of the active portion of the local L2P mapping table 412 in DRAM 410 and comparing the active size of the active portion with a threshold. This threshold may be the inactive size of the inactive portion of the local L2P mapping table 412. Various methods can be used to determine the active size. In the exemplary embodiment, circuitry 430 may include one or more counters, registers, and comparators. When an update from UFS memory 406 occurs, the counters count each active entry and optionally each inactive entry. The comparators can then compare the value of the counters with the total size of the local L2P mapping table 412 stored in the register to determine a percentage, etc. Equivalently, the exemplary embodiment of this invention contemplates determining the inactive size of the inactive portion of the local L2P mapping table 412 and comparing the inactive size of the inactive portion with a threshold. Again, various methods can be used to determine the inactive size.

[0031] Based on this comparison, two possible signal transmission scenarios 500 and 510 can occur, as shown in Figure 5. Specifically, signal transmission scenario 500 occurs when the control circuit 404 (e.g., using circuit 430) determines that the active portion is greater than the inactive portion. Based on this determination, the control circuit 404 infers that the information in the local L2P mapping table 412 is likely correct, and blindly switches to the local L2P mapping table 412 for all read transactions. Therefore, after determining that the active portion exceeds the threshold, signal transmission scenario 500 is similar to signal transmission scenario 320, which begins by obtaining a logical address from the local L2P mapping table 412 in the DRAM 410 at 502, and then sending a read command containing the logical address to the UFS memory 406 at 504. This general procedure is illustrated by the dashed line 500 in Figure 4. The UFS memory 406 then reads a logical block from the NAND memory element 418. The read data is then transferred to the SoC 402 at 506.

[0032] However, when the control circuit 404 determines that the activity size of the active portion does not exceed a threshold (e.g., the inactivity size of the inactive portion), although the HPB method exists, the exemplary state of this case can skip or omit the use of the local L2P mapping table 412 in DRAM 410 and use signaling state 510. Signaling state 510 is based on the inference that random read transactions are likely to have inaccurate addresses in the local L2P mapping table 412. Therefore, in signaling state 510, the control circuit 404 sends a read command to UFS memory 406 via memory bus 408, and specifically to SRAM 416 at 512. At 514, SRAM 416 checks the local L2P mapping table 422 for the logical address. Subsequently, UFS memory 406 reads a logical block from NAND memory element 418 and transfers the read data to SoC 402 at 516. Signal transmission condition 510 avoids cache misses as seen in signal transmission condition 330 and improves performance.

[0033] A more complete explanation of the procedure 600 in relation to the present invention is provided with reference to Figure 6. Procedure 600 begins with a read request from the file system in SoC 402 (block 602). The host controller or control circuit 404 begins command acquisition (block 604). The control circuit 404 may determine whether HPB is enabled (block 606).

[0034] If the answer to block 606 is no, HPB is not enabled, then program 600 enters traditional mode and obtains an address from memory controller 414 (block 608). Memory controller 414 updates the entry to SRAM 416 (block 610) and reads data from raw NAND memory element 418 (block 612). Note that this path corresponds to possible signal transmission scenarios 300 and 310.

[0035] However, if the answer to block 606 is yes, HPB is enabled, and program 600 determines the active size of the active portion in the local L2P mapping table 412 in DRAM 410 (block 614). Equivalently, but not illustrated, program 600, and specifically control circuitry 404, can determine the inactive size of the inactive portion. The determination of the active size can be done directly (e.g., how many addresses are active) or indirectly (e.g., finding out how many addresses are inactive, and then subtracting the number of inactive addresses from the total number of addresses to determine how many addresses are active). Control circuitry 404 can then compare the active size to a threshold (block 616). As noted, an exemplary threshold is the number of inactive addresses or inactive sub-regions. Note that this threshold can also be a percentage of inactive addresses. For example, whether the active size is greater than 55 percent of the inactive size. As another example, if the number of active addresses exceeds the number of inactive addresses, then the number of inactive addresses is effectively the threshold.

[0036] Based on the comparison, program 600 generates a branch. In the first path, control circuit 404 has determined that the active size in DRAM 410 exceeds the inactive size (block 618). Therefore, control circuit 404 obtains the physical address from DRAM 410 and specifically from the local L2P mapping table 412 (block 620). After receiving a read command with the physical address, UFS memory 406 performs the transaction of reading raw data from NAND memory element 418 (block 622).

[0037] In the second path, control circuit 404 has determined that the activity size in DRAM 410 is less than a threshold (block 624). Therefore, control circuit 404 obtains the physical address from SRAM 416, and specifically from a portion of L2P mapping table 422, instead of from DRAM 410 (block 626). If there is no entry in SRAM 416, the program can protect the address by entering conventional mode as described above. Once the physical address is located, UFS memory 406 performs the transaction of reading raw data from NAND memory element 418 (block 622).

[0038] The systems and methods for fast memory access disclosed herein can be provided in or integrated into any processor-based device. This is not a limitation; examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, smart glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players; video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, unmanned aerial vehicles, and multi-rotor aircraft.

[0039] At this point, Figure 7 illustrates an example of a processor-based system 700, which can employ the fast memory access procedures illustrated in Figures 4-6. Although mobile terminals with UFS memory may be specifically conceived as being able to benefit from the exemplary forms of the present invention, it should be understood that the present invention is not limited thereto but can be useful in any system having NAND-based memory elements.

[0040] Continuing to refer to FIG. 7, the processor-based system 700 includes an application processor 704 (sometimes referred to as a host) that communicates with a large storage element 706 (e.g., UFS memory 406) via a UFS bus 708 (e.g., UFS bus 408). The application processor 704 can also be connected to a display 710 via a display serial interface (DSI) bus 712 and to a camera 714 via a camera serial interface (CSI) bus 716. Various audio components (e.g., a microphone 718, a speaker 720, and an audio transcoder 722) can be coupled to the application processor 704 via a serial low-power inter-chip multimedia bus (SLIM bus) 724. In addition, audio components can communicate with each other via a SOUNDWIRE bus 726. A modem 728 can also be coupled to the SLIM bus 724 and / or the SOUNDWIRE bus 726. The modem 728 can also be connected to the application processor 704 via the Peripheral Component Interconnect (PCI) or PCIe bus 730 and / or the System Power Management Interface (SPMI) bus 732.

[0041] Continuing to refer to Figure 7, the SPMI bus 732 can also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 734, a power management integrated circuit (PMIC) 736, an accessory IC (sometimes referred to as a bridge chip) 738, and a radio frequency IC (RFIC) 740. It should be understood that separate PCI buses 742 and 744 can also couple the application processor 704 to the accessory IC 738 and the WLAN IC 734. The application processor 704 can also be connected to the sensor 746 via the sensor bus 748. The modem 728 and the RFIC 740 can communicate using bus 750.

[0042] Continuing to refer to Figure 7, RFIC 740 can be coupled to one or more RFFE components, such as antenna tuner 752, switch 754, and power amplifier 756, via RFFE bus 758. Furthermore, RFIC 740 can be coupled to envelope tracking power supply (ETPS) 760 via bus 762, and ETPS 760 can communicate with power amplifier 756. In summary, the RFFE components (including RFIC 740) can be considered as RFFE system 764. It should be understood that RFFE bus 758 can be formed by clock lines and data lines (not shown).

[0043] Those skilled in the art will also understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the forms disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As examples, the master and slave devices described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the various illustrative elements, blocks, modules, circuits, and steps have been described overall in relation to their function. How such function is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described function in a modified manner for each specific application, but such implementation decisions should not be construed as a departure from the scope of this document.

[0044] The various illustrative logic blocks, modules, and circuits described herein can be implemented or executed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, individual gate or transistor logic devices, individual hardware elements, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor; however, alternatively, it may be any known processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0045] The forms disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as separate components in a remote station, base station, or server.

[0046] It should be noted that the operational steps described in any of the exemplary forms herein are described to provide examples and discussion. The described operations can be performed in many different orders other than those shown. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary forms can be combined. It should be understood that many different modifications can be made to the operational steps shown in the flowcharts, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0047] To enable anyone skilled in the art to implement or use the content of this application, a description of the content of this application has been provided above. Various modifications to the content of this application will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, the content of this application is not intended to be limited to the examples and designs described herein, but rather to be consistent with the broadest scope of the principles and novel features revealed herein.

[0048] Examples of implementations are described in the following numbered clauses: 1. A system-on-a-chip (SoC) comprising: a memory bus interface configured to be coupled to a universal flash memory (UFS) having an external cache, the external cache including a local logic-to-physical (L2P) mapping table of the UFS; a local cache including a local L2P mapping table of the UFS; and control circuitry coupled to the memory bus interface and the local cache, and configured to: determine an active size of an active portion of the local L2P mapping table in the local cache; and compare the active size of the active portion with a threshold. 2. The SoC of clause 1, wherein the control circuitry configured to determine the active size is configured to: determine the active size by determining an inactive size of an inactive portion of the local L2P mapping table in the local cache. 3. SoC according to Clause 1 or Clause 2, wherein the threshold includes the inactive size of the inactive portion of the local L2P mapping table in the local cache. 4. SoC according to Clauses 1 to 3, wherein the control circuitry is also configured to: when the active size does not meet the threshold, execute a read call by sending a read command to the external cache without referencing the local L2P mapping table in the local cache. 5. SoC according to Clause 4, wherein the control circuitry is also configured to: for the read command, retrieve an L2P mapping entry from the portion of the L2P mapping table in the external cache. 6. SoC according to Clause 4 or Clause 5, wherein the control circuitry is also configured to: for the read command, when the portion of the L2P mapping table does not have an entry for the logical address in the read command, issue a direct call to the NAND memory element in the UFS memory. 7. In any of the foregoing clauses of the SoC, the control circuitry is also configured to access an address in the local L2P mapping table in the local cache when the activity size exceeds the threshold. 8. In any of the foregoing clauses of the SoC, the control circuitry is also configured to synchronize the local L2P mapping table in the local cache with the address table in the UFS memory. 9. In any of the foregoing clauses of the SoC, the control circuitry is also configured to determine whether host performance enhancement is enabled. 10. In any of the foregoing clauses of the SoC, the control circuitry configured to determine the activity size is based on the number of identical entries between the local L2P mapping table and the partial L2P mapping table. 11. In any of the foregoing clauses of the SoC, the local cache includes dynamic random access memory (DRAM).12. A system-on-a-chip (SoC) comprising: a memory bus interface configured to be coupled to a general-purpose flash memory (UFS) having an external cache, the external cache including a portion of a logic-to-physical (L2P) mapping table of the UFS; a local cache including a local L2P mapping table of the UFS; and control circuitry coupled to the memory bus interface and the local cache, and configured to: determine an inactive size of an inactive portion of the local L2P mapping table in the local cache; and compare the inactive size of the inactive portion with a threshold. 13. The SoC of claim 12, wherein the control circuitry configured to determine the inactive size is configured to: determine the inactive size by determining an active size of an active portion of the local L2P mapping table in the local cache. 14. A SoC according to Clause 12 or Clause 13, wherein the threshold includes the active size of the active portion of the local L2P mapping table in the local cache. 15. A SoC according to any of Clauses 12 to 14, wherein the control circuitry is also configured to: when the inactive size does not meet the threshold, execute a read call by sending a read command to the external cache without referencing the local L2P mapping table in the local cache. 16. A SoC according to Clause 15, wherein the control circuitry is also configured to: for the read command, retrieve an L2P mapping entry from the portion of the L2P mapping table in the external cache. 17. A SoC according to Clause 15, wherein the control circuitry is also configured to: for the read command, when the portion of the L2P mapping table does not have an entry for the logical address in the read command, issue a direct call to the NAND memory element in the UFS memory. 18. A SoC according to any of Clauses 12 to 17, wherein the control circuitry is also configured to: access the address in the local L2P mapping table in the local cache when the inactivity size exceeds the threshold. 19. A SoC according to any of Clauses 12 to 18, wherein the control circuitry is also configured to: synchronize the local L2P mapping table in the local cache with the address table in the UFS memory. 20. A SoC according to any of Clauses 12 to 19, wherein the control circuitry is also configured to: determine whether the host performance booster is enabled. 21. A SoC according to any of Clauses 12 to 20, wherein the control circuitry configured to determine the inactivity size is based on how many entries in the partial L2P mapping table are not found in the local L2P mapping table.22. A method for accessing memory from a host, comprising the steps of: determining the active size of an active portion of a local logic-to-entity (L2P) mapping table in a local cache associated with the host relative to an active portion of an L2P mapping table in an external cache in a remote memory device; and comparing the active size of the active portion with a threshold. 23. The method of claim 22, wherein determining the active size comprises: determining the inactive size of an inactive portion of the local L2P mapping table in the local cache. 24. The method of claim 22 or claim 23, wherein comparing the active size comprises: comparing the active size with the inactive size of an inactive portion of the local L2P mapping table in the local cache. 25. The method of any of claims 22 to 24, also comprising the steps of: when the active size does not meet the threshold: performing a read call by sending a read command to the external cache without referring to the local L2P mapping table in the local cache. 26. The method according to Clause 25 also includes the step of: retrieving an L2P mapping entry from the portion of the L2P mapping table in the external cache for the read command. 27. The method according to Clause 25 or Clause 26 also includes the step of: issuing a direct call to the NAND memory element in the UFS memory when the portion of the L2P mapping table does not have an entry for the logical address in the read command for the read command. 28. The method according to any of Clauses 22 to 27 also includes the step of: accessing the address in the local L2P mapping table in the local cache when the activity size exceeds the threshold. 29. The method according to any of Clauses 22 to 28 also includes the step of: determining whether the host performance booster is enabled. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a block diagram of a familiar computing system with its associated host and universal flash storage (UFS) memory;

[0008] Figure 2 is a block diagram of an exemplary computing system with associated UFS memory, which uses a host performance booster (HPB) to improve memory access time and can use the exemplary form of the present invention to further improve memory access time;

[0009] Figure 3 is a signal-time diagram showing the access times of known memory with cache hits and cache misses;

[0010] Figure 4 is a block diagram of a computing device having a host and associated UFS memory, illustrating memory access in an exemplary manner according to the content of this case;

[0011] Figure 5 is a signal-time diagram of memory access time in an exemplary state according to the content of this case;

[0012] Figure 6 is a flowchart of a procedure associated with an exemplary form of the content of this case, which works with conventional and functional devices; and

[0013] Figure 7 is a block diagram of a host computer and a UFS memory computing device that can operate in a fast memory access mode according to the content of this case. [Biomaterial Storage]

[0050] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A system-on-a-chip (SoC), comprising: A memory bus interface configured to be coupled to a general-purpose flash memory (UFS) having an external cache including a portion of the logic-to-physical (L2P) mapping table of the UFS; a local cache including a local L2P mapping table of the UFS; and a control circuit coupled to the memory bus interface and the local cache, and configured to: determine an active size of an active portion of the local L2P mapping table in the local cache based on how many entries are identical between the local L2P mapping table and the portion of the L2P mapping table; compare the active size of the active portion with a threshold; and wherein the control circuit is also configured to: when the active size does not meet the threshold: execute a read call by sending a read command to the external cache without referring to the local L2P mapping table in the local cache.

2. According to the SoC of request item 1, the control circuit configured to determine the activity size is configured to determine the activity size by determining an inactive size of an inactive portion of the local L2P mapping table in the local cache.

3. According to Request 1 of the SoC, wherein the threshold includes an inactive size of an inactive portion of the local L2P mapping table in the local cache.

4. According to the SoC of request item 1, wherein the control circuit is also configured to: in response to the read command, retrieve an L2P mapping entry from the L2P mapping table in the external cache.

5. According to Request 1, the SoC, wherein the control circuit is also configured to: for the read command, when the partial L2P mapping table does not have an entry for a logical address in the read command, issue a direct call to a NAND memory element in the UFS memory.

6. According to the SoC of request item 1, wherein the control circuit is also configured to access an address in the local L2P mapping table in the local cache when the activity size exceeds the threshold.

7. According to Request 1, the SoC, wherein the control circuit is also configured to synchronize the local L2P mapping table in the local cache with an address table in the UFS memory.

8. According to Request Item 1, the SoC, wherein the control circuit is also configured to: determine whether the host performance booster is enabled.

9. The SoC according to Request 1, wherein the local cache includes a dynamic random access memory (DRAM).

10. A system-on-a-chip (SoC), comprising: A memory bus interface configured to be coupled to a general-purpose flash memory (UFS) having an external cache including a portion of the logic-to-physical (L2P) mapping table of the UFS; a local cache including a local L2P mapping table of the UFS; a control circuit coupled to the memory bus interface and the local cache, and configured to: determine an inactive size of an inactive portion of the local L2P mapping table in the local cache based on how many entries in the portion of the L2P mapping table are not found in the local L2P mapping table; compare the inactive size of the inactive portion with a threshold; and wherein the control circuit is also configured to: when the inactive size does not meet the threshold: execute a read call by sending a read command to the external cache without referring to the local L2P mapping table in the local cache.

11. The SoC according to request 10, wherein the control circuit configured to determine the inactivity size is configured to determine the inactivity size by determining an active size of an active portion of the local L2P mapping table in the local cache.

12. The SoC according to request item 10, wherein the threshold includes an active size of an active portion of the local L2P mapping table in the local cache.

13. The SoC according to request item 10, wherein the control circuit is also configured to: in response to the read command, retrieve an L2P mapping entry from the portion of the L2P mapping table in the external cache.

14. According to the SoC of request item 10, wherein the control circuit is also configured to: for the read command, when the partial L2P mapping table does not have an entry for a logical address in the read command, issue a direct call to a NAND memory element in the UFS memory.

15. According to the SoC of request item 10, wherein the control circuit is also configured to access an address in the local L2P mapping table in the local cache when the inactivity size exceeds the threshold.

16. According to the SoC of request item 10, wherein the control circuit is also configured to synchronize the local L2P mapping table in the local cache with an address table in the UFS memory.

17. According to Request 10, the SoC, wherein the control circuit is also configured to: determine whether a host performance booster is enabled.

18. A method for accessing memory from a host, comprising the steps of: determining an active size of an active portion of an active portion of an active logical-to-physical (L2P) mapping table in a local cache associated with a host relative to an active portion of an active portion of an L2P mapping table in an external cache in a remote memory device, based on how many entries are identical between the local L2P mapping table and the partial L2P mapping table; comparing the active size of the active portion with a threshold; and also comprising the steps of: when the active size does not meet the threshold: performing a read call by sending a read command to the external cache without referencing the local L2P mapping table in the local cache.

19. The method of request item 18, wherein the step of determining the active size includes the following steps: determining an inactive size of an inactive portion of the local L2P mapping table in the local cache.

20. The method of request 18, wherein the step of comparing the active size includes the following steps: comparing the active size with an inactive size of an inactive portion of the local L2P mapping table in the local cache.

21. The method according to request item 18 also includes the following steps: for the read command, obtaining an L2P mapping entry from the portion of the L2P mapping table in the external cache.

22. The method according to request item 18 also includes the following steps: for the read command, when the partial L2P mapping table does not have an entry for a logical address in the read command, issuing a direct call to a NAND memory element in the UFS memory.

23. The method according to request item 18 also includes the following steps: when the activity size exceeds the threshold, accessing an address in the local L2P mapping table in the local cache memory.

24. The method according to request item 18 also includes the following steps: determining whether a host performance booster is enabled.

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