Semiconductor device and fabrication method thereof

Abstract

A semiconductor device includes a substrate having a flash memory region and a logic element region; at least one logic transistor disposed in the logic element region; and at least one flash memory transistor disposed in the flash memory region, wherein the at least one flash memory transistor includes a metal select gate having two opposing sidewalls and two memory gates disposed on the two opposing sidewalls of the metal select gate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an embedded flash memory (eFlash) and a manufacturing method thereof. Prior Art

[0002] With the introduction of automotive electronic control systems, many microcontroller units (MCUs) with embedded flash memory have been installed. Embedded flash memory (eFlash) is used for control program code storage and temporary data storage, providing greater flexibility for program updates and more sophisticated control. Because automotive flash MCUs require high data processing speeds, eFlash is inevitably integrated with high-speed logic CMOS circuits.

[0003] In the eFlash manufacturing process, it is important to balance the sufficient performance of the logic CMOS transistors and the reliability of the memory cells. Summary of the Invention

[0004] The main purpose of the present invention is to provide an improved embedded flash memory device and a manufacturing method thereof to solve the deficiencies or shortcomings of the prior art.

[0005] One aspect of the present invention provides a semiconductor device comprising: a substrate having a flash memory region and a logic element region; at least one logic transistor disposed in the logic element region; and at least one flash memory transistor disposed in the flash memory region, wherein the at least one flash memory transistor comprises a metal selection gate having two opposing sidewalls and two memory gates disposed on the two opposing sidewalls of the metal selection gate.

[0006] According to an embodiment of the present invention, the at least one logic transistor includes a metal gate.

[0007] According to an embodiment of the present invention, the metal gate and the metal selection gate have the same gate structure.

[0008] According to an embodiment of the present invention, the metal gate and the metal selection gate both include a high-k gate dielectric layer and a conductive gate.

[0009] According to an embodiment of the present invention, the top surface of the metal gate is flush with and coplanar with the top surface of the metal selection gate.

[0010] According to an embodiment of the present invention, the semiconductor device further includes: two charge storage structures disposed on the two opposite side walls of the metal selection gate.

[0011] According to an embodiment of the present invention, the two charge storage structures both include oxide-nitride-oxide (ONO) storage structures.

[0012] According to an embodiment of the present invention, the two charge storage structures are in direct contact with the high-k gate dielectric layer.

[0013] According to an embodiment of the present invention, the two memory gates are polysilicon gates.

[0014] According to an embodiment of the present invention, the semiconductor element further includes: two source / drain doping regions, which are arranged in the substrate and are respectively adjacent to the two memory gates.

[0015] Another aspect of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate having a flash memory region and a logic element region; forming at least one logic transistor in the logic element region; and forming at least one flash memory transistor in the flash memory region, wherein the at least one flash memory transistor includes a metal selection gate having two opposing sidewalls and two memory gates disposed on the two opposing sidewalls of the metal selection gate.

[0016] According to an embodiment of the present invention, the at least one logic transistor includes a metal gate.

[0017] According to an embodiment of the present invention, the metal gate and the metal selection gate have the same gate structure.

[0018] According to an embodiment of the present invention, the metal gate and the metal selection gate both include a high-k gate dielectric layer and a conductive gate.

[0019] According to an embodiment of the present invention, the top surface of the metal gate is flush with and coplanar with the top surface of the metal selection gate.

[0020] According to an embodiment of the present invention, the method further includes: forming two charge storage structures disposed on the two opposite sidewalls of the metal selection gate.

[0021] According to an embodiment of the present invention, the two charge storage structures both include oxide-nitride-oxide (ONO) storage structures.

[0022] According to an embodiment of the present invention, the two charge storage structures are in direct contact with the high-k gate dielectric layer.

[0023] According to an embodiment of the present invention, the two memory gates are polysilicon gates.

[0024] According to an embodiment of the present invention, the method further includes: forming two source / drain doping regions in the substrate, respectively adjacent to the two memory gates. Simple diagram description

[0025] 1 to 6 are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Implementation Method

[0026] The following description will be made with reference to the accompanying drawings, which constitute a part of the detailed description of the specification and are provided to illustrate specific examples of the embodiments. The following embodiments are described in sufficient detail to enable a person skilled in the art to carry out the embodiments.

[0027] Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments included therein are to be defined by the appended claims.

[0028] Please refer to Figures 1 to 6, which are schematic diagrams illustrating a method for fabricating a semiconductor device 1 according to an embodiment of the present invention. As shown in Figure 1, a substrate 100, such as a silicon substrate, is provided. The substrate 100 has a flash memory region MR and a logic device region DR. A gate dielectric layer 110 and a gate material layer 120 are formed on the substrate 100. For example, the gate dielectric layer 110 may comprise silicon oxide or silicon oxynitride, but is not limited thereto. For example, the gate material layer 120 may comprise polysilicon, but is not limited thereto. Subsequently, lithography and etching processes are performed to pattern the gate dielectric layer 110 and the gate material layer 120 within the flash memory region MR to form at least one select gate SG. The select gate SG has two opposing sidewalls SW.

[0029] As shown in Figure 2, a bilaterally symmetrical charge storage structure CS and memory gate MG are formed on opposite sidewalls SW of the select gate SG within the flash memory region MR. According to an embodiment of the present invention, the charge storage structure CS may comprise an oxide-nitride-oxide (ONO) storage structure. According to an embodiment of the present invention, the charge storage structure CS extends from the opposite sidewalls SW of the select gate SG to the substrate 100, forming an L-shaped profile. According to an embodiment of the present invention, the memory gate MG may be a polysilicon gate, but is not limited thereto.

[0030] As shown in Figure 3, lithography and etching processes are then performed to pattern the gate dielectric layer 110 and gate material layer 120 within the logic device region DR, forming at least one dummy gate DP. An ion implantation process is then performed to form source / drain doped regions 101 and 102 within the substrate 100 within the logic device region DR and the flash memory region MR, respectively. The source / drain doped regions 102 are adjacent to the memory gate MG. A chemical vapor deposition (CVD) process is then performed to deposit a dielectric layer 130, such as, but not limited to, a silicon oxide layer, over the entire surface of the substrate 100. A planarization process, such as a chemical mechanical polishing process, is then performed to ensure that the top surface S1 of the dummy gate DP, the top surface S3 of the select gate SG, and the top surface S2 of the dielectric layer 130 are flush and coplanar.

[0031] Next, a replacement metal gate (RMG) process is performed. As shown in FIG4 , a photoresist pattern PR is first formed. The photoresist pattern PR has an opening OP1 and an opening OP2. The opening OP1 exposes the logic device region DR, and the opening OP2 exposes the select gate SG in the flash memory region MR.

[0032] As shown in FIG5 , an etching process is then performed to remove the dummy gate DP in the logic device region DR and the select gate SG in the flash memory region MR, forming gate trenches GT1 and GT2, respectively. Subsequently, the photoresist pattern PR is removed.

[0033] As shown in FIG6 , a metal gate LGM and a metal select gate SGM are formed in gate trenches GT1 and GT2, respectively. This forms at least one logic transistor TL in the logic device region DR and at least one flash memory transistor TM in the flash memory region MR. According to an embodiment of the present invention, in the flash memory region MR, two memory gates MG are disposed on opposite sidewalls SWM of the metal select gate SGM.

[0034] According to an embodiment of the present invention, the metal gate LGM and the metal select gate SGM have the same gate structure. According to an embodiment of the present invention, both the metal gate LGM and the metal select gate SGM include a high-k gate dielectric layer 210 and a conductive gate 220. According to an embodiment of the present invention, the high-k gate dielectric layer 210 may comprise, but is not limited to, hafnium oxide. According to an embodiment of the present invention, the conductive gate 220 may comprise tungsten, copper, aluminum, titanium, titanium nitride, or any combination thereof.

[0035] According to an embodiment of the present invention, the top surface S4 of the metal gate LGM is flush with the top surface S5 of the metal select gate SGM. According to an embodiment of the present invention, the two charge storage structures CS are in direct contact with the high-k gate dielectric layer 210.

[0036] Structurally, as shown in FIG6 , a semiconductor device 1 includes a substrate 100 having a flash memory region MR and a logic device region DR. At least one logic transistor TL is disposed within the logic device region DR, and at least one flash memory transistor TM is disposed within the flash memory region MR. The flash memory transistor TM includes a metal select gate SGM having two opposing sidewalls SWM and two memory gates MG disposed on the two opposing sidewalls SWM of the metal select gate SGM. According to an embodiment of the present invention, the memory gates MG are polysilicon gates. According to an embodiment of the present invention, the semiconductor device 1 further includes two source / drain doped regions disposed within the substrate 100, respectively adjacent to the two memory gates MG.

[0037] According to an embodiment of the present invention, a logic transistor TL includes a metal gate LGM. The metal gate LGM and the metal select gate SGM have the same gate structure. Both the metal gate LGM and the metal select gate SGM include a high-k gate dielectric layer 210 and a conductive gate 220. The top surface S4 of the metal gate LGM is flush and coplanar with the top surface S5 of the metal select gate SGM.

[0038] According to an embodiment of the present invention, two charge storage structures CS are disposed on opposite sidewalls SWM of the metal select gate SGM. Both charge storage structures CS comprise an oxide-nitride-oxide (ONO) storage structure. Both charge storage structures CS are in direct contact with the high-k gate dielectric layer 210. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0039] 1: Semiconductor components 100: Base 101: Source / drain doping region 102: Source / drain doping region 110: Gate dielectric layer 120: Gate material layer 130: dielectric layer 210: High dielectric constant gate dielectric layer 220: conductive gate CS: Charge Storage Structure DP: dummy gate DR: Logic element area GT1, GT2: Gate trench LGM: Metal Gate MG: Memory Gate MR: Flash memory area OP1, OP2: Opening PR: Photoresist pattern S1, S2, S3, S4, S5: top surface SG: Select Gate SGM: Select Gate Metal SW, SWM: side wall TL: Logic transistor TM: Flash memory transistor

Claims

1. A semiconductor device comprising: a substrate having a flash memory region and a logic element region; at least one logic transistor disposed within the logic element region; and at least one flash memory transistor disposed within the flash memory region, wherein, The at least one flash memory transistor includes: a metal select gate having two opposing sidewalls; two memory gates respectively disposed on the two opposing sidewalls of the metal select gate; and two charge storage structures respectively disposed between the two memory gates and the substrate, wherein each of the two charge storage structures has an L-shaped profile; wherein the metal select gate includes a high dielectric constant gate dielectric layer, and the high dielectric constant gate dielectric layer is in direct contact with the two charge storage structures.

2. The semiconductor element as claimed in claim 1, wherein, The at least one logic transistor includes a metal gate.

3. The semiconductor element as claimed in claim 2, wherein, The metal gate and the metal selective gate have the same gate structure.

4. The semiconductor element as claimed in claim 2, wherein, Both the metal gate and the metal selective gate include a conductive gate.

5. The semiconductor element as claimed in claim 2, wherein, The top surface of the metal gate is flush with and coplanar with the top surface of the metal selector gate.

6. The semiconductor element as claimed in claim 1, wherein, It also includes: a dielectric layer disposed on the substrate and covering the metal selective gate.

7. The semiconductor element as claimed in claim 1, wherein, Both charge storage structures contain an oxide-nitride-oxide (ONO) storage structure.

8. The semiconductor element as claimed in claim 6, wherein, Each of the two charge storage structures includes a side surface, and the dielectric layer is in direct contact with the side surface.

9. The semiconductor element as claimed in claim 1, wherein, The two memory gates are polysilicon gates.

10. The semiconductor element as claimed in claim 1, wherein, It also includes: two source / drain doped regions located in the substrate, adjacent to the two memory gates respectively.

11. A method of forming a semiconductor device, comprising: providing a substrate having a flash memory region and a logic element region; forming at least one logic transistor in the logic element region; and forming at least one flash memory transistor in the flash memory region, wherein, The at least one flash memory transistor includes: a metal select gate having two opposing sidewalls; two memory gates respectively disposed on the two opposing sidewalls of the metal select gate; and two charge storage structures respectively disposed between the two memory gates and the substrate, wherein each of the two charge storage structures has an L-shaped profile; wherein the metal select gate includes a high dielectric constant gate dielectric layer, and the high dielectric constant gate dielectric layer is in direct contact with the two charge storage structures.

12. The method as described in claim 11, wherein, The at least one logic transistor includes a metal gate.

13. The method as described in claim 12, wherein, The metal gate and the metal selective gate have the same gate structure.

14. The method as described in claim 12, wherein, Both the metal gate and the metal selective gate include a conductive gate.

15. The method as described in claim 12, wherein, The top surface of the metal gate is flush with and coplanar with the top surface of the metal selector gate.

16. The method as described in claim 11, wherein, It also includes: forming a dielectric layer disposed on the substrate and covering the metal selective gate.

17. The method as described in claim 11, wherein, Both charge storage structures contain an oxide-nitride-oxide (ONO) storage structure.

18. The method as described in claim 16, wherein, Each of the two charge storage structures includes a side surface, and the dielectric layer is in direct contact with the side surface.

19. The method as described in claim 11, wherein, The two memory gates are polysilicon gates.

20. The method as described in claim 11, wherein, It also includes: forming two source / drain doped regions in the substrate, which are adjacent to the two memory gates respectively.

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