Layout pattern of static random access memory and its forming method

Abstract

This invention provides a layout pattern for a static random access memory (SRAM), comprising at least a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate. The plurality of transistors includes: two pull-up transistors (PU), two pull-down transistors (PD) forming a latch circuit, and two access transistors (PG) connected to the latch circuit. In any SRAM memory cell, the fin structure included by the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included by the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included by the access transistor (PG) is defined as a PG fin structure. The width of the PD fin structure is wider than the width of the PG fin structure.

Description

Technical Field

[0001] The present invention relates to a static random access memory (SRAM), and more particularly to a layout pattern of a static random access memory (SRAM) with higher performance and a method for forming the same. Prior Art

[0002] An embedded static random access memory (SRAM) consists of logic circuits and SRAM connected to them. SRAM itself is a volatile memory cell, meaning that the stored data is erased when the power to the SRAM is removed. SRAM stores data by utilizing the conductive state of transistors within the memory cell. Based on mutually coupled transistors, SRAM avoids the problem of capacitor discharge and requires no constant charging to maintain data. This differs from dynamic random access memory (DRAM), which is also a volatile memory and uses the charged state of capacitors to store data. SRAM has a very fast access speed, making it suitable for use as cache memory in computer systems. Summary of the Invention

[0003] The present invention provides a layout pattern for a static random access memory (SRAM), comprising at least a substrate with a plurality of SRAM memory cells arranged on the substrate, wherein each SRAM memory cell comprises: a plurality of fin structures located on the substrate; a plurality of gate structures located on the substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor comprises a portion of the gate structure spanning a portion of the fin structure; the plurality of transistors comprises: two pull-up transistors (PU), two pull-down transistors (PD), which together form a latch circuit (latch), and two access transistors (PG) connected to the latch circuit. In any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

[0004] The present invention further provides a method for forming a layout pattern of a static random access memory (SRAM), comprising at least: providing a substrate, forming a plurality of SRAM memory cells arranged on the substrate, wherein each SRAM memory cell comprises: a plurality of fin structures located on the substrate, a plurality of gate structures located on the substrate and spanning the plurality of fin structures, thereby forming a plurality of transistors distributed on the substrate, wherein each transistor comprises a portion of the gate structure spanning a portion of the fin structure, and the plurality of transistors comprises: two pull-up transistors (PU), two pull-down transistors (PD), which together form a latch circuit, and two access transistors (PG) connected to the latch circuit. In any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

[0005] The present invention is characterized by the need to increase the ratio of the on-current of the PD transistor to the on-current of the PG transistor to improve device quality. However, the width of the fin structure formed by sidewall pattern transfer cannot be adjusted solely by the mask pattern. The present invention employs the addition of dummy fin structures to achieve this goal. Furthermore, the specially shaped axis pattern formed in the present invention creates a larger number of dummy fin structures around the PG fin structure, while eliminating dummy fin structures around the PD fin structure. Consequently, after the etching step, the PG fin structure experiences more reflective etching, reducing its width. This achieves the goal of improving the SRAM beta value and static noise margin. Simple diagram description

[0006] FIG. 1 is a circuit diagram of a six-device SRAM (6T-SRAM) memory cell in the SRAM of the present invention. FIG. 2 is a layout diagram of a static random access memory according to a first preferred embodiment of the present invention. FIG3 is a schematic cross-sectional view taken along the section line AA′ in FIG2 , emphasizing the fin structure and the dummy fin structure. 4 to 8 are schematic diagrams illustrating the formation of a fin-shaped structure according to the present invention. Implementation Method

[0007] In order to enable those skilled in the art to further understand the present invention, the following lists preferred embodiments of the present invention and describes in detail the components and intended effects of the present invention in conjunction with the accompanying drawings.

[0008] For ease of explanation, the various figures of the present invention are merely illustrative to facilitate understanding of the present invention. The detailed proportions may be adjusted based on design requirements. Those skilled in the art will readily understand that the upper and lower relationships between components depicted in the figures refer to the relative positions of the objects. Therefore, the figures can be reversed to present the same components, and this is fully within the scope of this specification. This is further clarified.

[0009] FIG1 is a circuit diagram of a six-device SRAM (6T-SRAM) memory cell in the static random access memory (SRAM) of the present invention. Referring to FIG1 , in this embodiment, each 6T-SRAM memory cell 10 preferably comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1, and a second access transistor PG2 forming a flip-flop. The first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the second pull-down transistor PD2 form a latch circuit 22, enabling data to be latched in either storage node N1 or N2. Furthermore, the first pull-up transistor PU1 and the second pull-up transistor PU2 serve as active loads. They can also be replaced by conventional resistors as pull-up transistors. In this case, a four-device SRAM (4T-SRAM) is formed. Furthermore, in this embodiment, one source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and one source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0010] In one embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the 6T-SRAM memory cell 10 are formed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, and the first access transistor PG1, the second access transistor PG2 are formed of N-type metal oxide semiconductor (NMOS) transistors, but the present invention is not limited thereto. The first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and the two terminals of the series circuit formed by the first pull-up transistor PU1 and the first pull-down transistor PD1 are respectively coupled to a voltage source Vcc and a voltage source Vss. Similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter, and the two terminals of the series circuit formed by the second pull-up transistor PU2 and the second pull-down transistor PD2 are also respectively coupled to the voltage source Vcc and the voltage source Vss. The two inverters are coupled to each other to store data.

[0011] Furthermore, the storage node N1 is electrically connected to the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2, and the drains of the first pull-down transistor PD1, the first pull-up transistor PU1, and the first access transistor PG1. Similarly, the storage node N2 is electrically connected to the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1, and the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, and the second access transistor PG2. The gates of the first access transistor PG1 and the second access transistor PG2 are respectively coupled to the word line WL, while the sources of the first access transistor PG1 and the second access transistor PG2 are respectively coupled to the corresponding bit lines BL1 and BL2.

[0012] FIG2 is a layout diagram of a static random access memory (SRAM) according to a first preferred embodiment of the present invention. In this embodiment, as shown in FIG2 , a 6T-SRAM memory cell 10 is disposed on a substrate S, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate S can be a planar structure or can be provided with a plurality of fin structures F and a plurality of gate structures G disposed thereon. Other embodiments of the present invention can also be applied to planar SRAMs, meaning that the fin structures do not need to be formed on the substrate, but rather doped regions are formed within the substrate, which also falls within the scope of the present invention.

[0013] The layout diagram in Figure 2 also includes multiple metal layers. The metal layer connecting the gates of each transistor is defined as M0PY, while the metal layer connecting the source / drain of each transistor is defined as M0CT. In Figure 2, metal layers M0PY and M0CT are represented by different meshes. However, the difference between metal layers M0PY and M0CT lies in the components they connect to. Both are metal layers and can, but are not limited to, the same material. Figure 2 also includes multiple vias (V0), which connect metal layers M0PY and M0CT to other conductive layers (such as M1, V1, and M2, commonly found in semiconductor manufacturing processes) that will be formed later.

[0014] The layout pattern of the present invention takes a three-dimensional SRAM as an example (i.e., forming a fin structure F instead of a planar doped region). As shown in Figure 2, except for the locations where the fin structure F, gate structure G, connection structure M0PY, connection structure M0CT, and contact V0 are formed on the substrate S, the rest of the substrate S is covered with an insulating layer, such as a shallow trench isolation (STI), to isolate the various electronic components (such as transistors) and prevent short circuits. In addition, each gate structure G spans across a portion of the fin structure F to form transistors (such as the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2). For clarity, the locations of the aforementioned transistors are directly marked in Figure 2, particularly at the intersection of the gate structure G and the fin structure F.

[0015] As shown in FIG. 2 , for ease of explanation, the fin structures F spanned by the gate structure G in different transistors of the 6T-SRAM memory cell 10 are designated by different names. The fin structures F spanned by the gate structure G in the first pull-up transistor PU1 and the second pull-up transistor PU2 are designated as the PU fin structure (PU-F), the fin structures F spanned by the gate structure G in the first pull-down transistor PD1 and the second pull-down transistor PD2 are designated as the PD fin structure (PD-F), and the fin structures F spanned by the gate structure G in the first access transistor PG1 and the second access transistor PG2 are designated as the PG fin structure (PG-F). It is worth noting that the PD fin structure (PD-F) and the PG fin structure (PG-F) may be different parts of the same fin structure; that is, a portion of a fin structure F is designated as the PD fin structure (PD-F) while another portion is designated as the PG fin structure (PG-F).

[0016] One of the objectives of the present invention is to improve the static noise margin (SNM) of an SRAM. The static noise margin is related to the SRAM's beta ratio. The beta ratio is equal to the ratio of the on-state current of transistor PD to the on-state current of transistor PG. In other words, increasing the on-state current of transistor PD or decreasing the on-state current of transistor PG can achieve both the beta ratio and the static noise margin.

[0017] According to the following transistor equation (1), the current passing through the transistor is proportional to the channel width W. When the gate structure G spans the fin structure F, the transistor's channel width W is related to the width of the fin structure F. In other words, if the gate structure F is wider, the current passing through the transistor increases. Conversely, if the gate structure F is smaller, the current passing through the transistor decreases.

[0018] I=μ nC oxW / L[(V GS-V th)V DS-V 2 DS / 2]----------------------Equation 1

[0019] in:

[0020] I is the current value passing through the transistor;

[0021] W is the gate width (channel width) of the transistor;

[0022] L is the gate length (channel length) of the transistor;

[0023] μn is carrier mobility;

[0024] C ox is the unit capacitance of the gate oxide layer;

[0025] VGS is the gate-to-source voltage;

[0026] VDS is the voltage from drain to source;

[0027] Vth is the threshold voltage.

[0028] As mentioned above, increasing the width of the PD-fin structure (PD-F) or reducing the width of the PG-fin structure (PG-F) can achieve the goal of increasing the beta value. However, with advances in manufacturing processes, most current fin structures are formed using sidewall image transfer (SIT). Therefore, it is impossible to directly control the fin width by changing the mask pattern. Other methods are required to achieve the goal of changing the fin width.

[0029] Generally speaking, when patterning fin structures, in order to improve the overall uniformity of the device pattern and avoid errors caused by large variations in pattern density, in addition to the normal fin structures F, dummy fin structures (DF) are formed adjacent to the fin structures F. These dummy fin structures are not actually connected to other electronic components. The applicant has discovered that the arrangement and density of the dummy fin structures DF affect the width of the resulting fin structure F. More specifically, the applicant has discovered that if a fin structure F is surrounded by numerous dummy fin structures DF, the etching step to remove or reduce the dummy fin structures DF (such as, but not limited to, dry etching such as reactive ion etching) may result in more reflections, thereby reducing the width of the fin structure F. Conversely, if a fin structure F is not surrounded by dummy fin structures DF, the etching reduction is reduced, allowing the fin structure F to retain its original width. In other words, the width of the fin structure F (including the PU fin structure (PU-F), PD fin structure (PD-F), and PG fin structure (PG-F)) can be controlled by adjusting the arrangement position of the dummy fin structure DF.

[0030] Therefore, the present invention achieves the goal of controlling the widths of the PU fin structure (PU-F), PD fin structure (PD-F), and PG fin structure (PG-F) by adding and adjusting the position of a dummy fin structure DF. Figure 3 is a schematic cross-sectional view of the fin structure and the dummy fin structure, taken along the section line AA' in Figure 2. To simplify the illustration, Figure 3 focuses on the distribution of the fin structure, while other components, such as the gate structure G, contact structure M0PY, and contact structure M0CT, are omitted. Referring to Figure 3, the present invention is characterized in that the width of the PD fin structure (PD-F) is greater than the width of the PG fin structure (PG-F). In other words, the width of the PD fin structure (PD-F) is defined as W1, and the width of the PG fin structure (PG-F) is defined as W2, where W1>W2. Furthermore, the width of the PD fin structure (PD-F) is also greater than that of the PU fin structure (PU-F), but this is not limited to this. In addition to the aforementioned PU fin structure (PU-F), PD fin structure (PD-F), and PG fin structure (PG-F), the substrate S also includes multiple dummy fin structures (DF). The height and width of the dummy fin structures DF are smaller than those of the other fin structures F.

[0031] In this embodiment, the dummy fin structures DF are located between the PD-F and the adjacent PU-F, between the PU-F and the adjacent PU-F, between the PU-F and the adjacent PG-F, and between the PG-F and the adjacent PG-F, but not between the PD-F and the adjacent PD-F. As described above, the PD-F is not surrounded by densely packed dummy fin structures DF, so its width is not reduced during etching. In contrast, the widths of the other PU-F and PG-F structures are reduced during etching because they are surrounded by a larger number of dummy fin structures. Furthermore, during the etching process, the dummy fin structure DF may simply be reduced in size (as shown in FIG. 3 ), or in other embodiments, may be completely removed (thus excluding the dummy fin structure in the cross-sectional view), all of which fall within the scope of the present invention. It is worth noting that due to the smaller size of the dummy fin structure DF in FIG. 3 , it is not depicted in FIG. 2 .

[0032] Figures 4 through 8 illustrate the formation of the fin structure according to the present invention. Note that in Figures 4 through 8, the planned locations of the gate structure G, which will be formed later, are also indicated to facilitate understanding of the positions of the transistors. However, during the formation of the fin structure F, the gate structure G is not actually formed yet, as explained here. Furthermore, the locations of portions of the PU fin structure (PU-F), PD fin structure (PD-F), and PG fin structure (PG-F) are also indicated to facilitate comparison with the transistor locations.

[0033] First, as shown in Figure 4, multiple core patterns 30 are formed on a substrate. Next, sidewall patterns 32 are formed adjacent to the core patterns 30 by deposition and etching back. The formed sidewall patterns 32 are located near the boundaries of the core patterns 30. It is worth noting that while most core patterns 30 are linear, some are block-shaped and contain holes OP. The sidewall patterns 30 are located near the boundaries surrounding the core patterns 30 and within the holes OP. In this embodiment, the core patterns 30 may be made of, but are not limited to, insulating materials such as silicon oxide and silicon nitride. The sidewall patterns 32 may be made of, for example, silicon, and may subsequently serve as fin structures F.

[0034] As shown in FIG5 , the core pattern 30 is then removed by an etching step, leaving behind sidewall patterns 32. A portion of the remaining sidewall pattern 32 will subsequently serve as the fin structure F, while another portion will be reduced or removed as the dummy fin structure DF. Most sidewall patterns 32 are strip-shaped, while a few are square-shaped. These square-shaped sidewall patterns 32 increase the density of the dummy fin structure DF, thereby reducing the width of the surrounding fin structures F during the subsequent etching process. Notably, by designing the shape of the core pattern 30 in FIG4 , the square-shaped sidewall patterns 32 are located only between a PG fin structure (PG-F) and an adjacent PG fin structure (PG-F) (e.g., area A or area C in FIG5 ), but not between a PD fin structure (PD-F) and an adjacent PD fin structure (PD-F) (e.g., area B or area D in FIG5 ). Therefore, by designing the axis pattern 30 , more dummy fin structures DF can be included around the PG fin structure (PG-F), while no dummy fin structure DF can be included around the PD fin structure (PD-F).

[0035] As shown in FIG6 , an etching step is then performed to remove or reduce the unnecessary sidewall patterns 32 (i.e., the dummy fin structures DF). In FIG6 , a mask 34 indicates the area where the sidewall patterns 32 are to be removed or reduced. In other words, the sidewall patterns 32 (dummy fin structures DF) in the area covered by mask 34 will be reduced or removed. As described above, during this etching step, the PG fin structure (PG-F) or PU fin structure (PU-F) is surrounded by more dummy fin structures DF, resulting in a greater reduction in the width of the PG fin structure (PG-F) or PU fin structure (PU-F). Conversely, the PD fin structure (PD-F) is not surrounded by dummy fin structures DF, allowing the PD fin structure (PD-F) to maintain its original width.

[0036] As shown in FIG7 , another mask 36 is used to partially cut off the remaining sidewall pattern 32 (i.e., the fin structure F). In FIG7 , the sidewall pattern 32 (i.e., the fin structure F) in the area covered by mask 36 is removed. Finally, as shown in FIG8 , the remaining sidewall pattern 32 becomes the fin structure F, upon which other components, such as gate structures, metal layers, and contact structures, will be subsequently formed. The resulting SRAM memory cell is similar to that shown in FIG2 and will not be repeated here.

[0037] As can be seen from Figures 4 through 8 above, by forming a specially shaped core pattern 30 in this embodiment, a frame-like sidewall pattern 32 is formed adjacent to the PG-F structure (PG-F) but not adjacent to the PD-F structure (PD-F). Consequently, after the etching step shown in Figure 6, the PG-F structure (PG-F) is partially etched, resulting in a reduction in width, while the PD-F structure (PD-F) retains approximately its original width. Consequently, after the subsequent SRAM memory cell is completed, the current of the PG transistor can be reduced, thereby improving the beta value and static noise margin.

[0038] In summary, the present invention provides a layout pattern of a static random access memory (SRAM), comprising at least: a substrate S, a plurality of SRAM memory cells 10 arranged on the substrate S, wherein each of the SRAM memory cells 10 comprises a plurality of fin structures F located on the substrate S, a plurality of gate structures G located on the substrate S and spanning the plurality of fin structures F, thereby forming a plurality of transistors distributed on the substrate, wherein each transistor comprises a portion of the gate structure G spanning a portion of the fin structure F, and the plurality of transistors comprises: two pull-up transistors (PU1, PU2), two pull-down transistors (PD1, PD2), and a plurality of pull-up transistors (PU1, PU2). 1, PD2), together forming a latch circuit, and two access transistors (PG1, PG2) connected to the latch circuit, wherein in any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure PU-F, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure PD-F, and the fin structure included in the access transistor (PG) is defined as a PG fin structure PG-F, wherein a width W1 of the PD fin structure PD-F is wider than a width W2 of the PG fin structure PG-F (please also refer to FIG. 3).

[0039] In some embodiments of the present invention, it further includes forming a plurality of dummy fin structures DF located on a substrate, wherein the dummy fin structure DF is located between the PD fin structure PD-F and the adjacent PU fin structure PU-F, or between the PU fin structure PU-F and the adjacent PU fin structure PU-F, or between the PU fin structure PU-F and the adjacent PG fin structure PG-F, or between the PG fin structure PG-F and the adjacent PG fin structure PG-F.

[0040] In some embodiments of the present invention, the dummy fin structure DF is not located between the PD fin structure PD-F and an adjacent PD fin structure PD-F.

[0041] In some embodiments of the present invention, a height and a width of the dummy fin structure DF are smaller than a height and a width of the PG fin structure PG-F- (see FIG. 3 ).

[0042] In some embodiments of the present invention, a shortest distance between a PG fin structure PG-F and another adjacent PG fin structure PG-F is greater than a shortest distance between the PG fin structure PG-F and any dummy fin structure DF.

[0043] In some embodiments of the present invention, a dummy fin structure is included between the PU fin structure PU-F and another adjacent PU fin structure PU-F, and a dummy fin structure is also included between the PU fin structure PU-F and another adjacent PG fin structure PG-F.

[0044] In some embodiments of the present invention, two dummy fin structures are included between a PG fin structure PG-F and another adjacent PG fin structure PG-F.

[0045] In some embodiments of the present invention, in any SRAM memory cell, the PG fin structure PG-F and the PD fin structure PD-F are connected and arranged along the same direction (i.e., the PG fin structure PG-F and the PD fin structure PD-F are different parts of a fin structure F).

[0046] The present invention further provides a method for forming a layout pattern of a static random access memory (SRAM), comprising at least providing a substrate S, forming a plurality of SRAM memory cells 10 arranged on the substrate S, wherein each SRAM memory cell 10 includes a plurality of fin structures F located on the substrate S, a plurality of gate structures G located on the substrate S and spanning the plurality of fin structures F, thereby forming a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure G spanning a portion of the fin structure F, and the plurality of transistors include: two pull-up transistors (PU1, PU2), two pull-down transistors (PD1, PD2), and a plurality of pull-up transistors (PU1, PU2). , PD2), together forming a latch circuit, and two access transistors (PG1, PG2) connected to the latch circuit, wherein in any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure PU-F, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure PD-F, and the fin structure included in the access transistor (PG) is defined as a PG fin structure PG-F, wherein a width W1 of the PD fin structure PD-F is wider than a width W2 of the PG fin structure PG-F (please also refer to Figure 3).

[0047] In some embodiments of the present invention, the method of forming the dummy fin structure DF further includes forming a plurality of axis patterns 30 on a substrate S, forming a plurality of sidewall patterns 32 surrounding each axis pattern 30, removing each axis pattern 30 to leave each sidewall pattern 32, and performing an etching step to reduce the size of each sidewall pattern 32, wherein the reduced sidewall patterns 32 are the dummy fin structures DF.

[0048] In some embodiments of the present invention, after forming each sidewall pattern, at least one frame-shaped sidewall pattern 32 is located between the PG fin structure PG-F and the adjacent PG fin structure PG-F (see FIG. 5 ).

[0049] In some embodiments of the present invention, the frame-shaped sidewall pattern 32 is not located between the PD fin structure PD-F and an adjacent PD fin structure PD-F (see FIG. 5 ).

[0050] In summary, the present invention is characterized by the need to increase the ratio of the on-current of the PD transistor to the on-current of the PG transistor in order to improve device quality. However, the width of the fin structure formed by sidewall pattern transfer cannot be adjusted solely by the mask pattern. The present invention uses a method of adding dummy fin structures to achieve the goal of controlling the width of the fin structure. Furthermore, the present invention forms a specially shaped axis pattern, resulting in a larger number of dummy fin structures around the PG fin structure, while no dummy fin structures are around the PD fin structure. Therefore, after the etching step, the PG fin structure will be subjected to more reflective etching, reducing its width, thereby achieving the purpose of improving the beta value and static noise margin of the SRAM. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0051] 10:6T-SRAM memory cell 22: Latch circuit 30: Axis pattern 32: Sidewall pattern 34: Mask (etching area) 36: Mask (etching area) S: base F: Fin structure G: Gate structure M0PY: Connecting Structures M0CT: connection structure STI: Insulation layer V0: Contact PU1: First pull-up transistor PU2: Second pull-up transistor PD1: First pull-down transistor PD2: Second pull-down transistor PG1: First access transistor PG2: Second access transistor BL1: First bit line BL2: Second bit line WL: bit line Vcc: voltage source Vss: voltage source PU-F: PU fin structure PD-F: PD fin structure PG-F:PG fin structure DF: dummy fin structure A: Area B: Area C: Area D: Area OP: Hole W1: width W2: width

Claims

1. A layout pattern of static random access memory (SRAM), comprising at least: a substrate; a plurality of SRAM memory cells arranged on the substrate, wherein each SRAM memory cell includes: a plurality of fin structures located on the substrate; a plurality of gate structures located on the substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structures, the plurality of transistors including: two pull-up transistors (PU), two pull-down transistors (PD) forming a latch circuit, and two access transistors (PG) connected to the latch circuit; In any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein the width of the PD fin structure is wider than the width of the PG fin structure; and a plurality of dummy fin structures are located on the substrate, the dummy fin structures are located between the PU fin structure and an adjacent PU fin structure, between the PU fin structure and an adjacent PG fin structure, and between the PG fin structure and an adjacent PG fin structure, the dummy fin structures are not located between the PD fin structure and an adjacent PD fin structure, wherein there are two dummy fin structures between the PG fin structure and another adjacent PG fin structure.

2. The layout pattern of the static random access memory (SRAM) as described in claim 1, wherein the height and width of the dummy fin structure are smaller than the height and width of the PG fin structure.

3. The layout pattern of the static random access memory (SRAM) as described in claim 1, wherein a shortest distance between the PG fin structure and another adjacent PG fin structure is greater than a shortest distance between the PG fin structure and any dummy fin structure.

4. The layout pattern of the static random access memory (SRAM) as described in claim 1, wherein the PU fin structure includes a dummy fin structure between the PU fin structure and another adjacent PU fin structure, and the PU fin structure also includes a dummy fin structure between the PU fin structure and another adjacent PG fin structure.

5. The layout pattern of a static random access memory (SRAM) as described in claim 1, wherein in any SRAM memory cell, the PG fin structure is connected to the PD fin structure and arranged in the same direction.

6. A method for forming a layout pattern of static random access memory (SRAM), comprising at least: providing a substrate; forming a plurality of SRAM memory cells arranged on the substrate, wherein each SRAM memory cell includes: a plurality of fin structures located on the substrate; a plurality of gate structures located on the substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structures, the plurality of transistors including: two pull-up transistors (PU), two pull-down transistors (PD) forming a latch circuit, and two access transistors (PG) connected to the latch circuit; In any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein the width of the PD fin structure is wider than the width of the PG fin structure; and a plurality of dummy fin structures are formed on the substrate, the dummy fin structures being located between the PU fin structure and an adjacent PU fin structure, between the PU fin structure and an adjacent PG fin structure, and between the PG fin structure and an adjacent PG fin structure, the dummy fin structures not being located between the PD fin structure and an adjacent PD fin structure, wherein there are two dummy fin structures between the PG fin structure and another adjacent PG fin structure.

7. A method for forming a layout pattern of a static random access memory (SRAM) as described in claim 6, wherein a height and a width of the dummy fin structure are smaller than the height and a width of the PG fin structure.

8. A method for forming a layout pattern of static random access memory (SRAM) as described in claim 6, wherein a shortest distance between the PG fin structure and another adjacent PG fin structure is greater than a shortest distance between the PG fin structure and any dummy fin structure.

9. A method for forming a layout pattern of static random access memory (SRAM) as described in claim 6, wherein the PU fin structure includes a dummy fin structure between the PU fin structure and another adjacent PU fin structure, and the PU fin structure also includes a dummy fin structure between the PU fin structure and another adjacent PG fin structure.

10. A method for forming a layout pattern of static random access memory (SRAM) as described in claim 6, wherein the method for forming the dummy fin structure further comprises: forming a plurality of axial patterns on the substrate; forming a plurality of sidewall patterns surrounding each of the axial patterns; removing each of the axial patterns, leaving each of the sidewall patterns; and performing an etching step to reduce the size of each of the sidewall patterns, wherein the reduced sidewall patterns are the dummy fin structures.

11. A method for forming a layout pattern of a static random access memory (SRAM) as described in claim 10, wherein after forming each of the sidewall patterns, at least one frame-shaped sidewall pattern is located between the PG fin structure and the adjacent PG fin structure.

12. A method for forming a layout pattern of a static random access memory (SRAM) as described in claim 11, wherein the square sidewall pattern is not located between the PD fin structure and the adjacent PD fin structure.

13. A method for forming a layout pattern of a static random access memory (SRAM) as described in claim 6, wherein in any SRAM memory cell, the PG fin structure is connected to the PD fin structure and arranged in the same direction.

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