Low-power multi-antenna synchronization

Abstract

This discloses a system and method for low-power multi-antenna synchronization. In one embodiment, a computing device, such as an Internet of Things (IoT) computing device, may include a transceiver operating using BLUETOOTH Low Power (BLE) with multiple antennas. In an exemplary embodiment, each of the plurality of antennas is coupled to a respective edge detection circuit. When one of the edge detection circuits detects an input signal, the circuitry associated with the other of the plurality of antennas may be placed in a low-power mode, while the circuitry associated with the detecting edge detection circuit attempts to synchronize with the input signal to determine whether the input signal is a signal of interest.

Description

Technical Field

[0001] The technology of this invention is generally related to diversity antennas in low-power environments. Prior Technology

[0002] Computing devices are ubiquitous in modern society, especially mobile communication devices, which have become increasingly prevalent. This widespread use is partly due to the numerous functions these devices offer. The increased processing power means that mobile communication devices have evolved from simple communication tools into sophisticated mobile multimedia hubs, thus enhancing the user experience. With the proliferation of functions available to these devices, the pressure to reduce power consumption has also increased. This pressure is particularly pronounced in the category of computing devices known as the Internet of Things (IoT), which are typically small, wearable devices with relatively short operating ranges and powered by button batteries.

[0003] Due to battery size constraints, power saving is a commercially viable necessity. Historically, IEEE 802.15.4 (Zigbee) has been used in IoT devices. When Zigbee was used in devices with multiple antennas, the long synchronization word used by Zigbee allowed a single RF front-end (RFFE) to be used for all antennas in the configuration at a time. More details on this approach can be found in U.S. Patent No. 5,831,981. There is a trend towards Bluetooth Low Energy (BLE) in the industry. To succeed in smart home environments, BLE RF designs must be low-power and provide sufficient range throughout the home, even where line of sight may be limited. Current designs increase range by using lower data rates, such as 125 kbps and 500 kbps in the coded physical layer (PHY) mode. These modes require longer packet sizes and higher duty cycles, which in turn increases power consumption. This design allows IoT devices, especially those using BLE, greater flexibility in designing energy-efficient solutions. Summary of the Invention

[0004] The detailed description discloses systems and methods for low-power multi-antenna synchronization. Specifically, a computing device, such as an Internet of Things (IoT) computing device, may include a transceiver operating using BLUETOOTH Low Power (BLE) with multiple antennas. In one exemplary embodiment, each of the plurality of antennas is coupled to a respective edge detection circuit. When one of the edge detection circuits detects an input signal, circuitry associated with the others of the plurality of antennas may be placed in a low-power mode, while simultaneously, the circuitry associated with the detecting edge detection circuit attempts to synchronize with the input signal to determine if the input signal is a signal of interest. Power saving is achieved by placing portions of the circuitry in low-power or sleep modes.

[0005] In this regard, one embodiment discloses a receiver. The receiver includes a Received Signal Strength Indicator (RSSI) circuit configured to receive a signal from an antenna. The receiver also includes an edge detection circuit coupled to the RSSI circuit and configured to detect a new input signal relative to an existing environment. The receiver also includes a synchronization circuit configured to synchronize with the signal from the antenna using a correlation algorithm. The receiver also includes a control circuit configured to disable the synchronization circuit. The control circuit is also configured to enable the synchronization circuit in response to the edge detection circuit's detection of the new input signal.

[0006] In another embodiment, a method for controlling a receiver is disclosed. The method includes disabling a synchronization circuit. The method also includes detecting an input signal using an edge detection circuit. The method further includes turning on the synchronization circuit in response to the detection of the input signal. Simple Explanation of the Diagram

[0007] [Figure 1] is a block diagram of an exemplary multi-antenna system that uses edge detection to perform antenna selection; [Figure 2] is a flowchart illustrating an example procedure for operating the antenna system of Figure 1; [Figure 3] is a block diagram of an exemplary edge detection circuit used in the antenna system of Figure 1; [Figure 4] is a block diagram of an exemplary multi-antenna system with parallel synchronization blocks; and [Figure 5] is a block diagram of an exemplary single-antenna system that can use the edge detection of the present invention to save power. Implementation

[0008] The embodiments described below demonstrate the necessary information for those skilled in the art to implement the embodiments and illustrate the best mode of implementation. In view of the accompanying drawings, those skilled in the art will understand the concepts disclosed herein and recognize their application upon reading the following description, even if not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of this invention and the appended claims.

[0009] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, such elements should not be limited by such terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope disclosed herein. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0010] It should be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another component, the component may be directly located on or directly extended onto the other component, or an intervening component may be present. Conversely, when a component is referred to as being "directly on" or "directly extended" to another component, no intervening component is present. Similarly, when a component, such as a layer, region, or substrate, is referred to as being "above" or extending "above" another component, the component may be directly above or directly extended over the other component, or an intervening component may be present. In contrast, when a component is referred to as being "directly" above or "directly" extending "above" another component, no intervening component is present. It should also be understood that when a component is referred to as being "connected" or "coupled" to another component, the component may be directly connected or coupled to the other component, or an intervening component may be present. In contrast, when a component is referred to as being "directly connected" or "directly coupled" to another component, no intervening component is present.

[0011] Relative terms such as “below,” “above,” “over,” “below,” “horizontal,” or “vertical” are used herein to describe the relationship of one element, layer, or region to another element, layer, or region shown in the figures. It should be understood that these terms, and the terms mentioned above, are intended to cover different orientations of the device in addition to those shown in the figures.

[0012] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "the" are intended to include the plural forms as well. It will be further understood that, when used herein, the terms "comprising" and / or "including" specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or groups thereof.

[0013] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that the terms used herein shall be interpreted as having the same meaning as in the context of this specification and related art, and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0014] The detailed description discloses systems and methods for low-power multi-antenna synchronization. Specifically, a computing device, such as an Internet of Things (IoT) computing device, may include a transceiver operating using BLUETOOTH Low Power (BLE) with multiple antennas. In one exemplary embodiment, each of the plurality of antennas is coupled to a respective edge detection circuit. When one of the edge detection circuits detects an input signal, circuitry associated with the others of the plurality of antennas may be placed in a low-power mode, while simultaneously, the circuitry associated with the detecting edge detection circuit attempts to synchronize with the input signal to determine if the input signal is a signal of interest. Power saving is achieved by placing portions of the circuitry in low-power or sleep modes.

[0015] As mentioned above, BLE in IoT devices has evolved. An alternative to using the lower data rates associated with BLE to extend range is to utilize spatial diversity using a multi-antenna system. A low-power approach to implementing this multi-antenna system borrows the teachings of a '981 patent, where a single radio frequency front-end (RFFE) uses time-division multiplexing to switch between antennas. Data collected from each antenna is analyzed to select the optimal antenna for signal reception. This approach is suitable for applications involving angle of arrival, where a long tone is appended to the end of a packet and the antennas are switched during that tone, thus allowing phase measurements to be performed on each antenna. In other applications where such a tone is absent, BLE has a relatively short, non-repeating synchronization word, making synchronization using a time-division multiplexing antenna method difficult due to the need to account for steady-state transients whenever antenna switching occurs. Furthermore, this approach does not allow for antenna combination techniques to maximize system range.

[0016] In most diversity systems, each antenna may have some form of correlation-based synchronization circuitry that provides information about the signals received at its respective antenna. Based on this information, an antenna can be selected or a signal combination can be made. This correlation circuitry consumes power. For this system, more antennas mean more correlation circuitry, and therefore higher power consumption.

[0017] The exemplary embodiments of the present invention provide systems and methods that help reduce power consumption in multi-antenna systems (such as an IoT system using BLE). Specifically, the exemplary embodiments of the present invention keep the associated circuitry in a low-power mode until a signal of interest is detected. The antenna with the most interesting signal is selected, and this signal of interest is provided to the newly awakened associated circuitry. By delaying the activation of the associated circuitry, power consumption can be reduced.

[0018] In this regard, Figure 1 is a block diagram of a receiver 100 having antennas 102(1)-102(2). Although the entire description contained herein focuses primarily on dual-antenna systems, it should be understood that the teachings of the present invention are applicable to systems having more than two antennas. These antennas 102(1)-102(2) may be coupled to respective analog-to-digital converters (ADCs) 104(1)-104(2). In an exemplary embodiment, these ADCs 104(1)-104(2) may process the in-phase (I) and quadrature (Q) portions of these signals. Immediately before or after these ADCs 104(1)-104(2), other digital signal processing (DSP) blocks (e.g., a channel selection filter) may be provided to adjust the signal used for detection, such as those illustrated in DSPs 106A(1), 106B(1), 106A(2), and 106B(2). Following these ADCs 104(1)-104(2) (and possibly following these DSPs 106B(1)-106B(2)), there are respective nodes 108(1)-108(2).

[0019] The signals from the antennas 102(1)-102(2) are separated at their respective nodes 108(1)-108(2). The first portion of each signal is provided to buffers 110(1)-110(2). The buffers 110(1)-110(2) are large (or long) enough to accommodate the expected delay of the edge detection circuits 120(1)-120(2) (described below) so that data arriving just before the edge detection can be used for synchronization. The buffers 110(1)-110(2) are coupled to a multiplexer (MUX) 112. The MUX 112 is coupled to a synchronization circuit 114. The synchronization circuit 114 may be coupled to and controlled by a control circuit 116. The synchronization circuit 114 draws data from one or more of the buffers 110(1)-110(2) and uses this data to determine whether the signal of interest is an actual signal to be received. The control circuit 116 may also be coupled to and control the MUX 112. In one exemplary embodiment, the synchronization circuit 114 may conform to the teachings of U.S. Patent No. 10,667,102, the entire contents of which are incorporated herein by reference.

[0020] The second portion of each of these signals is provided from the nodes 108(1)-108(2) to the respective Received Signal Strength Indicator (RSSI) circuits 118(1)-118(2). The respective RSSI circuits 118(1)-118(2) are coupled to the respective edge detection circuits 120(1)-120(2). The edge detection circuits 120(1)-120(2) are coupled to an antenna selection circuit 122. Although shown as a different circuit in FIG1, the antenna selection circuit 122 may be part of the control circuit 116.

[0021] Figure 2 provides a flowchart of a procedure 200 for the receiver 100 in use. The procedure 200 begins with the synchronization circuit 114 being turned off or placed in a low-power mode (block 202). Similarly, the MUX 112 can also be turned off or placed in a low-power mode (block 204). In other words, both antenna paths can be activated, but the synchronization hardware is turned off. Electromagnetic waves and noise may impact the antennas 102(1)-102(2) and generate a current therein (block 206), which can be regulated by the DSPs 106(1)-106(2) and converted into a digital signal by the respective ADCs 104(1)-104(2) (block 208). This digital signal is stored in the buffers 110(1)-110(2) (block 210).

[0022] These digital signals are also processed by the RSSI circuits 118(1)-118(2), and the output is provided to the edge detection circuits 120(1)-120(2) to search for burst signal energy indicators of a potentially interesting signal relative to an existing environment (e.g., background noise, known received uninteresting signals (e.g., out of bandwidth) or the like) (block 212). As better explained with reference to Figure 3 below, the edge detection circuits 120(1)-120(2) determine whether a signal edge is detected (block 214). If the answer to block 214 is no, then procedure 200 returns to block 206. However, if a signal edge is detected in block 214, then the antenna selection circuit 122 selects an antenna 102(1)-102(2) with the maximum signal increase (block 216). By performing antenna selection before synchronization, only a single association and synchronization circuit 114 needs to be activated during synchronization, reducing power consumption compared to a typical antenna diversity system. The control circuit 116 then activates the synchronization circuit 114 (block 218), and the data stored in the buffers 110(1)-110(2) corresponding to the selected antennas 102(1)-102(2) is provided to the synchronization circuit 114 by the MUX 112. As noted, the buffers 110(1)-110(2) may contain data beyond the time of arrival edge detection and selection.

[0023] The synchronization circuit 114 then uses an association algorithm to perform a single-antenna association calculation on the signal, thereby synchronizing to a packet (block 220). The synchronization circuit 114 (or the control circuit 116) decides whether a packet has been detected (block 222) before a timeout occurs. If a timeout occurs, the synchronization circuit 114 stops searching for new packets, completes any existing calculations in progress, and the procedure 200 returns to block 206. Note that if another edge is detected before the timeout, the procedure 200 can reset the timer associated with the timeout. However, if a packet is detected in block 222, the procedure 200 ends with single-antenna detection (block 224) and signal processing.

[0024] In an exemplary configuration, the timeout may be approximately 150 microseconds (150 µs). 150 µs corresponds to a minimum time between BLE packet transmissions. As used herein, this means approximately five percent (5%). While approximately 150 µs is expected, it should be understood that even lower timeouts can be used in specific applications or to balance reliability and power consumption. Generally, the timeout should be set as short as possible to minimize power consumption, but long enough to cover the time between the start of a packet transmission and when, in a worst-case scenario, the device can actually synchronize with that packet. The timeout may also need to cover the time required for pre-transmission, including the time required to gradually increase the power amplifier or stabilize the analog frequency synthesizer. The timeout should also be chosen to be long enough to allow the long-term average time to converge to a new level that responds to the new signal environment. It should be understood that the timeout may be programmed as needed during installation or manufacturing.

[0025] Note that while the synchronization circuit 114 is operating, any non-selected antenna path (e.g., ADC, buffer, and DSP circuitry) can optionally be shut down. Shutting down a non-selected antenna path can save power, but if conditions change and that non-selected antenna path becomes the preferred receiving path, it may hinder diversity reception.

[0026] Figure 3 illustrates an edge detection circuit 120. This edge detection circuit 120 receives a signal from a correlated RSSI circuit 118. The RSSI circuit 118 averages the size of one I and Q sample over a short period, then adjusts the result using the current gain setting of a correlated RFFE. These results can be downsampled before being transmitted to the edge detection circuit 120. In the edge detection circuit 120, a first circuit 300 forms a short-term moving average, which may cover, for example, 6 µs. A second circuit 302 forms a long-term moving average, which may cover, for example, 16 µs. In an exemplary case, the edge detection circuit 120 may have a sampling rate of one MHz (1 MHz). A difference is obtained by a differential circuit 304. This difference is an indication of the strength of a valid signal (the short-term average) exceeding the general noise level (the long-term average). This difference is compared with a threshold value by a comparator 306, and if the threshold value is exceeded, a signal detection signal is provided to the antenna selection circuit 122.

[0027] Other embodiments of the present invention are possible. An alternative exemplary receiver 400 is illustrated in FIG. 4. The receiver 400 has antennas 402(1)-402(2). The antennas 402(1)-402(2) may be coupled to respective ADCs 404(1)-404(2). In an exemplary embodiment, the ADCs 404(1)-404(2) may process the I and Q portions of the signals. A DSP block (e.g., a channel selection filter) for adjusting the signal used for detection may be provided on any side of the ADCs 404(1)-402(2) (not shown). Respective nodes 408(1)-408(2) are present after the ADCs 404(1)-404(2).

[0028] The signals from the antennas 402(1)-402(2) are separated at their respective nodes 408(1)-408(2). The first portion of each signal is provided to buffers 410(1)-410(2). The buffers 410(1)-410(2) are coupled to their respective synchronization circuits 414(1)-414(2). The synchronization circuits 414(1)-414(2) may be coupled to and controlled by a control circuit 416.

[0029] The second portion of each of these signals is provided from the nodes 408(1)-408(2) to the respective RSSI circuits 418(1)-418(2). The respective RSSI circuits 418(1)-418(2) are coupled to the respective edge detection circuits 420(1)-420(2). The edge detection circuits 420(1)-420(2) may be the same as the edge detection circuit 120 of FIG3 and may be coupled to an antenna selection circuit 422, which may be a logic OR circuit. Although shown as a different circuit in FIG4, the antenna selection circuit 422 may be part of the control circuit 416.

[0030] In the receiver 400, both synchronization circuits 414(1)-414(2) are initially in a sleep or low-power mode, but can be activated together when one or more edge detection circuits 420(1)-420(2) detect a signal. These synchronization circuits 414(1)-414(2) can then operate to facilitate the generation of a combined signal, thereby utilizing diversity options available from the antennas 402(1)-402(2). This approach achieves better performance, although at the cost of higher power consumption. While not optimal for battery-powered IoT devices, a power-powered IoT device (e.g., a refrigerator, set-top box, or similar) may find such a design trade-off acceptable. This approach also works better when selecting a better antenna, as the antenna selection can be based on correlation calculations rather than just edge detection. Finally, this approach can be used for more advanced multiple-input multiple-output (MIMO) processing techniques, including spatial-temporal coding, where the transmission system encodes information across multiple antennas.

[0031] As an alternative that can be implemented by receiver 100 or receiver 400, control circuit 116 or 416 can initially select an antenna based on the outputs from edge detection circuits 120, 420(1)-420(2), but initiate association-based synchronization if ambiguity or uncertainty occurs. This method can achieve excellent antenna selection performance while generally reducing power consumption in most cases.

[0032] Another alternative receiver 500 is illustrated in Figure 5. This receiver 500 may be a single-antenna receiver with only an antenna 502. The antenna 502 may be coupled to an ADC 504. In an exemplary configuration, the ADC 504 may process the I and Q portions of the signal. Immediately before or after the ADC 504, other DSP blocks (e.g., a channel selection filter) may be provided to adjust the signal used for detection. A node 508 may be present after the ADC 504.

[0033] The signal from antenna 502 is split at node 508. A first portion of the signal is provided to a buffer 510. The buffer 510 is coupled to a synchronization circuit 514. The synchronization circuit 514 may be coupled to and controlled by a control circuit 516.

[0034] A second portion of the signal is provided from node 508 to an RSSI circuit 518. The RSSI circuit 518 is coupled to an edge detection circuit 520, which may be identical to the edge detection circuit 120. The edge detection circuit 520 may be coupled to the control circuit 516.

[0035] Similar to the discussion above, the synchronization circuit 514 can remain in a sleep or low-power mode until it is activated by the control circuit 516 based on a signal received and detected by the edge detection circuit 520. This configuration still provides power savings for the receiver 500 compared to a system that uses the synchronization circuit to detect signals.

[0036] It should also be noted that the operational steps described in any of the illustrative examples herein are described to provide examples and for discussion. The operations may be performed in many different sequences other than those shown. Furthermore, an operation described in a single operational step may actually be performed in many different steps. In addition, one or more operational steps discussed in these illustrative examples may be combined. It should be understood that the operational steps illustrated in the flowcharts may be modified in many different ways, as will be apparent to those skilled in the art. Those skilled in the art will also appreciate that information and signals can be presented using any of a variety of different techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0037] The foregoing description of the invention is provided to enable anyone skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, this disclosure is not intended to limit it to the embodiments and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

[0038] 100, 400, 500: Receiver 102(1), 102(2), 402(1), 402(2), 502: Antenna 104(1), 104(2), 404(1), 404(2), 504: Analog-to-digital converter (ADC) 106A(1), 106A(2), 106B(1), 106B(2): Digital Signal Processing (DSP) 108(1), 108(2), 408(1), 408(2), 508: Nodes 110(1), 110(2), 410(1), 410(2), 510: Buffer 112: Multiplexer (MUX) 114, 414(1), 414(2), 514: Synchronization circuits 116, 416, 516: Control circuit 118(1), 118(2), 118, 418(1), 418(2), 518: Received Signal Strength Indicator (RSSI) circuit 120(1), 120(2), 120, 420(1), 420(2), 520: Edge detection circuit 122, 422: Antenna selection circuit 200: Program Blocks 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224 300: First Circuit 302: Second Circuit 304: Differential Circuit 306: Comparator

Claims

1. A receiver comprising: a Received Signal Strength Indicator (RSSI) circuit configured to receive a signal from an antenna; an edge detection circuit coupled to the RSSI circuit and configured to detect a new input signal relative to an existing environment; a synchronization circuit configured to use an association algorithm to synchronize with the signal from the antenna; and a control circuit coupled to the edge detection circuit and the synchronization circuit and configured to: turn off the synchronization circuit; and turn on the synchronization circuit in response to the edge detection circuit's detection of the new input signal.

2. The receiver as requested in item 1, wherein the input signal includes a Bluetooth Low Energy (BLE) signal.

3. The receiver of claim 1, wherein the edge detection circuit is configured to sample an output of the RSSI circuit at one megahertz (1 MHz).

4. The receiver of claim 1 further includes an analog-to-digital converter (ADC) coupled to the RSSI circuit.

5. The receiver as claimed in claim 4 further includes a buffer located between the ADC and the synchronization circuit.

6. The receiver of claim 1 further comprises: a second RSSI circuit configured to receive a signal from a second antenna; and a second edge detection circuit coupled to the second RSSI circuit and configured to detect the new input signal relative to the existing environment.

7. The receiver of claim 6 further includes a second synchronization circuit configured to use the correlation algorithm to synchronize with the signal from the antenna, wherein the control circuit is configured to: turn off the second synchronization circuit; and turn on the synchronization circuit or one of the second synchronization circuits in response to the detection of the new input signal by the edge detection circuit or the second edge detection circuit.

8. The receiver of claim 5 further includes a second buffer and a second ADC configured to be coupled to the second antenna.

9. The receiver of claim 1, wherein the edge detection circuit includes a short-term averaging circuit and a long-term averaging circuit.

10. The receiver of claim 9, wherein the edge detection circuit further includes a set of functions to calculate a difference between an output from the short-term averaging circuit and an output from the long-term averaging circuit.

11. A method for controlling a receiver, comprising: turning off a synchronization circuit; detecting an input signal using a first edge detection circuit based on a first RSSI from a first Received Signal Strength Indicator (RSSI) circuit; detecting the input signal using a second edge detection circuit based on a second RSSI from a second RSSI circuit; and turning on the synchronization circuit in response to detecting the input signal.

12. The method of claim 11 further includes using a Received Signal Strength Indicator (RSSI) circuit to provide an RSSI signal to the edge detection circuit.

13. The method of request item 11 further includes buffering the input signal during detection.

14. The method of request 11 further includes detecting a packet in the input signal.

15. The method as described in claim 11 further includes not detecting a packet of the input signal in a predetermined timeout window.

16. The method as described in claim 11 further includes selecting among signals from at least two antennas.

17. A receiver comprising: a first node configured to be coupled to a first antenna; A second node configured to be coupled to a second antenna; a first received signal strength indicator (RSSI) circuit configured to receive a first signal from the first node; A second RSSI circuit configured to receive a second signal from the second node; a first edge detection circuit coupled to the first RSSI circuit and configured to detect a new input signal compared to an existing environment; a second edge detection circuit coupled to the second RSSI circuit and configured to detect the new input signal compared to the existing environment; a synchronization circuit configured to use a correlation algorithm to synchronize with the signal from the antennas; and a control circuit coupled to the edge detection circuit and the synchronization circuit and configured to: turn off the synchronization circuit; and turn on the synchronization circuit in response to either the first edge detection circuit or the second edge detection circuit detecting the new input signal.

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