Resistive memory device

Abstract

A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer, and the first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first storage cell and a second storage cell. The first storage cell and the second storage cell include a first common bottom electrode, and the first insulating structure is directly disposed on the first common bottom electrode.

Description

Technical Field

[0001] The present invention relates to a resistive memory device, in particular to a resistive memory device including an insulating structure and a common bottom electrode. Prior Art

[0002] Semiconductor memory is a semiconductor component used to store data in computers and electronic products. It can be broadly categorized as either volatile or non-volatile. Volatile memory is computer memory whose stored data disappears when the operating power is interrupted. In contrast, non-volatile memory is immune to power outages. Resistive random access memory (RRAM) is a type of non-volatile memory. Its low operating voltage, low power consumption, and high write speed make it a promising memory structure for use in many electronic devices. Summary of the Invention

[0003] The present invention provides a resistive memory device that utilizes an insulating structure penetrating a portion of a stacked structure to divide the stacked structure into two storage cells. The two storage cells have a common bottom electrode, thereby achieving the effects of reducing the size of a single storage cell, increasing the density of the storage cells, and / or improving operational efficiency.

[0004] One embodiment of the present invention provides a resistive memory device comprising a dielectric layer, a first through-hole connection structure, a first stacked structure, and a first insulating structure. The first through-hole connection structure is disposed in the dielectric layer, and the first stacked structure is disposed on the first through-hole connection structure and the dielectric layer. The first insulating structure vertically penetrates a portion of the first stacked structure and divides the first stacked structure into a first storage unit and a second storage unit. The first storage unit and the second storage unit include a first common bottom electrode, and the first insulating structure is directly disposed on the first common bottom electrode. Simple diagram description

[0005] FIG. 1 is a top view schematically illustrating a resistance memory device according to a first embodiment of the present invention. FIG2 is a schematic cross-sectional view taken along the AA′ line in FIG1 . FIG3 is a schematic cross-sectional view taken along the BB′ line in FIG1 . FIG4 to FIG7 are schematic diagrams showing a method for manufacturing a resistive memory device according to an embodiment of the present invention, wherein Figure 5 shows a schematic diagram of the situation after Figure 4; Figure 6 shows a schematic diagram of the situation after Figure 5; FIG. 7 is a schematic diagram showing the situation after FIG. 6 . FIG8 to FIG10 are schematic diagrams showing a method for manufacturing a resistive memory device according to another embodiment of the present invention, wherein Figure 9 shows a schematic diagram of the situation after Figure 8; FIG. 10 is a schematic diagram showing the situation after FIG. 9 . FIG. 11 is a top view schematically illustrating a resistance memory device according to a second embodiment of the present invention. FIG. 12 is a top view schematically illustrating a resistance memory device according to a third embodiment of the present invention. FIG. 13 is a schematic diagram of a resistive memory device according to a fourth embodiment of the present invention. Implementation Method

[0006] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the invention.

[0007] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0008] The terms “on,” “over,” and “over” are to be interpreted in the broadest sense, such that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0009] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0010] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0011] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0012] Please refer to Figures 1 and 2. Figure 1 is a top view schematically illustrating a resistive memory device 101 according to a first embodiment of the present invention, while Figure 2 is a cross-sectional view schematically illustrated along line AA' in Figure 1. As shown in Figure 1, in some embodiments, the resistive memory device 101 may include a plurality of stacked structures 40 arranged in an array. Each stacked structure 40 may be disposed on a corresponding via connection structure 18 in a vertical direction (e.g., direction D1), and each stacked structure 40 may be divided into two memory cells by a corresponding insulating structure 30S. In some embodiments, two adjacent stacked structures 40 in direction D2 may be respectively referred to as a first stacked structure 40-1 and a second stacked structure 40-2, but this is not limiting. Furthermore, in other embodiments, the resistive memory device may include only a single stacked structure 40, depending on design requirements. As shown in Figures 1 and 2, a resistive memory device 101 may include a dielectric layer 16, a via connection structure 18 (e.g., a first via connection structure 18-1), a stacked structure 40 (e.g., a first stacked structure 40-1), and an insulating structure 30S (e.g., a first insulating structure 30S-1). The first via connection structure 18-1 is disposed in the dielectric layer 16, while the first stacked structure 40-1 is disposed on the first via connection structure 18-1 and the dielectric layer 16. The first insulating structure 30S-1 extends through a portion of the first stacked structure 40-1 in a vertical direction (e.g., direction D1) and divides the first stacked structure 40-1 into a first storage cell 40A and a second storage cell 40B. The first storage cell 40A and the second storage cell 40B include a first common bottom electrode 20S-1, and the first insulating structure 30S-1 is directly disposed on the first common bottom electrode 20S-1. In other words, the first insulating structure 30S-1 does not penetrate the first common bottom electrode 20S-1, and the first common bottom electrode 20S-1 can be shared by the first storage cell 40A and the second storage cell 40B. Using the insulating structure 30S to divide the stacked structure 40 into two partially separated storage cells can reduce the vertical area occupied by a single storage cell, thereby increasing the storage cell arrangement density.

[0013] In some embodiments, the resistive memory device 101 may further include a dielectric layer 10, a conductive line 12, and a dielectric layer 14. The conductive line 12 may be disposed within the dielectric layer 10, and the dielectric layer 14 may be disposed between the dielectric layer 16 and the dielectric layer 10. A via structure 18 may penetrate the dielectric layer 16 and the dielectric layer 14 located above the conductive line 12 in a direction D1. A bottom surface 18BS of the via structure 18 may contact the conductive line 12 to form an electrical connection, and a top surface 18TS of the via structure 18 may be substantially coplanar with a top surface 16TS of the dielectric layer 16, but this is not a limitation. It should be noted that the top surface of a specific object described herein may include the topmost surface of the object in the direction D1, and the bottom surface of the specific object may include the bottommost surface of the object in the direction D1, but this is not a limitation. In some embodiments, dielectric layer 10, dielectric layer 14, and dielectric layer 16 may each comprise silicon oxide, silicon nitride, nitrogen-doped carbide (NDC), silicon carbide nitride, fluorosilicate glass (FSG), or other suitable dielectric materials, while via connection structure 18 and conductive line 12 may comprise a low-resistance material and a barrier layer, but are not limited thereto. The low-resistance material may comprise a material with relatively low resistivity, such as copper, aluminum, or tungsten, while the barrier layer may comprise titanium nitride, tantalum nitride, or other suitable conductive barrier materials, but are not limited thereto. In some embodiments, dielectric layer 10 may be disposed on a substrate (not shown), which may comprise a semiconductor substrate, such as a silicon substrate, a silicon-germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or other substrates formed of suitable materials. Furthermore, before forming the dielectric layer 10, devices (e.g., transistors) and / or circuits (not shown) may be formed on the substrate, and the conductive lines 12 may be electrically connected downwardly to the devices and / or circuits on the substrate, but the invention is not limited thereto. In some embodiments, the method for fabricating the resistive memory device 101 may be integrated with back-end of line (BEOL) processes in a semiconductor manufacturing process. The dielectric layers 10, 14, and 16 may be considered interlayer dielectric layers formed in the BEOL process, and the conductive lines 12 and via connection structures 18 may be considered part of an interconnect structure formed in the BEOL process, but the invention is not limited thereto.

[0014] In some embodiments, the vertical direction (e.g., direction D1) can be considered the thickness direction of the dielectric layer 10 and / or the dielectric layer 16. The dielectric layer 10 may have an upper surface and a bottom surface opposite each other in direction D1, and the dielectric layer 16, the through-hole connection structure 18, the stacked structure 40, and the insulating structure 30S may be disposed on one side of the upper surface of the dielectric layer 10. Horizontal directions substantially orthogonal to direction D1 (e.g., direction D2, direction D3, and other directions orthogonal to direction D1) may be substantially parallel to the upper surface and / or the bottom surface of the dielectric layer 10, but are not limited thereto. As described herein, the distance between a relatively higher position or / and component in the vertical direction (e.g., direction D1) and the bottom surface of the dielectric layer 10 in direction D1 may be greater than the distance between a relatively lower position or / and component in direction D1 and the bottom surface of the dielectric layer 10 in direction D1. The lower portion or bottom of each component may be closer to the bottom surface of the dielectric layer 10 in direction D1 than the upper portion or top of the component. Another component above a certain component may be considered to be relatively far away from the bottom surface of the dielectric layer 10 in direction D1, and another component below a certain component may be considered to be relatively close to the bottom surface of the dielectric layer 10 in direction D1.

[0015] In some embodiments, a stacked structure 40 (e.g., a first stacked structure 40-1) may include a common bottom electrode 20S (e.g., a first common bottom electrode 20S-1), a variable resistance material 22, and a conductive layer 26 stacked in a direction D1. The first common bottom electrode 20S-1 may be disposed on the dielectric layer 16 and the first via connection structure 18-1. The variable resistance material 22 and the conductive layer 26 may be disposed above the first common bottom electrode 20S-1 in the direction D1, and the variable resistance material 22 may be located between the first common bottom electrode 20S-1 and the conductive layer 26 in the direction D1. The common bottom electrode 20S (e.g., the first common bottom electrode 20S-1) and the conductive layer 26 may each comprise a conductive material such as platinum, tungsten, silver, copper, titanium, tantalum, alloys of these materials, conductive nitrides of these materials, or other suitable conductive materials. The variable resistance material 22 may comprise a metal oxide such as a transition metal oxide, perovskite oxide, or other suitable variable resistance material. The insulating structure 30S (e.g., the first insulating structure 30S-1) may penetrate the conductive layer 26 and the variable resistor material 22 in the direction D1, thereby dividing the conductive layer 26 and the variable resistor material 22 into two separate portions. The insulating structure 30S may include a single layer or multiple layers of insulating material, such as a nitride insulating material (e.g., silicon nitride) or other suitable insulating material (e.g., a low-k dielectric material). In some embodiments, the insulating structure 30S may include a seam SE, and the seam SE may include an air gap, but this is not limited to this.

[0016] In some embodiments, the first storage cell 40A may further include a first top electrode 26A and a first variable resistance layer 22A, and the second storage cell 40B may further include a second top electrode 26B and a second variable resistance layer 22B. The first top electrode 26A, the first variable resistance layer 22A, the second top electrode 26B, and the second variable resistance layer 22B may be disposed on the first common bottom electrode 20S-1 in direction D1. The first variable resistance layer 22A may be disposed between the first common bottom electrode 20S-1 and the first top electrode 26A in direction D1, and the second variable resistance layer 22B may be disposed between the first common bottom electrode 20S-1 and the second top electrode 26B in direction D1. In some embodiments, the first variable resistance layer 22A may be a first portion of the variable resistance material 22, and the second variable resistance layer 22B may be a second portion of the variable resistance material 22. The first and second portions of the variable resistance material 22 may be separated from each other by a first insulating structure 30S-1. Therefore, the first and second variable resistance layers 22A and 22B may have the same material composition and substantially the same thickness, but the present invention is not limited thereto. In some embodiments, the first top electrode 26A may be a first portion of the conductive layer 26, and the second top electrode 26B may be a second portion of the conductive layer 26. The first and second portions of the conductive layer 26 may be separated from each other by a first insulating structure 30S-1. Therefore, the first and second top electrodes 26A and 26B may have the same material composition and substantially the same thickness, but the present invention is not limited thereto. In each memory cell, each variable resistance layer can be considered a switching medium in the resistive memory cell. By applying appropriate voltages to the top and bottom electrodes in the stacked structure, the resistance value of the resistive memory cell can be changed, allowing the resistive memory cell to switch between a high resistance state (HRS) and a low resistance state (LRS), thereby implementing memory device operating modes such as storing data, reading data, and resetting. Furthermore, by using the insulating structure 30S to divide the stacked structure 40 into two separate memory cells sharing a common bottom electrode, the size of a single memory cell can be reduced, thereby increasing the density of memory cell arrangements. By reducing the size of the memory cell, the operating time of a single memory cell can also be relatively shortened. For example, the time required to apply a bias voltage to the memory cell to form a conductive path and reach a low resistance state (forming time) can be shortened, thereby improving operational efficiency.

[0017] In some embodiments, the stacked structure 40 (e.g., the first stacked structure 40-1) may further include a barrier layer 24 and a cap layer 28. The barrier layer 24 may be disposed between the variable resistor material 22 and the conductive layer 26 in the direction D1 to block and / or reduce the conductive layer 26 or other materials from entering the variable resistor material 22 and affecting the material properties of the variable resistor material 22. The cap layer 28 may be disposed on the conductive layer 26. The barrier layer 24 may include iridium or other suitable barrier materials, while the cap layer 28 may include an oxide insulating material (e.g., silicon oxide) or other suitable insulating materials. In some embodiments, the first storage cell 40A may further include a first barrier layer 24A and a first cap layer 28A, while the second storage cell 40B may further include a second barrier layer 24B and a second cap layer 28B. The first barrier layer 24A may be disposed between the first variable resistance layer 22A and the first top electrode 26A in direction D1, the second barrier layer 24B may be disposed between the second variable resistance layer 22B and the second top electrode 26B in direction D1, the first cap layer 28A may be disposed on the first top electrode 26A, and the second cap layer 28B may be disposed on the second top electrode 26B. In some embodiments, the first barrier layer 24A and the second barrier layer 24B may be two portions of the barrier layer 24 separated by an insulating structure 30S. Therefore, the first barrier layer 24A and the second barrier layer 24B may have the same material composition and substantially equal thickness. In some embodiments, the first cap layer 28A and the second cap layer 28B may be two portions of the cap layer 28 separated by an insulating structure 30S. Therefore, the first cap layer 28A and the second cap layer 28B may have the same material composition and substantially equal thickness. It is worth noting that the stacked structure 40 of the present invention is not limited to the above-described conditions. Other material layers may be provided in the stacked structure 40 depending on design requirements. Similarly, other material layers may be provided in each storage cell depending on design requirements. Furthermore, the resistive memory device 101 may further include a spacer substructure 42 (e.g., a first spacer substructure 42-1) and a dielectric layer 44. The first spacer substructure 42-1 may be provided on the sidewalls of the first stacked structure 40-1, and the dielectric layer 44 may be provided on the dielectric layer 16 and surround the first spacer substructure 42-1, the first stacked structure 40-1, and the first insulating structure 30S-1 in horizontal directions (e.g., directions D2 and D3 orthogonal to direction D1). The spacer substructure 42 may include a single layer or multiple layers of dielectric material, such as silicon nitride, silicon carbide, or other suitable dielectric materials, and the dielectric layer 44 may include silicon oxide, silicon nitride, or other suitable dielectric materials.

[0018] In some embodiments, the first storage cell 40A and the second storage cell 40B may be located on opposite sides of the first insulating structure 30S-1 in a horizontal direction (e.g., direction D3), and the first insulating structure 30S-1 may directly contact the first storage cell 40A and the second storage cell 40B. In other words, one side of the first insulating structure 30S-1 may be directly connected to the first capping layer 28A, the first top electrode 26A, the first barrier layer 24A, and the first variable resistance layer 22A in the first storage cell 40A, while the other side of the first insulating structure 30S-1 may be directly connected to the second capping layer 28B, the second top electrode 26B, the second barrier layer 24B, and the second variable resistance layer 22B in the second storage cell 40B. In some embodiments, at least a portion of the first insulating structure 30S-1 may be disposed above the first via connection structure 18-1 in direction D1. The first insulating structure 30S-1 does not penetrate the first common bottom electrode 20S-1. Therefore, a portion of the first common bottom electrode 20S-1 may be disposed between the first insulating structure 30S-1 and the first via connection structure 18-1 in direction D1. In some embodiments, a bottom surface 30BS of the first insulating structure 30S-1 may be lower than a top surface 20TS of the first common bottom electrode 20S-1 and higher than the top surface 18TS of the first via connection structure 18-1 in direction D1. Therefore, the first insulating structure 30S-1 may partially extend into the first common bottom electrode 20S-1 in direction D1 without penetrating the first common bottom electrode 20S-1, thereby ensuring that the variable resistive material 22 is separated into the first variable resistive layer 22A and the second variable resistive layer 22B. Furthermore, the design of the common bottom electrode 20S can prevent the process for forming the insulating structure 30S from damaging the through-hole connection structure 18 and / or relatively increase the contact area between the common bottom electrode 20S and the through-hole connection structure 18, which has a positive impact on the operating performance and / or manufacturing yield of the resistive memory device.

[0019] As shown in FIG. 1 , in some embodiments, a resistive memory device 101 may include a plurality of stacked structures 40 arranged in an array, with two adjacent stacked structures 40 in direction D2 being referred to as a first stacked structure 40-1 and a second stacked structure 40-2, respectively. Therefore, as shown in FIG. 1 and FIG. 3 , the resistive memory device 101 may include a second stacked structure 40-2, a second via connection structure 18-2 corresponding to the second stacked structure 40-2, and a second insulating structure 30S-2. The second via connection structure 18-2 may be disposed within the dielectric layer 16 and the dielectric layer 14, the second stacked structure 40-2 may be disposed on the second via connection structure 18-2 and the dielectric layer 16, and the second insulating structure 30S-2 may penetrate a portion of the second stacked structure 40-2 in direction D1 and divide the second stacked structure 40-2 into a third storage unit 40C and a fourth storage unit 40D. The third storage cell 40C and the fourth storage cell 40D may include a second common bottom electrode 20S-2, and the second insulating structure 30S-2 may be directly disposed on the second common bottom electrode 20S-2. In some embodiments, the material composition and relative arrangement of the second via connection structure 18-2, the second stacked structure 40-2, and the second insulating structure 30S-2 may be the same as the material composition and relative arrangement of the first via connection structure 18-1, the first stacked structure 40-1, and the first insulating structure 30S-1 shown in FIG. 2 above, but the present invention is not limited thereto. For example, the second stacked structure 40-2 may also include a common bottom electrode 20S (e.g., the second common bottom electrode 20S-2), a variable resistance material 22, a barrier layer 24, a conductive layer 26, and a capping layer 28 stacked in direction D1, but the present invention is not limited thereto. In some embodiments, the material composition of the second insulating structure 30S-2 and / or the second stacked structure 40-2 may differ from the material composition of the first insulating structure 30S-1 and / or the first stacked structure 40-1, depending on design requirements.

[0020] As shown in FIG1 and FIG3 , in some embodiments, the third storage cell 40C may include a third variable resistance layer 22C, a third barrier layer 24C, a third top electrode 26C, and a third cap layer 28C stacked in direction D1, while the fourth storage cell 40D may include a fourth variable resistance layer 22D, a fourth barrier layer 24D, a fourth top electrode 26D, and a fourth cap layer 28D stacked in direction D1. The third variable resistance layer 22C may be disposed between the second common bottom electrode 20S-2 and the third top electrode 26C in direction D1, the third barrier layer 24C may be disposed between the third variable resistance layer 22C and the third top electrode 26C in direction D1, and the third cap layer 28C may be disposed on the third top electrode 26C. In contrast, the fourth variable resistance layer 22D may be disposed between the second common bottom electrode 20S-2 and the fourth top electrode 26D in direction D1, the fourth barrier layer 24D may be disposed between the fourth variable resistance layer 22D and the fourth top electrode 26D in direction D1, and the fourth capping layer 28D may be disposed on the fourth top electrode 26D. The third variable resistance layer 22C and the fourth variable resistance layer 22D may be different portions of the variable resistance material 22 and separated from each other by the second insulating structure 30S-2. The third barrier layer 24C and the fourth barrier layer 24D may be different portions of the barrier layer 24 and separated from each other by the second insulating structure 30S-2. The third top electrode 26C and the fourth top electrode 26D may be different portions of the conductive layer 26 and separated from each other by the second insulating structure 30S-2. The third capping layer 28C and the fourth capping layer 28D may be different portions of the capping layer 28 and separated from each other by the second insulating structure 30S-2. One side of the second insulating structure 30S-2 can be directly connected to the third cover layer 28C, the third upper electrode 26C, the third barrier layer 24C and the third variable resistance layer 22C in the third storage unit 40C, and the other side of the second insulating structure 30S-2 can be directly connected to the fourth cover layer 28D, the fourth upper electrode 26D, the fourth barrier layer 24D and the fourth variable resistance layer 22D in the fourth storage unit 40D.

[0021] As shown in Figures 1 to 3, the first stacked structure 40-1 and the second stacked structure 40-2 may be separated from each other, the first common bottom electrode 20S-1 and the second common bottom electrode 20S-2 may be separated from each other, the gap substructure 42 disposed on the sidewall of the first stacked structure 40-1 may be a first gap substructure 42-1, and the gap substructure 42 disposed on the sidewall of the second stacked structure 40-2 may be a second gap substructure 42-2. In some embodiments, each insulating structure 30S may extend along a direction D2, and each gap substructure 42 may horizontally surround the corresponding stacked structure 40 and be directly connected to the corresponding insulating structure 30S. Therefore, the first insulating structure 30S-1 and the second insulating structure 30S-2 can extend respectively along the direction D2, the first insulating structure 30S-1 and the second insulating structure 30S-2 can be arranged adjacent to each other in the direction D2 but separated from each other, and the first gap substructure 42-1 can be directly connected to the two opposite side walls of the first insulating structure 30S-1 in the direction D2, and the second gap substructure 42-2 can be directly connected to the two opposite side walls of the second insulating structure 30S-2 in the direction D2.

[0022] Please refer to Figures 1 to 3 and Figures 4 to 7. Figures 4 to 7 illustrate a method for fabricating a resistive memory device according to an embodiment of the present invention. Figure 5 illustrates a state subsequent to Figure 4, Figure 6 illustrates a state subsequent to Figure 5, and Figure 7 illustrates a state subsequent to Figure 6. Figures 2 and / or 3 may be considered to illustrate a state subsequent to Figure 7, but this is not limiting. As shown in Figures 1 to 3, the method for fabricating a resistive memory device 101 according to this embodiment may include the following steps: forming a via connection structure 18 in a dielectric layer 16, forming a stacked structure 40 on the via connection structure 18 and the dielectric layer 16, and forming an insulating structure 30S. The insulating structure 30S penetrates a portion of the stacked structure 40 in a direction D1 and divides the stacked structure 40 into two memory cells. These two memory cells include a common bottom electrode 20S, and the insulating structure is directly disposed on the common bottom electrode 20S. The manufacturing method of this embodiment can be applied to the first stacking structure 40-1 shown in Figure 2 or / and the second stacking structure 40-2 shown in Figure 3, so the through-hole connection structure 18 can be the first through-hole connection structure 18-1 or the second through-hole connection structure 18-2, the insulating structure 30S can be the first insulating structure 30S-1 or the second insulating structure 30S-2, the common bottom electrode 20S can be the first common bottom electrode 20S-1 or the second common bottom electrode 20S-2, and the two storage units including the common bottom electrode 20S can be the first storage unit 40A and the second storage unit 40B or the third storage unit 40C and the fourth storage unit 40D.

[0023] To further illustrate, the method for fabricating a resistive memory device according to this embodiment may include, but is not limited to, the following steps. As shown in FIG. 3 , after forming a conductive line 12 in a dielectric layer 10 , a dielectric layer 14 and a dielectric layer 16 are formed on the dielectric layer 10 and the conductive line 12 . Then, a via connection structure 18 is formed, penetrating the dielectric layer 16 and the dielectric layer 14 located on the conductive line 12 in a direction D1 to contact and electrically connect the conductive line 12 . In some embodiments, the via connection structure 18 is formed by filling an opening through the dielectric layer 16 and the dielectric layer 14 with a conductive material and performing a planarization process to remove the conductive material outside the opening. The top surface 18TS of the via connection structure 18 and the top surface 16TS of the dielectric layer 16 may be substantially coplanar, but this is not limiting. Subsequently, as shown in FIG. 5 , a conductive layer 20 is formed on the via connection structure 18 and the dielectric layer 16 , a variable resistor material 22 is formed on the conductive layer 20 , and a conductive layer 26 is formed on the variable resistor material 22 . In some embodiments, a barrier layer 24 may be formed on the variable resistor material 22 before forming the conductive layer 26, and the conductive layer 26 may be formed on the barrier layer 24. Furthermore, a cap layer 28 may be formed on the conductive layer 26, but this is not limiting. Then, as shown in FIG. 6 , a patterning process may be performed on the cap layer 28, the conductive layer 26, the barrier layer 24, the variable resistor material 22, and the conductive layer 20 to form a stacked structure 40, with gap substructures 42 formed on the sidewalls of the stacked structure 40. Thus, the stacked structure 40 may include a common bottom electrode 20S, the variable resistor material 22, the barrier layer 24, the conductive layer 26, and the cap layer 28 stacked in the direction D1. The conductive layer 20 may be patterned by a patterning process to form the common bottom electrode 20S.

[0024] As shown in FIG. 7 , a dielectric layer 44 may be formed. After the dielectric layer 44 is formed, a trench TR is formed in the direction D1 through the cap layer 28, conductive layer 26, barrier layer 24, and variable resistance material 22 in the stacked structure 40, thereby forming the two memory cells described above with a common bottom electrode 20S. In some embodiments, a portion of the common bottom electrode 20S may be removed during the step of forming the trench TR (such as, but not limited to, an etching process), so that a bottom surface BS of the trench TR may be lower than a top surface 20TS of the common bottom electrode 20S in the direction D1, but this is not limited to the embodiment of the present invention. Subsequently, as shown in FIG. 2 and / or FIG. 3 , an insulating structure 30S may be formed in the trench TR. In some embodiments, an insulating material may be formed, partially filling the trench TR and partially forming outside the trench TR. A planarization process may then be performed to remove the insulating material formed outside the trench TR. The insulating material remaining in the trench TR after the planarization process may become the insulating structure 30S. Therefore, the upper surface 30TS of the insulating structure 30S and the upper surface 40TS of the stacked structure 40 may be substantially coplanar, but the present invention is not limited thereto.

[0025] Please refer to Figures 1 to 3 and Figures 8 to 10. Figures 8 to 10 illustrate a method for fabricating a resistive memory device according to another embodiment of the present invention. Figure 9 illustrates a state subsequent to Figure 8, and Figure 10 illustrates a state subsequent to Figure 9. Figures 2 and / or 3 may be considered to illustrate a state subsequent to Figure 10, but are not limited thereto. As shown in Figure 8, after forming the cap layer 28, a trench TR may be formed in a direction D1 through the cap layer 28, the conductive layer 26, the barrier layer 24, and the variable resistor material 22. Then, as shown in Figure 9, an insulating structure 30S may be formed in the trench TR. As shown in Figure 10, after forming the insulating structure 30S, the cap layer 28, the conductive layer 26, the barrier layer 24, the variable resistor material 22, and the conductive layer 20 may be patterned to form a stacked structure 40, and spacer substructures 42 may be formed on the sidewalls of the stacked structure 40. In some embodiments, the insulating structure 30S may be formed before the step of forming the stacked structure 40, and a portion of the insulating structure 30S may be removed during the step of forming the stacked structure 40, but the present invention is not limited thereto. Subsequently, as shown in FIG. 2 and / or FIG. 3 , a dielectric layer 44 may be formed after the insulating structure 30S, the stacked structure 40, and the spacer substructure 42 are formed.

[0026] It is worth noting that the method for manufacturing the resistive memory device of the present invention is not limited to the steps shown in Figures 4 to 7 and / or the steps shown in Figures 8 to 10 above. Depending on design requirements, other methods can be used to form the resistive memory device shown in Figures 1 to 3.

[0027] The following describes various embodiments of the present invention. For simplicity, the following description focuses on the differences between the various embodiments, without repetitively describing the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with identical reference numerals to facilitate cross-reference between the various embodiments.

[0028] Please refer to FIG. 11 . FIG. 11 is a top view schematically illustrating a resistive memory device 102 according to a second embodiment of the present invention. As shown in FIG. 11 , in the resistive memory device 102 , each insulating structure 30S may extend along a direction D2 . The length of each insulating structure 30S in direction D2 may be greater than the length of the corresponding stacked structure 40 in direction D2 . Furthermore, the gap substructure 42 may be divided into two separate portions by the corresponding insulating structure 30S. For example, the first insulating structure 30S-1 and the second insulating structure 30S-2 may be disposed adjacent to each other in direction D2 but separated from each other. The length L2 of the first insulating structure 30S-1 in direction D2 may be greater than the length L1 of the first stacked structure 40-1 in direction D2, and the length of the second insulating structure 30S-2 in direction D2 may be greater than the length of the second stacked structure 40-2 in direction D2. The first gap substructure 42-1 may include two portions separated from each other by the first insulating structure 30S-1, and the second gap substructure 42-2 may include two portions separated from each other by the second insulating structure 30S-2. By relatively increasing the length of the insulating structure 30S in direction D2, the probability of layers in the stacked structure 40, other than the common bottom electrode, not being completely separated into two separate portions by the insulating structure 30S can be reduced when the formation position of the insulating structure 30S shifts, thereby improving manufacturing yield.

[0029] Please refer to Figure 12 . Figure 12 illustrates a top view of a resistive memory device 103 according to a third embodiment of the present invention. As shown in Figure 12 , in the resistive memory device 103, adjacent stacked structures 40 in direction D2 may share a common insulating structure 30S, while the gap substructure 42 may be divided into two separate portions by the corresponding insulating structure 30S. Therefore, the first insulating structure 30S-1 corresponding to the first stacked structure 40-1 and the second insulating structure 30S-2 corresponding to the second stacked structure 40-2 may be different portions of the insulating structure 30S extending along direction D2 and directly connected. Furthermore, the length of each insulating structure 30S in direction D2 may be greater than the total length of the multiple stacked structures 40 corresponding to that insulating structure 30S in direction D2.

[0030] Please refer to FIG. 13 . FIG. 13 is a schematic diagram of a resistive memory device 104 according to a fourth embodiment of the present invention. As shown in FIG. 13 , in the resistive memory device 104, the bottom surface 30BS of the insulating structure 30S (e.g., the bottom surface of the first insulating structure and / or the bottom surface of the second insulating structure) can be substantially coplanar with the top surface 20TS of the common bottom electrode 20S (e.g., the top surface of the first common bottom electrode and / or the top surface of the second common bottom electrode). This prevents a portion of the common bottom electrode 20S from being removed by the process (e.g., etching process) used to form the trench TR. Furthermore, there is no need to increase the thickness of the common bottom electrode 20S to accommodate the trench TR formation process, which positively facilitates the process of forming the stacked structure. In some embodiments, the etching selectivity ratio of the process for forming the trench TR for the variable resistor material and the common bottom electrode 20S can be improved by selecting and matching the materials of the variable resistor material and the common bottom electrode 20S or / and adjusting the process conditions for forming the trench TR, thereby achieving a design in which the bottom surface 30BS of the insulating structure 30S and the top surface 20TS of the common bottom electrode 20S are substantially coplanar, but the present invention is not limited to this.

[0031] In summary, in the resistive memory device and its manufacturing method of the present invention, an insulating structure can be used to penetrate a portion of the stacked structure to divide the stacked structure into two storage units, and the two storage units have a common bottom electrode, thereby achieving the effects of improving the manufacturing yield, reducing the size of a single storage unit, increasing the density of the storage units, and / or improving the operating efficiency. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0032] 10: Dielectric layer 12: Wire 14: Dielectric layer 16: Dielectric layer 16TS: Top surface 18: Through-hole connection structure 18-1: First through-hole connection structure 18-2: Second through-hole connection structure 18BS: bottom surface 18TS: Upper surface 20: conductive layer 20S: common bottom electrode 20S-1: first common bottom electrode 20S-2: second common bottom electrode 20TS: Top surface 22: Variable resistor material 22A: first variable resistance layer 22B: Second variable resistance layer 22C: third variable resistance layer 22D: Fourth variable resistance layer 24: Barrier layer 24A: First barrier layer 24B: Second barrier layer 24C: The third barrier layer 24D: The fourth barrier layer 26: conductive layer 26A: first upper electrode 26B: Second upper electrode 26C: third upper electrode 26D: Fourth upper electrode 28: Covering layer 28A: First cover layer 28B: Second cover layer 28C: Third cover layer 28D: The fourth cover layer 30BS: bottom surface 30S: Insulation structure 30S-1: First insulation structure 30S-2: Second insulation structure 30TS: Top surface 40: Stacked structure 40-1: First stacking structure 40-2: Second stacking structure 40A: First storage unit 40B: Second storage unit 40C: Third storage unit 40D: Fourth storage unit 40TS: Top surface 42: Gap substructure 42-1: First gap substructure 42-2: Second gap substructure 44: dielectric layer 101: Resistive Memory Device 102: Resistive Memory Device 103: Resistive Memory Device 104: Resistive Memory Device BS: bottom surface D1: Direction D2: Direction D3: direction L1: Length L2: Length SE:Seams TR: Groove

Claims

1. A resistive memory device, comprising: One dielectric layer; A first through-hole connection structure is disposed in the dielectric layer; A first stacked structure is disposed on the first via connection structure and the dielectric layer; and a first insulating structure penetrates a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first storage cell and a second storage cell, wherein the first storage cell and the second storage cell include a first common bottom electrode, the first insulating structure is directly disposed on the first common bottom electrode, and a bottom surface of the first insulating structure is lower than an upper surface of the first common bottom electrode and higher than an upper surface of the first via connection structure in the vertical direction.

2. The resistive memory device as claimed in claim 1, wherein a portion of the first common bottom electrode is disposed in the vertical direction between the first insulating structure and the first through-hole connection structure.

3. The resistive memory device as described in claim 1, wherein the first stacked structure includes: A conductive layer is disposed on the first common bottom electrode in the vertical direction; And a variable resistance material is disposed in the vertical direction between the first common bottom electrode and the conductive layer, wherein the first insulating structure penetrates the conductive layer and the variable resistance material in the vertical direction.

4. The resistive memory device as claimed in claim 3, wherein the first storage unit further includes a first upper electrode and a first variable resistance layer disposed in the vertical direction between the first common bottom electrode and the first upper electrode, and the second storage unit further includes a second upper electrode and a second variable resistance layer disposed in the vertical direction between the first common bottom electrode and the second upper electrode.

5. The resistive memory device as claimed in claim 4, wherein the first variable resistance layer is a first portion of the variable resistance material, the second variable resistance layer is a second portion of the variable resistance material, and the first portion and the second portion of the variable resistance material are separated from each other by the first insulating structure.

6. The resistive memory device as claimed in claim 4, wherein the first upper electrode is a first portion of the conductive layer, the second upper electrode is a second portion of the conductive layer, and the first portion and the second portion of the conductive layer are separated from each other by the first insulating structure.

7. The resistive memory device as claimed in claim 4, wherein the first insulating structure is directly connected to the first variable resistive layer, the second variable resistive layer, the first upper electrode, and the second upper electrode.

8. The resistive memory device as described in claim 1, further comprising: A gap substructure is disposed on the sidewall of the first stacked structure.

9. The resistive memory device as claimed in claim 8, wherein the gap substructure surrounds the first stacked structure in a direction orthogonal to the vertical direction, and the first insulating structure is directly connected to the gap substructure.

10. The resistive memory device as claimed in claim 8, wherein the gap substructure comprises two parts separated from each other by the first insulating structure.

11. The resistive memory device as claimed in claim 1, wherein the length of the first insulating structure in a horizontal direction is greater than the length of the first stacked structure in the horizontal direction.

12. The resistive memory device as described in claim 1, further comprising: A second through-hole connection structure is disposed in the dielectric layer; A second stacked structure is disposed on the second via connection structure and the dielectric layer; And a second insulating structure that penetrates a portion of the second stacked structure in the vertical direction and divides the second stacked structure into a third storage unit and a fourth storage unit, wherein the third storage unit and the fourth storage unit include a second common bottom electrode, and the second insulating structure is directly disposed on the second common bottom electrode.

13. The resistive memory device as claimed in claim 12, wherein the first insulating structure and the second insulating structure extend along a horizontal direction and are disposed adjacent to each other in the horizontal direction.

14. The resistive memory device as claimed in claim 13, wherein the first insulating structure and the second insulating structure are separate from each other.

15. The resistive memory device as claimed in claim 13, wherein the first insulating structure and the second insulating structure are different portions of an insulating structure extending along the horizontal direction and are directly connected.

16. The resistive memory device as claimed in claim 12, wherein the first stack structure and the second stack structure are separated from each other, and the first common bottom electrode and the second common bottom electrode are separated from each other.

17. The resistive memory device as claimed in claim 12, wherein the third storage cell further includes a third upper electrode and a third variable resistance layer disposed in the vertical direction between the second common bottom electrode and the third upper electrode, and the fourth storage cell further includes a fourth upper electrode and a fourth variable resistance layer disposed in the vertical direction between the second common bottom electrode and the fourth upper electrode.

18. The resistive memory device as claimed in claim 17, wherein the third upper electrode and the fourth upper electrode are separated from each other by the second insulating structure, the third variable resistive layer and the fourth variable resistive layer are separated from each other by the second insulating structure, and the second insulating structure is directly connected to the third variable resistive layer, the fourth variable resistive layer, the third upper electrode and the fourth upper electrode.

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