Semiconductor device

Abstract

A semiconductor device includes: a substrate, a semiconductor layer, a source electrode, a first metal layer, a back-side via, and a back-side metal layer. The substrate has a front side and a back side opposite to each other. The semiconductor layer is disposed on the front side of the substrate. The source electrode is disposed on the semiconductor layer. The first metal layer is disposed on the source electrode. The back-side via extends from the back side of the substrate to the bottom surface of the first metal layer. The back-side via is laterally separated from the source electrode by a non-zero distance. The back-side metal layer is disposed on the back side of the substrate and extends to cover the surface of the back-side via.

Description

semiconductor components The present invention relates to a semiconductor device, and more particularly to a high electron mobility transistor (HEMT) device and a method for forming the same. For semiconductor technology, continuously reducing the size of semiconductor structures, improving speed, enhancing performance, increasing density, and reducing the cost per unit integrated circuit are important development goals of semiconductor technology. However, regardless of the size of the component, its electronic properties must still be maintained or even improved to meet the market requirements for electronic products. Generally speaking, if there are unnecessary excess materials remaining in the various layers of the semiconductor component structure, or if there are damage or poor surface properties at the formed location, it will have a significant impact on the electronic properties of the component. Therefore, this is one of the important issues that need to be paid attention to when manufacturing semiconductor components. For example, when performing chip probe (CP) testing or wire bonding, the pressure of the test probe or wire bonding can easily damage the structure under the pad, thereby affecting the component yield and reliability. The present invention provides a semiconductor device comprising: a substrate, a semiconductor layer, a source electrode, a first metal layer, a backside via, and the backside metal layer. The substrate has a front side and a backside opposite to each other. The semiconductor layer is disposed on the front side of the substrate. The source electrode is disposed on the semiconductor layer. The first metal layer is disposed on the source electrode. The backside via extends from the back side of the substrate to the bottom surface of the first metal layer. The backside via is laterally separated from the source electrode by a non-zero distance. The backside metal layer is disposed on the back side of the substrate and extends over the surface of the backside via. In one embodiment of the present invention, the backside via is physically separated from the source electrode by a dielectric material. In one embodiment of the present invention, the backside via penetrates the substrate, the semiconductor layer, and the dielectric material to contact the first metal layer. In one embodiment of the present invention, the backside metal layer conformally covers the surface of the backside through hole to form a hollow space in the backside through hole. In one embodiment of the present invention, the semiconductor device further includes: a filling material filling the hollow space, such that the back metal layer covers the filling material. In one embodiment of the present invention, the filling material includes an insulating material. In one embodiment of the present invention, the filling material includes a metal material. In one embodiment of the present invention, the filling material and the back metal layer are made of the same material. In one embodiment of the present invention, the bottom surface of the filling material is higher than the lowest bottom surface of the back metal layer. In one embodiment of the present invention, the bottom surface of the filling material is substantially flush with the lowest bottom surface of the back metal layer. In one embodiment of the present invention, the top-view shape of the back-side through hole includes a circle, an ellipse, or a combination thereof. In one embodiment of the present invention, the diameter of the back-side through hole is between 30 μm and 60 μm, and the height of the back-side through hole is between 50 μm and 200 μm. In one embodiment of the present invention, the above-mentioned semiconductor element further includes: a drain electrode, configured on the semiconductor layer; and a gate electrode, configured on the semiconductor layer between the source electrode and the drain electrode, wherein the source electrode, the gate electrode and the drain electrode are covered by a dielectric material and are physically separated from each other by the dielectric material. In one embodiment of the present invention, the semiconductor device further includes: a second metal layer disposed on the first metal layer; and an air bridge buried between the first metal layer and the second metal layer. In one embodiment of the present invention, the first metal layer is configured to serve as a wafer probe test pad. In one embodiment of the present invention, the semiconductor device further comprises: a bonding wire bonded to the top surface of the first metal layer, wherein the backside via and the bonding wire are laterally offset such that the backside via does not overlap with the bonding wire when viewed from above. In one embodiment of the present invention, the source electrode completely overlaps with the first metal layer when viewed from above. In one embodiment of the present invention, the source electrode does not overlap with the back-side through hole when viewed from above. In one embodiment of the present invention, the backside metal layer includes a sputtered layer and an electroplated layer overlying the sputtered layer. In one embodiment of the present invention, the semiconductor layer is a GaN epitaxial layer. In summary, embodiments of the present invention separate the backside via from the source electrode laterally by a non-zero distance, ensuring that the backside via directly contacts the bottom surface of the first metal layer (e.g., M1) and is physically separated from the source electrode. In this manner, pressure from CP test probes and / or wire bonding does not damage the backside via, thereby improving device yield and reliability. Furthermore, embodiments of the present invention optionally incorporate a filler material (e.g., a metal or insulating material) into the hollow space formed by the backside via to increase the mechanical strength of the backside via and / or enhance heat dissipation performance. The present invention will be more fully described with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. Identical or similar reference numerals denote identical or similar elements and will not be redundantly described in the following paragraphs. Figure 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 2 is a schematic top view of a semiconductor device according to one embodiment of the present invention. The semiconductor device in the following embodiments is described using a high electron mobility transistor (HEMT) device as an example, but the present invention is not limited thereto. Referring to FIG. 1 , an embodiment of the present invention provides a semiconductor device 1 comprising a substrate 100, a semiconductor layer 102, a source electrode 104, a drain electrode 106, a gate electrode 108, first metal layers 114 and 116, and a backside metal layer 120. Specifically, the substrate 100 may have a front side 100a and a back side 100b opposite to each other. In one embodiment, the substrate 100 comprises a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, but the present invention is not limited thereto. The semiconductor layer 102 may be disposed on the front side 100a of the substrate 100. In one embodiment, the semiconductor layer 102 includes a Group III-V semiconductor, such as a gallium nitride (GaN) epitaxial layer. In one embodiment, the semiconductor layer 102 may be formed by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or the like. Furthermore, the semiconductor device 1 further includes an isolation structure 101 embedded within the semiconductor layer 102 and the substrate 100 to define an active region 103. In one embodiment, the isolation structure 101 may be a shallow trench isolation (STI) structure formed of silicon oxide. The source electrode 104, the drain electrode 106, and the gate electrode 108 may be disposed on the semiconductor layer 102. Specifically, the source electrode 104, the drain electrode 106, and the gate electrode 108 are laterally separated from each other, and the gate electrode 108 may be disposed on the semiconductor layer 102 between the source electrode 104 and the drain electrode 106. In one embodiment, the source electrode 104, the drain electrode 106, and the gate electrode 108 all comprise a metal material. For example, the source electrode 104, the drain electrode 106, and the gate electrode 108 may each comprise a metal material such as gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In this embodiment, the gate electrode 108 may be formed of a Schottky metal, while the source electrode 104 and the drain electrode 106 may be formed of an ohmic contact metal. In some embodiments, the source electrode 104 , the drain electrode 106 , and the gate electrode 108 may be formed by forming an electrode material using a plating process, a sputtering process, a resistance heating evaporation process, an electron beam evaporation process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or the like, and then patterning the electrode material. The first metal layer 114 can be disposed on and in contact with the source electrode 104 , while the first metal layer 116 can be disposed on and in contact with the drain electrode 106 . In one embodiment, both the first metal layers 114 and 116 include a metal material. For example, the first metal layers 114 and 116 can each include a metal material such as gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, the first metal layers 114 and 116 can be formed by forming the metal material using a plating process, a sputtering process, a resistance heating evaporation process, an electron beam evaporation process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or the like, and then patterning the metal material. In this embodiment, the first metal layers 114 and 116 can be considered first-level metal (M1). The dielectric material 110 may cover the source electrode 104, the drain electrode 106, the gate electrode 108, and the first metal layers 114 and 116, such that the source electrode 104, the drain electrode 106, the gate electrode 108, and the first metal layers 114 and 116 are physically separated from each other by the dielectric material 110. In one embodiment, the dielectric material 110 includes a first dielectric layer 112 and a second dielectric layer 118 disposed on the first dielectric layer 112. The first dielectric layer 112 and the second dielectric layer 118 may include different materials. For example, the first dielectric layer 112 may be a silicon nitride layer, and the second dielectric layer 118 may be a silicon oxide layer. However, the present invention is not limited thereto. In other embodiments, the first dielectric layer 112 and the second dielectric layer 118 may also include the same material, such as silicon oxide. In addition, the semiconductor device 1 further includes a backside via hole 105. The backside via hole 105 can extend from the back side 100b of the substrate 100 to the bottom surface of the first metal layer 114, and the backside via hole 105 and the source electrode 104 are laterally separated by a non-zero distance 107. Here, the non-zero distance 107 can be adjusted according to product requirements. As long as the backside via hole 105 can be physically separated from the source electrode 104 by the dielectric material 110, it is protected by the present invention. Specifically, the backside via hole 105 can penetrate the substrate 100, the semiconductor layer 102, and the dielectric material 110 to contact the first metal layer 114. In one embodiment, the height 105h of the backside via hole 105 is between 50 μm and 200 μm. Furthermore, a backside metal layer 120 may be disposed on the back side 100b of the substrate 100 and extend to cover the surface of the backside via 105. In one embodiment, the backside metal layer 120 may conformally cover the surface of the backside via 105 to form a hollow space within the backside via 105. In this case, the portion of the backside metal layer 120 that conformally covers the surface of the backside via 105 may serve as a backside conductive via 125. The backside conductive via 125 may electrically connect the first metal layer 114 and the backside metal layer 120, thereby transmitting the electrical signal from the source electrode 104 on the front side 100a of the substrate 100 to the back side 100b of the substrate 100 through the backside conductive via 125, thereby providing greater flexibility in metal routing. It is noteworthy that in this embodiment, the backside via 125 is laterally separated from the source electrode 104 by a non-zero distance 107, such that the backside via 125 directly contacts the bottom surface of the first metal layer 114 and is physically separated from the source electrode 104. In this case, the first metal layer 114 can be configured to function as a wafer probing (CP) test pad or a wire bond pad. Specifically, when a CP test probe and / or wire bond is applied to the first metal layer 114 through the opening 119, the CP test probe and / or wire bond will land on the first metal layer 114 directly above the source electrode 104. Therefore, pressure from the CP test probe and / or wire bond will not fall on the first metal layer 114 directly above the backside via 125, thereby protecting the backside via 125 from damage and improving the yield and reliability of the semiconductor device 1. In one embodiment, the backside metal layer 120 comprises a metal material, such as gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, the backside metal layer 120 can be formed using an electroplating process, a sputtering process, a resistance heating evaporation process, an electron beam evaporation process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or the like. For example, the backside metal layer 120 may include a sputtered layer and an electroplated layer overlying the sputtered layer. In one embodiment, the thickness of the backside metal layer 120 is between 4 μm and 6 μm. From top view 2, semiconductor device 1 may include a plurality of backside vias 125. Specifically, a portion of backside vias 125 may be laterally separated from source electrode 104 by a non-zero distance 107 and may directly contact the bottom surface of first metal layer 114. In one embodiment, source electrode 104 completely overlaps with first metal layer 114 when viewed from above, and source electrode 104 does not overlap backside vias 125 (or backside through-holes 105) when viewed from above. In other words, when a wire bond is made to the top surface of first metal layer 114, backside vias 125 are laterally offset from the wire bond, preventing them from overlapping when viewed from above, thereby preventing damage to backside vias 125. Another portion of backside vias 125 may be located at the first metal level (M1) of interconnect structure 115 to provide greater metal routing flexibility. Although the top-view shape of the backside via 125 (or backside through hole 105) depicted in FIG2 is elliptical, the present invention is not limited to this. In other embodiments, the top-view shape of the backside via 125 (or backside through hole 105) may also be elliptical or a combination of circular and elliptical. For example, the diameter of the backside via 125 is between 30 μm and 60 μm. For example, the major and minor axis lengths of the backside via 125 may be 60 μm and 30 μm, respectively, but the present invention is not limited to this. FIG3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The semiconductor device 2 in Figure 3 is similar to the semiconductor device 1 in Figure 1 . Similar components and configurations have been described in detail in the preceding paragraphs and will not be repeated here. The primary difference between semiconductor device 2 and semiconductor device 1 is that semiconductor device 2 further includes a second metal layer 240 and an air bridge 230 . Specifically, the second metal layer 240 may be disposed on and in contact with the first metal layer 114 . In one embodiment, one end of the second metal layer 240 is connected to the first metal layer 114 , while the other end of the second metal layer 240 is connected to the adjacent first metal layer 114 , thereby forming the air bridge 230 . In this embodiment, the air bridge 230 is filled with air, which has a dielectric constant close to 1. This effectively reduces the capacitance of the interconnect structure and reduces resistance-capacitance delay (RC delay), thereby improving device operating efficiency. The air bridge 230 may be defined by the first metal layer 114 and the second metal layer 240 . In other words, the air bridge 230 may be embedded between the first metal layer 114 and the second metal layer 240 . FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an alternative embodiment of the present invention. The semiconductor element 3 in FIG4 is similar to the semiconductor element 2 in FIG3 . Similar components and configurations have been described in detail in the above paragraphs and will not be repeated here. The main difference between the semiconductor element 3 and the semiconductor element 2 is that the semiconductor element 3 further includes a filling material 305. Since the back metal layer 120 conformally covers the surface of the back through hole 105, a hollow space can be formed in the back through hole 105. The filling material 305 can fill the hollow space so that the back metal layer 120 covers the filling material 305. In one embodiment, the back metal layer 120 and the filling material 305 are made of the same material, such as a metal material. In this case, the portion of the back metal layer 120 and the filling material 305 that conformally covers the surface of the back through hole 105 can be used as the back conductive hole 325. The backside via 325 electrically connects the first metal layer 114 and the backside metal layer 120, thereby transmitting the electrical signal from the source electrode 104 on the front side 100a of the substrate 100 to the back side 100b of the substrate 100 through the backside via 125, thereby providing greater metal wiring flexibility. It is worth noting that in this embodiment, the solid structure of the backside via 325 not only reduces the impedance of the backside via 325 but also enhances the mechanical strength of the backside via 325 and improves heat dissipation efficiency. Furthermore, the bottom surface 305bt of the filling material 305 can be substantially flush with the lowest bottom surface 120bt of the backside metal layer 120, facilitating subsequent connection to external components. However, the present invention is not limited to this. In other embodiments, the bottom surface 305bt of the filling material 305 can also be higher than the lowest bottom surface 120bt of the backside metal layer 120. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The semiconductor device 4 of FIG. 5 is similar to the semiconductor device 3 of FIG. 4 . Similar components and configurations have been described in detail in the preceding paragraphs and will not be repeated here. The primary difference between semiconductor device 4 and semiconductor device 3 is that the filler material 405 and the backside metal layer 120 of semiconductor device 4 are made of different materials. Specifically, the backside metal layer 120 is a metal material, while the filler material 405 is an insulating material, such as silicon nitride. In this case, the portion of the backside metal layer 120 and the filler material 405 that conformally covers the surface of the backside via 105 can serve as the backside conductive via 425. It is noteworthy that in this embodiment, the filler material 405 made of an insulating material can increase the mechanical strength of the backside conductive via 425. Furthermore, the bottom surface 405bt of the filler material 405 can be higher than the lowest bottom surface 120bt of the backside metal layer 120. However, the present invention is not limited thereto. In other embodiments, the bottom surface 405 bt of the filling material 405 may also be substantially flush with the lowest bottom surface 120 bt of the back metal layer 120 . In summary, embodiments of the present invention separate the backside via from the source electrode laterally by a non-zero distance, ensuring that the backside via directly contacts the bottom surface of the first metal layer (e.g., M1) and is physically separated from the source electrode. In this manner, pressure from CP test probes and / or wire bonding does not damage the backside via, thereby improving device yield and reliability. Furthermore, embodiments of the present invention optionally incorporate a filler material (e.g., a metal or insulating material) into the hollow space formed by the backside via to increase the mechanical strength of the backside via and / or enhance heat dissipation performance. Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent applications. 1, 2, 3, 4: Semiconductor device 100: Substrate 100a: Front side 100b: Back side 101: Isolation structure 102: Semiconductor layer 103: Active region 104: Source electrode 105: Backside via 105h: Height 106: Drain electrode 107: Non-zero distance 108: Gate electrode 110: Dielectric material 112: First dielectric layer 114, 116: First metal layer 115: Interconnect structure 118: Second dielectric layer 119: Opening 120: Backside metal layer 120bt: Lowest bottom surface 125, 325, 425: Backside via 230: Air bridge 240: Second metal layer 305, 405: Filling material 305bt, 405bt: Bottom surface FIG1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG2 is a schematic top view of a semiconductor device according to another embodiment of the present invention. FIG3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. FIG4 is a schematic cross-sectional view of a semiconductor device according to an alternative embodiment of the present invention. FIG5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 1: Semiconductor components 100: Base 100a: front side 100b: back 101: Isolation Structure 102: semiconductor layer 103: Active Zone 104: Source electrode 105: Back side through hole 105h: Height 106: Drain electrode 107: Non-zero distance 108: Gate electrode 110: Dielectric material 112: first dielectric layer 114, 116: first metal layer 115:Internal connection structure 118: second dielectric layer 119: Opening 120: Back metal layer 125: Backside via

Claims

1. A semiconductor element, comprising: The base has an anterior and a posterior side that are opposite to each other; A semiconductor layer is disposed on the front side of the substrate; The source electrode is disposed on the semiconductor layer; A first metal layer disposed on the source electrode; an opening formed on the top surface of the first metal layer and located directly above the source electrode, wherein the opening completely overlaps the first metal layer and the source electrode in an upward viewing angle; a back-side via extending from the back side of the substrate to the bottom surface of the first metal layer, wherein the back-side via is laterally separated from the source electrode by a non-zero distance; and a back-side metal layer disposed on the back side of the substrate and extending to cover the surface of the back-side via.

2. The semiconductor device as claimed in claim 1, wherein the back-side via is physically separated from the source electrode by a dielectric material.

3. The semiconductor element as claimed in claim 2, wherein the back-side via penetrates the substrate, the semiconductor layer, and the dielectric material to contact the first metal layer.

4. The semiconductor device of claim 1, wherein the back-side metal layer conformally covers the surface of the back-side via to form a hollow space in the back-side via.

5. The semiconductor element as described in claim 4, further comprising: The hollow space is filled with a filling material, so that the back metal layer covers the filling material.

6. The semiconductor element as claimed in claim 5, wherein the filler material includes an insulating material.

7. The semiconductor device as claimed in claim 5, wherein the filler material comprises a metallic material.

8. The semiconductor device as claimed in claim 5, wherein the filler material has the same material as the back metal layer.

9. The semiconductor element as claimed in claim 5, wherein the bottom surface of the filler material is higher than the lowest bottom surface of the back metal layer.

10. The semiconductor device of claim 5, wherein the bottom surface of the filler material is substantially flush with the lowest bottom surface of the back metal layer.

11. The semiconductor element of claim 1, wherein the top-view shape of the back-side via includes a circle, an ellipse, or a combination thereof.

12. The semiconductor device of claim 1, wherein the diameter of the back-side via is between 30 μm and 60 μm, and the height of the back-side via is between 50 μm and 200 μm.

13. The semiconductor element as claimed in claim 1, further comprising: A drain electrode is disposed on the semiconductor layer; And a gate electrode, disposed on the semiconductor layer between the source electrode and the drain electrode, wherein the source electrode, the gate electrode and the drain electrode are covered by a dielectric material and physically separated from each other by the dielectric material.

14. The semiconductor element as claimed in claim 1, further comprising: A second metal layer is disposed on the first metal layer; And an air bridge, embedded between the first metal layer and the second metal layer.

15. The semiconductor element as claimed in claim 1, wherein the first metal layer is configured to serve as a wafer probe test pad.

16. The semiconductor element as claimed in claim 1, further comprising: The wire bonding is applied to the top surface of the first metal layer, wherein the back-side via is laterally offset from the wire bonding such that the back-side via does not overlap with the wire bonding at the upward viewing angle.

17. The semiconductor device of claim 1, wherein the source electrode completely overlaps the first metal layer at the upward viewing angle.

18. The semiconductor device of claim 1, wherein the source electrode does not overlap with the back via at the upward viewing angle.

19. The semiconductor device of claim 1, wherein the back metal layer comprises a sputtered layer and an electroplated layer covering the sputtered layer.

20. The semiconductor device as claimed in claim 1, wherein the semiconductor layer is a GaN epitaxial layer.

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