Semiconductor structures, methods for forming the semiconductor structures, and apparatuses for performing the methods

Abstract

A method for forming a semiconductor structure including a gallium nitride dipole layer is disclosed. An exemplary method includes depositing a dipole layer including gallium nitride on a surface of a gate dielectric using a cyclic deposition process. The cyclic deposition process may include: providing a gallium precursor to a reaction chamber; and separately providing a nitrogen reactant to the reaction chamber. The cyclic deposition process may, if desired, be a thermal cyclic deposition process. Exemplary structures may include field-effect transistor structures, such as gate-all-around structures.

Description

Technical Field

[0001] This invention generally relates to a method for forming a semiconductor structure including a dipole layer, and more specifically, to a method for forming a semiconductor structure including a gallium nitride dipole layer. This invention also generally relates to structures including gallium nitride-based dipole layers. Prior Technology

[0002] Scaling of semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) devices, has led to significant improvements in the speed and density of integrated circuits. However, conventional device scaling techniques face significant challenges for future technology nodes.

[0003] For example, a persistent challenge has been finding a suitable conductive material for use as the gate electrode in CMOS devices. CMOS devices conventionally use n-type doped polysilicon as the gate electrode material. However, doped polysilicon may not be the ideal gate electrode material for advanced node applications. Although doped polysilicon is conductive, it may still have surface regions that can deplete the carrier under bias conditions. This region may appear as an added gate insulator thickness (commonly referred to as gate depletion) and can contribute an equivalent oxide thickness. Although the gate depletion region may be thin (on the order of several angstroms (Å), it can become significant as the gate oxide thickness decreases in advanced node applications. As another example, polysilicon does not exhibit an ideal effective work function (eWF) for both NMOS and PMOS devices. To overcome the non-ideal effective work function of doped polysilicon, threshold voltage adjustment implantation can be used. However, as device geometry decreases in advanced node applications, threshold voltage adjustment implantation processes may become increasingly complex and impractical.

[0004] To overcome the problems associated with doped polycrystalline silicon gate electrodes, alternative materials (such as those containing metal layers, such as titanium nitride layers) can be used to replace the polycrystalline silicon gate materials. Titanium nitride layers can provide a more desirable efficient work function for CMOS applications. However, in some cases where a higher work function value is required, such as in the PMOS region of CMOS devices, improved materials for the gate electrodes are needed.

[0005] Any discussion presented in this section, including discussions of problems and solutions, is included in this invention solely for the purpose of providing background context. Such discussions should not be construed as an admission that any or all information was known at the time of completion of this invention or otherwise constituted prior art. Summary of the Invention

[0006] The present invention can be presented in a simplified form to describe the following series of concepts, which can be described in more detail. The present invention is not intended to necessarily identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] Various embodiments of the present invention relate to methods for forming structures including, and specifically including, gallium nitride dipole layers. Dipole layers can be used in a variety of applications, including gate stack layers and logic (e.g., DRAM) electrode layer applications. As a specific example, gallium nitride dipole layers can be used as work function adjustment layers.

[0008] According to an exemplary embodiment of the present invention, a method for forming a metal-oxide-semiconductor (MOS) structure is disclosed. The exemplary method for forming an MOS structure includes: providing a substrate in a reaction chamber, the substrate including a gate dielectric; and performing one or more cycles of a cyclic deposition process to deposit a dipole layer including gallium nitride on a surface of the gate dielectric. The cyclic deposition process may include (e.g., sequentially and individually) providing a gallium precursor to the reaction chamber and providing a nitrogen reactant to the reaction chamber. The gallium precursor may include one or more of, for example, gallium β-diketone compounds, gallium alkoxide compounds, alkyl gallium compounds, alkyl acetylamine gallium compounds, gallium halide compounds, and gallane compounds. The gallium precursor may also include one or more of, for example, trimethylamine gallium, acetylacetonate gallium(III), isopropanol dimethyl gallium, gallium monochloride, triethyl gallium, and trimethyl gallium. Nitrogen reactants may include, for example, one or more of ammonia, hydrazine, substituted hydrazine derivatives, and nitrogen-based plasma. In certain instances, nitrogen reactants may include one or more of substituted hydrazine derivatives, such as tributylhydrazine, methylhydrazine, dimethylhydrazine, and diethylhydrazine.

[0009] Cyclic deposition processes may include one or more of an atomic layer deposition process and a cyclic chemical vapor deposition process. Cyclic deposition processes may include a thermal process, i.e., a process that does not use plasma activation agents. In some cases, a reactant may be exposed to a plasma to form an activated reactant agent.

[0010] According to an exemplary embodiment, the metal-oxide-semiconductor structure may include a gate-all-around transistor. Furthermore, the average film thickness of the gallium nitride dipole layer may be between 5 angstroms and 15 angstroms, and the gallium nitride dipole layer may induce a threshold voltage transition of gallium nitride per angstrom thickness between 5 mV and 100 mV.

[0011] In an exemplary embodiment, a method of forming a metal-oxide-semiconductor (MOS) structure may include depositing a gallium nitride (GaN)-containing dipole layer onto a surface of a gate dielectric. In a particular exemplary embodiment, the surface of the gate dielectric may include at least one of a high-k dielectric surface or a silicon oxide surface, and the GaN-containing dipole layer may be deposited directly onto the surface of the gate dielectric. In other exemplary embodiments, a method of forming a MOS structure may include performing one or more cycles of an initial deposition process prior to depositing the GaN-containing dipole layer to deposit an initial dipole layer containing gallium oxide onto the surface of the gate dielectric. According to some embodiments, the GaN-containing dipole layer may be deposited directly on the initial GaO-containing dipole layer, and the initial GaO-containing dipole layer may be deposited directly onto a surface of the gate dielectric. For example, an average film thickness of the initial GaO-containing dipole layer may be between 5 angstroms and 15 angstroms.

[0012] According to other exemplary embodiments of the present invention, a semiconductor structure may be formed using the methods described herein. The semiconductor structure may include: a substrate including a gate dielectric; and a dipole layer comprising gallium nitride, formed to cover a surface of the gate dielectric. The exemplary semiconductor structure may further include additional layers, such as additional metal-containing or conductive layers covering one or more dipole layers. The exemplary semiconductor structure may further include one or more insulating or dielectric layers under the dipole layers. The structure may be a metal-oxide-semiconductor (MOS) structure or a portion thereof, such as one or more of PMOS and NMOS structures, or other device structures. The structure may also be a MOS device structure or a portion thereof forming a gate stack for a MOS device structure, such as a gate-all-around transistor.

[0013] According to yet another embodiment of the invention, a device or a portion thereof can be formed using the methods and / or structures described herein. The device may include a substrate, one or more insulating or dielectric layers, a gallium nitride dipole layer (covering one or more insulating or dielectric layers), and an additional metal layer (covering the dipole layer). The device may be, for example, a CMOS device or a portion thereof. In other additional embodiments, a device may further include an initial dipole layer containing gallium oxide, covering one or more insulating or dielectric layers. In such additional embodiments, the device may include a gallium nitride layer covering the gallium oxide layer; and may further include an additional metal layer covering the gallium nitride dipole layer.

[0014] According to other additional embodiments of the invention, an apparatus is disclosed that is configured to perform the methods described herein and / or form part of a structure, device, or either.

[0015] Those skilled in the art will readily understand these and other embodiments from the following detailed description of certain embodiments with reference to the accompanying drawings. The invention is not limited to any of the specific embodiments disclosed. Simple Explanation of the Diagram

[0016] A more complete understanding of embodiments of the invention can be obtained by considering the following illustrative drawings in conjunction with the detailed description and the claims. Figures 1A and 1B illustrate a method according to an exemplary embodiment of the invention; and Figures 2 and 3 illustrate an exemplary structure according to an embodiment of the invention. It will be understood that the components in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some components in the figures may be enlarged relative to other components to aid in understanding the embodiments of the invention illustrated. Implementation

[0017] The descriptions of exemplary embodiments of methods, structures, apparatuses, and devices provided below are merely illustrative and intended for illustrative purposes only; the following descriptions are not intended to limit the scope of the invention or the claims. Furthermore, the reference to multiple embodiments having the stated features is not intended to exclude other embodiments having additional features or other embodiments combining different combinations of the stated features. For example, various embodiments are presented as exemplary embodiments and may be enumerated in the appendix. Unless otherwise indicated, exemplary embodiments or components thereof may be combined or used separately from each other.

[0018] As described in more detail below, various embodiments of the present invention provide methods for forming structures suitable for a variety of applications. For example, exemplary methods can be used to form a gallium nitride dipole layer suitable for metal-oxide-semiconductor (MOS) applications, such as in the formation of complementary MOS (CMOS) devices. For example, gallium nitride dipole layers can be used to form logic devices, dynamic random-access memory (DRAM), and three-dimensional NAND devices. However, unless otherwise stated, the present invention is not necessarily limited to such examples.

[0019] In this invention, "gas" may include materials, vaporized solids, and / or vaporized liquids that are gases at normal temperature and pressure (NTP), and may consist of a single gas or a mixture of gases depending on the context. Gases other than process gases (i.e., gases not introduced through a gas distribution assembly, other gas distribution device, or the like) may be used, for example, to seal the reaction space, and may include sealing gases (such as rare gases). In some cases, the term "precursor" may refer to a compound that participates in a chemical reaction to produce another compound, and specifically, a compound that constitutes the thin film matrix or the main body of the thin film; the term "reactant" may be used interchangeably with the term "precursor." The term "inert gas" may refer to a gas that does not participate in a chemical reaction and / or does not become part of the thin film matrix to a considerable extent. Several exemplary inert gases include helium, argon, and any combination thereof. In some cases, inert gases may include nitrogen and / or hydrogen.

[0020] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or thin films can be formed. A substrate may include bulk materials such as silicon (e.g., single-crystal silicon); other group IV materials such as germanium; or other semiconductor materials such as group II-VI or III-V semiconductor materials, and may include one or more layers covering above or below the bulk material. Furthermore, a substrate may include various features such as recesses, protrusions, and the like, formed within or on at least a portion of one layer of the substrate. As an example, a substrate may include a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material.

[0021] As used herein, the terms "film" and / or "layer" can refer to any continuous or discontinuous structure and material, such as materials deposited by the methods disclosed herein. For example, films and / or layers can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers, or partial or complete atomic layers, or atomic and / or molecular clusters. Films or layers may contain materials or layers with pinholes, and may be at least partially continuous.

[0022] As used herein, "structure" may refer to or include a substrate as described herein. A structure may include one or more layers covering or within a substrate, such as one or more layers formed according to the methods described herein. All or part of the means may be included within or on the structure.

[0023] The term "cyclic deposition process" or "cyclical deposition process" can refer to the process of sequentially introducing precursors (and / or reactants) into a reaction chamber to deposit a layer on a substrate, and includes process technologies such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes that include ALD components and cyclic CVD components.

[0024] The term "atomic layer deposition" can refer to a vapor deposition process in which deposition cycles (typically multiple consecutive deposition cycles) are performed in a process chamber. When performed with alternating pulses of one or more precursor / reactive gases and one or more purging (e.g., inert carrier) gases, the term atomic layer deposition, as used herein, also means processes specified by related terms such as chemical vapor deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy.

[0025] Typically, for ALD processes, during each deposition cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the deposition surface (e.g., a substrate surface containing previously deposited material or other materials from a previous ALD cycle), forming a monolayer or submonolayer material that is not readily reacting with additional precursors (i.e., a self-limiting reaction). Subsequently, in some cases, reactants (e.g., another precursor or reactive gas) may be introduced into the process chamber to convert the chemisorbed precursor into the desired material on the deposition surface. The reactants may be able to further react with the precursor. Any excess precursor can be removed from the process chamber and / or any excess reactants and / or reaction byproducts from the reaction chamber during one or more deposition cycles (e.g., during each step of each cycle).

[0026] As used herein, the term "dipole layer" can refer to one or more material layers that, when formed in, on, or above the gate dielectric of a metal-oxide-semiconductor (MOS) structure, induce a change in the effective work function of the MOS structure. For example, a change in the effective work function of an MOS structure may result in a threshold voltage change in a transistor containing the MOS structure.

[0027] As used herein, "gallium nitride" is a material that can be represented by a chemical formula including gallium and nitrogen. In some embodiments, gallium nitride may not include elements other than gallium and nitrogen in significant proportions. In some embodiments, gallium nitride comprises GaN. In some embodiments, gallium nitride may consist substantially of GaN. In some embodiments, gallium nitride may consist of gallium nitride. A layer composed of gallium nitride may include acceptable amounts of impurities (such as hydrogen, carbon, chlorine and / or the like) that may be derived from one or more precursors used to deposit gallium nitride.

[0028] As used herein, "gallium oxide" is a material that can be represented by a chemical formula including gallium and oxygen. In some embodiments, gallium oxide may not include elements other than gallium and oxygen in significant proportions. In some embodiments, gallium oxide comprises GaO x. In some embodiments, gallium oxide may consist substantially of GaO x. In some embodiments, gallium oxide may consist of gallium oxide. A layer consisting of gallium oxide may include acceptable amounts of impurities (such as hydrogen, carbon, chlorine and / or the like) that may be derived from one or more precursors used for depositing gallium nitride.

[0029] As used herein, "gallium precursor" includes gases or materials that can be converted into a gaseous state and can be represented by a chemical formula including gallium.

[0030] The term "nitrogen reactant" can refer to a gas or material that can be converted into a gaseous state and can be represented by a chemical formula including nitrogen. In some cases, the chemical formula includes both nitrogen and hydrogen. In some cases, nitrogen reactants do not include diatomic nitrogen.

[0031] As used herein, the term "gate-all-around transistor" or "GAA transistor" can refer to a form of metal-oxide-semiconductor (MOS) device, which may include a gate structure (gate stack) where the gate structure contacts the conductive channel region on all sides, i.e., the gate stack surrounds the conductive channel region. As used herein, the term "gate-all-around transistor" can also refer to various device architectures, such as nanosheet devices, fork-shaped devices, vertical field-effect transistors, stacked device architectures, etc.

[0032] Furthermore, in this invention, any two numbers of a variable can constitute a feasible range of the variable, and any indicated range may include or exclude endpoints. Additionally, any numerical value of the indicated variable (regardless of whether such values ​​are prefixed with "about") may refer to an exact value or an approximate value, including equivalent values, and may refer to averages, medians, representative values, multi-values, etc. Furthermore, in some embodiments of this invention, the terms "comprising," "consisting of," and "having" individually mean "typically or broadly comprising," "including," "substantially composed of," or "consisting of." In some embodiments of this invention, any defined meaning does not necessarily exclude the general and conventional meaning.

[0033] In this specification, the terms "on" or "over" should be understood as describing relative positional relationships. Another component, membrane, or layer may be directly on the mentioned layer, or another layer (intermediate layer) or element may be inserted therebetween, or a layer may be disposed on the mentioned layer but not completely cover the surface of the mentioned layer. Therefore, unless the term "directly" is used alone, the terms "on" or "over" will be interpreted as relative concepts. Similarly, the terms "under," "underlying," or "below" will be understood as relative concepts.

[0034] This invention may include a method for forming a semiconductor structure comprising a gallium nitride dipole layer. More specifically, a dipole layer may be employed within the gate stack of a metal-oxide-semiconductor (MOS) device to modulate the effective work function (EWF) of the overall gate stack, thereby improving the performance of the MOS device. In some embodiments, the dipole layer may be formed, for example, on or directly thereon the gate dielectric of the MOS device by a deposition process, and the properties of the dipole layer (including, but not limited to, material composition, thickness, and deposition method) may alter the band alignment in the MOS device to provide better operating performance. In certain embodiments, a change in the thickness of the dipole layer disposed on the gate dielectric of the MOS device may induce a significant change in the threshold voltage of the MOS device. Therefore, in some embodiments, a dipole layer that is relatively inert to thickness variations that may be induced by subsequent MOS device fabrication processes may be required.

[0035] Therefore, the present invention may include a method for forming a semiconductor structure. In some embodiments, the method may include: providing a substrate including a gate dielectric in a reaction chamber; and performing one or more deposition cycles of a cyclic deposition process to deposit a gallium nitride-containing dipole layer on the surface of the gate dielectric. For example, the cyclic deposition process may include: providing a gallium precursor to the reaction chamber; and providing a nitrogen reactant to the reaction chamber.

[0036] More specifically, Figure 1A illustrates an exemplary method 100 for forming a semiconductor structure comprising a gallium nitride dipole layer. In short, method 100 may include the steps of: providing a substrate in a reaction chamber of a reactor (step 102); and depositing a gallium nitride dipole layer onto a surface of the substrate using a cyclic deposition process (step 104), and specifically, depositing the dipole layer on the surface of a gate dielectric. In some embodiments, the surface of the gate dielectric may comprise at least one of a high-k dielectric surface or a silicon oxide surface.

[0037] More specifically, exemplary method 100 may include step 102, which includes providing a substrate within a reaction chamber. The reaction chamber used in step 102 may be or include the reaction chamber of a chemical vapor deposition reactor system configured to perform a deposition process. The deposition process may be a chemical vapor deposition process and / or a cyclic deposition process. The reaction chamber may be a single reaction chamber or part of a clustering tool. The reaction chamber may be a batch processing tool. In some embodiments, a flow reactor may be used. In some embodiments, a showerhead reactor may be used. In some embodiments, a space-separated reactor may be used. In some embodiments, a single-wafer reactor capable of mass production may be used. In other embodiments, a batch reactor comprising multiple substrates may be used. For embodiments in which a batch reactor is used, the number of substrates may range from 10 to 200, or 50 to 150, or even from 100 to 130. The reactor may be configured as a thermal reactor (without plasma excitation equipment). Alternatively, the reactor may include direct and / or remote plasma equipment.

[0038] The substrate placed in the reaction chamber can be heated to the required deposition temperature for subsequent deposition. For example, the substrate can be heated to a temperature below about 800°C, or below about 600°C, or below about 400°C, or even below about 200°C. In some embodiments of the invention, the substrate temperature during step 102 can be greater than room temperature, between about 200°C and 800°C, or between about 200°C and 600°C, or between about 200°C and 400°C. The temperature during step 104 (i.e., the cyclic deposition process) can also be within these ranges.

[0039] In addition to controlling the temperature of the substrate, the pressure in the reaction chamber can also be adjusted to achieve the deposition of the desired dipole layer. For example, in some embodiments of the present invention, the pressure in the reaction chamber may be less than 760 Torr, or between 0.1 Torr and 10 Torr, or between 0.5 Torr and 5 Torr, or between 1 Torr and 4 Torr.

[0040] Once the substrate temperature has been set to the desired deposition temperature and the required pressure in the reaction chamber has been adjusted as needed, method 100 may continue to step 104, which includes depositing a gallium nitride-containing dipole layer onto the surface of the substrate using a cyclic deposition process. For example, embodiments of the present invention may include performing one or more deposition cycles of a cyclic deposition process to deposit a gallium nitride-containing dipole layer onto the surface of the substrate, and specifically onto the surface of the gate dielectric.

[0041] Figure 1B illustrates an exemplary cyclic deposition process of step 104 and its constituent sub-steps 104A and 104B for depositing the dipole layer of the present invention. In short, the cyclic deposition process 104 (Figure 1B) may include providing a gallium precursor to the reaction chamber (sub-step 104A) and providing a nitrogen reactant to the reaction chamber (sub-step 104B). With or without an interventional reaction chamber rinsing sequence, the gallium precursor and nitrogen reactant may be provided to the reaction chamber individually and / or sequentially. Sub-steps 104A and 104B (and any interventional rinsing sequence) may constitute a deposition cycle, and the deposition cycle may be repeated one or more times to deposit a gallium nitride-containing dipole layer on the substrate (and specifically on the gate dielectric) to the desired thickness.

[0042] More specifically, substep 104A includes providing a gallium precursor to the reaction chamber. The gallium precursor may be applied to the reaction chamber in a pulsed manner. The term "pulse" can be understood as including feeding the precursor into the reaction chamber for a predetermined amount of time. Unless otherwise stated, the term "pulse" does not limit the length or duration of the pulse, and the pulse can be of any duration. The gallium precursor pulse may be supplied to the reaction chamber along with a carrier gas flow. In some embodiments, the gallium precursor may comprise a volatile gallium species that is reactive with one or more surfaces of the substrate. The gallium precursor pulse may self-saturate the substrate surface, such that excess components of the gallium precursor pulse will not further react with the molecular layer formed by this process.

[0043] Gallium precursor pulses are preferably supplied as gas-phase reactants. For the purposes of this invention, gallium precursors can be considered "volatile" if the species exhibits sufficient vapor pressure under process conditions to deliver the species to the substrate surface at a sufficient concentration to saturate the exposed surface.

[0044] According to some embodiments of the present invention, gallium precursors may include one or more of gallium halide compounds, gallium oxyhalide compounds, gallium organometallic compounds, gallium metal organometallic compounds, or the like.

[0045] In some embodiments of the present invention, the gallium precursor may comprise one or more of β-diketone gallium compounds, gallium alkoxide compounds, alkyl gallium compounds, alkylacetyl gallium compounds, gallium halide compounds, and gallium alkane compounds. For example, the gallium precursor may comprise one or more β-diketone gallium compounds, such as triacetyl gallium acetonitrile and triacetyl(2,2,6,6-tetramethyl-3,5-heptadecyl)gallium(III). The gallium precursor may also comprise one or more alkyl gallium compounds, such as triethyl gallium (TEG) and trimethyl gallium (TMG). For example, the gallium precursor may also comprise one or more alkylacetyl gallium compounds, such as triacetyl(dimethylacetyl)gallium (TDMAGa). The gallium precursor may comprise one or more gallium halide compounds, such as gallium monochloride, gallium trichloride, gallium tribromide, and gallium triiodide.

[0046] As a non-limiting example, gallium precursors may include trimethylamine gallium, acetylacetonate gallium(III) (Ga(acac)3), gallium alkoxide (such as isopropanol dimethyl gallium), and / or alkyl gallium (such as trimethyl gallium (TMGa)). In some embodiments, gallium carboxylates may be used as precursors, such as gallium triacetate or gallium tripropionate.

[0047] In some embodiments of the present invention, gallium precursors may be pulsed onto the reaction chamber for a duration sufficient to form a gallium monolayer or sub-monolayer on the surface of the substrate. In some embodiments, excess gallium precursors may be flushed away by stopping the gallium precursor flow while continuing to flow carrier gas, flushing gas, or mixed gas for a sufficient time to diffuse from or flush away excess precursors and any reactant byproducts from the reaction chamber. The supply and removal of gallium precursors may be considered as the first stage or "gallium stage" of the cyclic deposition process 104 (FIG. 1B).

[0048] The cyclic deposition process 104 (Figure 1B) can be continued by supplying nitrogen reactants to the reaction chamber (sub-step 104B). Exemplary nitrogen reactants may be selected from one or more of the following: ammonia (NH₃), hydrazine (N₂H₄), other nitrogen and hydrogen-containing gases (e.g., a mixture of nitrogen and hydrogen) and the like. Nitrogen reactants may include nitrogen and hydrogen or consist of nitrogen and hydrogen. In some cases, nitrogen reactants do not include diatomic nitrogen.

[0049] In some embodiments, the nitrogen reactant comprises a substituted hydrazine compound. For example, during sub-step 104B, a nitrogen reactant comprising a substituted hydrazine compound may be provided to the reaction chamber. In some embodiments, the substituted hydrazine compound may comprise an alkyl hydrazine selected from the group consisting of: tert-butylhydrazine (C4H9N2H3), methylhydrazine (CH3NHNH2), dimethylhydrazine (C2H8N2), and diethylhydrazine (C4H12N2). In some embodiments of the invention, the substituted hydrazine compound may comprise one or more of the following: 1,1-diethylhydrazine, 1-ethyl-1-methylhydrazine, isopropylhydrazine, phenylhydrazine, 1,1-diphenylhydrazine, 1,2-diphenylhydrazine, N-methyl-N-phenylhydrazine, 1,1-diphenylhydrazine, 1,2-diphenylhydrazine, 1-ethyl-1-phenylhydrazine, 1-methyl-1-(m-tolyl)hydrazine, and 1-ethyl-1-(p-tolyl)hydrazine.

[0050] In some embodiments, the nitrogen reactant may be pulsed into the reaction chamber as previously described with respect to gallium precursors, and after sufficient time has been allowed to fully saturate the previously absorbed molecular layer and allow it to react with the nitrogen reactant, excess reactant and reaction byproducts may be removed from the reaction chamber. Similar to the removal of gallium precursor reactants, this step may include stopping the flow of nitrogen reactant into the reaction chamber while continuing the flow of a carrier gas, purge gas, or mixture of gases for a sufficient time to diffuse or purge excess reactant and reactant byproducts (if present) from the reaction chamber.

[0051] In some embodiments of the invention, the cyclic deposition process 104 (FIG. 1B) includes a deposition cycle comprising (1) providing a gallium precursor to a reaction chamber (sub-step 104A) and (2) providing a nitrogen reactant to a reaction chamber (sub-step 104B), with rinsing or moving steps following steps (1) and / or (2), depending on the circumstances. The deposition cycle may be repeated multiple times, the number of repetitions depending on, for example, the required thickness of the dipole layer to be deposited (e.g., the required thickness of a gallium nitride dipole layer). For example, if the thickness of the gallium nitride dipole layer is less than the thickness required for a particular application, the steps of providing the gallium precursor to the reaction chamber and providing the nitrogen reactant to the reaction chamber may be repeated one or more times. Once the gallium nitride-containing dipole layer has been deposited to the required thickness, the substrate may undergo additional processes to form the desired structure and / or, for example, a device such as a metal-oxide-semiconductor device.

[0052] In some embodiments, method 100 may include performing multiple deposition cycles of cyclic deposition process 104 to deposit a gallium nitride-containing dipole layer on the surface of a gate dielectric. For example, repeated deposition cycles may deposit a gallium nitride-containing dipole layer with an average layer thickness between about 5 Å and about 15 Å. Furthermore, the gallium nitride-containing dipole layer may be deposited on the gate dielectric, wherein the step coverage is equal to or greater than about 50%, or greater than about 80%, or greater than about 90%, or about 95%, or about 98%, or about 99%, or higher.

[0053] Although the exemplary cyclic deposition process 104 (Figure 1B) is generally referred to herein as beginning with a gallium stage, it may be considered in other embodiments that the deposition cycle may begin with a nitrogen stage. Those skilled in the art will recognize that the first precursor stage typically follows the capping reaction left by the final stage in the previous cycle. Therefore, if nitrogen is the first stage in the deposition cycle, although no reactant may be pre-absorbed on the substrate surface or present in the reaction chamber, the reactive species stage will still effectively follow the gallium stage in subsequent cycles. In some embodiments, method 100 provides one or more different cycles (e.g., different numbers, precursors, flow rates, or the like).

[0054] According to some embodiments of the present invention, the cyclic deposition process 104B (FIG. 1B) may include a thermal deposition process. For example, the cyclic deposition process 104 may include one or more of a thermal atomic layer deposition process or a thermal cyclic chemical vapor deposition process. In such cases, the thermal cyclic deposition process does not include the use of plasma to form activated species for use in the cyclic deposition process. For example, the cyclic deposition process may not include the formation or use of nitrogen plasma, may not include the formation or use of excited nitrogen species, and / or may not include the formation or use of nitrogen free radicals.

[0055] Alternatively, according to some embodiments of the invention, such as by generating nitrogen-based plasma, the plasma can be used during step 104 to form an activated species (or reactant) for depositing a gallium nitride-containing dipole layer.

[0056] In some embodiments, method 100 (FIG. 1A) may include additional steps. As a non-limiting example, method 100 may include additional steps prior to the cyclic deposition of the gallium nitride dipole layer and / or additional steps after the cyclic deposition of the gallium nitride dipole layer.

[0057] In some embodiments, method 100 may include additional steps prior to the cyclic deposition of a gallium nitride dipole layer. As a non-limiting example, the additional steps of method 100 prior to depositing the gallium nitride dipole layer may include depositing an initial dipole layer directly onto the surface of a substrate. In some embodiments, the initial dipole layer may comprise a gallium oxide dipole layer deposited via an initial cyclic deposition process, and the gallium oxide dipole layer may be deposited directly onto the surface of a gate dielectric. In these embodiments, method 100 may further include performing one or more deposition cycles of an initial cyclic deposition process to deposit an initial dipole layer comprising gallium oxide on the surface of a gate dielectric prior to depositing a gallium nitride-containing dipole layer. Method 100 may further include depositing the gallium nitride-containing dipole layer directly onto the gallium oxide-containing initial dipole layer.

[0058] In some embodiments, method 100 may include additional steps following the cyclic deposition of a gallium nitride dipole layer. As a non-limiting example, the additional steps of method 100 after depositing the gallium nitride dipole layer may include depositing a metal-containing layer directly on the gallium nitride-containing dipole layer, wherein the metal-containing layer is deposited using a halide-containing metal precursor.

[0059] Figure 2 illustrates a portion of the structure of a device 200 according to an additional embodiment of the present invention. The device or structure 200 includes a substrate 202, a dielectric or insulating material 205, and a gallium nitride dipole layer 208. In the illustrated example, structure 200 also includes, for example, an additional conductive layer 210 containing a metal layer.

[0060] The substrate 202 may be or include any of the substrate materials described herein.

[0061] The dielectric or insulating material 205 may include one or more dielectric or insulating material layers. As an example, the dielectric or insulating material 205 may include an interface layer 204 and a high-k material 206 deposited to cover the interface layer 204. In some cases, the interface layer 204 may be absent or may be present only to a perceptible degree. The interface layer 204 may include an oxide (such as silicon oxide), which may be formed on the surface of the substrate 202 using, for example, a chemical oxidation process or an oxide deposition process. The high-k material 206 may be, for example, a metallic oxide having a dielectric constant greater than about 7. In some embodiments, the high-k material has a dielectric constant greater than that of silicon oxide. Exemplary high-k materials include one or more of the following: hafnium oxide (HfO 2), tantalum oxide (Ta 2O 5), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium silicate (HfSiO x), aluminum oxide (Al 2O 3), lanthanum oxide (La 2O 3), and mixtures / layers containing one or more of these layers.

[0062] The gallium nitride-containing dipole layer 208 can be formed according to the process described herein. In some cases, the dipole layer (208) may have a stoichiometric composition. The work function and other properties of the gallium nitride-containing dipole layer 208 can be altered by changing the deposition parameters during deposition cycles.

[0063] The gallium nitride dipole layer 208 may include impurities (such as halides, hydrogen and the like) in amounts, alone or in combination, less than 1 atomic percent, less than 0.2 atomic percent, less than 0.1 atomic percent, or less than 0.05 atomic percent.

[0064] The average layer thickness of the gallium nitride dipole film 208 can be varied depending on the desired application. In some exemplary embodiments, the average layer thickness of the gallium nitride dipole layer can be between about 5 Å and about 15 Å.

[0065] The structure / part of device 200 may further include an additional conductive layer 210, such as a metal such as a high-melting-point metal or the like. As an example, conductive layer 210 may be or include one or more of the following: titanium nitride; vanadium nitride; a metal stack including titanium nitride and metals (e.g., W, Co, Ru, Mo) or titanium nitride, titanium aluminum carbon and titanium nitride; tungsten; tungsten nitride carbon; cobalt; copper; molybdenum; ruthenium; or the like.

[0066] Although the gallium nitride dipole layer 208 is described as covering the dielectric or insulating material 205, in some cases, the dipole layer 208 may additionally or alternatively be formed directly on the substrate 202 (which may include various layers and / or topologies) and / or under the dielectric or insulating material 205, between the interface layer 204 and the high-k material 206 and / or between layers of the high-k material 206.

[0067] In some embodiments, the gallium nitride dipole layer 208 can induce a threshold transition in a MOS-type device fabricated with the structure illustrated in FIG2. In some embodiments, the gallium nitride dipole layer can induce a threshold voltage transition between 5 mV and 100 mV per angstrom of the gallium nitride dipole layer thickness. In some embodiments, the effective work function of a device having a gallium nitride dipole layer deposited according to the method of the present invention can transition from about 30 meV to about 400 meV, or from about 30 meV to about 200 meV, or from about 50 meV to about 100 meV. The thickness and / or composition of the gallium nitride dipole layer 208 can be manipulated to obtain the desired work function and / or threshold voltage transition.

[0068] Figure 3 illustrates another structure 300 according to an example of the present invention. Structure 300 is suitable for gate-all-around field-effect transistor (GAA FET) devices (also known as lateral nanowire FETs) and the like. In the illustrated example, structure 300 includes a semiconductor material 302, a dielectric material 304, a gallium nitride dipole layer 306, and a conductive layer 308. Structure 300 can be formed as a cover substrate, including any substrate material as described herein.

[0069] Semiconductor material 302 may include any suitable semiconductor material. For example, semiconductor material 302 may include group IV, group III-V, or group II-VI semiconductor materials. As an example, semiconductor material 302 includes silicon.

[0070] The dielectric material 304, gallium nitride dipole layer 306, and conductive layer 308 may be the same as or similar to the dielectric or insulating material 205, gallium nitride dipole layer 208, and conductive layer 210 described above. According to other embodiments of the invention, the gallium nitride dipole layer 406 may be formed covering the semiconductor material 302 and / or under the dielectric material 304.

[0071] Embodiments of the present invention may further include semiconductor structures formed according to the methods described herein.

[0072] Embodiments of the present invention may further include devices configured to perform the methods as described herein.

[0073] The exemplary embodiments of the invention described above do not limit the scope of the invention, as these embodiments are merely examples of embodiments of the invention, as defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the invention. In fact, in addition to what is shown and described herein, various modifications to this disclosure, such as alternative and useful combinations of components, will become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

[0074] 100: Method 102: Steps 104: Steps 104A: Sub-step 104B: Sub-step 200: Device 202:Substrate 204: Interface Layer 205: Dielectric or insulating material 206: High-k materials 208: Dipole layer 210: Additional conductive layer 300: Structure 302: Semiconductor Materials 304: Dielectric material 306: Gallium nitride dipole layer 308: Conductive layer

Claims

1. A method of forming a semiconductor structure, comprising: providing a substrate in a reaction chamber, the substrate including a gate dielectric; and performing one or more deposition cycles of a cyclic deposition process to deposit a dipole layer including gallium nitride on a surface of the gate dielectric, wherein the cyclic deposition process includes: providing a gallium precursor to the reaction chamber; and providing a nitrogen reactant to the reaction chamber.

2. The method of claim 1, wherein the gallium precursor comprises one or more of a β-diketone gallium compound, an alkane gallium oxide compound, an alkyl gallium compound, an alkylacetyl gallium compound, a gallium halide compound, and a gallium alkane compound.

3. The method of claim 1, wherein the gallium precursor comprises one or more of trimethylamine gallium, acetylacetonate gallium (III), isopropanol dimethyl gallium, gallium monochloride, gallium trichloride, gallium triiodide, triethyl gallium, and trimethyl gallium.

4. The method of claim 1, wherein the nitrogen reactant comprises one or more of ammonia, hydrazine, a substituted hydrazine derivative, and a nitrogen-based plasma.

5. The method of claim 4, wherein the substituted hydrazine derivative comprises one or more of tert-butylhydrazine, methylhydrazine, dimethylhydrazine, and diethylhydrazine.

6. The method of claim 1, wherein the cyclic deposition process comprises one or more of a thermal atomic layer deposition process or a thermal cyclic chemical vapor deposition process.

7. The method of claim 1, wherein the semiconductor structure includes a gate-all-around transistor.

8. The method of claim 1, wherein the average layer thickness of one of the gallium nitride dipole layers is between 5 Å and 15 Å.

9. The method of claim 1, wherein the gallium nitride dipole layer induces a threshold voltage transition of the gallium nitride at a thickness per Å between 5 mV and 100 mV.

10. The method of claim 1, further comprising: depositing a metal-containing layer directly on the dipole layer comprising gallium nitride, wherein the metal-containing layer is deposited using a halide-containing metal precursor.

11. The method of claim 1, wherein the surface of the gate dielectric comprises at least one of a high-k dielectric surface or a silicon oxide surface.

12. The method of claim 1, wherein the dipole layer comprising gallium nitride is directly deposited on the surface of the gate dielectric.

13. The method of claim 1, further comprising: performing one or more deposition cycles of an initial deposition process prior to depositing the dipole layer comprising gallium nitride to deposit an initial dipole layer comprising gallium oxide on the surface of the gate dielectric.

14. The method of claim 13, wherein the dipole layer comprising gallium nitride is deposited directly on the initial dipole layer comprising gallium oxide.

15. The method of claim 13, wherein the average film thickness of one of the initial dipole layers of gallium oxide is between 5 Å and 15 Å.

16. A semiconductor structure formed according to any one of claims 1 to 15.

17. An apparatus configured to perform the method of any one of requests 1 to 15.

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