Edmos and fabricating method of the same

Abstract

An extended drain-type metal-oxide-semiconductor transistor includes a substrate, a gate disposed on the substrate, a source doped region disposed in the substrate on one side of the gate, a drain doped region disposed in the substrate on the other side of the gate, a thin gate dielectric layer disposed below the gate, a thick gate dielectric layer disposed below the gate, wherein the thick gate dielectric layer extends from below the gate to contact the drain doped region, a first well region of a second conductivity type is disposed in the substrate and surrounds the source doped region and the drain doped region, and a deep well region is disposed in the substrate and surrounds the first well region of the second conductivity type.

Description

Extended Drain Metal Oxide Semiconductor Transistor and Fabrication Method Thereof The present invention relates to an extended drain metal oxide semiconductor transistor (EDMOS) and a fabrication method thereof, and particularly to a transistor having a thick gate dielectric layer disposed between a gate and a drain doping region and a fabrication method thereof. Common high-voltage components include vertical double-diffused metal oxide semiconductors, lateral double-diffused metal oxide semiconductor transistor components, and extended drain metal oxide semiconductor transistors. Compared with lateral double-diffused metal oxide semiconductors, extended drain metal oxide semiconductors have relatively high on-resistance and fewer process steps than lateral double-diffused metal oxide semiconductors. Traditionally, a drift region with a low doping concentration is disposed between the drain doping region and the channel in an extended drain metal oxide semiconductor. This drift region is used to increase the breakdown voltage between the drain doping region and the channel. With the continuous improvement of semiconductor materials in the development of the industry and according to requirements, the performance of extended drain metal oxide semiconductors needs to be further improved. In view of this, the present invention provides a new extended drain metal oxide semiconductor transistor and a fabrication method thereof. According to a preferred embodiment of the present invention, an extended drain metal oxide semiconductor transistor includes a substrate, a gate disposed on the substrate, a source doping region disposed in the substrate on one side of the gate, a drain doping region disposed in the substrate on the other side of the gate, a thin gate dielectric layer disposed under the gate, and a thick gate dielectric layer disposed under the gate, wherein the thick gate dielectric layer extends from under the gate to contact the drain doping region, and the thickness of the thick gate dielectric layer is greater than the thickness of the thin gate dielectric layer. A first well region of a second conductivity type is disposed in the substrate and surrounds the source doping region and the drain doping region, and a deep well region is disposed in the substrate and surrounds the first well region of the second conductivity type. To make the above objects, features, and advantages of the present invention more obvious and understandable, the following preferred embodiments are specifically described below in conjunction with the accompanying drawings. However, the following preferred embodiments and the drawings are only for reference and illustration purposes and are not used to limit the present invention. FIG. 1 is an extended drain metal oxide semiconductor transistor illustrated according to a first preferred embodiment of the present invention. FIG. 2 illustrates a top view of some components of the extended drain metal oxide semiconductor transistor in the first preferred embodiment. As shown in FIG. 1, an extended drain metal-oxide-semiconductor transistor 100 includes a substrate 10 having a second conductivity type. A gate G is disposed on the substrate 10. The gate G is preferably a metal gate. A source doping region S is disposed in the substrate 10 on one side of the gate G, and a drain doping region D is disposed in the substrate 10 on the other side of the gate G. A thin gate dielectric layer 12a is disposed under the gate G, and a thick gate dielectric layer 12b is disposed under the gate G, wherein the thick gate dielectric layer 12b extends from under the gate G to contact the drain doping region D. The thickness of the thick gate dielectric layer 12b is greater than the thickness of the thin gate dielectric layer 12a. The thick gate dielectric layer 12b and the thin gate dielectric layer 12a are preferably silicon oxide. It should be noted that: the thin gate dielectric layer 12a is partially buried in the substrate 10, and the thick gate dielectric layer 12b is completely buried in the substrate 10. In addition, the thin gate dielectric layer 12a and the thick gate dielectric layer 12b are connected, and a stepped profile 14 is formed between the thin gate dielectric layer 12a and the thick gate dielectric layer 12b. The position of the stepped profile 14 is preferably below the middle of the gate G. Additionally, the upper surface of the entire thick gate dielectric layer 12b is flush with the upper surface of the substrate 10, and the upper surface of the entire drain doping region D is flush with the upper surface of the substrate 10. In addition, please also refer to FIG. 2. The extended drain metal-oxide-semiconductor transistor 100 further includes a first well region Wb1 of the second conductivity type disposed in the substrate 10, and the first well region Wb1 of the second conductivity type surrounds the source doping region S and the drain doping region D. A deep well region DW is disposed in the substrate 10 and surrounds the first well region Wb1 of the second conductivity type. A well region Wa of the first conductivity type surrounds the first well region Wb1 of the second conductivity type. A second well region Wb2 of the second conductivity type surrounds the well region Wa of the first conductivity type, and the second well region Wb2 of the second conductivity type is outside the well region Wa of the first conductivity type. The well region Wa of the first conductivity type and the second well region Wb2 of the second conductivity type do not overlap. Specifically, as shown in FIG. 2, the second well region Wb2 of the second conductivity type is in the outermost periphery, the first well region Wb1 of the second conductivity type is in the innermost circle, and the well region Wa of the first conductivity type is sandwiched between the second well region Wb2 of the second conductivity type and the first well region Wb1 of the second conductivity type. The second well region Wb2 of the second conductivity type surrounds the well region Wa of the first conductivity type, and the well region Wa of the first conductivity type surrounds the first well region Wb1 of the second conductivity type. A first lightly doped drain region LDD1 of a first conductivity type is located below the thick gate dielectric layer 12b and below the drain doped region D. A second lightly doped drain region LDD2 of a first conductivity type is located below the thin gate dielectric layer 12a and below the source doped region S. A first doped region Rb1 of a second conductivity type is located in a first well region Wb1 of a second conductivity type and is adjacent to the source doped region S. A second doped region Rb2 of a second conductivity type is located in the first well region Wb1 of a second conductivity type and is located on one side of the first doped region Rb1 of a second conductivity type. A first shallow trench isolation STI1 is located between the first doped region Rb1 of a second conductivity type and the second doped region Rb2 of a second conductivity type and contacts the first doped region Rb1 of a second conductivity type and the second doped region Rb2 of a second conductivity type. A doped region Ra of a first conductivity type is located in a well region Wa of a first conductivity type. A second shallow trench isolation STI2 is disposed between the doped region Ra of a first conductivity type and the second doped region Rb2 of a second conductivity type. Additionally, in this embodiment, the second lightly doped drain region LDD2 of a first conductivity type does not overlap with the first doped region Rb1 of a second conductivity type. A third doped region Rb3 of a second conductivity type, a second high voltage well region HVW2 of a second conductivity type, and a first high voltage well region HVW1 of a second conductivity type are disposed on one side of the deep well region DW and are located outside the deep well region DW. In addition, the third doped region Rb3 of a second conductivity type, the first high voltage well region HVW1 of a second conductivity type, the second high voltage well region HVW2 of a second conductivity type, and the source doped region S are all on the same side of the gate G. The first high voltage well region HVW1 of a second conductivity type is deeper than the second high voltage well region HVW2 of a second conductivity type. The second high voltage well region HVW2 of a second conductivity type is deeper than the third doped region Rb3 of a second conductivity type. In addition, a sidewall substructure 16 is located on both sides of the gate G. The sidewall substructure 16 includes a single-layer material layer or a multi-layer material layer. In this embodiment, at least a portion of the thick gate dielectric layer 12b does not overlap with the gate G and the sidewall substructure 16. The source doped region S is closer to the sidewall substructure 16, and the drain doped region D is farther from the sidewall substructure 16. Specifically, there is a spacing A between the drain doped region D and the sidewall substructure 16. In addition, there is no salicide block between the gate G and the drain doped region D. Specifically, no salicide block is provided on the spacing A. Furthermore, the thick gate dielectric layer 12b is not fabricated by the shallow trench isolation process. Therefore, the thickness of the thick gate dielectric layer 12b is different from that of the general shallow trench isolation. Here, the thickness refers to the distance from the surface of the substrate 10 to the bottom of the component in the substrate 10. Specifically, the thickness of the thick gate dielectric layer 12b is less than the thickness of the first shallow trench isolation STI1. For example, the thickness of the thick gate dielectric layer 12b is one-third of the thickness of the first shallow trench isolation STI1. The thickness of the drain doping region D is less than the thickness of the first shallow trench isolation STI1 but greater than the thickness of the thick gate dielectric layer 12b. The thickness of the first lightly doped drain region LDD1 of the first conductivity type is greater than the thickness of the drain doping region D. The source doping region S, the first doped region Rb1 of the second conductivity type, and the second doped region Rb2 of the second conductivity type are electrically connected to each other, for example, by metal plugs and metal wires. The doped region Ra of the first conductivity type is externally connected to a voltage as a trigger contact (pickup) of the deep well region DW, and the third doped region Rb3 of the second conductivity type is externally connected to a voltage as a trigger contact of the substrate 10. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. However, in different embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. In addition, the doping concentration of the source doping region S is greater than the doping concentration of the second lightly doped drain region LDD2 of the first conductivity type. The doping concentration of the drain doping region D is greater than the doping concentration of the first lightly doped drain region LDD1 of the first conductivity type. The doping concentration of the first well region Wb1 of the second conductivity type is greater than the doping concentration of the deep well region DW. The doping concentrations of the source doping region S, the drain doping region D, the first doped region Rb1 of the second conductivity type, and the second doped region Rb2 of the second conductivity type are all greater than the doping concentration of the deep well region DW. The doping concentrations of the first doped region Rb1 of the second conductivity type and the second doped region Rb2 of the second conductivity type are both greater than the doping concentration of the first well region Wb1 of the second conductivity type. The doping concentration of the doped region Ra of the first conductivity type is greater than the doping concentration of the first well region Wa of the first conductivity type. The doping concentration of the third doped region Rb3 of the second conductivity type is greater than the doping concentration of the second high-voltage well region HVW2 of the second conductivity type. The doping concentration of the second high-voltage well region HVW2 of the second conductivity type is greater than the doping concentration of the first high-voltage well region HWV1 of the second conductivity type. Setting a thicker gate dielectric layer 12b on one side close to the drain doping region D of the present invention can enable the extended drain metal-oxide-semiconductor transistor 100 to obtain a higher breakdown voltage, and setting a thinner gate dielectric layer 12a on one side close to the source doping region S can enable the extended drain metal-oxide-semiconductor transistor 100 to obtain a higher current. By having gate dielectric layers with different thicknesses in the transistor, different requirements for the operation of the transistor at higher and lower voltages can be achieved. In addition, the present invention particularly buries the thick gate dielectric layer 12b and most of the thin gate dielectric layer 12a in the substrate 10. Therefore, the upper surface of the substrate 10 is almost horizontal. In this way, when the gate G is disposed on the upper surface of the substrate 10, the bottom of the gate G will not fluctuate too much to affect the shape and function of the gate G. Furthermore, the present invention particularly extends the thick gate dielectric layer 12b from below the gate G to contact the drain doping region D. In this way, the gap A between the drain doping region D and the gate G can be filled with the thick gate dielectric layer 12b, so that current flow occurs from the drain doping region D only when the transistor is turned on. Therefore, the thick gate dielectric layer 12b can extend the length of the channel, enabling the extended drain metal-oxide-semiconductor transistor 100 to withstand high voltages. In addition, although using a metal silicide block disposed in the gap A can achieve a similar effect to the thick gate dielectric layer 12b, using a metal silicide block requires at least one additional process step in the manufacturing process to form the metal silicide block. Therefore, using the thick gate dielectric layer 12b to fill the gap A between the gate G and the drain doping region D can reduce the manufacturing process steps. The manufacturing method of the extended drain metal-oxide-semiconductor transistor of the present invention may include forming a deep well region DW and a first high-voltage well region HVW1 of a second conductivity type on the substrate 10, and then forming a groove (not shown) in the substrate 10, which is subsequently used to dispose the thick gate dielectric layer 12b. Then, multiple shallow trench isolations (such as the first shallow trench isolation STI1 and the second shallow trench isolation STI2), a first well region Wb1 of a second conductivity type, a well region Wa of a first conductivity type, a second well region Wb2 of a second conductivity type, and a second high-voltage well region HVW2 of a second conductivity type are formed. Then, a first lightly doped drain region LDD1 of a first conductivity type, a second lightly doped drain region LDD2 of a first conductivity type, a drain doping region D, a source doping region S, a first doped region Rb1 of a second conductivity type, a second doped region Rb2 of a second conductivity type, a doped region Ra of a first conductivity type, and a third doped region Rb3 of a second conductivity type are formed. Then, the thick gate dielectric layer 12b is deposited in the aforementioned trenches. After that, the substrate 10 is oxidized to form the thin gate dielectric layer 12a. Finally, the gate G is formed, and thus the extended drain metal-oxide-semiconductor transistor 100 is completed. FIG. 3 is an extended drain metal-oxide-semiconductor transistor illustrated according to a second preferred embodiment of the present invention, wherein elements having the same functions and positions will use the element numbers in the first preferred embodiment. The difference between the extended drain metal-oxide-semiconductor transistor 100 and the extended drain metal-oxide-semiconductor transistor 200 is that the second lightly doped region LDD2 of the first conductivity type in the extended drain metal-oxide-semiconductor transistor 200 only partially overlaps with the first doped region Rb1 of the second conductivity type, that is, the second lightly doped region LDD2 of the first conductivity type does not completely overlap with the first doped region Rb1 of the second conductivity type. Other components are the same as those in the first preferred embodiment and will not be described in detail herein. FIG. 4 is an extended drain metal-oxide-semiconductor transistor illustrated according to a third preferred embodiment of the present invention, wherein components having the same functions and positions will use the component reference numerals in the first preferred embodiment. As shown in FIGS. 1 and 4, the difference between the extended drain metal-oxide-semiconductor transistor 300 and the extended drain metal-oxide-semiconductor transistor 100 is that a ramp region 14a is formed between the thin gate dielectric layer 12a and the thick gate dielectric layer 12b of the extended drain metal-oxide-semiconductor transistor 300 to connect the thin gate dielectric layer 12a and the thick gate dielectric layer 12b. Other components are the same as those in the first preferred embodiment and will not be described in detail herein. FIG. 5 is an extended drain metal-oxide-semiconductor transistor illustrated according to a fourth preferred embodiment of the present invention, wherein components having the same functions and positions will use the component reference numerals in the first preferred embodiment. As shown in FIG. 5, both the thin gate dielectric layer 12a and the thick gate dielectric layer 12b of the extended drain metal-oxide-semiconductor transistor 400 are disposed above the upper surface of the substrate 10. Therefore, the step profile 14 is also formed above the upper surface of the substrate 10, which will cause the bottom of the gate G to be uneven. If a metal gate is used, electrical problems will occur. Therefore, in this embodiment, the gate G must be a polysilicon gate. Other components are the same as those in the first preferred embodiment and will not be described in detail herein. The above are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention. 10: Substrate 12a: Thin gate dielectric layer 12b: Thick gate dielectric layer 14: Step profile 14a: Ramp region 16: Sidewall substructure 100: Extended drain metal-oxide-semiconductor transistor 200: Extended drain metal-oxide-semiconductor transistor 300: Extended drain metal-oxide-semiconductor transistor 400: Extended drain metal-oxide-semiconductor transistor A: Pitch D: Drain doping region DW: Deep well region G: Gate HVW1: First high-voltage well region of the second conductivity type HVW2: Second high-voltage well region of the second conductivity type LDD1: First lightly doped region of the first conductivity type LDD2: Second lightly doped region of the first conductivity type Ra: Doping region of the first conductivity type Rb1: First doping region of the second conductivity type Rb2: Second doping region of the second conductivity type Rb3: Third doping region of the second conductivity type STI1: First shallow trench isolation STI2: Second shallow trench isolation Wa: Well region of the first conductivity type Wb1: First well region of the second conductivity type Wb2: Second well region of the second conductivity type S: Source doping region FIG. 1 is an extended drain metal-oxide-semiconductor transistor according to a first preferred embodiment of the present invention. FIG. 2 shows a top view of some elements of the extended drain metal-oxide-semiconductor transistor in the first preferred embodiment. FIG. 3 is an extended drain metal-oxide-semiconductor transistor according to a second preferred embodiment of the present invention. FIG. 4 is an extended drain metal-oxide-semiconductor transistor according to a third preferred embodiment of the present invention. FIG. 5 is an extended drain metal-oxide-semiconductor transistor according to a fourth preferred embodiment of the present invention. 10: Substrate 12a: Thin gate dielectric layer 12b: Thick gate dielectric layer 14: Step profile 16: Sidewall substructure 100: Extended drain metal-oxide-semiconductor transistor A: Pitch D: Drain doping region DW: Deep well region G: Gate HVW1: First high-voltage well region of the second conductivity type HVW2: Second high-voltage well region of the second conductivity type LDD1: First lightly doped region of the first conductivity type LDD2: Second lightly doped region of the first conductivity type Ra: Doping region of the first conductivity type Rb1: First doping region of the second conductivity type Rb2: Second doping region of the second conductivity type Rb3: Third doping region of the second conductivity type STI1: First Shallow Trench Isolation STI2: Second Shallow Trench Isolation Wa: First Conductivity Type Well Region Wb1: Second Conductivity Type First Well Region Wb2: Second Conductivity Type Second Well Region S: Source Doping Region

Claims

1. An extended drain-type metal-oxide-semiconductor transistor, comprising: a substrate; a gate disposed on the substrate; a source-doped region disposed in the substrate on one side of the gate; a drain-doped region disposed in the substrate on the other side of the gate; a thin gate dielectric layer disposed below the gate; a thick gate dielectric layer disposed below the gate, wherein the thick gate dielectric layer extends from below the gate to contact the drain-doped region, wherein the thickness of the thick gate dielectric layer is greater than the thickness of the thin gate dielectric layer; a first well region of a second conductivity type disposed in the substrate and surrounding the source-doped region and the drain-doped region; a deep well region disposed in the substrate and surrounding the first well region of the second conductivity type; a first well region of a first conductivity type surrounding the first well region of the second conductivity type; and a second well region of a second conductivity type surrounding the first well region of the first conductivity type, and the second well region of the second conductivity type being outside the first well region of the first conductivity type.

2. The extended drain-type metal-oxide-semiconductor transistor as described in claim 1, wherein the entire upper surface of the thick gate dielectric layer is flush with the upper surface of the substrate.

3. The extended drain-type metal-oxide-semiconductor transistor as described in claim 1, wherein the entire upper surface of the drain-doped region is flush with the upper surface of the substrate.

4. The extended drain-type metal-oxide-semiconductor transistor as described in claim 1, wherein the thick gate dielectric layer is completely embedded in the substrate.

5. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 1, wherein the thin gate dielectric layer is disposed on the upper surface of the substrate, and the thick gate dielectric layer is disposed on the upper surface of the substrate.

6. The extended drain-type metal-oxide-semiconductor transistor as described in claim 5, wherein the gate is a polysilicon gate.

7. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 1, wherein the thin gate dielectric layer and the thick gate dielectric layer are connected, and a stepped profile is formed between the thin gate dielectric layer and the thick gate dielectric layer.

8. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 1, further comprising: a first conductivity type first lightly doped region located below the thick gate dielectric layer and below the drain doped region; a first conductivity type second lightly doped region located below the thin gate dielectric layer and below the source doped region; a second conductivity type first doped region located in the second conductivity type first well region and adjacent to the source doped region; a second conductivity type second doped region located in the second conductivity type first well region and located on one side of the second conductivity type first doped region; a first shallow trench isolation located between the second conductivity type first doped region and the second conductivity type second doped region and contacting the second conductivity type first doped region and the second conductivity type second doped region; and a first conductivity type doped region located in the first conductivity type well region.

9. The extended drain-type metal-oxide-semiconductor transistor as described in claim 8, wherein the second lightly doped region of the first conductivity type does not completely overlap with the first doped region of the second conductivity type.

10. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 9, wherein the second lightly doped region of the first conductivity type does not overlap with the first doped region of the second conductivity type.

11. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 1, further comprising a sidewall substructure located on both sides of the gate, wherein at least a portion of the thick gate dielectric layer does not overlap with the gate and the sidewall substructure.

12. The extended drain-type metal-oxide-semiconductor transistor as described in claim 1, wherein the gate is a metal gate.

13. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 1, wherein there is no salicide block between the gate and the drain doped region.

14. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 1, wherein the thick gate dielectric layer and the thin gate dielectric layer are silicon oxide.

15. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 8, further comprising: a second shallow trench isolation disposed between the second conductivity type second doped region and the first conductivity type doped region.

16. The extended drain-type metal-oxide-semiconductor transistor as claimed in claim 1, wherein the thin gate dielectric layer and the thick gate dielectric layer are connected, and a ramp region is formed between the thin gate dielectric layer and the thick gate dielectric layer to connect the thin gate dielectric layer and the thick gate dielectric layer.

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