Methods for stripping and cleaning semiconductor structures

Abstract

Methods for removing oxide films and for cleaning silicon-on-insulator structures are disclosed. These methods may involve immersing the silicon-on-insulator structure in a stripping bath to peel off the oxide film from the surface of the silicon-on-insulator structure. The stripped silicon-on-insulator structure may be immersed in an ozone bath containing ozone. The ozone-treated silicon-on-insulator structure may be immersed in an SC-1 bath containing ammonium hydroxide and hydrogen peroxide to clean the structure.

Description

[Technical Field]

[0001] The field of the present invention relates to a method for removing oxides from a silicon-on-insulator (SOI) structure and for cleaning such a structure. [Previous Technology]

[0002] Semiconductor structures such as silicon-on-insulator ("SOI") structures may undergo an annealing process prior to downstream processing. This annealing can result in the formation of an oxide (SiO2) on the surface of the SOI structure. This oxide is typically removed from the top surface of the structure. During cleaning of the structure after the oxide is removed, some areas on the surface of the silicon-on-insulator structure form wafer surface protrusions or "bumps". Previous attempts to remove these bumps, such as by increasing the stripping process time, have not successfully eliminated the formation of these bumps.

[0003] There is a need for methods for reducing or eliminating protrusions from the surface of an SOI structure, for removing oxides from the top surface of an SOI structure, and for cleaning the structure.

[0004] This section is intended to introduce to the reader various technical aspects that may relate to the various aspects of the invention described and / or claimed below. This discussion is intended to help provide the reader with background information to facilitate a better understanding of the various aspects of the invention. Accordingly, it should be understood that these statements should be interpreted in this light and not as an admission of prior art. [Summary of the Invention]

[0005] One aspect of the present invention relates to a method for stripping and cleaning a surface of a silicon-on-insulator structure. The silicon-on-insulator structure includes a treatment structure, a silicon top layer, and a dielectric layer disposed between the treatment structure and the silicon top layer. The silicon-on-insulator structure has an oxide film on one of its top surfaces. The silicon-on-insulator structure is immersed in a stripping bath to remove the oxide film from the surface of the silicon-on-insulator structure and prepare a stripped silicon-on-insulator structure. The stripping bath includes hydrofluoric acid and a surfactant. The stripped silicon-on-insulator structure is immersed in an ozone bath including ozone to prepare an ozone-treated silicon-on-insulator structure. The ozone-treated silicon-on-insulator structure is immersed in an SC-1 bath including ammonium hydroxide and hydrogen peroxide to prepare an SC-1-treated silicon-on-insulator structure.

[0006] Various modifications exist to the features described in the above-mentioned embodiments of the present invention. Further features may also be incorporated into the above-mentioned embodiments of the present invention. Such modifications and additional features may exist individually or in any combination. For example, various features discussed below with respect to any of the illustrated embodiments of the present invention may be incorporated individually or in any combination into any of the above-mentioned embodiments of the present invention.

Implementation Method

[0017] This application claims priority to U.S. Nonprovisional Patent Application No. 17 / 670,167, filed February 11, 2022, the entire contents of which are incorporated herein by reference.

[0018] The present invention relates to a method for stripping and cleaning a surface of a semiconductor structure. In some embodiments, oxides (e.g., SiO2) are removed from the surface of the semiconductor structure by immersing it in a stripping bath comprising hydrofluoric acid and a surfactant. After stripping, the semiconductor structure is immersed in a bath comprising ozone before subsequent cleaning operations to remove defects (e.g., nanoscale defects) to prevent such defects from acting as an etching mask, thereby forming protrusions on the surface of the semiconductor structure.

[0019] These methods are generally applicable to removing oxides from any semiconductor structure (e.g., a single layer or a bonded structure), such as any bonded wafer structure in which it is desirable to remove an oxide film. According to embodiments of the invention, the semiconductor structure being cleaned has a front surface, a rear surface, a circumferential edge, and a central axis. The semiconductor structure can be of any diameter suitable for use by those skilled in the art, including, for example, substrates with diameters of about 200 mm, about 300 mm, greater than about 300 mm, or even about 450 mm.

[0020] In some embodiments, the structure being processed may be a silicon-on-insulator structure. Such structures may include a disposal wafer, a silicon layer (sometimes referred to as a "silicon device layer" or "silicon top layer"), and a dielectric layer disposed between the disposal wafer and the silicon layer. The following is merely one example of a method for fabricating a silicon-on-insulator structure, and other methods may be used unless otherwise stated.

[0021] Figure 1 illustrates an example of a donor structure 30 that can be bonded to a disposal structure to form a bonded wafer structure. The donor structure 30 may be formed by depositing a dielectric layer 15 on a prior surface of a donor wafer 12. It should be understood that, alternatively, the dielectric layer 15 may be grown or deposited on the disposal wafer or a dielectric layer may be grown on both the donor wafer and the disposal wafer, and such structures can be bonded in any of various configurations without limitation. A suitable donor wafer 12 may be composed of silicon, germanium, silicon-germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, and any combination thereof. In some embodiments, the donor wafer is composed of single-crystal silicon.

[0022] The dielectric layer 15 can be any electrically insulating material suitable for use in an SOI structure, such as materials including SiO2, Si3N4, aluminum oxide, or magnesium oxide. In some embodiments, the dielectric layer 15 is SiO2 (i.e., the dielectric layer is essentially composed of SiO2). In embodiments where the dielectric layer is silicon dioxide (SiO2), the dielectric layer is sometimes referred to as a "buried oxide" or "BOX" layer 15. The dielectric layer 15 can be applied according to any known technique in this art, such as thermal oxidation, wet oxidation, thermal nitriding, or a combination of such techniques.

[0023] As shown in Figure 2, ions (e.g., hydrogen atoms, helium atoms, or a combination of hydrogen and helium atoms) can be implanted at a substantially uniform specified depth below the surface 22 of the donor structure to define a split plane 17. It should be noted that when helium and hydrogen ions are co-implanted into the structure to form the split plane 17, the helium and hydrogen ions can be implanted simultaneously or sequentially. In some embodiments, the ions are implanted before depositing the dielectric layer 15. When implantation is performed before depositing the dielectric layer 15, subsequent growth or deposition of the dielectric layer on the donor wafer 12 is appropriately performed at a sufficiently low temperature to prevent premature separation or splitting along the plane 17 in the donor layer (i.e., before the wafer bonding procedure steps).

[0024] The treatment structure 10 (FIG. 3) may include a treatment wafer obtained from any suitable material used to prepare a multilayer structure, such as silicon, silicon carbide, sapphire, germanium, silicon-germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, quartz, and combinations thereof. The treatment structure 10 may include a dielectric layer deposited on a treatment wafer, or, as in other embodiments, may consist of only a treatment wafer (i.e., without a dielectric layer). The treatment wafer and the donor wafer may be single-crystal silicon wafers and may be single-crystal silicon wafers diced from a single-crystal ingot grown according to the conventional Chuklaski crystal growth method.

[0025] As shown in Figure 3, the front surface of the dielectric layer 15 of the donor structure is appropriately bonded to the front surface of the treatment structure 10 to form a bonded wafer structure 20 through a bonding process. The dielectric layer 15 and the treatment structure 10 can be bonded together while performing a surface activation by exposing the surfaces of these structures to a plasma containing, for example, oxygen or nitrogen. The wafers are then pressed together and a bonding interface 18 is formed between them. Generally, wafer bonding can be achieved using any technique known in this art, provided that the energy used to achieve the formation of the bonding interface is sufficient to ensure the integrity of the bonding interface is maintained during subsequent processing (i.e., layer transfer performed by separating along the cleaving or separation plane 17 in the donor wafer).

[0026] Once fabricated, the bonded wafer structure 20 is placed in a cleaving apparatus to separate (i.e., cleave) a portion of the donor wafer along a cleaving plane to form a layered semiconductor structure (e.g., an SOI structure). Generally, the cleaving apparatus may use techniques known in the art, such as thermal and / or mechanically induced cleaving techniques, to induce this fracture.

[0027] Referring to FIG. 4, during separation, two structures 30 and 31 are formed. Because the separation of the bonded wafer structure 20 occurs along the cleaving plane 17 in the donor structure 12 (FIG. 3), a portion of the donor structure retains portions of both structures (i.e., a portion of the donor wafer is transferred together with the dielectric layer 15). Structure 30 includes a portion of the donor wafer. Structure 31 is an SOI structure and includes a disposal structure 10, a dielectric layer 15, and a silicon top layer 25 disposed on top of the dielectric layer 15 (the portion of the donor wafer retained after cleaving). In embodiments where both the donor structure and the disposal structure include a dielectric layer, the dielectric layers are combined to form the dielectric layer 15 of the SOI structure.

[0028] The cleaving device used to separate the bonded wafer structure along the cleaving plane can be a mechanical cleaving device in which separation is induced or achieved by mechanical force alone or as a supplement to annealing. For example, the bonded structure can be placed in a jig in which mechanical force is applied perpendicular to the opposite side of the bonded structure to pull a portion of the donor structure away from the bonded structure.

[0029] One example of a cleaving device includes a chuck that applies mechanical force near a pre-cleaving edge of one of the bonded wafer structures 20. The separation of this portion of the donor wafer can be initiated by applying a mechanical wedge or blade at the edge of the bonded wafer at the cleaving plane 17 to initiate the propagation of a crack along the cleaving plane 17. The mechanical force applied by the chuck then pulls this portion of the donor structure from the bonded structure, thus forming an SOI structure. Mechanical cleaving devices are commercially available, such as Debond & Cleave Tools from Silicon Genesis Corporation (San Jose, California).

[0030] In an alternative embodiment, the splitting apparatus is a thermal splitting apparatus, wherein splitting is achieved by annealing the bonded structure. For example, thermal splitting can be performed in an inert atmosphere (e.g., argon or nitrogen) at a temperature of about 200°C to about 800°C or from about 250°C to about 650°C for a period of at least about 10 seconds, at least about 1 minute, at least about 15 minutes, at least about 1 hour, or even at least about 3 hours (the higher the temperature, the shorter the annealing time required, and vice versa). The thermal splitting apparatus can be a strip furnace, wherein the propagation of splitting is achieved at the leading edge of the bonded structure (i.e., the leading edge of the structure in the direction of travel through the furnace) and continues toward the trailing edge of the bonded wafer structure. Other types of splitting apparatus may also be used.

[0031] The layers of SOI structure 31 (treatment structure 10, dielectric layer 15, and silicon top layer 25) may typically have any thickness that allows such layers to function as described herein. In some embodiments, the silicon top layer 25 is relatively thin (e.g., about 0.1 μm to about 0.3 μm thick), and the dielectric layer 15 is relatively thick (about 1.0 μm or more).

[0032] The method for generating an SOI structure described herein is an example method and other methods may be used without departing from the scope of the invention.

[0033] Referring now to FIG. 5, one method 100 of the present invention is illustrated. Although the method of the present invention may be described herein with reference to a silicon-on-insulator structure, in some embodiments, other semiconductor structures may be processed by the disclosed method. In a first step 110, a silicon-on-insulator structure 101 is immersed in a stripping bath to remove oxides (e.g., SiO2) from the top surface of the silicon-on-insulator structure 101 and to prepare a stripped silicon-on-insulator structure 112. The stripping bath includes hydrofluoric acid and a surfactant. In some embodiments, the surfactant is a nonionic surfactant. In some embodiments, the nonionic surfactant includes an ether group. In some embodiments, the ether surfactant is a polyoxyalkylene alkyl ether. Commercially available ether surfactants include the TRITON X series (Dow Chemical Company (Midland, Michigan)) and NCW1001 and NCW1002 (Wako Chemicals USA (Richmond, Virginia)).

[0034] In some embodiments, a mega-frequency ultrasonic field may be applied to the various cleaning baths described herein during the stripping or cleaning of the semiconductor substrate. Typical frequencies for mega-frequency ultrasonic cleaning range from 750 kHz to approximately 1.5 MHz. Mega-frequency ultrasonic cleaning induces cavitation, which facilitates the removal of particles from the surface of the substrate. In other embodiments, no mega-frequency ultrasonic field is applied during the various stripping and cleaning steps described herein.

[0035] The amount of surfactant in the stripping bath may be any effective amount that allows the stripping bath to function as described herein. In some embodiments, the amount of surfactant is at least 0.01 wt%, or as in other embodiments at least about 0.025 wt% or at least 0.05 wt%, or from 0.01 wt% to about 0.1 wt%, or from 0.025 wt% to 0.075 wt%. The ratio (v:v) of deionized water to hydrofluoric acid (HF) may be less than 100:1, less than 50:1, less than 25:1, at least 1:1, at least 5:1, from 1:1 to 100:1, or from 1:1 to 25:1. The time period during which the silicon structure on the insulator is immersed in the stripping bath may be at least 5 minutes, at least 10 minutes, or from 5 minutes to about 60 minutes, or from about 5 minutes to about 30 minutes. In some embodiments, the stripping bath does not contain acetic acid.

[0036] The stripping bath (and any additional baths mentioned below) can be held in any suitable container, such as a container as part of a wet immersion station apparatus. One example of such a system is the GAMA automated wet immersion station, available from Naura-Akrion (Arlanton, Pennsylvania), which may include multiple containers for immersing structures in different baths. Multiple semiconductor structures (e.g., at least 5, 10, 25, or 50 or more) can be loaded onto a wafer carrier (or "cassette" or "crystal boat"), and one or more of these carriers can be immersed in a bath held within the container. The components used to hold these structures in the bath are typically high-purity parts, such as PTFE, quartz, or coated aluminum or stainless steel. Commercially available cleaning equipment is available from Echo Giken Ltd. (Tokyo, Japan) and Akrion Systems LLC (Arlanton, Pennsylvania). In other embodiments, the structures can be immersed in a bath within a "cassette-less" system.

[0037] According to embodiments of the invention, “immersing” the silicon-on-insulator structure in a stripping bath or other bath described below involves completely immersing the silicon-on-insulator structure in the bath. Typically, and according to embodiments of the invention, the substrate is not rotated during the cleaning process in these immersion procedures.

[0038] In a second step 120 of one method, the stripped silicon-on-insulator structure 111 is immersed in an ozone bath to prepare an ozone-treated silicon-on-insulator structure 121. The ozone bath comprises ozone (O3). In some embodiments, the concentration of ozone in the ozone bath is at least 5 ppm, or at least 10 ppm, at least 20 ppm, or from 5 ppm to 40 ppm. The stripped silicon-on-insulator structure 111 may be immersed in the ozone bath for at least 1 minute, at least 5 minutes, or at least 10 minutes (e.g., from 1 minute to 30 minutes or from 5 minutes to about 20 minutes).

[0039] In a third step 130, the ozone-treated silicon-on-insulator structure 121 is immersed in an SC-1 bath to prepare an SC-1 treated silicon-on-insulator structure 131. The "SC-1" bath is an aqueous cleaning bath known to those skilled in the art and may also be referred to as "Standard Cleaning-1" or "RCA-1" bath.

[0040] The SC-1 bath comprises ammonium hydroxide (NH₄OH) and hydrogen peroxide (H₂O₂). The amount of ammonium hydroxide in the SC-1 bath may be at least 0.1 wt%, at least 0.5 wt%, or at least 1.0 wt% (e.g., from 0.1 wt% to 5 wt% or from 1 wt% to 3 wt%). The amount of hydrogen peroxide in the SC-1 bath may be at least 0.5 wt%, at least 1 wt%, at least 2 wt%, from 0.5 wt% to 10 wt%, or from 2 wt% to about 5 wt%.

[0041] In another embodiment of the method, as shown in FIG6, after immersion in the SC-1 bath, the SC-1 treated silicon-on-insulator structure 131 is immersed in the SC-2 bath to form an SC-2 treated silicon-on-insulator structure 141. The "SC-2" bath is an aqueous cleaning bath known to those skilled in the art and may also be referred to as "Standard Clean-2" or "RCA-2" bath. The SC-2 bath includes hydrochloric acid (HCl). In some embodiments, the SC-2 bath includes at least 0.01 wt% hydrochloric acid, at least 0.1 wt% hydrochloric acid, at least 0.25 wt% hydrochloric acid, from 0.01 wt% to 5 wt% hydrochloric acid, or from 0.1 wt% to 5 wt% hydrochloric acid. The silicon-on-insulator structure may be immersed in the SC-2 bath for at least 5 minutes, at least 7.5 minutes, or from 5 minutes to 20 minutes.

[0042] Figure 7 illustrates another embodiment of a method for stripping and cleaning a surface of a silicon-on-insulator structure. In a rinsing step 115, the stripped silicon-on-insulator structure 111 (i.e., the structure after immersion in the stripping bath in step 110) is rinsed, in which the structure is contacted with deionized water, such as by immersion in deionized water (DIW). In a second rinsing step 135, the SC-1 treated silicon-on-insulator structure 131 is rinsed with DIW water. The SC-2 treated structure 141 may undergo a third rinsing step 150, such as by contacting the structure 141 with DIW (e.g., immersion). The rinsed silicon-on-insulator structure may be dried in a drying step 160. For example, the structure may be dried in an isopropyl alcohol vapor (IPA) dryer (Marangoni drying).

[0043] The various baths described herein may be at room temperature (about 25°C). In other embodiments, a heated bath is used (e.g., at least 30°C, at least 40°C, at least 60°C, from 30°C to 95°C, or from 30°C to 80°C).

[0044] The method described above and shown in Figures 5 to 7 for stripping and cleaning one surface of a silicon structure on an insulator is exemplary and may include additional steps, or the steps may be reordered or one or more steps may be eliminated.

[0045] The method of the present invention has several advantages compared to conventional methods for removing oxides from a silicon-on-insulator (SOI) structure. Unbound by any particular theory, it is believed that the surfactants used during oxide stripping cause nanoscale defects to form on the surface of the SOI structure. These nanoscale defects can be surfactants or surfactant-bound contaminants. These defects are nanoscale and cannot be detected by conventional wafer inspection tools (e.g., the KLA-Tencor Surfscan SPx wafer surface analysis system). These defects are believed to act as an etching mask during the subsequent cleaning step (SC-1 cleaning). Ozone treatment has been found to remove these defects prior to the cleaning process, thus reducing or eliminating protrusions from the surface of the SOI structure. Examples

[0046] The procedure of the present invention is further illustrated by the following examples. These examples should not be considered as limiting. Example 1: Protrusions on the SOI surface under conventional methods

[0047] A 200 mm SOI structure was fabricated using the method described herein. The SOI structure was annealed to form oxide (SiO2) on the top surface of the silicon device layer of the SOI structure. The structure was then immersed in an HF bath containing a surfactant, subjected to DIW rinsing, and then immersed in an SC-1 bath. Figure 8 is a reproduction of an AFM image of the SOI structure, showing nanoscale protrusions on the surface of the structure. Figure 9 is an AFM graph showing the height of the protrusions. When the 200 mm SOI structure with oxide (SiO2) on the top surface of the silicon device layer of the SOI structure was immersed in an ozone bath before SC-1 cleaning, defects shown in the AFM image were eliminated.

[0048] As used herein, the terms “about,” “substantially,” “essentially,” and “approximately” are intended, when used in conjunction with ranges of size, concentration, temperature, or other physical or chemical properties or characteristics, to cover variations that may exist above and / or below the range of such properties or characteristics, including variations caused, for example, by rounding, measurement methods, or other statistical variations.

[0049] In describing elements of the present invention or its embodiments(s), the articles "a" and "the" are intended to mean that one or more of the elements are present. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that additional elements besides those listed may also be present. The use of terms indicating a particular orientation (e.g., "top," "bottom," "side," etc.) is for ease of description and does not require any particular orientation of the described items.

[0050] Since various changes can be made to the above structure and method without departing from the scope of the invention, all matters contained in the above description and shown in the accompanying drawings are intended to be interpreted as illustrative rather than limiting. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a cross-sectional view of a donor structure having a donor wafer and a dielectric layer thereon;

[0008] Figure 2 is a cross-sectional view of the donor structure during an ion implantation procedure;

[0009] Figure 3 is a cross-sectional view of one of the donor structures joined to a treatment structure;

[0010] Figure 4 is a cross-sectional view of one of the bonded wafer structures when the donor structure is split at the splitting plane;

[0011] Figure 5 illustrates one method for removing oxides and cleaning silicon structures on an insulator;

[0012] Figure 6 shows another embodiment of a method for removing oxides and cleaning silicon structures on an insulator;

[0013] Figure 7 shows another embodiment of a method for removing oxides and cleaning silicon structures on an insulator;

[0014] Figure 8 is a reproduction of an AFM image of a nano-sized defect formed in a conventional method for removing oxides and cleaning silicon structures on an insulator; and

[0015] Figure 9 is a chart showing the height of the defect shown in Figure 8.

[0016] Through the diagram, the corresponding component symbol indicates the corresponding part.

Claims

1. A method for stripping and cleaning a surface of a silicon-on-insulator structure, the silicon-on-insulator structure comprising a treatment structure, a silicon top layer, and a dielectric layer disposed between the treatment structure and the silicon top layer, the silicon-on-insulator structure having an oxide film on a top surface of the silicon-on-insulator structure, the method comprising: The silicon-on-insulator structure is immersed in a stripping bath to remove the oxide film from the surface of the silicon-on-insulator structure, thereby preparing a stripped silicon-on-insulator structure. The stripping bath includes hydrofluoric acid and a surfactant. The stripped silicon-on-insulator structure is then immersed in an ozone bath containing ozone to prepare an ozone-treated silicon-on-insulator structure. Finally, the ozone-treated silicon-on-insulator structure is immersed in an SC-1 bath containing ammonium hydroxide and hydrogen peroxide to prepare an SC-1-treated silicon-on-insulator structure.

2. The method of claim 1, further comprising immersing the SC-1 treated silicon-on-insulator structure in an SC-2 bath comprising hydrochloric acid to form an SC-2 treated silicon-on-insulator structure.

3. The method of claim 2, comprising rinsing the SC-1 treated silicon-on-insulator structure with water before immersing it in the SC-2 bath.

4. The method of claim 2, comprising drying the SC-2 treated silicon-on-insulator structure by contacting the SC-2 treated silicon-on-insulator structure with isopropanol vapor.

5. The method of claim 4, further comprising rinsing the SC-2 treated silicon-on-insulator structure with water before drying the SC-2 treated silicon-on-insulator structure.

6. The method of claim 1, wherein the stripping bath comprises at least about 0.01 wt% of a surfactant.

7. The method of claim 1, wherein the surfactant is a nonionic surfactant.

8. The method of claim 7, wherein the nonionic surfactant is an ether surfactant with an ether group.

9. The method of claim 8, wherein the ether surfactant is a polyoxyalkylene alkyl ether.

10. The method of claim 1, wherein the ozone bath comprises at least 20 ppm of ozone.

11. The method of claim 1, wherein the stripped silicon structure on the insulator is immersed in the ozone bath for at least 5 minutes.

12. The method of claim 1, wherein the stripped silicon structure on the insulator is immersed in the ozone bath for between 5 and 20 minutes.

13. The method of claim 1, wherein the silicon structure on the insulator is immersed in the stripping bath for at least 5 minutes.

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