Semiconductor device

Abstract

A semiconductor device includes: a substrate, a doped ring, a plurality of contact windows, and conductive wires. The substrate includes a first region and a second region. The second region surrounds the first region. The doped ring is located in the substrate of the second region, surrounding the first region. The doped ring includes a first doped region and a plurality of second doped regions. The first doped region is located in the substrate of the second region, surrounding the first region, wherein the first doped region has an opening. The plurality of second doped regions are separated from each other and located in the substrate with the opening. The plurality of contact windows are electrically connected to the ends of the plurality of second doped regions and the first doped region. The plurality of conductive wires connect the plurality of contact windows and are connected to a plurality of conductive layers on the first region.

Description

Semiconductor Component The present invention relates to an integrated circuit, and more particularly to a semiconductor component. Plasma is often used in the deposition and etching processes of semiconductor manufacturing. However, during the process, plasma discharge may damage semiconductor components. For example, when plasma is used in the back-end process of semiconductors, it is very likely to damage the gate dielectric layer of memory components on the substrate due to discharge, resulting in a decrease in the retention performance of memory components. An embodiment of the present invention provides a semiconductor component that can protect the memory, avoid plasma from damaging the gate dielectric layer or tunneling layer of the memory, and improve the retention performance of the memory. A semiconductor component according to an embodiment of the present invention includes: a substrate, a doped ring, a plurality of contact windows, and wires. The substrate includes a first region and a second region. The second region surrounds the first region. The doped ring is located in the substrate of the second region and surrounds the first region, wherein the doped ring includes a first doped region and a plurality of second doped regions. The first doped region is located in the substrate of the second region and surrounds the first region. The first doped region has an opening. The plurality of second doped regions are separated from each other and are located in the substrate of the opening. The plurality of contact windows are electrically connected to the plurality of second doped regions and the ends of the first doped region. The plurality of wires are connected to the plurality of contact windows and are connected to a plurality of conductor layers on the first region. A semiconductor component according to another embodiment of the present invention includes: a semiconductor component, including: a substrate, a plurality of memory components, a plurality of diodes, a plurality of contact windows, and a plurality of wires. The substrate includes a first region and a second region, and the second region surrounds the first region. The plurality of memory components are located in the first region. The plurality of diodes are located in the substrate of the second region. The plurality of contact windows are electrically connected to the plurality of diodes. The plurality of wires are connected to the plurality of contact windows and are connected to the plurality of memory components. Based on the above, an embodiment of the present invention protects the memory component by setting a diode (doped ring), avoiding plasma used in subsequent metallization processes from damaging the gate dielectric layer of the memory component, and improving the retention performance of the memory component. FIG. 1A is a top view of a semiconductor component according to an embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line I-I' of FIG. 1A. FIG. 1C is another cross-sectional view taken along line I-I' of FIG. 1A. Referring to FIGS. 1A and 1B, a semiconductor device SD1 according to an embodiment of the present invention includes: a substrate 10, a plurality of memory elements 116A, a guard ring 16, a plurality of diodes 33, a plurality of contact windows 42, and a plurality of wires 44. The substrate 10 is, for example, a semiconductor or a semiconductor compound. The semiconductor includes silicon, such as bulk Si or silicon-on-insulator (SOI). The semiconductor compound is, for example, germanium silicide. The isolation structure 14 is located in the substrate 10. The isolation structure 14 is, for example, silicon oxide, silicon nitride, or a combination thereof. The isolation structure 14 defines a first region AR and a second region PR in the substrate 10. The first region AR is, for example, a memory array region. The second region PR is, for example, a peripheral region. The second region PR surrounds the first region AR. A plurality of memory elements 116A are located in the region 100A of the first region AR. The plurality of memory elements 116A can be arranged in multiple rows and multiple columns to form a memory array. The memory element 116A can be a flash memory element. The flash memory element can have various structures. For example, the flash memory element includes a tunneling layer 118, a floating gate layer 120, an inter-gate dielectric layer 125, a control gate layer 128, a capping layer 130, and a spacer 132. The tunneling layer 118, the floating gate layer 120, the inter-gate dielectric layer 125, the control gate layer 128, and the capping layer 130 are stacked from bottom to top to form a gate stack structure SK1. The tunneling layer 118 is, for example, silicon oxide. The floating gate layer 120 is, for example, polysilicon. The inter-gate dielectric layer 125 includes, for example, a silicon oxide layer 122, a silicon nitride layer 124, and a silicon oxide layer 126. The control gate layer 128 is, for example, polysilicon. The capping layer 130 is, for example, silicon nitride. The spacer 132 covers the sidewalls of the gate stack structure SK1 formed by the tunneling layer 118, the floating gate layer 120, the inter-gate dielectric layer 125, the control gate layer 128, and the capping layer 130. Referring to FIG. 1A, the semiconductor device SD1 may further include a plurality of dummy memory elements 116A'. The plurality of dummy memory elements 116A' are located in the first region AR outside the region 100A. The plurality of dummy memory elements 116A' may have a similar composition and components to the plurality of memory elements 116A. Referring to FIGS. 1A and 1B, a guard ring 16 is disposed on a substrate 10 of a second region PR. The guard ring 16 is a closed ring that surrounds a plurality of memory elements 116A, which can reduce the impact of the load effect caused by different densities in a first region AR and a second region PR during the manufacturing process to protect the memory elements 116A. The composition of the guard ring 16 can be similar to the composition of the gate stack structure SK1 of the memory elements 116A. In some embodiments, the guard ring 16 can include a dielectric layer 18, a conductor layer 20, dielectric layers 22, 24, and 26, a conductor layer 28, a capping layer 30, and a spacer 32. The dielectric layer 18, the conductor layer 20, the dielectric layers 22, 24, and 26, the conductor layer 28, the capping layer 30, and the spacer 32 can be made of the same materials as the tunneling layer 118, the floating gate layer 120, the inter-gate dielectric layer 125, the control gate layer 128, and the capping layer 130, respectively, and the two can be formed simultaneously. Referring to FIGS. 1A and 1B, a plurality of diodes 33 of an embodiment of the present invention are disposed in a substrate 10 of a second region PR. The plurality of diodes 33 include a well region 12 and a doped ring 38. The well region 12 extends from below an isolation structure 14 between the first region AR and the second region PR into the second region PR and then extends below the isolation structure 14 outside the second region PR, but is not limited thereto. The well region 12 is, for example, a dopant having a first conductivity type. The dopant of the well region 12 can be P-type, such as boron or boron trifluoride. The dopant of the well region 12 can be N-type, such as phosphorus or arsenic. Referring to FIGS. 1A and 1B, both the doped ring 38 and the guard ring 16 are disposed within the well region 12. The doped ring 38 is adjacent to the guard ring 16. The doped ring 38 can partially overlap with the guard ring 16 (as shown in FIG. 1B), or not overlap (as shown in FIG. 1C) and be separated by a non-zero distance. The doped ring 38 is disposed within the guard ring 16 and is thus closer to the first region AR than the guard ring 16. Referring to FIG. 1A, the doped ring 38 is located in the well region 12 of the second region PR, as shown in FIG. 1B. Referring to FIG. 1A, the doped ring 38 includes a first doped region 38A and a plurality of second doped regions 38B. The first doped region 38A is, for example, an open non-closed ring that surrounds the well region 12 outside the first region AR. In other words, the first doped region 38A has an opening 38C. The plurality of second doped regions 38B are located in the well region 12 of the opening 38C. The plurality of second doped regions 38B are, for example, in the shape of islands and are separated from each other. In other words, the doped ring 38 formed by the first doped region 38A and the plurality of second doped regions 38B is a non-closed ring. Referring to FIGS. 1A and 1B, the first doped region 38A and the plurality of second doped regions 38B of the doped ring 38 each include a lightly doped region 36 and a heavily doped region 34. The lightly doped region 36 is located in the well region 12, and the heavily doped region 34 is located in the lightly doped region 36. The conductivity type of the dopants in the lightly doped region and the heavily doped region is different from the conductivity type of the dopants in the well region. The lightly doped region 36 and the heavily doped region 34 are, for example, dopants having a second conductivity type. The dopants in the lightly doped region 36 and the heavily doped region 34 can be N-type, such as phosphorus or arsenic. The dopants in the lightly doped region 36 and the heavily doped region 34 can be P-type, such as boron or boron trifluoride. The lightly doped region 36 is located in the well region 12 and is adjacent to the guard ring 16. The lightly doped region 36 can partially overlap with the guard ring 16 (as shown in FIG. 1B), or can be non-overlapping (as shown in FIG. 1C) and spaced apart by a non-zero distance. The heavily doped region 34 does not overlap with the guard ring 16 (as shown in FIGS. 1B and 1C) and is spaced apart by a non-zero distance. Referring to FIGS. 1A and 1B, the interconnection structure 50 is located on the substrate 10. The interconnection structure 50 includes a dielectric layer 160, a plurality of contact windows 42, 142, and a plurality of conductive wires 44. Referring to FIG. 1B, the dielectric layer 160 is, for example, silicon oxide. The dielectric layer 160 can have a flat surface via a planarization process. The contact windows 42, 142 are formed in the dielectric layer 160. The contact window 42 extends through the dielectric layer 160 and electrically connects to the heavily doped region 34. The contact window 142 extends through the dielectric layer 160 and the capping layer 130 and electrically connects to the control gate 128. The plurality of contact windows 42 electrically connect to the ends E1 and E2 of the first doped region 38A and the plurality of second doped regions 38B, as shown in FIG. 1A. Referring to FIGS. 1A and 1B, the conductive wires 44 are formed on the dielectric layer 160 and extend from the first region AR to the second region PR. The conductive wires 44 can be connected to the control gate 128 of the first region AR via the contact window 142 and can be connected to a decoder. The conductive wires 44 are also connected to the heavily doped region 34 of the diode 33 via the contact window 42. In other words, the contact windows 42 and 142 are connected to the same conductive wire 44 and are thus at the same electrical potential. In some embodiments, the semiconductor element SD1 further includes metal silicide layers 140, 40 to reduce the contact resistance. The metal silicide layer 140 is located between the contact window 142 and the control gate layer 128. The metal silicide 40 is located between the contact window 42 and the heavily doped region 34. Since the contact window 42 is disposed outside the periphery of the first region AR. Therefore, in the subsequent metallization process, the plasma discharge 46 used will, before entering the first region AR, first use the wire 44 and the contact window 42 as the discharge path and be introduced into the diode 33. Thus, it is possible to avoid the plasma discharge from damaging the tunneling layer (gate dielectric layer) 118 of the memory element, and improve the retention performance of the memory element. Since the contact window 42 and the contact window 142 can be formed via the same photomask, there is no need to add an additional photomask. In the above embodiment, the diode 33 is disposed between the guard ring 16 and the memory element 116A. In other embodiments, referring to FIGS. 2A and 2B, the diode 33 of the semiconductor element SD2 can also be disposed outside the guard ring 16. That is, the guard ring 16 is interposed between the memory element 116A and the diode 33. FIG. 2A is a top view of a semiconductor element according to an embodiment of the present invention. FIG. 2B is a cross-sectional view taken along line II-II' of FIG. 2A. FIG. 2C is another cross-sectional view taken along line II-II' of FIG. 2A. Referring to FIG. 2B, similarly, the doped ring 38 is adjacent to the guard ring 16. The doped ring 38 and the guard ring 16 are both disposed in the well region 12. The doped ring 38 can partially overlap with the guard ring 16 (as shown in FIG. 2B), or not overlap (as shown in FIG. 2C) and be separated by a non-zero distance. The doped ring 38 is disposed outside the guard ring 16, and thus is farther from the first region AR than the guard ring 16. The doped ring 38 is located in the well region 12 of the second region PR, as shown in FIG. 2B. Referring to FIG. 2A, the doped ring 38 includes a first doped region 38A and a plurality of second doped regions 38B. The first doped region 38A is, for example, an open non-closed ring surrounding the well region 12 on the periphery of the first region AR. In other words, the first doped region 38A has an opening 38C. The plurality of second doped regions 38B are located in the well region 12 of the opening 38C. The plurality of second doped regions 38B are, for example, in an island shape and are separated from each other. In other words, the doped ring 38 formed by the first doped region 38A and the plurality of second doped regions 38B is a non-closed ring. The lightly doped region 36 can partially overlap with the guard ring 16 (as shown in FIG. 2B), or not overlap (as shown in FIG. 2C) and be spaced apart by a non-zero distance. The heavily doped region 34 does not overlap with the guard ring 16 (as shown in FIGS. 2B and 2C) and is spaced apart by a non-zero distance. The above description is based on the memory element 116A. However, embodiments of the present invention can also be applied to various memory elements 116B, 116C, 116D, as shown in FIGS. 3A and 3B, FIGS. 4A and 4B, and FIGS. 5A and 5B respectively. In FIGS. 3A, 4A, and 5A, the example of the diode 33 being disposed within the guard ring 16 is illustrated. However, embodiments of the present invention are not limited thereto. The diode 33 can also be disposed outside the guard ring 16, as shown in FIGS. 2A and 2B. The diode 33 can also have components and structures similar to those of the semiconductor elements SD1 or SD4. For the sake of brevity, the diode 33 is not shown in FIGS. 3B, 4B, and 5B. FIG. 3A is a top view of a semiconductor element according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line III-III' of FIG. 3A. FIG. 4A is a top view of a semiconductor element according to an embodiment of the present invention. FIG. 4B is a cross-sectional view taken along line IV-IV' of FIG. 4A. FIG. 5A is a top view of a semiconductor element according to an embodiment of the present invention. FIG. 5B is a cross-sectional view taken along line V-V' of FIG. 5A. Referring to FIGS. 3A and 3B, the memory element 116B within the region 100B of the semiconductor element SD3 includes a gate stack structure SK2, a select gate structure SG, a word line structure WL, and a doped region 138. The gate stack structure SK2 includes a tunneling layer 118, a floating gate layer 120, an inter-gate dielectric layer 125, a control gate layer 128, a capping layer 130, and a spacer 132. The select gate structure SG is between two adjacent gate stack structures SK2. The word line structure WL is outside the two gate stack structures SK2. The select gate structure SG and the word line structure WL respectively include a gate dielectric layer and a gate conductor layer. The doped region 138 is located in the substrate 10 outside the two word line structures WL and below the select gate structure SG. The semiconductor element SD3 can further include a metal silicide layer on the gate conductor layers of the select gate structure SG and the word line structure WL. The guard ring 16 can have components and structures similar to those of the gate stack structure SK2. For the sake of simplicity, the detailed components of the guard ring 16 are not shown. Referring to FIGS. 4A and 4B, the memory element 116C within the region 100C of the semiconductor element SD4 includes a gate stack structure SK3, a select gate structure SG, and a doped region 138. The gate stack structure SK3 includes a tunneling layer 117, a charge storage layer 119, a blocking layer 121, and a control gate layer 128. The tunneling layer 117 is, for example, silicon oxide. The charge storage layer 119 is, for example, silicon nitride. The blocking layer 121 is, for example, silicon oxide. The control gate layer 128 is, for example, polysilicon. The select gate structure SG includes a gate dielectric layer and a gate conductor layer. The doped region 138 is in the substrate 10 outside the gate stack structure SK3 and the select gate structure SG. The protection ring 16 may have components and structures similar to those of the gate stack structure SK3. For simplicity, the detailed components of the protection ring 16 are not shown. Referring to FIGS. 5A and 5B, the memory element 116D of the semiconductor device SD5 includes a gate stack structure SK4. The gate stack structure SK4 includes a tunneling layer 118, a floating gate layer 120, an inter-gate dielectric layer 125, a control gate layer 128, and a metal silicide layer 140. The metal silicide layer 140 covers most or all of the top surface of the control gate layer 128. The metal silicide layer 140 also covers the top surface of the doped region 130. The protection ring 16 may have components and structures similar to those of the gate stack structure SK4. For simplicity, the detailed components of the protection ring 16 are not shown. In summary, in the embodiments of the present invention, by providing a diode, the memory element is protected to avoid the plasma discharge used in the subsequent metallization process from damaging the gate dielectric layer / tunneling layer of the memory, thereby improving the retention performance of the memory element. The diode may partially overlap or not overlap with the protection ring. The diode may be disposed between the protection ring and the memory array, or disposed around the protection ring. 10: Substrate 12: Well region 14: Isolation structure 16: Protection ring 18: Dielectric layer 20: Conductor layer 22: Dielectric layer 24: Dielectric layer 26: Dielectric layer 28: Conductor layer 30: Capping layer 32: Spacer 33: Diode 34: Heavily doped region 36: Lightly doped region 38: Doped ring 38A: First doped region 38B: Second doped region 38C Opening 40: Metal silicide layer 42: Contact window 44: Wire 46: Plasma discharge 50: Interconnection structure 100A: Region 100B: Region 100C: Region 100D: Region 116A: Memory element 116A’:Dummy memory element 116B: Memory element 116C: Memory element 116D: Memory element 117: Tunneling layer 118: Tunneling layer 119: Charge storage layer 120: Floating gate layer 121: Barrier layer 122: Silicon oxide layer 124: Silicon nitride layer 125: Inter-gate dielectric layer 126: Silicon oxide layer 128: Control gate layer 130: Capping layer 132: Spacer 138: Doped region 140: Metal silicide layer 142: Contact window 160: Dielectric layer AR: First region E1: End E2: End PR: Second region SD1: Semiconductor element SD2: Semiconductor element SD3: Semiconductor element SD4: Semiconductor element SD5: Semiconductor element SG: Select gate structure SK1: Gate stack structure SK2: Gate stack structure SK3: Gate stack structure SK4: Gate stack structure WL: Word line structure I-I’: Line II-II’: Line III-III: Line IV-IV’: Line V-V’: Line FIG. 1A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line I-I’ of FIG. 1A. FIG. 1C is another cross-sectional view taken along line I-I’ of FIG. 1A. FIG. 2A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 2B is a cross-sectional view taken along line II-II’ of FIG. 2A. FIG. 2C is another cross-sectional view taken along line II-II’ of FIG. 2A. FIG. 3A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line III-III’ of FIG. 3A. FIG. 4A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 4B is a cross-sectional view taken along line IV-IV’ of FIG. 4A. FIG. 5A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 5B is a cross-sectional view taken along line V-V’ of FIG. 5A. 10: Substrate 12: Well region 14: Isolation structure 16: Protection ring 18: Dielectric layer 20: Conductor layer 22: Dielectric layer 24: Dielectric layer 26: Dielectric layer 28: Conductor layer 30: Capping layer 32: Spacer 33: Diode 34: Heavily doped region 36: Lightly doped region 38: Doped ring 42: Contact window 44: Conductor line 46: Plasma discharge 50: Interconnection structure 116A: Memory element 118: Tunneling layer 120: Floating gate layer 122: Silicon oxide layer 124: Silicon nitride layer 125: Inter-gate dielectric layer 126: Silicon oxide layer 128: Control gate layer 130: Capping layer 132: Spacer 140: Metal silicide layer 142: Contact window 160: Dielectric layer AR: First region PR: Second region SD1: Semiconductor element SK1: Gate stack structure I-I’: Line

Claims

1. A semiconductor element, comprising: The substrate includes a first region and a second region, the second region surrounding the first region; A doped ring, located in the substrate of the second region and surrounding the first region, wherein the doped ring comprises: a first doped region, located in the substrate of the second region and surrounding the first region, wherein the first doped region has an opening; a plurality of second doped regions, separated from each other, located in the substrate of the opening; a plurality of contact windows electrically connecting the plurality of second doped regions and the ends of the first doped region; and a plurality of wires connecting the plurality of contact windows and connected to a plurality of conductor layers on the first region.

2. The semiconductor element as claimed in claim 1, wherein the plurality of wires connect the plurality of control gates to the decoder of the plurality of control gates.

3. The semiconductor element as claimed in claim 1 further includes a guard ring on the substrate of the second region, adjacent to the doped ring.

4. The semiconductor device as claimed in claim 3, wherein the guard ring partially overlaps with the doped ring.

5. The semiconductor device as claimed in claim 3, wherein the guard ring does not overlap with the doped ring.

6. The semiconductor element as claimed in claim 3, wherein the doping ring is closer to the first region than the guard ring.

7. The semiconductor device as claimed in claim 3, wherein the doping ring is farther away from the first region than the guard ring.

8. The semiconductor device of claim 3, wherein each of the first doped region and each of the plurality of second doped regions comprises: A lightly doped region is located in the well region, which is at least located in the substrate of the second region; And a densely doped region located within the lightly doped region, wherein the conductivity of the dopant in the well region is different from that of the dopant in the lightly doped region and the densely doped region.

9. The semiconductor element as claimed in claim 8, wherein the guard ring is located within the well region.

10. The semiconductor element as claimed in claim 8, further comprising: A metal silicate layer is located on the heavily doped region.

11. The semiconductor element as claimed in claim 8, further comprising: An isolation structure is located between the first region and the second region.

12. A semiconductor element, comprising: The substrate includes a first region and a second region, the second region surrounding the first region; Multiple memory elements are located in the first region; Multiple diodes are located in the substrate of the second region; multiple contact windows are electrically connected to the multiple diodes; and multiple wires connecting the multiple contact windows and the multiple memory elements, wherein each diode includes: a well region located in the substrate of the second region; a lightly doped region located in the well region; and a heavily doped region located in the lightly doped region, wherein the conductivity of the dopant in the well region is different from the conductivity of the dopant in the lightly doped region and the heavily doped region.

13. The semiconductor element as claimed in claim 12, further comprising: A metal silicate layer is located on the heavily doped region.

14. The semiconductor element as claimed in claim 12 further includes a guard ring on the substrate of the second region, adjacent to the plurality of diodes.

15. The semiconductor element of claim 14, wherein the guard ring partially overlaps with the plurality of diodes.

16. The semiconductor element as claimed in claim 14, wherein the guard ring does not overlap with the plurality of diodes.

17. The semiconductor element of claim 14, wherein the plurality of diodes are closer to the first region than the guard ring.

18. The semiconductor element of claim 14, wherein the plurality of diodes are farther away from the first region than the guard ring.

19. The semiconductor device of claim 12, wherein the plurality of memory elements comprises a plurality of flash memory elements, and the plurality of wires connect a plurality of control gates of the plurality of flash memory elements to a decoder of the plurality of control gates.

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