Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed on the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed horizontally between the first semiconductor channel layer and the second semiconductor channel layer, the first horizontal portion is disposed vertically between the first semiconductor channel layer and the semiconductor substrate, and the second horizontal portion is disposed vertically between the second semiconductor channel layer and the semiconductor substrate, with the first horizontal portion and the second horizontal portion respectively connected to the vertical portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device including a plurality of semiconductor channel layers and a method for manufacturing the same. Prior Art

[0002] As semiconductor device technology continues to advance, the traditional planar metal-oxide-semiconductor (MOS) transistor process is becoming increasingly difficult to scale. Consequently, the industry has proposed replacing planar transistors with three-dimensional or non-planar multi-gate transistors. For example, dual-gate Fin Field Effect Transistors (FinFETs), tri-gate FinFETs, and omega FinFETs have all been proposed. Furthermore, gate-all-around (GAA) transistors, which utilize nanowires and nanosheets as channel structures, have recently been developed as a solution to further increase device integration and performance. However, within the GAA design concept, further improving operating performance through process and / or structural design remains a constant pursuit for researchers in the field. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, which utilizes an isolation structure having a horizontal portion provided on a semiconductor substrate to reduce the off current of the semiconductor device, thereby improving the relevant operating performance of the semiconductor device.

[0004] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed on the semiconductor substrate. The isolation structure comprises a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed horizontally between the first semiconductor channel layer and the second semiconductor channel layer, the first horizontal portion is disposed vertically between the first semiconductor channel layer and the semiconductor substrate, and the second horizontal portion is disposed vertically between the second semiconductor channel layer and the semiconductor substrate. The first and second horizontal portions are respectively connected to the vertical portion.

[0005] One embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps. A first semiconductor channel layer and a second semiconductor channel layer are formed on a semiconductor substrate. Then, an isolation structure is formed on the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is horizontally disposed between the first semiconductor channel layer and the second semiconductor channel layer, the first horizontal portion is vertically disposed between the first semiconductor channel layer and the semiconductor substrate, and the second horizontal portion is vertically disposed between the second semiconductor channel layer and the semiconductor substrate. The first and second horizontal portions are respectively connected to the vertical portion. Simple diagram description

[0006] FIG. 1 is a schematic top view of a semiconductor device according to a first embodiment of the present invention. FIG2 is a schematic cross-sectional view taken along the AA′ line in FIG1 . FIG3 is a schematic cross-sectional view taken along the BB′ line in FIG1 . FIG4 to FIG13 are schematic diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 5 shows a schematic diagram of the situation after Figure 4; Figure 6 shows a schematic diagram of the situation after Figure 5; Figure 7 shows a schematic diagram of the situation after Figure 6; Figure 8 shows a schematic diagram of the situation after Figure 7; Figure 9 shows a schematic diagram of the situation after Figure 8; Figure 10 shows a schematic diagram of the situation after Figure 9; Figure 11 shows another schematic cross-sectional view of the situation in Figure 10; Figure 12 shows a schematic diagram of the situation after Figure 11; FIG. 13 is a schematic diagram showing the situation after FIG. 10 . FIG14 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 15 is another schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention. FIG. 16 to FIG. 18 are schematic diagrams showing a method for manufacturing a semiconductor device according to another embodiment of the present invention, wherein Figure 17 is a schematic cross-sectional view taken along line C-C 'in FIG. 16; FIG18 is a schematic cross-sectional view taken along the DD' line in FIG16. Implementation Method

[0007] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the invention.

[0008] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0009] The terms “on,” “over,” and “over” are to be interpreted in the broadest sense, such that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0010] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0011] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0012] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0013] Please refer to Figures 1 to 3. Figure 1 is a schematic top view of a semiconductor device 101 according to a first embodiment of the present invention. Figure 2 is a schematic cross-sectional view taken along line AA' in Figure 1, and Figure 3 is a schematic cross-sectional view taken along line BB' in Figure 1. As shown in Figures 1 to 3, the semiconductor device 101 includes a semiconductor substrate 10, a first semiconductor channel layer 16A, a second semiconductor channel layer 16B, and an isolation structure S1. The first semiconductor channel layer 16A, the second semiconductor channel layer 16B, and the isolation structure S1 are disposed on the semiconductor substrate 10 in a vertical direction D3. The isolation structure S1 includes a vertical portion S11, a first horizontal portion S12, and a second horizontal portion S13. The vertical portion S11 is disposed between the first semiconductor channel layer 16A and the second semiconductor channel layer 16B in a horizontal direction D1. The first horizontal portion S12 is disposed between the first semiconductor channel layer 16A and the semiconductor substrate 10 in a vertical direction D3. The second horizontal portion S13 is disposed between the second semiconductor channel layer 16B and the semiconductor substrate 10 in a vertical direction D3. The first horizontal portion S12 and the second horizontal portion S13 are respectively connected to the vertical portion S11. By disposing the first horizontal portion S12 and the second horizontal portion S13 of the isolation structure S1 between the semiconductor substrate 10 and the first semiconductor channel layer 16A and between the semiconductor substrate 10 and the second semiconductor channel layer 16B, respectively, the off current of the semiconductor device 101 can be reduced, thereby improving the operating performance of the semiconductor device 101, such as improving the subthreshold swing (SS) of the semiconductor device 101.

[0014] In some embodiments, the vertical direction D3 can be considered as the thickness direction of the semiconductor substrate 10. The semiconductor substrate 10 may have a top surface 10TS and a bottom surface 10BS opposite to each other in the vertical direction D3. The first semiconductor channel layer 16A, the second semiconductor channel layer 16B, and the isolation structure S1 may be disposed on one side of the top surface TS of the semiconductor substrate 10. Horizontal directions substantially orthogonal to the vertical direction D3 (e.g., the horizontal direction D1, the horizontal direction D2, and other directions orthogonal to the vertical direction D3) may be substantially parallel to the top surface 10TS and / or the bottom surface 10BS of the semiconductor substrate 10, but are not limited thereto. As described herein, the distance between a relatively high position or / and component in the vertical direction D3 and the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3 may be greater than the distance between a relatively low position or / and component in the vertical direction D3 and the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3. The lower portion or bottom of each component may be closer to the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3 than the upper portion or top of the component. Another component above a component may be considered relatively far away from the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3, while another component below a component may be considered relatively close to the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3. Furthermore, the upper surface of a component described herein may include the topmost surface of the component in the vertical direction D3, and the bottom surface of a component may include the bottommost surface of the component in the vertical direction D3, but the present invention is not limited thereto.

[0015] In some embodiments, the semiconductor device 101 may include a plurality of first semiconductor channel layers 16A and a plurality of second semiconductor channel layers 16B. The plurality of first semiconductor channel layers 16A may overlap with each other in a vertical direction D3 but may be separated from each other and / or not directly connected to each other. The plurality of second semiconductor channel layers 16B may overlap with each other in a vertical direction D3 but may be separated from each other and / or not directly connected to each other. The plurality of first semiconductor channel layers 16A may be disposed on a first horizontal portion S12 of an isolation structure S1 in the vertical direction D3, and the plurality of second semiconductor channel layers 16B may be disposed on a second horizontal portion S13 of the isolation structure S1 in the vertical direction D3. In some embodiments, a plurality of first semiconductor channel layers 16A and a plurality of second semiconductor channel layers 16B may be disposed on opposite sides of a vertical portion S11 of the isolation structure S1 in the horizontal direction D1. The vertical portion S11 may be partially sandwiched between the first semiconductor channel layers 16A and the corresponding second semiconductor channel layers 16B in the horizontal direction D1, and each first semiconductor channel layer 16A and each second semiconductor channel layer 16B may be directly connected to the vertical portion S11. In some embodiments, the first semiconductor channel layers 16A and the second semiconductor channel layers 16B may each comprise a semiconductor material such as silicon, silicon germanium, or other suitable semiconductor materials. The first semiconductor channel layers 16A and the second semiconductor channel layers 16B may be considered nanosheets due to their shape and / or size (for example, but not limited to, a thickness between 5 nm and 100 nm), but the present invention is not limited thereto. Furthermore, the material composition of the vertical portion S11 of the isolation structure S1 can be the same as or different from the material composition of the first horizontal portion S12 and the material composition of the second horizontal portion S13, depending on design requirements. In some embodiments, the vertical portion S11, the first horizontal portion S12, and the second horizontal portion S13 of the isolation structure S1 can each comprise an insulating material, such as an oxide insulating material (for example, but not limited to, silicon oxide), a nitride insulating material (for example, but not limited to, silicon nitride), a low-k dielectric material (for example, but not limited to, a dielectric material with a dielectric constant less than 2.7), or other suitable insulating materials. In some embodiments, the vertical portion S11 can include a dielectric layer 22 and a dielectric layer 24. The dielectric layer 24 can be disposed on the dielectric layer 22. The dielectric layer 22 can have a U-shaped structure in a cross-sectional view of the semiconductor device 101, horizontally surrounding the dielectric layer 24. The material composition of the dielectric layer 22 can be different from the material composition of the dielectric layer 24 (for example, a nitride insulating material and an oxide insulating material, respectively), but the present invention is not limited thereto.

[0016] In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. Furthermore, the semiconductor device 101 may further include a trench isolation structure 18 disposed within the semiconductor substrate 10 to isolate regions corresponding to different transistors within the semiconductor substrate 10. The trench isolation structure 18 may include a single layer or multiple layers of insulating material, such as an oxide insulating material (e.g., silicon oxide) or other suitable insulating material. In some embodiments, a portion of the trench isolation structure 18 may be located below the vertical portion S11 of the isolation structure S1 in the vertical direction D3, but is not limited thereto. Furthermore, the semiconductor device 101 may further include a first gate structure GS1 and a second gate structure GS2 disposed above the semiconductor substrate 10. The first gate structure GS1 may surround each first semiconductor channel layer 16A, and the second gate structure GS2 may surround each second semiconductor channel layer 16B. A portion of the first gate structure GS1 may be sandwiched between two adjacent first semiconductor channel layers 16A in the vertical direction D3. Another portion of the first gate structure GS1 may be sandwiched between the bottommost first semiconductor channel layer 16A and the first horizontal portion S12 of the isolation structure S1 in the vertical direction D3. Another portion of the first gate structure GS1 may be disposed above the topmost first semiconductor channel layer 16A and the vertical portion S11 of the isolation structure S1 in the vertical direction D3. Similarly, a portion of the second gate structure GS2 may be sandwiched between two adjacent second semiconductor channel layers 16B in the vertical direction D3. Another portion of the second gate structure GS2 may be sandwiched between the bottommost second semiconductor channel layer 16B and the second horizontal portion S13 of the isolation structure S1 in the vertical direction D3. Another portion of the second gate structure GS2 may be disposed above the topmost second semiconductor channel layer 16B and the vertical portion S11 of the isolation structure S1 in the vertical direction D3.

[0017] In some embodiments, the first gate structure GS1 and the second gate structure GS2 may be connected to each other, and the material composition of the first gate structure GS1 may be different from the material composition of the second gate structure GS2, but the present invention is not limited thereto. For example, the first gate structure GS1 may include a first portion 38A of an interface layer 38, a first portion 40A of a dielectric layer 40, a first portion 44A of a second work function layer 44, and a first portion 46A of a conductive layer 46 stacked in sequence, while the second gate structure GS2 may include a second portion 38B of the interface layer 38, a second portion 40B of the dielectric layer 40, a first work function layer 42, a second portion 44B of the second work function layer 44, and a second portion 46B of the conductive layer 46 stacked in sequence. The interface layer 38 may include an oxide dielectric material or other suitable dielectric material, and the first portion 38A and the second portion 38B of the interface layer 38 may be directly connected. The dielectric layer 40 may include a single layer or multiple layers of a high-k dielectric material or other suitable dielectric material, and the first portion 40A and the second portion 40B of the dielectric layer 40 may be directly connected. The high-k dielectric material may include hafnium oxide (HfOx), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other suitable high-k dielectric materials. The first work function layer 42 and the second work function layer 44 may respectively comprise titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl3), aluminum titanium nitride (TiAlN), or other suitable conductive work function materials. The material composition of the first work function layer 42 may be different from the material composition of the second work function layer 44, and the first portion 44A and the second portion 44B of the second work function layer 44 may be directly connected. The conductive layer 46 may comprise a metallic conductive material, such as tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable conductive materials with relatively low resistivity. The first portion 46A and the second portion 46B of the conductive layer 46 may be directly connected.

[0018] In some embodiments, the semiconductor device 101 may further include a first source / drain structure 34A and a second source / drain structure 34B. The first source / drain structure 34A may be disposed on the first horizontal portion S12 of the isolation structure S1, and the second source / drain structure 34B may be disposed on the second horizontal portion S13 of the isolation structure S1. The vertical portion S11 of the isolation structure S1 may be partially disposed in or / and sandwiched between the first source / drain structure 34A and the second source / drain structure 34B in the horizontal direction D1. Furthermore, the first source / drain structure 34A may be directly connected to each first semiconductor channel layer 16A, and the second source / drain structure 34B may be directly connected to each second semiconductor channel layer 16B. In some embodiments, the semiconductor device 101 may include two first source / drain structures 34A and two second source / drain structures 34B. The two first source / drain structures 34A may be respectively arranged on two opposite sides of the first gate structure GS1 in the horizontal direction D2, and the two second source / drain structures 34B may be respectively arranged on two opposite sides of the second gate structure GS2 in the horizontal direction D2. The horizontal direction D2 may be substantially orthogonal to the horizontal direction D1, but is not limited thereto.

[0019] In some embodiments, the first gate structure GS1, the first semiconductor channel layer 16A, and the two first source / drain structures 34A may form at least a portion of transistor T1, while the second gate structure GS2, the second semiconductor channel layer 16B, and the two second source / drain structures 34B may form at least a portion of transistor T2. The vertical portion S11 of the isolation structure S1 may be used to isolate the semiconductor channel layers and source / drain structures of transistors T1 and T2. In some embodiments, transistors T1 and T2 may each be considered a gate-all-around (GAA) transistor structure, but this is not limiting. In some embodiments, the first source / drain structure 34A and the second source / drain structure 34B may each comprise an epitaxial material such as epitaxial silicon, epitaxial silicon germanium (SiGe), epitaxial silicon phosphide (SiP), or other suitable epitaxial materials. Furthermore, the material composition of the first source / drain structure 34A may differ from the material composition of the second source / drain structure 34B, particularly when transistor T1 and transistor T2 are different types of transistor structures. For example, transistor T1 may be an n-type field-effect transistor (FET) and transistor T2 may be a p-type FET. The first work function layer 42 may be a p-type work function layer. The first source / drain structure 34A may comprise epitaxial silicon phosphide, while the second source / drain structure 34B may comprise epitaxial silicon germanium, but the present invention is not limited thereto. In some embodiments, corresponding conductive silicide layers (not shown) may be disposed on the surfaces of the first source / drain structure 34A and the second source / drain structure 34B according to design requirements to improve the electrical connection between the source / drain structure and the contact structure (not shown).

[0020] In some embodiments, the semiconductor device 101 may further include a spacer structure 30 and a dielectric layer 36. The spacer structure 30 and the dielectric layer 36 may be disposed on the semiconductor substrate 10. The spacer structure 30 may be located on the sidewalls of the first gate structure GS1, the sidewalls of the second gate structure GS2, the sidewalls of the first source / drain structure 34A, and the sidewalls of the second source / drain structure 34B. The dielectric layer 36 may cover the spacer structure 30, the first source / drain structure 34A, the second source / drain structure 34B, and a portion of the vertical portion S11 of the isolation structure S1. The spacer structure 30 may include a single layer or multiple layers of insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials. The dielectric layer 36 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or other suitable dielectric materials. In a top view of the semiconductor device 101 (e.g., FIG. 1 ), the first gate structure GS1 and the second gate structure GS2 may be different portions of a gate structure GS extending along a horizontal direction D1. The vertical portion S11 of the isolation structure S1 may extend along the horizontal direction D2, and the gate structure GS may straddle the vertical portion S11 of the isolation structure S1. Furthermore, as shown in FIG. 2 , a portion of the first gate structure GS1 may be sandwiched between the spacer substructure 30 and the first horizontal portion S12 of the isolation structure S1 in the horizontal direction D1, and a portion of the second gate structure GS2 may be sandwiched between the spacer substructure 30 and the second horizontal portion S13 of the isolation structure S1 in the horizontal direction D1. In some embodiments, a first gate structure GS1 sandwiched between the spacer substructure 30 and the first horizontal portion S12 in the horizontal direction D1, and a second gate structure GS2 sandwiched between the spacer substructure 30 and the second horizontal portion S13 in the horizontal direction D1, can be disposed above the trench isolation structure 18. The first horizontal portion S12 and the second horizontal portion S13 of the isolation structure S1 can respectively form an isolation effect between the first gate structure GS1 and the semiconductor substrate 10, and between the second gate structure GS2 and the semiconductor substrate 10. Therefore, the first horizontal portion S12 can be used to reduce leakage current between the transistor T1 and the semiconductor substrate 10, while the second horizontal portion S13 can be used to reduce leakage current between the transistor T2 and the semiconductor substrate 10, thereby improving the operating performance of the semiconductor device 101.

[0021] Please refer to Figures 4 to 13, and also to Figures 1 to 3. Figures 4 to 13 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 5 illustrates a state subsequent to Figure 4, Figure 6 illustrates a state subsequent to Figure 5, Figure 7 illustrates a state subsequent to Figure 6, Figure 8 illustrates a state subsequent to Figure 7, Figure 9 illustrates a state subsequent to Figure 8, Figure 10 illustrates a state subsequent to Figure 9, Figure 11 illustrates another cross-sectional view of the state of Figure 10, Figure 12 illustrates a state subsequent to Figure 11, and Figure 13 illustrates a state subsequent to Figure 10. In some embodiments, Figure 2 may be considered to illustrate a state subsequent to Figure 13, and Figure 3 may be considered to illustrate a state subsequent to Figure 12, but this is not limiting. As shown in Figures 1 to 3, the fabrication method of this embodiment may include the following steps: forming a first semiconductor channel layer 16A and a second semiconductor channel layer 16B on a semiconductor substrate 10, and forming an isolation structure S1 on the semiconductor substrate 10. The isolation structure S1 includes a vertical portion S11, a first horizontal portion S12, and a second horizontal portion S13. The vertical portion S11 is disposed between the first semiconductor channel layer 16A and the second semiconductor channel layer 16B in a horizontal direction D1, the first horizontal portion S12 is disposed between the first semiconductor channel layer 16A and the semiconductor substrate 10 in a vertical direction D3, and the second horizontal portion S13 is disposed between the second semiconductor channel layer 16B and the semiconductor substrate 10 in a vertical direction D3. The first horizontal portion S12 and the second horizontal portion S13 are respectively connected to the vertical portion S11.

[0022] To further illustrate, the fabrication method of this embodiment may include, but is not limited to, the following steps. As shown in FIG. 4 , a first sacrificial layer 12 may be formed on the upper surface 10TS of the semiconductor substrate 10. After the first sacrificial layer 12 is formed, a plurality of second sacrificial layers 14 and a plurality of semiconductor layers 16 are alternately stacked and formed on the first sacrificial layer 12. Each semiconductor layer 16 may be located above at least one second sacrificial layer 14. In some embodiments, a second sacrificial layer 14 is disposed between two adjacent semiconductor layers 16 in the vertical direction D3, a second sacrificial layer 14 is disposed between the bottommost semiconductor layer 16 and the first sacrificial layer 12, and a second sacrificial layer 14 is disposed above the topmost semiconductor layer 16, but this is not limiting. In some embodiments, the semiconductor layer 16 may include silicon, silicon germanium, or other suitable semiconductor materials. The material composition of the semiconductor layer 16 is different from that of the second sacrificial layer 14, and the material composition of the second sacrificial layer 14 may be different from that of the first sacrificial layer 12, to achieve a desired etching selectivity in subsequent processes, but this is not limiting. For example, the semiconductor layer 16 may be a semiconductor silicon layer, while the first sacrificial layer 12 and the second sacrificial layer 14 may each be a silicon-germanium material layer with different composition ratios, or other suitable sacrificial materials. For example, the chemical formula of the material of the first sacrificial layer 12 may be Si1-xGex, while the chemical formula of the material of the second sacrificial layer 14 may be Si1-yGey, where x is greater than 0.5 and y is less than 0.3, but the present invention is not limited thereto. Furthermore, in some embodiments, the thickness of each semiconductor layer 16 may be between 2 nm and 5 nm, while the thickness of the first sacrificial layer 12 and the second sacrificial layer 14 may be adjusted based on design requirements, for example, between 2 nm and 5 nm, between 5 nm and 8 nm, or between 10 nm and 30 nm, but the present invention is not limited thereto.

[0023] As shown in Figures 4 and 5, a patterning process 90 may be performed. In some embodiments, the patterning process 90 may include forming a mask pattern (not shown) on the topmost semiconductor layer 16 and performing one or more etching steps using the mask pattern as an etching mask to etch the second sacrificial layer 14, the semiconductor layer 16, the first sacrificial layer 12, and the semiconductor substrate 10 to achieve a patterned effect, but the present invention is not limited thereto. At least a portion of each second sacrificial layer 14 may be patterned by the patterning process 90 to form a first portion 14A and a second portion 14B that are separated from each other. At least a portion of each semiconductor layer 16 may be patterned by the patterning process 90 to form a first semiconductor channel layer 16A and a second semiconductor channel layer 16B that are separated from each other. At least a portion of each first sacrificial layer 12 may be patterned by the patterning process 90 to form a first sacrificial pattern 12A and a second sacrificial pattern 12B that are separated from each other. In some embodiments, the first portion 14A of the second sacrificial layer 14 and the first semiconductor channel layer 16A may be alternately disposed on the first sacrificial pattern 12A in the vertical direction D3, while the second portion 14B of the second sacrificial layer 14 and the second semiconductor channel layer 16B may be alternately disposed on the second sacrificial pattern 12B in the vertical direction D3. In some embodiments, a portion of the semiconductor substrate 10 may be removed by the patterning process 90 to form a trench TR in the semiconductor substrate 10, but this is not limiting. It is worth noting that the method for forming the first semiconductor channel layer 16A and the second semiconductor channel layer 16B in the present invention may include, but is not limited to, the steps described above. Therefore, other suitable methods may be used to form the first semiconductor channel layer 16A and the second semiconductor channel layer 16B depending on design requirements.

[0024] As shown in FIG5 and FIG6 , a trench isolation structure 18 may be formed in the trench TR. After the trench isolation structure 18 is formed, a first dielectric structure DS1 may be formed on the semiconductor substrate 10. A portion of the first dielectric structure DS1 may be sandwiched between the first semiconductor channel layer 16A and the second semiconductor channel layer 16B in the horizontal direction D1. Another portion of the first dielectric structure DS1 may be sandwiched between the first sacrificial pattern 12A and the second sacrificial pattern 12B in the horizontal direction D1. Another portion of the first dielectric structure DS1 may be sandwiched between the first portion 14A and the second portion 14B of the second sacrificial layer 14 in the horizontal direction D1. In some embodiments, the first dielectric structure DS1 may directly contact the first sacrificial pattern 12A, the second sacrificial pattern 12B, the first semiconductor channel layer 16A, the second semiconductor channel layer 16B, and the first portion 14A and the second portion 14B of the second sacrificial layer 14. The first dielectric structure DS1 may include, but is not limited to, the aforementioned dielectric layer 22 and dielectric layer 24. In some embodiments, a dielectric layer 22 may be conformally formed on the surfaces of the first sacrificial pattern 12A, the second sacrificial pattern 12B, the first semiconductor channel layer 16A, the second semiconductor channel layer 16B, the second sacrificial layer 14, and the trench isolation structure 18, and a dielectric layer 24 may be formed on the dielectric layer 22. After the dielectric layer 24 is formed on the dielectric layer 22, an etch-back process may be performed on the dielectric layer 24 and the dielectric layer 22 to remove portions of the dielectric layer 24 and the dielectric layer 22 to form the first dielectric structure DS1, but the present invention is not limited thereto.

[0025] As shown in Figures 6 and 7 , after forming the first dielectric structure DS1, the first and second sacrificial patterns 12A and 12B can be removed to form a gap G between the bottommost second sacrificial layer 14 and the semiconductor substrate 10. In some embodiments, an isotropic etching process with relatively high etch selectivity (such as, but not limited to, wet etching) can be utilized in conjunction with the material composition difference between the first and second sacrificial layers 12 and 14 to reduce etching damage to other material layers during the removal of the first and second sacrificial patterns 12A and 12B, but the invention is not limited thereto. Then, as shown in Figures 7 and 8 , a dielectric material 26 can be formed on the semiconductor substrate 10. The dielectric material 26 can cover the first dielectric structure DS1, the second sacrificial layer 14, the semiconductor layer 16, and the trench isolation structure 18, and can fill the gap G. In some embodiments, the gap G can be completely filled with the dielectric material 26, but the invention is not limited thereto. Thereafter, as shown in FIG8 and FIG9 , the dielectric material 26 may be subjected to an etch-back process to remove a portion of the dielectric material 26, thereby forming a second dielectric structure DS2 between the first portion 14A of the bottom-most second sacrificial layer 14 and the semiconductor substrate 10, and a third dielectric structure DS3 between the second portion 14B of the bottom-most second sacrificial layer 14 and the semiconductor substrate 10. In other words, the second dielectric structure DS2 and the third dielectric structure DS3 may be different portions of the dielectric material 26, and thus the material composition of the second dielectric structure DS2 may be the same as the material composition of the third dielectric structure DS3.

[0026] Furthermore, the first portion 14A of the bottom-most second sacrificial layer 14 can be sandwiched between the first semiconductor channel layer 16A and the second dielectric structure DS2 in the vertical direction D3, and the second portion 14B of the bottom-most second sacrificial layer 14 can be sandwiched between the second semiconductor channel layer 16B and the third dielectric structure DS3 in the vertical direction D3. The second dielectric structure DS2 and the third dielectric structure DS3 can each be directly connected to the first dielectric structure DS. As shown in Figures 6 to 9, the method for fabricating the isolation structure S1 of this embodiment can include replacing the first sacrificial pattern 12A with the second dielectric structure DS2 and replacing the second sacrificial pattern 12B with the third dielectric structure DS3. The second dielectric structure DS2 can be the first horizontal portion S12 of the isolation structure S1, the third dielectric structure DS3 can be the second horizontal portion S13 of the isolation structure S1, and the first dielectric structure DS1 can be the vertical portion S11 of the isolation structure S1, but the present invention is not limited thereto. In addition, the manufacturing method of the first dielectric structure DS1, the second dielectric structure DS2, and the third dielectric structure DS3 or the manufacturing method of the isolation structure S1 may include but is not limited to the manufacturing steps of Figures 5 to 9 above. Therefore, other suitable methods can be used to form the first dielectric structure DS1, the second dielectric structure DS2, and the third dielectric structure DS3 according to design requirements.

[0027] As shown in FIG9 and FIG2, after the second dielectric structure DS2 and the third dielectric structure DS3 are formed, the first gate structure GS1 and the second gate structure GS2 described above can be formed on the semiconductor substrate 10. The first gate structure GS1 and the second gate structure GS2 can be partially disposed on the first dielectric structure DS1, and the first gate structure GS1 and the second gate structure GS2 can be connected to each other. As shown in FIG9 and FIG10, in some embodiments, after the second dielectric structure DS2 and the third dielectric structure DS3 are formed, a dummy gate structure 28 can be formed on the first semiconductor channel layer 16A, the second semiconductor channel layer 16B, and the first dielectric structure DS1. The dummy gate structure 28 may include polysilicon, amorphous silicon, or other suitable materials. After forming the dummy gate structure 28, a spacer structure 30 can be formed on the semiconductor substrate 10, and a portion of the spacer structure 30 can be located on the sidewalls of the dummy gate structure 28. After forming the spacer structure 30, the first portion 14A and the second portion 14B of the second sacrificial layer 14 can be replaced with spacer sub-layers 32A and 32B, respectively. Thus, the spacer sub-layers 32A and the first semiconductor channel layer 16A can be alternately disposed on the second dielectric structure DS2 in the vertical direction D3, while the spacer sub-layers 32B and the second semiconductor channel layer 16B can be alternately disposed on the third dielectric structure DS3 in the vertical direction D3. In some embodiments, the spacer sub-layers 32A and 32B can be different portions of the spacer material 32 and thus have the same material composition. The material composition of the spacer material 32 can be different from the material composition of the first dielectric structure DS1, the second dielectric structure DS2, the third dielectric structure DS3, and the semiconductor layer 16. For example, the spacer material 32 can include, but is not limited to, an oxide insulating material or other suitable spacer material.

[0028] As shown in FIG10 and FIG13 , the dummy gate structure 28, the spacer layer 32A, and the spacer layer 32B can be removed to expose the first semiconductor channel layer 16A, the second semiconductor channel layer 16B, the first dielectric structure DS1, the second dielectric structure DS2, and the third dielectric structure DS3. An interface layer 38 can then be conformally formed on the spacer structure 30, the trench isolation structure 18, the first semiconductor channel layer 16A, the second semiconductor channel layer 16B, the first dielectric structure DS1, the second dielectric structure DS2, and the third dielectric structure DS3. A dielectric layer 40 can then be conformally formed on the interface layer 38, and a first work function layer 42 can then be conformally formed on the dielectric layer 40. As shown in Figures 13 and 2, in some embodiments, a portion of the first work function layer 42 (for example, the first work function layer 42 on the first semiconductor channel layer 16A and the second dielectric structure DS2) can be removed. After removing this portion of the first work function layer 42, a second work function layer 44 and a conductive layer 46 can be formed, and a removal process (for example, but not limited to a chemical mechanical polishing process) is performed to remove a portion of the interface layer 38, a portion of the dielectric layer 40, a portion of the first work function layer 42, a portion of the second work function layer 44, and a portion of the conductive layer 46 to form a first gate structure GS1 and a second gate structure GS2.

[0029] As shown in Figures 10 and 11, Figure 11 may be a cross-sectional view corresponding to the location where the source / drain structure will be subsequently formed. In some embodiments, after the spacer sub-layers 32A and 32B are formed, another portion of the spacer sub-structure 30 may be located on the sidewalls of the spacer sub-layers 32A and 32B, the first semiconductor channel layer 16A, the second semiconductor channel layer 16B, the second dielectric structure DS2, and the third dielectric structure DS3. As shown in Figures 11 and 12, the spacer sub-layers 32A and 32B may be removed. After the spacer sub-layers 32A and 32B are removed, the first source / drain structure 34A may be formed on the second dielectric structure DS2, and the second source / drain structure 34B may be formed on the third dielectric structure DS3. A portion of the first dielectric structure DS1 may be located between the first source / drain structure 34A and the second source / drain structure 34B in the horizontal direction D1, and a portion of the spacer substructure 30 may be located on the sidewalls of the first source / drain structure 34A and the sidewalls of the second source / drain structure 34B. In some embodiments, the fabrication steps corresponding to FIG. 12 may be performed after the fabrication steps corresponding to FIG. 10 and before the fabrication steps corresponding to FIG. 13 . Therefore, the first source / drain structure 34A and the second source / drain structure 34B may be formed before the steps of forming the first gate structure and the second gate structure, and the dummy gate structure 28 in FIG. 10 may be formed before the steps of forming the first source / drain structure 34A and the second source / drain structure 34B in FIG. 12 .

[0030] As shown in FIG12 and FIG3 , a dielectric layer 36 can be formed to cover the spacer substructure 30, the first source / drain structure 34A, the second source / drain structure 34B, and a portion of the first dielectric structure DS1. In some embodiments, the fabrication steps corresponding to FIG13 can be performed after the fabrication steps corresponding to FIG3 , and the dummy gate structure 28, the spacer sublayer 32A, and the spacer sublayer 32B in FIG10 can be removed after the step of forming the dielectric layer 36 in FIG3 . In other words, after the spacer substructure 30, the first source / drain structure 34A, the second source / drain structure 34B, and the dielectric layer 36 are formed, the dummy gate structure 28 can be removed and the first gate structure GS1 and the second gate structure GS2 can be formed. It is worth noting that the manufacturing method of the first gate structure GS1, the second gate structure GS2, the first source / drain structure 34A and the second source / drain structure 34B of the present embodiment may include but is not limited to the manufacturing steps of Figures 10 to 13, Figure 2 and Figure 3 above. Therefore, other suitable methods can be used to form the first gate structure GS1, the second gate structure GS2, the first source / drain structure 34A and the second source / drain structure 34B according to design requirements.

[0031] The following describes various embodiments of the present invention. For simplicity, the following description focuses on the differences between the various embodiments, without repetitively describing the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with identical reference numerals to facilitate cross-reference between the various embodiments.

[0032] Please refer to Figures 14 and 15. Figure 14 illustrates a schematic cross-sectional view of a semiconductor device 102 according to a second embodiment of the present invention, while Figure 15 illustrates another schematic cross-sectional view of the semiconductor device 102 according to this embodiment. In some embodiments, the corresponding cross-sectional positions of Figure 14 in the top view of the semiconductor device 102 may be similar to the corresponding cross-sectional positions of Figure 2 in Figure 1, and the corresponding cross-sectional positions of Figure 15 in the top view of the semiconductor device 102 may be similar to the corresponding cross-sectional positions of Figure 3 in Figure 1, but are not limited thereto. As shown in Figures 14 and 15, the semiconductor device 102 includes a semiconductor substrate 10, a first semiconductor channel layer 16A, a second semiconductor channel layer 16B, and an isolation structure S2. The first semiconductor channel layer 16A, the second semiconductor channel layer 16B, and the isolation structure S2 are disposed above the semiconductor substrate 10 in a vertical direction D3. The isolation structure S2 includes a vertical portion S21, a first horizontal portion S22, and a second horizontal portion S23. The vertical portion S21 is arranged between the first semiconductor channel layer 16A and the second semiconductor channel layer 16B in the horizontal direction D1, the first horizontal portion S22 is arranged between the first semiconductor channel layer 16A and the semiconductor substrate 10 in the vertical direction D3, and the second horizontal portion S23 is arranged between the second semiconductor channel layer 16B and the semiconductor substrate 10 in the vertical direction D3, and the first horizontal portion S22 and the second horizontal portion S23 are respectively connected to the vertical portion S21. Unlike the first embodiment, the vertical portion S21, the first horizontal portion S22, and the second horizontal portion S23 of the isolation structure S2 in the semiconductor device 102 can each be an air void. This can further reduce the equivalent dielectric constant of the isolation structure S2 (the dielectric constant of air is approximately 1), thereby enhancing the isolation effect of the isolation structure S2. For example, the vertical portion S21, which is an air void, can be used to reduce the parasitic capacitance between the first semiconductor channel layer 16A and the second semiconductor channel layer 16B. Furthermore, the first and second horizontal portions S22 and S23, which are air voids, can be used to further reduce the off-state current of transistors T1 and T2 in the semiconductor device 102, thereby improving the subthreshold swing of transistors T1 and T2. In some embodiments, the isolation structure S2 can be composed solely of air voids without including other materials, but is not limited thereto. Furthermore, the relative relationship between the isolation structure S2 and other components in the semiconductor device 102 may be the same as the relative relationship between the isolation structure S1 and other components in the semiconductor device 101 shown in FIG. 1 to FIG. 3 , but is not limited thereto.

[0033] As shown in FIG14 and FIG15 , semiconductor device 102 may further include an etch-stop layer 52, a dielectric layer 54, an etch-stop layer 56, a contact structure 58, a dielectric layer 62, and a conductive layer 64. Etch-stop layer 52 is disposed on first gate structure GS1, second gate structure GS2, spacer structure 30, and dielectric layer 36. Dielectric layer 54 is disposed on etch-stop layer 52. Etch-stop layer 56 is disposed on dielectric layer 54. Dielectric layer 62 is disposed on etch-stop layer 56. Contact structure 58 is disposed in opening OP1 penetrating etch-stop layer 56, dielectric layer 54, and etch-stop layer 52, and contacts and electrically connects to first gate structure GS1 and / or second gate structure GS2. Conductive layer 64 may be disposed in dielectric layer 62 and connected to contact structure 58. Etch stop layer 52 and etch stop layer 56 may comprise silicon nitride or other suitable dielectric materials. Dielectric layer 54 and dielectric layer 62 may comprise silicon oxide, silicon oxynitride, a low-k dielectric material, or other suitable dielectric materials. Contact structure 58 and conductive layer 64 may comprise, but are not limited to, a barrier layer (not shown) and a conductive material (not shown) disposed on the barrier layer. The barrier layer may comprise titanium nitride, tantalum nitride, or other suitable barrier materials, while the conductive material may comprise, but is not limited to, a material with relatively low resistivity such as tungsten, aluminum, copper, titanium aluminide, titanium, etc. In some embodiments, semiconductor device 102 may further comprise an air gap AG and an opening OP2. Opening OP2 may penetrate etch stop layer 56, dielectric layer 54, etch stop layer 52, and dielectric layer 36 located on vertical portion S21 of isolation structure S2 in a vertical direction D3. Air gap AG may be disposed within opening OP2. The air gap AG may be located on the vertical portion S21 of the isolation structure S2 connected to the first source / drain structure 34A and the second source / drain structure 34B, and may be directly connected to the vertical portion S21, which is also an air gap. In some embodiments, the air gap AG may extend upward in the vertical direction D3 and partially reside in the dielectric layer 62, but the air gap AG does not penetrate the dielectric layer 62.

[0034] Please refer to Figures 14 to 18 in conjunction with Figures 1 to 3. Figures 16 to 18 illustrate a method for fabricating a semiconductor device according to another embodiment of the present invention. Figure 17 is a cross-sectional view taken along line C-C' in Figure 16, and Figure 18 is a cross-sectional view taken along line D-D' in Figure 16. In some embodiments, Figure 17 may be considered to illustrate a state subsequent to Figure 2, Figure 18 may be considered to illustrate a state subsequent to Figure 3, Figure 14 may be considered to illustrate a state subsequent to Figure 17, and Figure 15 may be considered to illustrate a state subsequent to Figure 18, but this is not limiting. As shown in Figures 2, 3, and 16 to 18, in the fabrication method of this embodiment, after forming the first gate structure GS1 and / or the second gate structure GS2, the aforementioned etch stop layer 52, dielectric layer 54, and etch stop layer 56 are formed, and an opening OP1 and two openings OP2 are formed. The opening OP1 may be located on the first gate structure GS1 and / or the second gate structure GS2, while the two openings OP2 may be located on opposite sides of the opening OP1 in the horizontal direction D2. The opening OP2 may be located on the first dielectric structure DS1 in the vertical direction D3 to expose at least a portion of the first dielectric structure DS1, and a contact structure 58 may be formed in the opening OP1.

[0035] Then, as shown in Figures 16 to 18, Figure 14, and Figure 15, a removal process can be performed to remove the first dielectric structure DS1, the second dielectric structure DS2, and the third dielectric structure DS3 to form an air gap isolation structure S2. In some embodiments, the removal process can include a wet etching process with a relatively high etch selectivity, etching the first dielectric structure DS1 exposed by the opening OP2 through the opening OP2 to remove the first dielectric structure DS1, the second dielectric structure DS2, and the third dielectric structure DS3. In addition, the material composition of the interface layer 38 can be different from the material composition of the first dielectric structure DS1, the second dielectric structure DS2, and the third dielectric structure DS3, thereby reducing damage and / or other negative effects of the removal process on the interface layer 38 and other material layers, but the present invention is not limited to this. Then, dielectric layer 62 and conductive layer 64 can be formed. Dielectric layer 62 can be formed by controlling the size of opening OP2 or / and using a process with poor gap-filling performance, thereby preventing or / and reducing the amount of dielectric layer 62 material from filling opening OP2 and the air gap below opening OP2. In this case, air gap AG formed in opening OP2 can partially extend upward into dielectric layer 62, so that the uppermost portion of air gap AG can be higher than the bottom surface of dielectric layer 62 and the upper surface of etch stop layer 56 in vertical direction D3, but the present invention is not limited thereto. It is worth noting that the method for fabricating isolation structure S2 in semiconductor device 102 may include, but is not limited to, the steps described above. Therefore, other fabrication methods may be used to form the vertical portion S21, first horizontal portion S22, and second horizontal portion S23 of isolation structure S2, each of which is an air gap, depending on design requirements.

[0036] In summary, in the semiconductor device and its fabrication method of the present invention, an isolation structure having vertical and horizontal portions can be provided on a semiconductor substrate to provide isolation between different transistor structures, thereby reducing the off-current of the semiconductor device and improving the semiconductor device's operating performance. Furthermore, in some embodiments, the vertical and horizontal portions of the isolation structure can be formed as air gaps to further enhance the isolation effect of the isolation structure. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0037] 10:Semiconductor substrate 10BS: bottom surface 10TS: Top surface 12: First sacrificial layer 12A: First sacrificial pattern 12B: Second sacrificial pattern 14: Second sacrificial layer 14A: Part 1 14B: Part 2 16: Semiconductor layer 16A: first semiconductor channel layer 16B: Second semiconductor channel layer 18: Trench isolation structure 22: Dielectric layer 24: Dielectric layer 26: Dielectric materials 28: Virtual gate structure 30: Gap substructure 32: Interstitial Materials 32A: Gap sublayer 32B: Gap sublayer 34A: First source / drain structure 34B: Second source / drain structure 36: Dielectric layer 38: Interface layer 38A: Part 1 38B: Part 2 40: dielectric layer 40A: Part 1 40B: Part 2 42: first work function layer 44: Second work function layer 44A: Part 1 44B: Part 2 46: conductive layer 46A: Part 1 46B: Part 2 52: Etching stop layer 54: dielectric layer 56: Etch stop layer 58: Contact structure 62: dielectric layer 64: conductive layer 90: Patterning process 101: Semiconductor Device 102: Semiconductor device AG: Air Gap D1: horizontal direction D2: horizontal direction D3: vertical direction DS1: First dielectric structure DS2: Second dielectric structure DS3: The third dielectric structure G:Interval GS: Gate structure GS1: First Gate Structure GS2: Second gate structure OP1: Opening OP2: Opening S1: Isolation structure S11: vertical part S12: first horizontal section S13: Second horizontal section S2: Isolation Structure S21: Vertical section S22: first horizontal section S23: Second horizontal section T1: transistor T2: transistor TR: Groove

Claims

1. A semiconductor device, comprising: A semiconductor substrate; A first semiconductor channel layer is disposed on the semiconductor substrate; A second semiconductor channel layer is disposed on the semiconductor substrate; An isolation structure is disposed on the semiconductor substrate, wherein the isolation structure includes: a vertical portion disposed in a horizontal direction between the first semiconductor channel layer and the second semiconductor channel layer; a first horizontal portion disposed in a vertical direction between the first semiconductor channel layer and the semiconductor substrate; and a second horizontal portion disposed in the vertical direction between the second semiconductor channel layer and the semiconductor substrate, wherein the first horizontal portion and the second horizontal portion are respectively connected to the vertical portion; a first gate structure disposed on the semiconductor substrate and surrounding the first semiconductor channel layer; and a second gate structure disposed on the semiconductor substrate and surrounding the second semiconductor channel layer, wherein the first gate structure and the second gate structure are partially disposed on the vertical portion of the isolation structure, and the first gate structure and the second gate structure are connected to each other.

2. The semiconductor device as claimed in claim 1, wherein the material composition of the vertical portion is different from the material composition of the first horizontal portion and the material composition of the second horizontal portion.

3. The semiconductor device as claimed in claim 1, wherein the vertical portion, the first horizontal portion, and the second horizontal portion are air gaps.

4. The semiconductor device as claimed in claim 1, wherein the material composition of the first gate structure is different from the material composition of the second gate structure.

5. The semiconductor device as described in claim 1, further comprising: A first source / drain structure is disposed on the first horizontal portion of the isolation structure; And a second source / drain structure disposed on the second horizontal portion of the isolation structure, wherein the vertical portion of the isolation structure is partially disposed between the first source / drain structure and the second source / drain structure in the horizontal direction.

6. The semiconductor device as claimed in claim 5, wherein the material composition of the first source / drain structure is different from the material composition of the second source / drain structure.

7. The semiconductor device as described in claim 7, further comprising: A gap substructure is disposed on the semiconductor substrate, wherein the gap substructure is located on the sidewall of the first gate structure, the sidewall of the second gate structure, the sidewall of the first source / drain structure, and the sidewall of the second source / drain structure.

8. The semiconductor device as claimed in claim 7, wherein a portion of the first gate structure is sandwiched in the horizontal direction between the first horizontal portion of the gap substructure and the isolation structure, and a portion of the second gate structure is sandwiched in the horizontal direction between the second horizontal portion of the gap substructure and the isolation structure.

9. The semiconductor device as claimed in claim 1, wherein the first semiconductor channel layer and the second semiconductor channel layer are respectively directly connected to the vertical portion of the isolation structure.

10. A method for manufacturing a semiconductor device, comprising: A first semiconductor channel layer and a second semiconductor channel layer are formed on a semiconductor substrate; An isolation structure is formed on the semiconductor substrate, wherein the isolation structure includes: a vertical portion disposed in a horizontal direction between the first semiconductor channel layer and the second semiconductor channel layer; a first horizontal portion disposed in a vertical direction between the first semiconductor channel layer and the semiconductor substrate; and a second horizontal portion disposed in a vertical direction between the second semiconductor channel layer and the semiconductor substrate, wherein the first horizontal portion and the second horizontal portion are respectively connected to the vertical portion; and a first gate structure and a second gate structure are formed on the semiconductor substrate, wherein the first gate structure surrounds the first semiconductor channel layer, the second gate structure surrounds the second semiconductor channel layer, the first gate structure and the second gate structure are partially disposed on the vertical portion of the isolation structure, and the first gate structure and the second gate structure are connected to each other.

11. A method for fabricating a semiconductor device as claimed in claim 10, wherein the method for forming the first semiconductor channel layer and the second semiconductor channel layer comprises: A semiconductor layer is formed on the semiconductor substrate; And a patterning process is performed, wherein at least a portion of the semiconductor layer is patterned by the patterning process to become the first semiconductor channel layer and the second semiconductor channel layer that are separated from each other.

12. A method for manufacturing a semiconductor device as claimed in claim 11, wherein the method for forming the isolation structure comprises: Before forming the semiconductor layer, a first sacrificial layer is formed on the semiconductor substrate and a second sacrificial layer is formed on the first sacrificial layer, wherein the semiconductor layer is located above the second sacrificial layer, and at least a portion of the first sacrificial layer is patterned by the patterning process to become a first sacrificial pattern and a second sacrificial pattern that are separated from each other; a first dielectric structure is formed on the semiconductor substrate, wherein a portion of the first dielectric structure is sandwiched between the first semiconductor channel layer and the second semiconductor channel layer in the horizontal direction, and another portion of the first dielectric structure is sandwiched between the first sacrificial pattern and the second sacrificial pattern in the horizontal direction; and after forming the first dielectric structure, the first sacrificial pattern is replaced with a second dielectric structure, and the second sacrificial pattern is replaced with a third dielectric structure.

13. A method of fabricating a semiconductor device as claimed in claim 12, wherein a portion of the second sacrificial layer is sandwiched between the first semiconductor channel layer and the second dielectric structure in the vertical direction, and another portion of the second sacrificial layer is sandwiched between the second semiconductor channel layer and the third dielectric structure in the vertical direction.

14. A method of manufacturing a semiconductor device as claimed in claim 12, wherein the first dielectric structure is the vertical portion of the isolation structure, the second dielectric structure is the first horizontal portion of the isolation structure, and the third dielectric structure is the second horizontal portion of the isolation structure.

15. A method of manufacturing a semiconductor device as claimed in claim 12, wherein the first gate structure and the second gate structure are partially disposed on the first dielectric structure.

16. A method for manufacturing a semiconductor device as described in claim 15, wherein the method for forming the isolation structure further comprises: After the first gate structure and the second gate structure are formed, the first dielectric structure, the second dielectric structure and the third dielectric structure are removed, wherein the vertical portion, the first horizontal portion and the second horizontal portion of the isolation structure are air gaps.

17. A method for manufacturing a semiconductor device as claimed in claim 15, wherein the material composition of the first gate structure is different from the material composition of the second gate structure.

18. The method of manufacturing the semiconductor device as described in claim 15, further comprising: Before forming the first gate structure and the second gate structure, a first source / drain structure is formed on the second dielectric structure, and a second source / drain structure is formed on the third dielectric structure, wherein a portion of the first dielectric structure is located between the first source / drain structure and the second source / drain structure in the horizontal direction.

19. The method of manufacturing a semiconductor device as described in claim 18, further comprising: Before forming the first source / drain structure and the second source / drain structure, a dummy gate structure is formed on the first semiconductor channel layer, the second semiconductor channel layer, and the first dielectric structure; after forming the dummy gate structure, a gap substructure is formed on the semiconductor substrate, wherein the gap substructure is located on the sidewall of the dummy gate structure, the sidewall of the first source / drain structure, and the sidewall of the second source / drain structure; and after forming the first source / drain structure and the second source / drain structure and after forming the gap substructure, the dummy gate structure is removed, and the first gate structure and the second gate structure are formed.

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