Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate. A plurality of first filler layers are formed, the plurality of first filler layers filling the first trenches and having protrusions extending from the substrate. Spacers are formed on the sidewalls of the protrusions of the first filler layers. The spacers expose portions of the substrate between adjacent first filler layers. A plurality of second trenches are formed around the first trenches by etching the portions of the substrate exposed by the spacers. A plurality of second filler layers are formed to fill the second trenches. The first filler layers and spacers are completely removed. A gate material layer conformally covering the inner walls of the first trenches is formed. A pair of gate structures are formed in each of the first trenches by separating the gate material layer.

Description

Method of manufacturing a semiconductor device The present inventive concept relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device by using self-alignment. [Cross-reference to related applications] This application claims the priority of Korean Patent Application No. 10-2022-0050075, filed on Apr. 22, 2022, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Manufacturing semiconductor devices with a smaller size requires high-capacity data processing. Therefore, it is necessary to increase the integration degree of such semiconductor devices, and it is necessary to miniaturize the patterns formed on the semiconductor devices. Accordingly, research is being conducted on fine patterns having fine widths and pitches beyond the resolution limit of the photolithography process. Embodiments of the present inventive concept provide a semiconductor device in which grooves formed in a later process are self-aligned with previously formed grooves, thereby preventing misalignment and increasing the reliability of the semiconductor device. In addition, the technical objectives to be achieved by the embodiments of the present inventive concept are not limited to the technical objectives mentioned above, and other technical objectives can be clearly understood by those of ordinary skill in the art from the following description. According to an embodiment of the present inventive concept, there is provided a method of manufacturing a semiconductor device, the method including forming a plurality of first grooves in a substrate. The plurality of first grooves are spaced apart from each other in a first horizontal direction, and each of the plurality of first grooves extends in a second horizontal direction orthogonal to the first horizontal direction. A plurality of first filling layers filling the plurality of first grooves are formed. Each of the plurality of first filling layers has a protruding portion extending to protrude from the substrate. A spacer is formed on a sidewall of the protruding portion of the plurality of first filling layers. The spacer exposes a portion of the substrate between adjacent first filling layers of the plurality of first filling layers. By etching the portion of the substrate exposed by the spacer, a plurality of second grooves are formed around the plurality of first grooves. A plurality of second filling layers are formed, the plurality of second filling layers filling the plurality of second grooves and having a top surface at the same level as a top surface of the substrate. The plurality of first filling layers and the spacer are all removed. A gate material layer is formed to conformally cover inner walls of the plurality of first grooves. By separating the gate material layer, a pair of gate structures are formed in each of the plurality of first grooves. A third filling layer is formed between the pair of gate structures in each of the plurality of first grooves. According to an embodiment of the inventive concept, a method of manufacturing a semiconductor device includes forming a plurality of first grooves in a substrate. The plurality of first grooves are spaced apart from each other in a first horizontal direction, and each of the plurality of first grooves extends in a second horizontal direction orthogonal to the first horizontal direction. A plurality of first fill layers filling the plurality of first grooves are formed. Each of the plurality of first fill layers has a protrusion extending to protrude from the substrate. Spacers are formed on sidewalls of the protrusions of the plurality of first fill layers. The spacers expose a portion of the substrate that is between adjacent first fill layers of the plurality of first fill layers. By etching the portion of the substrate exposed by the spacers, a plurality of second grooves are formed around the plurality of first grooves. A plurality of second fill layers are formed, the plurality of second fill layers filling the plurality of second grooves and having a top surface at the same level as a top surface of the substrate. All of the plurality of first fill layers and the spacers are removed. A sacrificial material layer conformally covering inner walls of the plurality of first grooves is formed. A portion of the sacrificial material layer is removed and separated from the plurality of first grooves to expose a portion of a bottom surface of the plurality of first grooves. A plurality of third fill layers are formed, the plurality of third fill layers filling the plurality of first grooves and directly contacting an exposed portion of the bottom surface of the plurality of first grooves and sidewalls of the sacrificial material layer. The sacrificial material layer is completely removed. A pair of gate structures are formed in an empty space defined by the plurality of third fill layers in each of the plurality of first grooves. According to an embodiment of the inventive concept, a method of manufacturing a semiconductor device includes forming a mask layer having a plurality of openings on a substrate. A plurality of first grooves are formed by etching the substrate using the mask layer as an etch mask. The plurality of first grooves are spaced apart from each other in a first horizontal direction, and each of the plurality of first grooves extends in a second horizontal direction orthogonal to the first horizontal direction. The mask layer is removed. A plurality of sacrificial layers filling the plurality of first grooves are formed. An upper portion of the substrate is removed by a first thickness such that portions of the plurality of sacrificial layers protrude from the substrate. Spacers are formed on sidewalls of the protruding portions of the plurality of sacrificial layers. The spacers expose a portion of the substrate that is between adjacent sacrificial layers of the plurality of sacrificial layers. By etching the portion of the substrate exposed by the spacers, a plurality of second grooves are formed around the plurality of first grooves. A plurality of element isolation layers are formed, the plurality of element isolation layers filling the plurality of second grooves and having a top surface at the same level as a top surface of the substrate. All of the plurality of sacrificial layers and the spacers are removed. A gate material layer conformally covering inner walls of the plurality of first grooves is formed. By separating the gate material layer, a pair of gate structures are formed in each of the plurality of first grooves. An epitaxial growth layer is formed between the pair of gate structures in each of the plurality of first grooves. FIG. 1 is a block diagram illustrating a method of manufacturing a semiconductor device according to an embodiment. Referring to FIG. 1, a method S10 of manufacturing a semiconductor device may include operations S110 to S190. In some embodiments where certain operations are implemented in a manner different from that of FIG. 1, specific operations may be performed in an order different from that described below. For example, two consecutively described operations may be performed substantially simultaneously, or may be performed in an order opposite to the order described below. However, embodiments of the inventive concept are not necessarily limited thereto. A method S10 of manufacturing a semiconductor device according to an embodiment of the inventive concept may include: a first operation S110 of forming a plurality of first grooves in a substrate, the plurality of first grooves being spaced apart from each other in a first horizontal direction and extending in a second horizontal direction orthogonal to the first horizontal direction; a second operation S120 of forming a plurality of first filling layers filling the first grooves and having protrusions extending from the substrate; a third operation S130 of forming spacers on sidewalls of the protrusions of the first filling layers, the spacers exposing portions of the substrate between the first filling layers; a fourth operation S140 of forming a plurality of second grooves around the first grooves by etching the portions of the substrate exposed by the spacers; a fifth operation S150 of forming a plurality of second filling layers having a top surface at the same level as the top surface of the substrate by filling the second grooves; a sixth operation S160 of removing all of the first filling layers and the spacers; a seventh operation S170 of forming a gate material layer extending while conformally covering inner walls of the first grooves; an eighth operation S180 of forming a pair of gate structures in each of the first grooves by separating the gate material layer; and a ninth operation S190 of forming a third filling layer between the pair of gate structures in each of the first grooves. Technical features of each of the first operation S110 to the ninth operation S190 will be described in detail later with reference to FIGS. 3A to 3U. FIG. 2 is a layout diagram showing main components of a cell region of a semiconductor device according to an embodiment. Referring to the embodiment of FIG. 2, a semiconductor device 10 may include a plurality of active regions ACT arranged to have a major axis in a first horizontal direction (X direction). A plurality of word lines WL may cross the active regions ACT and extend parallel to each other in a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction). A plurality of bit lines BL may extend parallel to each other in the second horizontal direction Y above (or below) the word lines WL. In a semiconductor device 10 according to an embodiment of the inventive concept, the major axis of the active region ACT may be orthogonal to the word line WL. For example, the major axis of the active region ACT may be parallel to the bit line BL. The bit line BL can be connected to the active region ACT via a direct contact DC. According to some embodiments, a plurality of buried contacts may be formed between two adjacent bit lines BL among the bit lines BL. Each of the buried contacts may extend to an upper portion of any one of the two adjacent bit lines BL. According to some embodiments, the buried contacts may be linearly arranged in a first horizontal direction (X direction) and a second horizontal direction (Y direction). A method for manufacturing main components of the cell region of the semiconductor device 10 will be described in detail below. FIGS. 3A to 3U are cross-sectional views of a method for manufacturing a semiconductor device according to a manufacturing sequence and an embodiment. Specifically, FIGS. 3A to 3U are cross-sectional views corresponding to the cutting line X-X' shown in FIG. 2 above. Referring to FIG. 3A, a photolithography process for forming a mask layer MP having a plurality of openings on a substrate 100 is performed. In an embodiment, the substrate 100 may include a wafer containing silicon (Si). Alternatively, the substrate 100 may include a wafer containing a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In an embodiment, the substrate 100 may have a silicon-on-insulator (SOI) structure. In addition, the substrate 100 may include a conductive region (e.g., an impurity-doped well or an impurity-doped structure). A mask layer MP having a plurality of openings may be formed on the top surface of the substrate 100. According to some embodiments, the mask layer MP having a plurality of openings may be formed by an ArF lithography process or an extreme ultraviolet (EUV) lithography process. However, embodiments of the inventive concept are not necessarily limited thereto. Referring to FIG. 3B, an etching process for forming a plurality of first trenches 110T in the substrate 100 is performed. The first trenches 110T may be formed by etching the substrate 100 using the mask layer MP having a plurality of openings as an etching mask. In an embodiment, the etching may be anisotropic etching, such as plasma etching. Referring to FIG. 3C, a process of removing the mask layer MP (refer to FIG. 3B) having a plurality of openings from the substrate 100 is performed. For example, in an embodiment, the mask layer MP (refer to FIG. 3B) having a plurality of openings may be completely removed by an ashing process and a stripping process. However, embodiments of the inventive concept are not necessarily limited thereto. Accordingly, the first grooves 110T may each have a first width W1 in the first horizontal direction (X direction) and may extend in the second horizontal direction (Y direction). In addition, adjacent first grooves 110T may be spaced apart from each other by a first separation distance D1. Referring to FIG. 3D, a sacrificial material layer 111M is conformally formed along the inner walls of the first grooves 110T. For example, in an embodiment, the sacrificial material layer 111M may be formed by, for example, a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The sacrificial material layer 111M may include silicon oxide, silicon nitride, or a combination thereof. However, embodiments of the inventive concept are not necessarily limited thereto. Referring to FIG. 3E, a first filling material layer 113M is formed to fill the first grooves 110T and protrude from the substrate 100. The first filling material layer 113M is formed to completely fill the first grooves 110T and cover the sacrificial material layer 111M. In an embodiment, the first filling material layer 113M may be formed by, for example, a CVD method or an ALD method. The first filling material layer 113M may include titanium nitride, tantalum nitride, or a combination thereof. The first filling material layer 113M may be a sacrificial film. In an embodiment, the sacrificial material layer 111M and the first filling material layer 113M may include different materials. Referring to FIG. 3F, the first filling material layer 113M (refer to FIG. 3E) is planarized to expose the top surface of the sacrificial material layer 111M, thereby forming a plurality of first filling layers 113. In an embodiment, the planarization process of the first filling material layer 113M (refer to FIG. 3E) may be, for example, a chemical mechanical polishing (CMP) process. However, embodiments of the inventive concept are not necessarily limited thereto. By the planarization process, a first filling layer 113 is formed to fill (e.g., completely fill) the first grooves 110T. The top surface of the first filling layer 113 may be located substantially at the same level as the top surface of the sacrificial material layer 111M (e.g., in the Z direction). Referring to FIG. 3G, an etching process is performed to remove a part of the upper portion of the substrate 100 and the sacrificial material layer 111M (refer to FIG. 3F). The etching process may selectively remove only the materials constituting the substrate 100 and the sacrificial material layer 111M (refer to FIG. 3F). For example, the portion of the first filling layer 113 may not be removed by the etching process. By the etching process, the sacrificial material layer 111M (refer to FIG. 3F) is formed as a plurality of sacrificial layers 111 located only on the inner walls and the bottom surface of the first grooves 110T. Each of the first filling layers 113 includes a protruding portion 113P that protrudes from the substrate 100 by a certain height H1. The height H1 of the protruding portion 113P can determine the height of the spacer 115 (refer to FIG. 3I) in the process of forming the spacer 115 (refer to FIG. 3I) to be described later. Referring to FIG. 3H, a spacer material layer 115M is formed to conformally cover the exposed surface of the substrate 100, the exposed surface of the sacrificial layer 111, and the protruding portion 113P of the first filling layer 113. In an embodiment, the spacer material layer 115M may include a material having a high etching selectivity with respect to the material constituting the substrate 100. The etching selectivity can be quantitatively represented by the ratio of the etching rate of one material to the etching rate of another material. In an embodiment, the spacer material layer 115M may include titanium nitride, tantalum nitride, or a combination thereof. For example, the spacer material layer 115M and the first filling layer 113 may include the same material. However, the embodiments of the inventive concept are not necessarily limited thereto. For example, in an embodiment, the spacer material layer 115M may include silicon nitride. In an embodiment, the ALD method may be used such that the spacer material layer 115M is formed to have a uniform thickness T1. The thickness T1 of the spacer material layer 115M can determine the width of the second trench 120T in the process of forming the second trench 120T to be described later. Referring to FIG. 3I, the spacer 115 is formed by partially removing the spacer material layer 115M (refer to FIG. 3H). For example, in an embodiment, a portion of the spacer material layer 115M (refer to FIG. 3H) is removed by performing an etch-back process to partially expose the top surface of the substrate 100 around the first filling layer 113. For example, the exposed top surface of the substrate 100 may be located between adjacent first filling layers 113. Therefore, the spacers 115 are formed on two sidewalls of the protruding portion 113P in each of the first filling layers 113. In an embodiment, the spacer 115 can be used as an etching mask for forming the second trench 120T to be described later. The size of the exposed surface of the substrate 100 exposed by the spacer 115 can correspond to the size of the second trench 120T to be described later. Referring to FIG. 3J, the exposed portion of the substrate 100 is etched by using the spacer 115 as an etching mask, thereby forming a plurality of second trenches 120T. For example, the sidewalls of adjacent spacers 115 that face each other and are opposite to the sidewalls in contact with the protruding portion 113P can be used as etching masks. In an embodiment, during the etching process, the height of the spacer 115 and the height of the protrusion 113P can be reduced by performing a partial etching. Therefore, considering the thickness removed during the etching process, the heights of the protrusion 113P and the spacer 115 determined during the previous process can be determined to be sufficient to remain. For example, the greater the aspect ratio of the second groove 120T, the greater the heights of the protrusion 113P and the spacer 115 can be. According to an embodiment of the inventive concept, since the second groove 120T is formed by using the spacer 115 formed on the sidewall of the first filling layer 113, the second groove 120T can be formed to be spaced apart from the first filling layer 113 by a constant distance. In addition, according to an embodiment of the inventive concept, since the process of forming the second groove 120T uses self-alignment rather than a photolithography process, the second groove 120T, which is a deep groove pattern with a fine size, can be formed in a uniform distribution without misalignment. Referring to FIG. 3K, a second filling material layer 102M is formed to fill the second groove 120T and protrude from the first filling layer 113. For example, in an embodiment, the second filling material layer 102M can protrude in the Z direction from the upper surface of the protrusion 113P, the upper surface of the spacer 115, and the upper surface of the second groove 120T. According to some embodiments, the second filling material layer 102M can include silicon oxide, silicon nitride, or a combination thereof. The second filling material layer 102M can be an insulating composite layer including a buffer oxide layer, a trench liner nitride layer, and a filling oxide layer. However, the embodiments of the inventive concept are not necessarily limited thereto. In other embodiments, the second filling material layer 102M can include at least one material selected from high temperature oxide (HTO), high density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), or undoped silicate glass (USG). In an embodiment, after the process of forming the second filling material layer 102M, an annealing process for densifying the film quality can be additionally performed. Referring to FIG. 3L, a plurality of second filling layers 102 are formed by planarizing the second filling material layer 102M (refer to FIG. 3K) to expose the top surface of the substrate 100. For example, the plurality of second filling layers 102 can be element isolation films including one or more of the above insulating materials. A planarization process may be performed on the second filler material layer 102M (refer to FIG. 3K). In an embodiment, the planarization process may be, for example, a CMP process. Through the planarization process, a second filler layer 102 filling the second trench 120T is formed. In addition, through the planarization process, the protrusion 113P and the spacer 115 are completely removed from the first filler layer 113. Accordingly, the top surface of the second filler layer 102 may be substantially at the same level as the top surface of the substrate 100. In an embodiment of the inventive concept, the second filler layer 102 may be used as an element isolation layer. For example, the second filler layer 102 may constitute a shallow trench isolation (STI). Refer to FIG. 3M. The sacrificial layer 111 and the first filler layer 113 are completely removed from the first trench 110T. Through the removal process, the first trench 110T surrounded by the second filler layer 102 may be redefined in the substrate 100. In a first horizontal direction (e.g., the X direction), a first width W1 of each of the first trenches 110T may be greater than a second width W2 of each of the second filler layers 102, and a first vertical level LV1 of the bottom surface of each of the first trenches 110T may be positioned higher from the bottom surface of the substrate 100 than a second vertical level LV2 of the bottom surface of each of the second filler layers 102. Here, the second width W2 of each of the second filler layers 102 and the second vertical level LV2 of the bottom surface of each of the second filler layers 102 may correspond to the width of each of the second trenches 120T (refer to FIG. 3K) and the vertical level of the bottom surface of each of the second trenches 120T (refer to FIG. 3K). Refer to FIG. 3N. A first insulating material layer 121M is formed to conformally extend along the top surface of the substrate 100 and the inner wall of the first trench 110T. In an embodiment, the first insulating material layer 121M may be formed by, for example, a CVD method or an ALD method. The first insulating material layer 121M may include silicon oxide, silicon nitride, or a combination thereof. However, the embodiments of the inventive concept are not necessarily limited thereto. Refer to FIG. 3O. A gate material layer 123M is formed to conformally extend along the first trench 110T on the first insulating material layer 121M. In an embodiment, the gate material layer 123M may be formed by, for example, a physical vapor deposition (PVD) method, a CVD method, or an ALD method. The gate material layer 123M may include a metal, a metal nitride, or doped polycrystalline silicon. However, the embodiments of the inventive concept are not necessarily limited thereto. The gate material layer 123M can be formed to have a certain thickness T2. The thickness T2 of the gate material layer 123M can determine the width W3 of the gate structure 123 (refer to FIG. 3P) in the first horizontal direction (X direction) during the process of forming a pair of gate structures 123 which will be described later. For example, in an embodiment, the width W3 of the gate structure 123 can be substantially equal to the thickness T2 of the gate material layer 123M. Referring to FIG. 3P, a plurality of first insulating layers 121 and a plurality of gate structures 123 are formed by removing portions of the first insulating material layer 121M (refer to FIG. 3O) and portions of the gate material layer 123M (refer to FIG. 3O). In the first trench 110T, the first insulating material layer 121M (refer to FIG. 3O) and the gate material layer 123M (refer to FIG. 3O) can be separated by an anisotropic etching process, thereby forming a pair of gate structures 123 in each of the first trenches 110T. For example, the gate material layer 123M (refer to FIG. 3O) can be divided into two gate structures 123 respectively disposed on the first sidewall and the second sidewall facing each other (e.g., in the X direction) of each of the first trenches 110T. Each of the gate structures 123 can have a width W3 in the first horizontal direction (X direction) and can extend in the second horizontal direction (Y direction). The first insulating layer 121 can be disposed between the inner wall of each of the first trenches 110T and the gate structure 123. In other words, the gate structure 123 and the substrate 100 may not be in direct contact with each other. Referring to FIG. 3Q, a second insulating material layer 125M is formed to conformally extend along the top surface and one side surface of the gate structure 123 and the bottom surface of the first trench 110T. In an embodiment, the second insulating material layer 125M can be formed by, for example, a CVD method or an ALD method. The second insulating material layer 125M can include silicon oxide, silicon nitride, or a combination thereof. For example, the first insulating material layer 121M and the second insulating material layer 125M can include substantially the same material. Referring to FIG. 3R, a plurality of second insulating layers 125 are formed by removing portions of the second insulating material layer 125M (refer to FIG. 3Q) to expose the top surface of the substrate 100 and the bottom surface of the first trench 110T. The second insulating material layer 125M (refer to FIG. 3Q) can be separated in each of the first trenches 110T, thereby forming a second insulating layer 125 on one sidewall of the gate structure 123 where the first insulating layer 121 is not formed. Referring to FIG. 3S, a third filling layer 103 is formed between the pair of gate structures 123 in each of the first trenches 110T (refer to FIG. 3R). In an embodiment, the third filling layer 103 may be formed by an epitaxial growth process. The third filling layer 103 may be an epitaxial growth layer that grows using the bottom surface of the first trench 110T (refer to FIG. 3R) below it as a seed. For example, the third filling layer 103 may be formed to include the same material as the substrate 100. In an embodiment, the third filling layer 103 may include Si or silicon germanium (SiGe). Referring to FIG. 3T, a recess 123R is formed by partially etching the gate structure 123. The recess 123R that is recessed into the first trench 110T (refer to FIG. 3R) may be formed on the gate structure 123. Accordingly, the top surface of each of the gate structures 123 may be at a level lower than the level of the top surface of the substrate 100. Referring to FIG. 3U, a plurality of top cap layers 131 are formed on the gate structure 123 to fill the recess 123R (refer to FIG. 3T). The top cap layer 131 formed on the gate structure 123 may include an insulating material. In an embodiment, the top cap layer 131 may include, for example, silicon oxide, silicon nitride, or a combination thereof. However, embodiments of the inventive concept are not necessarily limited thereto. According to some embodiments, each of the gate structures 123 may be a buried gate structure including a conductive material. For example, each of the gate structures 123 may correspond to a word line WL (refer to FIG. 2). However, embodiments of the inventive concept are not necessarily limited thereto. For example, in other embodiments, each of the gate structures 123 may be a vertical gate structure including a conductive material, and each of the gate structures 123 may correspond to a gate electrode 440 (refer to FIG. 8). By a process, a semiconductor device 10 according to an embodiment of the inventive concept may be manufactured. In the method of manufacturing a semiconductor device 10 according to an embodiment of the inventive concept, misalignment may be prevented because the trenches formed in subsequent processes are self-aligned with the previously formed trenches, and the reliability of the semiconductor device 10 may be improved because the trenches are uniformly distributed. FIG. 4 is a block diagram illustrating a method of manufacturing a semiconductor device according to an embodiment. Referring to FIG. 4, a method S20 of manufacturing a semiconductor device may include a first operation S210 to a sixth operation S260. In some embodiments, specific operations may be performed in an order different from that described below. For example, two consecutively described operations may be performed substantially simultaneously, or may be performed in an order opposite to the order described below. The method S20 of manufacturing a semiconductor device according to an embodiment of the inventive concept may include: a first operation S210 of forming a plurality of first grooves and a plurality of second grooves in a substrate; a second operation S220 of forming a sacrificial material layer that extends while conformally covering the inner walls of the first grooves; a third operation S230 of removing a portion of the sacrificial material layer and separating it from the first grooves; a fourth operation S240 of forming a plurality of third filling layers by filling the first grooves to contact the exposed bottom surfaces of the first grooves and the sidewalls of the sacrificial material layer; a fifth operation S250 of completely removing the sacrificial material layer; and a sixth operation S260 of forming a pair of gate structures in the empty spaces defined by the third filling layers in each of the first grooves. The first operation S210 may include operations substantially the same as the first operation S110 to the sixth operation S160 (refer to FIG. 1) of the above-described method S10 (refer to FIG. 1) of manufacturing a semiconductor device. Therefore, for the sake of economy of description, a detailed description thereof will be omitted. The technical features of each of the first operation S210 to the sixth operation S260 will be described in detail later with reference to FIGS. 5A to 5K. FIGS. 5A to 5K are cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment according to a manufacturing sequence. FIGS. 5A to 5K are cross-sectional views corresponding to the cutting line X-X' shown in FIG. 2 above. Referring to FIG. 5A, a first groove 110T and a second filling layer 102 are formed in a substrate 100. In the method of manufacturing a semiconductor device 20 (refer to FIG. 5K), the process of forming the first groove 110T and the second filling layer 102 in the substrate 100 is substantially the same as the process described above with reference to FIGS. 3A to 3M. Therefore, for the sake of economy of description, a detailed description thereof will be omitted. Referring to FIG. 5B, a first sacrificial material layer 211M is conformally formed along the inner walls of the first groove 110T and the top surface of the substrate 100. In an embodiment, the first sacrificial material layer 211M may be formed by, for example, a CVD method or an ALD method. The first sacrificial material layer 211M may include silicon oxide, silicon nitride, or a combination thereof. However, the embodiments of the present disclosure are not limited thereto. Referring to FIG. 5C, a second sacrificial material layer 213M that extends conformally along the first groove 110T is formed on the first sacrificial material layer 211M. In an embodiment, the second sacrificial material layer 213M may be formed by, for example, a CVD method or an ALD method. The second sacrificial material layer 213M may include titanium nitride, tantalum nitride, or a combination thereof. For example, the first sacrificial material layer 211M and the second sacrificial material layer 213M may include different materials. Referring to FIG. 5D, a plurality of first sacrificial layers 211 and a plurality of second sacrificial layers 213 are formed by removing portions of the first sacrificial material layer 211M (refer to FIG. 5C) and portions of the second sacrificial material layer 213M (refer to FIG. 5C) to expose the bottom surface of the first trench 110T. In an embodiment, by using an anisotropic etching process to separate the first sacrificial material layer 211M (refer to FIG. 5C) from the second sacrificial material layer 213M (refer to FIG. 5C) in the first trench 110T, an empty space defined by the sidewalls of the first sacrificial layer 211 and the sidewalls of the second sacrificial layer 213 can be formed in each of the first trenches 110T. However, the embodiments of the present disclosure are not limited thereto. Referring to FIG. 5E, a third filling material layer 203M is formed between a pair of second sacrificial layers 213 in each of the first trenches 110T (refer to FIG. 5D). In an embodiment, the third filling material layer 203M can be formed by, for example, a PVD method, a CVD method, or an ALD method. The third filling material layer 203M can include a metal, a metal nitride, or doped polysilicon. However, the embodiments of the present inventive concept are not necessarily limited thereto, and the third filling material layer 203M can include an insulating material such as silicon oxide or silicon nitride. Referring to FIG. 5F, all of the second sacrificial layers 213 are removed to expose the first sacrificial layers 211 and the third filling material layer 203M. The third filling material layer 203M can be disposed to protrude from the top surface of the substrate 100. In addition, the third filling material layer 203M can be disposed to protrude from the top surface of the first sacrificial layer 211. Referring to FIG. 5G, all of the first sacrificial layers 211 are removed to expose the inner wall of the first trench 110T. In an embodiment, during the removal process, the height of the third filling material layer 203M (refer to FIG. 5F) can also be reduced by performing a partial etching. Therefore, considering the thickness removed during the removal process, the height of the third filling material layer 203M (refer to FIG. 5F) determined during the previous process can be determined to be sufficient to be retained. The third filling material layer 203M (refer to FIG. 5F) is partially removed to form a third filling layer 203. The top surface of the third filling layer 203 can be at the same level as the top surface of the substrate 100. Therefore, an empty space defined by the third filling layer 203 can be formed in the first trench 110T. Referring to FIG. 5H, an insulating material layer 221M is formed that conformally extends along the inner wall of the first trench 110T and the outer wall of the third filling layer 203. In an embodiment, the insulating material layer 221M may be formed by, for example, a CVD method or an ALD method. The insulating material layer 221M may include silicon oxide, silicon nitride, or a combination thereof. However, embodiments of the present disclosure are not limited thereto. Referring to FIG. 5I, a gate material layer 223M is formed to fill the first trench 110T and protrude from the substrate 100. The gate material layer 223M is formed to completely fill the first trench 110T and cover the insulating material layer 221M. In an embodiment, the gate material layer 223M may be formed by, for example, a PVD method, a CVD method, or an ALD method. The gate material layer 223M may include a metal, a metal nitride, or doped polysilicon. However, embodiments of the present disclosure are not limited thereto. Referring to FIG. 5J, the gate material layer 223M is partially etched to form a plurality of gate structures 223. A recess 223R that is recessed into the first trench 110T (refer to FIG. 5H) may be formed on the gate structure 223. Accordingly, the top surface of each of the gate structures 223 may be at a level lower than the level of the top surface of the substrate 100. Referring to FIG. 5K, a plurality of top cap layers 231 are formed on the gate structure 223 to fill the recess 223R (refer to FIG. 5J). The top cap layer 231 formed on the gate structure 223 may include an insulating material. In an embodiment, the top cap layer 231 may include, for example, silicon oxide, silicon nitride, or a combination thereof. However, embodiments of the present disclosure are not limited thereto. By the process, a semiconductor device 20 according to an embodiment of the present inventive concept can be manufactured. In the method of manufacturing the semiconductor device 20 according to an embodiment of the present inventive concept, since the trenches formed in subsequent processes are self-aligned with the previously formed trenches, misalignment can be prevented, and since the trenches have a uniform distribution, the reliability of the semiconductor device 20 can be improved. FIG. 6 is a layout diagram showing main components of a cell region of a semiconductor device according to an embodiment, and FIG. 7 is a cross-sectional view of a cross-sectional configuration taken along line X-X' shown in FIG. 6. Most of the components constituting the semiconductor device 30 to be described below and the materials constituting the components are substantially the same as or similar to the components and materials described above with reference to FIGS. 2 and 3A to 3U. Therefore, for ease of explanation, the following description will focus on the differences from the above-described semiconductor device 10. Referring to FIGS. 6 and 7 together, the semiconductor device 30 may include a plurality of shield lines SL extending parallel to each other in a second horizontal direction (Y direction). The semiconductor device 30 may include an active region ACT, and the active region ACT is arranged to have a major axis in a first horizontal direction (X direction). The character line WL may cross the active region ACT and extend parallel to each other in a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction). The bit line BL may extend parallel to each other in the second horizontal direction Y above (or below) the character line WL. The bit line BL may be connected to the active region ACT via a direct contact DC. In the semiconductor element 30 of the embodiment of FIG. 6, a shielding line SL extending in the second horizontal direction (Y direction) may be formed between two active regions ACT adjacent to each other (e.g., in the X direction) in the active region ACT. For example, in the process of forming the second filling layer 102 (refer to FIG. 3L), a plurality of shielding structures 301 may be formed. In an embodiment, the shielding structure 301 may be buried in a portion of the second filling layer 102 (refer to FIG. 3L) and may extend parallel to each other in the second horizontal direction (Y direction). As shown in the embodiment of FIG. 7, the top surface of the shielding structure 301 in the semiconductor element 30 may be substantially at the same level as the top surface of the substrate 100 (e.g., in the Z direction). Each of the shielding structures 301 may include a conductive material surrounded by an insulating material. For example, in each of the shielding structures 301, an insulating pad may be provided at a portion in contact with the substrate 100, and a conductive material may be provided to fill the inside of the insulating pad. FIG. 8 is a layout diagram showing a semiconductor element according to an embodiment, and FIG. 9 is a cross-sectional view of a cross-sectional configuration along lines X-X' and Y-Y' shown in FIG. 8. Referring to FIGS. 8 and 9 together, the semiconductor element 40 may include a substrate 410, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating layer 450, and a capacitor structure 480. The semiconductor element 40 may be a memory element including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer 430 extends from the substrate 410 in a vertical direction (e.g., the Z direction). A lower insulating layer 412 may be provided on the substrate 410, and on the lower insulating layer 412, the first conductive lines 420 may be spaced apart from each other in a first horizontal direction (X direction) and may extend in a second horizontal direction (Y direction). A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill the space between the first conductive lines 420. The first insulating patterns 422 may extend in the second horizontal direction (Y direction), and the top surface of the first insulating patterns 422 may be at the same level as the top surface of the first conductive lines 420. The first conductive lines 420 may be used as bit lines of the semiconductor element 40. According to some embodiments, the first conductive line 420 may include doped polycrystalline silicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, in an embodiment, the first conductive line 420 may include doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuO x or a combination thereof. However, embodiments of the inventive concept are not necessarily limited thereto. The first conductive line 420 may include a single layer or multiple layers formed of the above materials. According to some embodiments, the first conductive line 420 may include a two-dimensional semiconductor material, where the two-dimensional semiconductor material may include, for example, graphene, carbon nanotubes, or a combination thereof. The channel layer 430 may be disposed above the first conductive line 420 to be spaced apart from each other in a matrix shape in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The channel layer 430 may have a first width in the first horizontal direction (X direction) and a first height in the vertical direction (Z direction). The first height may be greater than the first width. In an embodiment, a bottom portion of the channel layer 430 may serve as a first source / drain region, an upper portion of the channel layer 430 may serve as a second source / drain region, and a portion of the channel layer 430 located between the first source / drain region and the second source / drain region may serve as a channel region. According to some embodiments, the channel layer 430 may include an oxide semiconductor, for example, the oxide semiconductor may include In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Hf x In y ZnOAl x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga y O or a combination thereof. However, embodiments of the inventive concept are not necessarily limited thereto. The channel layer 430 may include a single layer or multiple layers formed of an oxide semiconductor. According to some embodiments, the channel layer 430 may have a bandgap energy greater than that of silicon. For example, the channel layer 430 may have a bandgap energy in the range of about 1.5 electron volts to about 5.6 electron volts. For example, when the channel layer 430 has a bandgap energy in the range of about 2.0 electron volts to about 4.0 electron volts, the channel layer 430 may exhibit optimal channel performance. For example, the channel layer 430 may be polycrystalline or amorphous. However, embodiments of the inventive concept are not necessarily limited thereto. According to some embodiments, the channel layer 430 may include a two-dimensional semiconductor material, where the two-dimensional semiconductor material may include, for example, graphene, carbon nanotubes, or a combination thereof. The gate electrodes 440 may extend in a first horizontal direction (X direction) on two sidewalls of the channel layer 430. Each of the gate electrodes 440 may include a first sub-gate electrode 440P1 and a second sub-gate electrode 440P2. The first sub-gate electrode 440P1 faces the first sidewall of the channel layer 430, and the second sub-gate electrode 440P2 faces the second sidewall of the channel layer 430 opposite to the first sidewall of the channel layer 430. Since one channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor device 40 may have a dual-gate transistor structure. However, embodiments of the inventive concept are not necessarily limited thereto, and a single gate transistor structure may be implemented by omitting the second sub-gate electrode 440P2 and forming only the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430. In the semiconductor device 40 of this embodiment, the gate electrodes 440 may be formed by using the above-described method S10 or S20 for manufacturing a semiconductor device. For example, the gate electrodes 440 may be formed in a uniformly distributed manner by a process of forming grooves and a process of filling the grooves. The gate electrodes 440 may include a metal, a metal nitride, a metal carbide, or a combination thereof. According to some embodiments, the gate electrodes 440 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. However, embodiments of the inventive concept are not necessarily limited thereto. The gate insulating layer 450 may surround the sidewalls of the channel layer 430 and may be disposed between the channel layer 430 and the gate electrodes 440. For example, all sidewalls of the channel layer 430 may be surrounded by the gate insulating layer 450, and a part of the sidewalls of the gate electrodes 440 may be in contact with the gate insulating layer 450. According to other embodiments, the gate insulating layer 450 may extend in a direction in which the gate electrodes 440 extend (e.g., the first horizontal direction), and among the sidewalls of the channel layer 430, only the two sidewalls of the channel layer 430 facing the gate electrodes 440 may be in contact with the gate insulating layer 450. According to some embodiments, the gate insulating layer 450 may include silicon oxide, silicon oxynitride, a high-k material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k material may include a metal oxide or a metal oxynitride. For example, the high-k material that may constitute the gate insulating layer 450 may include, but is not necessarily limited to, HfO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO 2 、Al 2 O 3 or a combination thereof. A plurality of second insulating patterns 432 may extend in a second horizontal direction (Y direction) on the first insulating pattern 422, and the channel layer 430 may be disposed between two adjacent second insulating patterns 432 among the second insulating patterns 432. In addition, the first filling layer 434 and the second filling layer 436 may be disposed between two adjacent second insulating patterns 432 in the space between two adjacent channel layers 430. The first filling layer 434 may be disposed at the bottom of the space between two adjacent channel layers 430 and may contact the first conductive line 420, and the second filling layer 436 may be formed on the first filling layer 434 to fill the remaining part of the space between the two adjacent channel layers 430. The top surface of the second filling layer 436 may be at the same level as the top surface of the channel layer 430, and the second filling layer 436 may cover the top surface of the gate electrode 440. Alternatively, the second insulating pattern 432 may be formed as a material layer continuous with the first insulating pattern 422, or the second filling layer 436 may be formed as a material layer continuous with the first filling layer 434. The capacitor contact 460 may be disposed on the channel layer 430. The capacitor contact 460 may be disposed to overlap the channel layer 430 in the vertical direction and may be disposed in a matrix shape spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). In an embodiment, the capacitor contact 460 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuO x or a combination thereof. However, embodiments of the inventive concept are not necessarily limited thereto. The upper insulating layer 462 may surround the sidewalls of the capacitor contact 460 on the second insulating pattern 432 and the second filling layer 436. An etch stop layer 470 may be disposed on the upper insulating layer 462, and a capacitor structure 480 may be disposed on the etch stop layer 470. The capacitor structure 480 may include a lower electrode 482, a capacitor dielectric layer 484, and an upper electrode 486. The lower electrode 482 can penetrate the etch stop layer 470 and can be electrically connected to the top surface of the capacitor contact 460. In an embodiment, the lower electrode 482 can be formed in a columnar shape extending in the vertical direction (Z direction). However, embodiments of the inventive concept are not necessarily limited thereto. According to some embodiments, the lower electrode 482 can be arranged to overlap the capacitor contact 460 in the vertical direction and can be arranged in a matrix shape spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). As an alternative, a bonding pad can be further provided between the capacitor contact 460 and the lower electrode 482, and thus the lower electrode 482 can be arranged in a hexagonal shape. Although embodiments of the inventive concept have been specifically shown and described with reference to non-limiting embodiments of the inventive concept, it should be understood that various changes in form and detail can be made thereto without departing from the spirit and scope of the inventive concept. 10, 20, 30, 40: Semiconductor components 100, 410: Substrate 102, 436: Second filling layer 102M: Second filling material layer 103, 203: Third filling layer 110T: First groove 111: Sacrificial layer 111M: Sacrificial material layer 113: First filling layer 113M: First filling material layer 113P: Protrusion 115: Spacer 115M: Spacer material layer 120T: Second groove 121: First insulating layer 121M: First insulating material layer 123, 223: Gate structure 123M, 223M: Gate material layer 123R, 223R: Depression 125: Second insulating layer 125M: Second insulating material layer 131, 231: Capping layer 203M: Third filling material layer 211: First sacrificial layer 211M: First sacrificial material layer 213: Second sacrificial layer 213M: Second sacrificial material layer 221M: Insulating material layer 301: Shielding structure 412: Lower insulating layer 420: First conductive line 422: First insulating pattern 430: Channel layer 432: Second insulating pattern 434: First filling layer 440: Gate electrode 440P1: First sub-gate electrode 440P2: Second sub-gate electrode 450: Gate insulating layer 460: Capacitor contact 462: Upper insulating layer 470: Etch stop layer 480: Capacitor structure 482: Lower electrode 484: Capacitor dielectric layer 486: Upper electrode ACT: Active region BL: Bit line D1: First separation distance DC: Direct contact H1: Height LV1: First vertical level LV2: Second vertical level MP: Mask layer S10, S20: Methods S110: First operation / operation S120: Second operation / operation S130: Third operation / operation S140: Fourth operation / operation S150: Fifth operation / operation S160: Sixth operation / operation S170: Seventh operation / operation S180: Eighth operation / operation S190: Ninth operation / operation S210: First operation S220: Second operation S230: Third operation S240: Fourth operation S250: Fifth operation S260: Sixth operation SL: Shielding line T1, T2: Thickness W1: First width W2: Second width W3: Width WL: Word line X, Z: Directions X-X': Cutting line / line Y: Second horizontal direction / direction Y-Y': Line Embodiments of the concept of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram showing a method of manufacturing a semiconductor element according to an embodiment of the concept of the present invention. FIG. 2 is a layout diagram showing the main components of a cell region of a semiconductor element according to an embodiment of the concept of the present invention. FIGS. 3A to 3U are cross-sectional views taken along line X-X' shown in FIG. 2, showing a method of manufacturing a semiconductor element according to an embodiment of the concept of the present invention. FIG. 4 is a block diagram showing a method of manufacturing a semiconductor element according to an embodiment of the concept of the present invention. FIGS. 5A to 5K are cross-sectional views taken along line X-X' shown in FIG. 2, showing a method of manufacturing a semiconductor element according to an embodiment of the concept of the present invention. FIG. 6 is a layout diagram showing the main components of a cell region of a semiconductor element according to an embodiment of the concept of the present invention. FIG. 7 is a cross-sectional view of a cross-sectional configuration taken along line X-X' shown in FIG. 6 according to an embodiment of the concept of the present invention. FIG. 8 is a layout diagram showing a semiconductor element according to an embodiment. FIG. 9 is a cross-sectional view of a configuration taken along lines X-X' and Y-Y' shown in FIG. 8 according to an embodiment of the concept of the present invention. 10: Semiconductor element 100: Substrate 102: Second filling layer 103: Third filling layer 121: First insulating layer 123: Gate structure 125: Second insulating layer 131: Top cover layer X, Z: Directions X-X': Cutting line / line Y: Second horizontal direction / direction

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A plurality of first trenches are formed in a substrate, the plurality of first trenches being spaced apart from each other in a first horizontal direction, and each of the plurality of first trenches extending in a second horizontal direction orthogonal to the first horizontal direction; a plurality of first filler layers are formed to fill the plurality of first trenches, each of the plurality of first filler layers having a protrusion extending to project from the substrate such that the top surface of the substrate is located between the top surface and the bottom surface of each of the plurality of first filler layers; Spacers are formed on the sidewalls of the protrusions of the plurality of first filler layers, the spacers exposing portions of the substrate between adjacent first filler layers, wherein the spacer material is different from the substrate material; a plurality of second trenches are formed between the plurality of first trenches by etching the portions of the substrate exposed by the spacers; a plurality of second filler layers are formed, the plurality of second filler layers filling the plurality of second trenches and having a top surface at the same level as the top surface of the substrate; all of the plurality of first filler layers and the spacers are removed; a gate material layer conformally covering the inner walls of the plurality of first trenches is formed; a pair of gate structures are formed in each of the plurality of first trenches by separating the gate material layer; and a third filler layer is formed between the pair of gate structures in each of the plurality of first trenches.

2. The method as described in claim 1, wherein forming the plurality of first fill layers comprises: The plurality of first trenches are filled with a first filling layer material; And remove the upper portion of the base by a first thickness to expose the sidewall of the protrusion.

3. The method as described in claim 1, wherein forming the spacer comprises: The spacer material conformally covers the substrate and the protrusion; And partially etch the spacer material to expose portions of the substrate located between adjacent first fill layers in the plurality of first fill layers.

4. The method as described in request item 1, wherein: Each of the plurality of first filling layers is a sacrificial film; each of the plurality of second filling layers is an element isolation film containing insulating material; and the third filling layer is an epitaxial growth layer.

5. The method as described in request item 1, wherein: Each of the plurality of first filler layers is a sacrificial film; and at least one of the plurality of second filler layers and the third filler layer comprises a conductive material.

6. The method of claim 5, wherein a portion of each of the plurality of second filling layers includes a shielding structure extending in the second horizontal direction and comprising the conductive material.

7. The method as described in request item 1, wherein: The width of each of the plurality of first grooves in the first horizontal direction is greater than the width of each of the plurality of second grooves in the first horizontal direction; and the vertical level of the bottom surface of each of the plurality of first grooves is positioned higher than the vertical level of the bottom surface of each of the plurality of second grooves.

8. The method of claim 1, wherein the width of each of the pair of gate structures in the first horizontal direction is substantially equal to the thickness of the gate material layer.

9. The method as described in request item 1, wherein: In the substrate, a plurality of active regions surrounded by the plurality of second filler layers have a long axis in the first horizontal direction; and the direction of the long axis of the active regions is orthogonal to the direction in which the pair of gate structures extend.

10. The method of claim 1, wherein each of the pair of gate structures is a word line constituting a vertical channel transistor.

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