Light-emitting device and manufacturing method thereof

Abstract

This application discloses a light-emitting element comprising: a substrate having a main surface and a plurality of protrusions, wherein, viewed from above by one of the light-emitting elements, a plurality of polygonal patterns composed of the plurality of protrusions are arranged on the main surface, wherein each of the polygonal patterns is composed of a plurality of adjacent protrusions, and one of the polygonal patterns includes a non-parallel first virtual edge and a second virtual edge; and a semiconductor stack located on the main surface, comprising a lower semiconductor stack and an upper semiconductor stack located on the lower semiconductor stack; wherein the lower semiconductor stack includes a first sidewall and an edge, the first sidewall having an obtuse inner angle with the main surface; the edge, viewed from above, includes a first convex-concave pattern, the first convex-concave pattern including an adjacent first sub-edge and a second sub-edge; the first sub-edge and the second sub-edge are substantially parallel to the first virtual edge and the second virtual edge, respectively.

Description

Light-emitting element and method for manufacturing the same This application relates to a light-emitting element and a method for manufacturing the same, and particularly to a light-emitting element capable of enhancing brightness and a method for manufacturing the same. Light-emitting diodes (LEDs) have characteristics such as low power consumption, low heat generation, long lifespan, small size, fast response speed, and good optoelectronic properties, such as having a stable emission wavelength. Therefore, they have been widely used in household devices, indicator lights, optoelectronic products, etc. Conventional light-emitting diodes include a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer formed on the substrate, as well as p and n electrodes formed on the p-type / n-type semiconductor layers respectively. When an electric current is passed through the light-emitting diode via the electrodes and at a specific value of forward bias voltage, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer combine within the active layer to emit light. However, the light emitted by the light-emitting diode may undergo total internal reflection within its semiconductor layer and its substrate, making it difficult for the light to be导出 from the light-emitting diode, resulting in deteriorated light extraction and brightness. This application discloses a light-emitting element, comprising: a substrate, which includes a main surface and a plurality of protruding portions, wherein, when viewed from above one of the light-emitting elements, a plurality of polygonal patterns composed of the plurality of protruding portions are arranged on the main surface, and each of the polygonal patterns is respectively composed of a plurality of adjacent ones of the protruding portions, and one of the polygonal patterns includes a non-parallel first virtual edge and a second virtual edge; and a semiconductor stack located on the main surface, including a lower semiconductor stack and an upper semiconductor stack located on the lower semiconductor stack; wherein, the lower semiconductor stack includes a first sidewall and an edge, and there is an obtuse inner included angle between the first sidewall and the main surface; the edge includes a first concavo-convex pattern when viewed from above, and the first concavo-convex pattern includes adjacent first sub-edges and second sub-edges; the first sub-edge and the second sub-edge are substantially parallel to the first virtual edge and the second virtual edge respectively. In the following, exemplary embodiments of the present application will be described in detail with reference to the drawings, so that those skilled in the art of the present application can fully understand the spirit of the present invention. The present application is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some identical symbols, which represent elements with the same or similar structures, functions, and principles, and those with general knowledge in the industry can infer them according to the teachings of this specification. For the sake of brevity of the specification, the elements with the same symbols will not be restated. It is expected that the elements and features in one embodiment can be advantageously incorporated into another embodiment without further elaboration. In addition, other layers / structures or steps can be incorporated in the following embodiments. For example, the description of "forming a second layer / structure on a first layer / structure" can include embodiments where the first layer / structure is in direct contact with the second layer / structure, or embodiments where the first layer / structure is in indirect contact with the second layer / structure, that is, there are other layers / structures between the first layer / structure and the second layer / structure. In addition, the spatial relative relationship between the first layer / structure and the second layer / structure can change according to the operation or use of the device. The first layer / structure itself is not limited to a single layer or a single structure. The first layer can include a plurality of sub-layers, and the first structure can include a plurality of sub-structures. In addition, for the spatial-related descriptive terms mentioned in the present application, such as: "under", "low", "below", "above", "on", "top", "bottom", and similar terms, for the convenience of description, their usages are all to describe the relative relationship between one element or feature and another element or feature in the drawing. In addition to the orientation shown in the drawing, these spatial-related terms are also used to describe the possible orientations of the light-emitting element during use and operation. As the orientation of the semiconductor element changes (rotating 90 degrees or other orientations), the spatial-related descriptions used to describe its orientation should also be interpreted in a similar manner. FIG. 1A shows a light-emitting element 1 according to a first embodiment of the present application; FIG. 1B is a cross-sectional view taken along line A-A' in FIG. 1A. The light-emitting element 1 includes a substrate 10, a semiconductor stack 12 disposed on a main surface 10a of the substrate 10, a transparent conductive layer 18 located on the semiconductor stack 12, a first electrode 20, and a second electrode 30. As shown in FIGS. 1A and 1B, the main surface 10a of the substrate includes an element region A1 covered by the semiconductor stack 12 and a runway region A2 not covered by the semiconductor stack 12 and surrounding the element region A1 in a top view. In one embodiment, the semiconductor stack 12 has, for example, a rectangular appearance and includes an upper semiconductor stack 12a and a lower semiconductor stack 12b, where the lower semiconductor stack 12b includes an upper surface 121a of the first semiconductor layer, a first sidewall S1, and first to fourth edges E1 to E4, where the first edge E1 and the third edge E3 are opposite to each other, and the second edge E2 and the fourth edge E4 are opposite to each other. The first sidewall S1 is joined to the upper surface 121a of the first semiconductor layer to form the first to fourth edges E1 to E4. The upper edges of each first sidewall S1 are the first to fourth edges E1 to E4, respectively. The upper semiconductor stack 12a includes a second sidewall S2. Both the first sidewall S1 and the second sidewall S2 are inclined with respect to the main surface 10a, and the inner included angle θ1 between the first sidewall S1 and the main surface 10a of the substrate 10 is an obtuse angle. In one embodiment, θ1 is between 100 and 160 degrees. Viewed from above, as shown in FIG. 1A, the first to fourth edges E1 to E4 include a concavo-convex pattern. For example, the first edge E1 and the third edge E3 each include a first concavo-convex pattern composed of a plurality of first protrusions 40a and first recesses 40b. The second edge E2 and the fourth edge E4 each include a second concavo-convex pattern composed of a plurality of second protrusions 42a and second recesses 42b. The first concavo-convex pattern and the second concavo-convex pattern are different. The substrate 10 can be a growth substrate for epitaxial growth, and its materials include gallium arsenide (GaAs) and gallium phosphide (GaP) for growing aluminum gallium indium phosphide (AlGaInP), or sapphire (Al2O3), gallium nitride (GaN), silicon carbide (SiC), and aluminum nitride (AlN) for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). In an embodiment, referring to FIG. 1B, the substrate 10 can be a patterned substrate, that is, the substrate 10 includes a main body and a plurality of protrusions P formed on the main body, and a plurality of protrusions P are arranged at intervals on the main surface 10a of the substrate 10. In an embodiment, the light emitted from the semiconductor stack 12 can be refracted, reflected, or scattered by the protrusions P, thereby improving the light extraction efficiency of the light-emitting element. In addition, the protrusions P can slow down or suppress the dislocation caused by lattice mismatch between the substrate 10 and the semiconductor stack 12, thereby improving the epitaxial quality of the semiconductor stack 12. The three-dimensional shape of the protrusions P can be a cone (such as a cone, a polyhedral cone, or a truncated cone), a cylinder, or a hemisphere, etc. In this embodiment, the protrusion P is a cone. In an embodiment, the protrusion P and the main body of the substrate 10 are made of the same material. As shown in FIG. 1B, the protrusion P and the substrate 10 are integrally formed. In another embodiment, the protrusion P and the main body of the substrate 10 are made of different materials, and the protrusion P includes a transparent insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In an embodiment of the present application, the semiconductor stack 12 can be formed on the substrate 10 by means of metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation. The semiconductor stack 12 includes a first semiconductor layer 121, an active region 123, and a second semiconductor layer 122. In one embodiment, the semiconductor stack 12 further includes a buffer structure (not shown in the figure) located between the first semiconductor layer 121 and the substrate 10. The buffer structure can reduce the above-mentioned lattice mismatch and suppress dislocations, thereby improving the epitaxial quality. The material of the buffer structure includes GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes multiple sub-layers (not shown in the figure), and the sub-layers include the same material or different materials. In one embodiment, the buffer structure includes two sub-layers, wherein the formation method of the first sub-layer is different from that of the second sub-layer. For example, the formation method of the first sub-layer is sputtering; the formation method of the second sub-layer is MOCVD. In one embodiment, the buffer structure further includes a third sub-layer, wherein the formation method of the third sub-layer is MOCVD, and the growth temperature of the second sub-layer is different from that of the third sub-layer. In one embodiment, the first, second, and third sub-layers include the same material, such as AlN. In one embodiment, the first semiconductor layer 121 and the second semiconductor layer 122 are cladding layers or confinement layers. In one embodiment, the first semiconductor layer 121 and the second semiconductor layer 122 have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 121 includes an n-type semiconductor, and the second semiconductor layer 122 includes a p-type semiconductor. The active region 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. Electrons and holes combine in the active region 123 under the drive of current, converting electrical energy into light energy to emit light. The wavelength of the light emitted by the light-emitting element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical compositions of one or more layers in the semiconductor stack 12. The material of the semiconductor stack 12 includes III-V group semiconductor compound materials, such as Al x In y Ga (1-x-y) N (AlInGaN series) or Al x In y Ga (1-x-y)P (AlInGaP series), where 0 ≤ x, y ≤ 1; x + y ≤ 1. According to the material of the active region, when the material of the semiconductor stack 12 is of the AlInGaP series, red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack 12 is of the AlInGaN series, for example, when the active region 123 contains InGaN material, blue light or deep blue light with a peak wavelength between 400 nm and 490 nm, or green light with a peak wavelength between 490 nm and 550 nm can be emitted. When the active region 123 contains AlInGaN or AlGaN material, UV light with a peak wavelength between 400 nm and 250 nm can be emitted. The active region 123 can include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active region 123 can be an i-type, p-type, or n-type semiconductor. The first semiconductor layer 121 includes that the upper surface 121a of the first semiconductor layer is not covered by the active region 123 and the second semiconductor layer 122. In the description of this case, the semiconductor stack 12 above the extension line L (and the extended surface) of the upper surface 121a of the first semiconductor layer is called the upper semiconductor stack 12a, and the semiconductor stack 12 below the extension line L is called the lower semiconductor stack 12b. The upper surface 121a of the first semiconductor layer is also the upper surface of the lower semiconductor stack 12b. The upper semiconductor stack 12a includes the second semiconductor layer 122 and the active region 123. In an embodiment, the upper semiconductor stack 12a further includes a part of the first semiconductor layer 121. The lower semiconductor stack 12b includes all or another part of the first semiconductor layer 121 and a buffer structure. The first electrode 20 is located on the upper surface 121a of the first semiconductor layer and is electrically connected to the first semiconductor layer 121. The second electrode 30 is located on the second semiconductor layer 122 and is electrically connected to the second semiconductor layer 121. In one embodiment, the first electrode 20 includes a first pad electrode 201 and a first extension electrode 202 extending from the first pad electrode 201. The second electrode 30 includes a second pad electrode 301 and a second extension electrode 302 extending from the second pad electrode 301. The first pad electrode 201 and the second pad electrode 301 are used for wire bonding or soldering to electrically connect the light-emitting element 1 to an external power source or an external electronic component. In other embodiments, the first electrode 20 and / or the second electrode 30 may only include a pad electrode without an extension electrode. The size and shape of the pad electrode can be adjusted according to the form of electrical connection between the light-emitting element 1 and an external power source or an external electronic component. For example, wire bonding with the electrode surface facing up and connected by a metal wire, or flip chip bonding with the electrode surface facing down and connected by a solder bump. The materials of the first electrode 20 and the second electrode 30 include metals, such as metals like chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), rhodium (Rh), tungsten (W), indium (In), or platinum (Pt), or alloys or laminates of the above materials. In one embodiment, the metal laminate of the first electrode 20 and / or the second electrode 30 includes a current conduction layer and a reflective layer (not shown) from bottom to top, where the conductivity of the current conduction layer is greater than that of the reflective layer, and the reflectivity of the reflective layer for the light emitted by the semiconductor laminate 12 is greater than that of the current conduction layer. When the light-emitting element 1 is packaged in a package, the light emitted by the light-emitting element 1 in the package can be reflected by the reflective layer located on the uppermost layer of the first electrode 20 and / or the second electrode 30, avoiding the absorption of the light by the electrode surface when the light reflects back and forth in the package, so as to increase the brightness of the package. In another embodiment, the electrode includes a pad electrode and an extension electrode, and the reflective layer can be located on the side surface and the upper surface of the extension electrode, and the reflective layer can be located on the side surface of the pad electrode but not on the upper surface. In this way, when wire bonding, it is beneficial to the adhesion of the metal wire on the upper surface of the pad electrode. The transparent conductive layer 18 is located below the second electrode 30, covering the second semiconductor layer 122 and being electrically connected to the second semiconductor layer 122 for laterally dispersing current. The transparent conductive layer 18 can be a metal or a transparent conductive material. The metal can be selected from thin metal layers with light transmissivity, and the transparent conductive material is transparent to the light emitted by the active region 123, including materials such as indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), or indium zinc oxide (IZO). In one embodiment, the transparent conductive layer 18 has an opening 180 corresponding to the position of the second pad electrode 301, enabling the second pad electrode 301 to contact the second semiconductor layer 122 through the opening 180. In one embodiment, the light-emitting element 1 may further include a current blocking layer (not shown in the figure) located between the transparent conductive layer 18 and the second semiconductor layer 122, and / or between the first electrode 20 and the first semiconductor layer 121. FIG. 2A shows a partial enlarged view of the region R1 in FIG. 1A, and FIG. 2B shows a partial enlarged view of the region R2 in FIG. 1A. A plurality of protrusions P are arranged on the main surface 10a of the substrate 10 in a specific array manner and form a plurality of repetitively arranged polygonal patterns H. Among them, each polygonal pattern H is respectively composed of a plurality of adjacent ones among the plurality of protrusions P. For example, in this embodiment, the polygonal pattern H is a regular hexagon composed of six adjacent protrusions P surrounding another protrusion P. The polygonal patterns H respectively include a first virtual edge e1, a second virtual edge e2, and a third virtual edge e3 that are not parallel to each other. The opposite edge of the first virtual edge e1 in the polygonal pattern H, which is parallel to the first virtual edge e1, is also referred to as the first virtual edge e1 in the specification of this application. By analogy, the second virtual edge e2 and the third virtual edge e3 are the same. In one embodiment, the substrate 10 includes a material with a single-crystal hexagonal lattice structure, such as sapphire (Al 2 O 3)。The XY plane in FIGS. 2A and 2B is substantially parallel to the c-plane of the single-crystalline hexagonal lattice structure, and the XZ plane is substantially parallel to the a-plane. The first edge E1 includes a first sub-edge E11, a second sub-edge E12, and a third sub-edge E13 in three different directions. Referring to FIGS. 1A and 2A, the first convex portion 40a in the first concavo-convex pattern is composed of the first sub-edge E11 and the second sub-edge E12, and the first concave portion 40b is composed of the third sub-edge E13 and the first sub-edge E11 and the second sub-edge E12 on both sides thereof. The first sub-edge E11, the second sub-edge E12, and the third sub-edge E13 are substantially parallel to the first virtual edge e1, the second virtual edge e2, and the third virtual edge e3 of the polygonal pattern H, respectively. The pitch D1 between two adjacent first convex portions 40a is between 10 - 35 μm. Referring to FIGS. 1A and 2B, the second edge E2 includes a fourth sub-edge E21 and a fifth sub-edge E22. The second convex portion 42a in the second concavo-convex pattern is composed of the fourth sub-edge E21 and the fifth sub-edge E22, and the second concave portion 42b is composed of the fourth sub-edge E21 and another fifth sub-edge E22. The fourth sub-edge E21 and the fifth sub-edge E22 are substantially parallel to the first virtual edge e1 and the second virtual edge e2 of the polygonal pattern H, respectively. The pitch D2 between adjacent second convex portions 42a is between 10 - 35 μm. The first sidewall S1 can be inclined with respect to the substrate 10. For example, an obtuse angle is formed between the first sidewall S1 and the inner included angle θ1 of the main surface 10a of the substrate 10. By having sidewalls with different inclination angles in the semiconductor stack 12, the chance of internal total reflection of light in the semiconductor stack 12 can be reduced. In addition, the first sidewall S1 is composed of sub-sidewalls arranged in a staggered manner in multiple different directions, corresponding to forming the edges of the concavo-convex pattern of the lower semiconductor stack 12b. The first sidewall S1 can increase the light-emitting area of the sidewall of the semiconductor stack and increase the brightness of the light-emitting element 1. Figures 3A to 3C show a method for manufacturing the light-emitting element 1 according to an embodiment of the present application. Figure 3A shows a partial top view of the wafer 100 in the manufacturing step. The wafer 100 includes a substrate 10 and a semiconductor stack 12 formed thereon. Figure 3B shows a cross-sectional view taken along the line B-B' in Figure 3A. Referring to Figures 3A and 3B, after the semiconductor stack 12 is formed on the substrate 10, a part of the second semiconductor layer 122 and the active region 123 are removed from the upper surface of the semiconductor stack 12 to expose the upper surface 121a of the first semiconductor layer, and a plurality of upper semiconductor stacks 12a are formed. The removal method includes, but is not limited to, etching. Then, a protective layer (not shown) is formed on the semiconductor stack 12, and a plurality of holes 60x and 60y are formed along the X and Y directions respectively on the upper surface 121a of the first semiconductor layer. The method for forming the plurality of holes includes laser and etching. In one embodiment, for example, dry etching can be used to form the holes. In this embodiment, the holes 60x and 60y are formed by laser irradiation from the upper surface of the semiconductor stack 12. The holes 60x and 60y pass through the protective layer (not shown) and extend downward into the lower semiconductor stack 12b. By controlling the laser parameters in the X direction and the Y direction, d1 and d2 can be the same or different. In one embodiment, the depth of the holes 60x and 60y does not exceed the thickness of the lower semiconductor stack 12b, so that the bottoms of the holes 60x and 60y do not touch the substrate 10, which can avoid the main surface 10a of the substrate from being deteriorated by laser energy to generate a light-absorbing region. Then referring to Figure 3C, the lower semiconductor stack 12b is etched. The etching step can adopt wet etching. The etching solution can penetrate from the holes 60x and 60y and etch the exposed lower semiconductor stack 12b to remove a part of the lower semiconductor stack 12b, forming the first sidewall S1 as shown in Figure 3C, and forming the concavo-convex pattern as shown in Figures 1A, 2A, and 2B at the edge of the lower semiconductor stack 12b. In one embodiment, the etching rate and the morphology of the concavo-convex pattern can be adjusted by adjusting the hole size and the distance between adjacent holes. The distance between adjacent holes 60x in the X direction is d1, and the distance between adjacent holes 60y in the Y direction is d2. In one embodiment, d1 and d2 are greater than 10 μm. In another embodiment, d1 and d2 are between 10 - 35 μm. When d1 and d2 are less than 10 μm, it is not easy to form a significant concavo-convex pattern. After the first sidewall S1 is formed, the main surface 10a of the substrate exposed between the adjacent semiconductor stacks 12 forms a walkway area A2. Then, a transparent conductive layer 18, a first electrode 20, and a second electrode 30 are formed, and the wafer 100 is cut and separated along the walkway area A2 to form independent light-emitting elements 1. In one embodiment, the etching solution includes sulfuric acid, phosphoric acid, hydrochloric acid, hydrofluoric acid, or a combination thereof. The angle θ1 between the first sidewall S1 and the main surface 10a can be controlled by adjusting the composition of the etching solution, the etching time, and the temperature.In another embodiment, an internal included angle θ1 less than or equal to 90 degrees can be formed by reducing the temperature of the etching solution or shortening the etching time. FIGS. 4A and 4B show partial enlarged views of the region R3 in FIG. 3A during the etching process. FIG. 4A shows the etching solution entering the lower semiconductor stack 12b from the hole 60x, gradually etching and removing the lower semiconductor stack 12b from the hole to the periphery, and the arrow in FIG. 4A indicates the etching direction. The region where the lower semiconductor stack 12b is etched away is referred to as the etching region 60' in the present specification. During the etching process, the plurality of spaced etching regions 60' formed by the plurality of spaced holes 60x gradually expand and overlap. Referring to FIG. 4B, when adjacent etching regions overlap and the etching is still in progress, the edges of the lower semiconductor stack 12b retract into the semiconductor stack 12. In one embodiment, the etching rate may vary according to the type of etching solution, the materials constituting the layers in the lower semiconductor stack 12b, the epitaxial quality, or the lattice plane of the epitaxial layer material. By selecting a specific etching solution, such as phosphoric acid and sulfuric acid, and the material of the lower semiconductor stack 12b, such as aluminum nitride and gallium nitride, and adjusting through the epitaxial bottom layer near the substrate 10, such as the epitaxial layer material and epitaxial quality, and adjusting the etching conditions, such as time and etching temperature, when the uneven patterns 40a and 40b are generated on the lower semiconductor stack 12b, the aforementioned internal included angle θ1 and the columnar structure 70 (for the columnar structure 70, please refer to FIGS. 5B and subsequent descriptions) are also formed. In one embodiment, when the etching process is approaching termination, an etching stop surface is substantially formed according to a specific lattice plane of the lower semiconductor stack 12b to generate the uneven patterns 40a and 40b. In another embodiment, with the protrusion P provided on the substrate 10, the material of the protrusion P is different from that of the semiconductor stack 12 and is less susceptible to erosion by the above-mentioned etching solution, and the protrusion P has the effect of blocking the etching solution from invading into the lower semiconductor stack 12b. When the etching process is approaching termination, an etching stop line can be substantially formed according to the arrangement direction of the protrusion P and the polygonal pattern H to avoid over-etching the semiconductor body 12b, and to form the uneven patterns on the edges of the lower semiconductor stack 12b and the columnar structure 70 on each sub-edge. In the X direction, an etching stop line is substantially formed according to the arrangement direction of the protrusion P and the polygonal pattern H to form the first uneven patterns 40a and 40b on the edges E1 and E3 of the lower semiconductor stack 12b. The first sub-edge E11, the second sub-edge E12, and the third sub-edge E13 are substantially parallel to the first virtual edge e1, the second virtual edge e2, and the third virtual edge e3 of the polygonal pattern H, respectively. Similarly, in the Y direction, an etching stop line is substantially formed according to the arrangement direction of the protrusion P and the polygonal pattern H to form the second uneven patterns on the edges E2 and E4 of the lower semiconductor stack 12b. The fourth sub-edge E21 and the fifth sub-edge E22 are substantially parallel to the first virtual edge e1 and the second virtual edge e2 of the polygonal pattern H, respectively. In one embodiment, the light-emitting element 1 formed by the aforementioned manufacturing method, wherein the protruding portion P located in the aisle area A2 may have a smaller size and / or a different shape compared to the protruding portion P located in the element area A1. FIG. 5A shows a partial top-view appearance photo of the light-emitting element 1, and FIG. 5B shows an appearance photo of the first sidewall S1 observed in the direction of the arrow in FIG. 5A. As shown in FIG. 5B, the lower semiconductor stack 12b includes a plurality of connected columnar structures 70, wherein the surface of the columnar structure 70 constitutes the first sidewall S1. In one embodiment, the upper edge of the surface of the columnar structure 70 is connected to the upper surface 121a of the first semiconductor layer. Therefore, the upper edges of the surfaces of the plurality of connected columnar structures 70 are the first edge E1. More specifically, the plurality of columnar structures 70 are located in the first convex portion 40a and the first concave portion 40b, and are respectively connected to the upper surface 121a of the first semiconductor layer at the first sub-edge E11, the second sub-edge E12, and the third sub-edge E13. Although the appearance photo of the third edge E3 is not shown, those skilled in the art can understand that the first sidewall S1 located at the third edge E3 may also have the above structure through the disclosure of this specification. Similarly, when observing the first sidewall S1 of the light-emitting element 1 in another vertical direction, a plurality of connected columnar structures 70 can also be observed, and their upper edges are connected to the second edge E2 and the fourth edge E4. The plurality of columnar structures 70 are located in the second convex portion 42a and the second concave portion 42b, and are respectively connected to the upper surface 121a of the first semiconductor layer at the fourth sub-edge E21 and the fifth sub-edge E22. It should be noted that in the top-view schematic diagrams such as FIGS. 1A, 2A, 2B, and 4B, each sub-edge is represented by a straight line for overall viewing. However, microscopically, each sub-edge corresponding to the plurality of columnar structures 70 may show some micro-bends. FIG. 6 shows a top view of the light-emitting element 2 according to the second embodiment of the present application. The light-emitting element 2 has a similar structure to the light-emitting element 1, and the differences are described in detail below. The first to fourth edges (E1-E4) of the light-emitting element 2 respectively include a first portion L1, a second portion L2, and a third portion L3 located between the first portion L1 and the second portion L2. The first portion L1 or the second portion L2 of any edge and the first portion L1 or the second portion L2 of another adjacent edge form a corner of the lower semiconductor stack 12b. Among them, the third portion L3 includes the aforementioned concavo-convex pattern, and the first portion L1 and the second portion L2 do not include the aforementioned concavo-convex pattern. Specifically, the third portions L3 of the first edge E1 and the third edge E3 include first concavo-convex patterns 40a and 40b, and the first portion L1 and the second portion L2 do not include the first concavo-convex pattern. The third portions L3 of the second edge E2 and the fourth edge E4 include second concavo-convex patterns 42a and 42b, and the first portion L1 and the second portion L2 do not include the second concavo-convex pattern. In an embodiment, similar to the aforementioned first light-emitting element 1, the lower semiconductor stack 12b of the light-emitting element 2 includes a plurality of columnar structures 70 connected to each other, wherein the surface of the columnar structure 70 constitutes a first sidewall S1, and the columnar structure 70 is located in the first portion L1, the second portion L2, and the third portion L3. According to a manufacturing method of the light-emitting element 2 in an embodiment of the present application, FIG. 7 shows a partial top view of the wafer 100 in the manufacturing steps. The manufacturing method of the light-emitting element 2 is similar to that of the light-emitting element 1, and the differences are described in detail below. In the step of irradiating the upper surface of the semiconductor stack 12 with a laser along the X and Y directions respectively to form holes 60x and 60y, by adjusting the parameters of the laser, such as speed, frequency, etc., the distance between adjacent holes in different sections of the laser path in the same direction is different. As shown in FIG. 7, the laser path includes a first section L1', a third section L3', and a second section L3'. The hole pitch in the first section L1' and the second section L2' of the laser path is smaller than the hole pitch in the third section L3'. In an embodiment, the hole pitch in the first section L1' and the second section L2' is less than 10 μm, and the hole pitch in the third section L3' is greater than or equal to 10 μm. In another embodiment, two adjacent holes in the first section L1' and the second section L2' may overlap. Between four adjacent upper semiconductor stacks 12a, that is, in the vicinity of the intersection of holes 60x and 60y, make the pitch of a plurality of holes 60x and the pitch of a plurality of holes 60y both less than 10 μm. Or, two adjacent holes 60x can overlap, and two adjacent holes 60y can overlap. Next, etch the lower semiconductor stack 12b with an etching solution to form a first sidewall S1, and form the uneven pattern as described above at the edge of the lower semiconductor stack 12b corresponding to the third section L3’, but do not form the uneven pattern at the edges of the lower semiconductor stack 12b corresponding to the first section L1’ and the second section L2’. Next, in the same manner as the manufacturing method of the light-emitting element 1, form a transparent conductive layer 18, a first electrode 20, and a second electrode 30, and cut and separate the wafer 100 along the aisle area A2 to form independent light-emitting elements 2. The first section L1’ to the third section L3’ respectively correspond to form the first part L1 to the third part L3 of the edge of the light-emitting element 2. In some cases, when the light emitted by the semiconductor stack 12 irradiates the internal corners and the sidewalls in their vicinity, the incident light at certain angles may not be effectively extracted from the sidewalls corresponding to the first sub-edge E11 to the fifth sub-edge E22. Therefore, in this embodiment, the portions of the edge of the lower semiconductor stack 12b located at or near the corners (the first part L1 and the second part L2) and their corresponding sidewalls are set not to have the aforementioned uneven pattern, so that the light extraction of each part of the semiconductor stack 12 is optimized. In one embodiment, the length of the third part L3 is greater than the total length of the first part L1 and the second part L2. FIG. 8A shows a partial cross-sectional view of the light-emitting element 3 of the third embodiment of the present application near the aisle area A2. The light-emitting element 3 has a similar structure to the light-emitting element 1 or the light-emitting element 2, except that the protruding portion P of the light-emitting element 3 has a different material from the main body of the substrate 10, and the protruding portion P includes a transparent insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In the process of removing part of the lower semiconductor stack 12b and forming the first sidewall S1, the protruding portion P on the aisle area A2 can be removed simultaneously. Therefore, after the light-emitting element 3 is manufactured, there is no protruding portion P on the aisle area A2, or the size of the protruding portion P on the aisle area A2 is smaller than the size of the protruding portion P on the element area A1 (not shown in the figure). FIG. 8B shows a partial cross-sectional view of the light-emitting element 4 of the fourth embodiment of the present application located near the aisle area A2. The light-emitting element 4 has a similar structure to the light-emitting element 1 or the light-emitting element 2, except that the protrusion P on the substrate 10 of the light-emitting element 4 includes a lower part P1 and an upper part P2, where the lower part P1 has the same material as the main body of the substrate 10, and the upper part P2 and the lower part P1 include different materials. For example, the upper part P2 includes a transparent insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. During the process of removing part of the lower semiconductor stack 12b and forming the first sidewall S1, the upper part P2 in the aisle area A2 can be removed simultaneously. Therefore, after the light-emitting element 4 is fabricated, there is no upper part P2 on the aisle area A2, and only the lower part P1 remains. Or in the aisle area A2, the size of the upper part P2 is smaller than the size of the upper part P2 in the element area A1 (not shown in the figure). FIG. 9 shows a cross-sectional view of a light-emitting element package 200 according to an embodiment of the present application. As shown in FIG. 9, the light-emitting element package 200 includes a main body 16 having a cavity 160, a first lead terminal 50a and a second lead terminal 50b disposed in the cavity 160, light-emitting elements 1 to 4 according to any embodiment of the present application, a wire 14, a metal solder ball 80, and a packaging material 23. The cavity 160 may include an opening structure recessed from the top surface of the main body 16. In one embodiment, the sidewall of the main body 16 in the cavity 160 may include a reflective structure. The first lead terminal 50a is disposed in a first area of the bottom area of the cavity 160, and the second lead terminal 50b is disposed in a second area of the bottom area of the cavity 160. The first lead terminal 50a and the second lead terminal 50b are spaced apart from each other in the cavity 160. The light-emitting elements 1 to 4 are disposed on at least one of the first and second lead terminals 50a and 50b. For example, the light-emitting elements 1 to 4 may be disposed on the first lead terminal 50a, and the first electrodes 20 and the second electrodes 30 of the light-emitting elements 1 to 4 are electrically connected to the first and second lead terminals 50a and 50b respectively by the wire 14 and the metal solder ball 80. The packaging material 23 is disposed in the cavity 160 of the main body 16 to cover and protect the light-emitting elements. The packaging material 23 includes, for example, silicone or epoxy resin, and its structure may be single-layer or multi-layer. In one embodiment, the packaging material 23 may further include a wavelength conversion material for changing the wavelength of the light generated by the light-emitting elements, such as a phosphor, and / or a scattering material. However, the above embodiments are only illustrative of the principles and effects of the present application, and are not used to limit the present application. Any person with ordinary knowledge in the technical field to which the present application belongs can modify and change the above embodiments without departing from the technical principles and spirit of the present application. All equivalent changes and modifications made according to the shape, structure, features, and spirit described in the patent scope of the present application should be included in the patent scope of the present application. 1, 2: Light-emitting element; 10: Substrate; 10a: Main surface; 10b: Lower surface; 12: Semiconductor stack; 12a: Upper semiconductor layer; 12b: Lower semiconductor layer; 121: First semiconductor layer; 121a: Upper surface of the first semiconductor layer; 122: Second semiconductor layer; 123: Active region; 14: Conductor wire; 50a, 50b: Conductor wire terminals; 16: Body; 160: Cavity; 18: Transparent conductive layer; 180: Opening; 20: First electrode; 201: First pad electrode; 202: First extension electrode; 30: Second electrode; 301: Second pad electrode; 302: Second extension electrode; 23: Encapsulation material; 40a: First protrusion; 40b: First recess; 42a: Second protrusion; 42b: Second recess; 60x, 60y: Holes; 60’: Etching region; 70: Columnar structure; 80: Metal solder ball; 100: Wafer; 200: Light-emitting element package; A1: Element region; A2: Aisle region; d1, d2, D1, D2: Pitch; E1, E2, E3, E4: First edge - Fourth edge; E11, E12, E13: First sub-edge - Third sub-edge; E21, E22: Fourth sub-edge, Fifth sub-edge; e1, e2, e3: First virtual edge - Third virtual edge; H: Polygonal pattern; L: Extension line (extended plane); L1, L2, L3: First part - Third part; L1’, L2’, L3’: First section - Third section; P: Protrusion; P1, P2: Lower part, Upper part; R1, R2, R3: Region; S1: First side wall; S2: Second side wall; θ1: Included angle FIG. 1A shows a top view of a light-emitting element 1 according to an embodiment of the present application. FIG. 1B shows a cross-sectional view taken along line segment A - A’ in FIG. 1A. FIG. 2A shows a partial enlarged view of region R1 in FIG. 1A. FIG. 2B shows a partial enlarged view of region R2 in FIG. 1A. FIGS. 3A to 3C show a manufacturing method of the light-emitting element 1 according to an embodiment of the present application. FIGS. 4A and 4B show partial enlarged views of the manufacturing method of the light-emitting element 1 according to an embodiment of the present application. FIG. 5A shows a partial top view appearance photo of the light-emitting element 1 according to an embodiment of the present application. FIG. 5B shows an appearance photo of the first side wall S1 observed in the direction of the arrow in FIG. 5A. FIG. 6 shows a top view of a light-emitting element 2 according to another embodiment of the present application. FIG. 7 shows a manufacturing method of the light-emitting element 2 according to another embodiment of the present application. FIG. 8A shows a partial cross-sectional view of a light-emitting element 3 according to another embodiment of the present application. FIG. 8B shows a partial cross-sectional view of a light-emitting element 3 according to another embodiment of the present application. FIG. 9 shows a light-emitting element package 200 according to an embodiment of the present application. 1: Light-emitting element 10: Substrate 12a: Upper semiconductor layer 121a: Upper surface of the first semiconductor layer 18: Transparent conductive layer 180: Opening 20: First electrode 201: First pad electrode 202: First extension electrode 30: Second electrode 301: Second pad electrode 302: Second extension electrode 40a: First convex portion 40b: First concave portion 42a: Second convex portion 42b: Second concave portion E1, E2, E3, E4: First edge ~ Fourth edge

Claims

1. A light-emitting element, comprising: a substrate including a main surface and a plurality of protrusions, wherein, Viewed from above by one of the light-emitting elements, a plurality of polygonal patterns, each composed of a plurality of protrusions, are arranged on the main surface. Each of the polygonal patterns is composed of a plurality of adjacent protrusions. One of the polygonal patterns includes a non-parallel first virtual edge, a second virtual edge, and a third virtual edge. A semiconductor stack is located on the main surface, including a lower semiconductor stack and an upper semiconductor stack on the lower semiconductor stack. The lower semiconductor stack includes a first sidewall and an edge, with an obtuse inner angle between the first sidewall and the main surface. The edge, viewed from above, includes a first convex-concave pattern, which includes an adjacent first sub-edge, a second sub-edge, and a third sub-edge. The first sub-edge and the second sub-edge are substantially parallel to the first virtual edge and the second virtual edge, respectively. Wherein, the third virtual edge is not parallel to the first virtual edge and the second virtual edge; and wherein, the third sub-edge is adjacent to the first sub-edge and substantially parallel to the third virtual edge.

2. The light-emitting element as described in claim 1, wherein: The edge includes a first edge, a second edge relative to the first edge, a third edge, and a fourth edge relative to the third edge; the first edge includes a first portion, a second portion, and a third portion located between the first portion and the second portion; and the third portion includes the first embossed pattern, while the first portion and the second portion do not include the first embossed pattern.

3. The light-emitting element of claim 2, wherein the length of the third part is greater than the total length of the first part and the second part.

4. The light-emitting element of claim 1, wherein the lower semiconductor stack includes a first upper surface, the upper semiconductor stack includes a second sidewall, the second sidewall being inclined to the first upper surface.

5. The light-emitting element of claim 1, wherein the edge includes a first edge, a second edge relative to the first edge, a third edge, and a fourth edge relative to the third edge; the first embossed pattern is located on the first edge; the third edge includes a second embossed pattern, the second embossed pattern being different from the first embossed pattern.

6. The light-emitting element of claim 1, wherein the substrate comprises a single-crystal hexagonal lattice structure, the main surface comprises the c-plane of the single-crystal hexagonal lattice structure, and the third sub-edge is substantially perpendicular to the a-axis of the single-crystal hexagonal lattice structure.

7. The light-emitting element of claim 1, wherein the first sidewall comprises a plurality of connected columnar structures.

8. The light-emitting element of claim 7, wherein the plurality of columnar structures are respectively connected to the first sub-edge and the second sub-edge.

9. The light-emitting element of claim 1, wherein the first embossed pattern comprises a plurality of recesses and a plurality of convexities, the spacing between adjacent convexities being between 10 and 35 μm.

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