Image sensor with asymmetrically passivated isolation structure and methods thereof

Abstract

This invention describes a pixel for an image sensor. The pixel includes a photodiode disposed within a semiconductor substrate and between a first side and a second side of the semiconductor substrate, and an isolation structure. The isolation structure includes a bottom sidewall coupled to a first sidewall and a second sidewall of the isolation structure. The isolation structure is at least partially disposed between a gate electrode and the second side of the semiconductor substrate. A first implantation region of the semiconductor substrate is disposed close to the first sidewall of the isolation structure. The first implantation region is disposed between the photodiode and the first sidewall. A first dopant concentration in the first implantation region is greater than the bulk dopant concentration in the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates generally to complementary metal oxide semiconductor devices and, particularly but not exclusively, to CMOS image sensors. Prior Art

[0002] Image sensors, a type of complementary metal oxide semiconductor (CMOS) device, have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, their functionality and performance metrics are expected to be enhanced in various ways (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing.

[0003] A typical image sensor operates in response to image light reflected from an external scene and incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge shortly thereafter. The image charge generated by the pixel light can be measured as analog output image signals on row bit lines that vary with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light. The image light is read out from the bit lines as analog image signals and converted into digital values ​​to produce a digital image (i.e., image data) representing the external scene. Simple diagram description

[0004] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Not all instances of a component are necessarily labeled to avoid cluttering the drawings where appropriate. The figures are not necessarily drawn to scale, emphasis instead being placed on illustrating the principles being described.

[0005] 1A illustrates a top view of an exemplary pixel included in an image sensor having an asymmetric passivated isolation structure, according to embodiments of the present invention.

[0006] 1B illustrates a cross-sectional view of an example pixel along line AA′ shown in FIG. 1A , according to an embodiment of the present invention.

[0007] 1C illustrates a cross-sectional view of an example pixel along line BB' shown in FIG. 1A, according to an embodiment of the present invention.

[0008] 1D illustrates a cross-sectional view of an example pixel along line CC' shown in FIG. 1A , according to an embodiment of the present invention.

[0009] IE illustrates a cross-sectional view of an example pixel along line DD' shown in FIG. 1A , according to an embodiment of the present invention.

[0010] 2A illustrates a cross-sectional view of an exemplary isolation portion having a structurally asymmetric passivation portion, in accordance with an embodiment of the present invention.

[0011] 2B illustrates a graph representing an example doping profile for the example isolation structure shown in FIG. 2A , according to an embodiment of the invention.

[0012] 3 illustrates a method for forming an isolation structure with asymmetric passivation according to an embodiment of the present invention.

[0013] 4A-4D illustrate examples of angled implants for forming isolation structures with asymmetric passivation, according to an embodiment of the invention.

[0014] 5 illustrates an example imaging system including an image sensor having one or more isolation structures with asymmetric passivation, according to an embodiment of the invention. Implementation Method

[0015] Described herein are embodiments of apparatus, systems, and methods each relating to a complementary metal oxide semiconductor (CMOS) device having one or more asymmetric passivation isolation structures. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details, or with other methods, components, materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0016] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0017] Throughout this specification, several technical terms are used. These terms will have their ordinary meanings in the art unless otherwise specifically defined herein or the context of their use clearly indicates otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0018] It should be understood that the formation of isolation structures (e.g., shallow trench isolation structures, deep trench isolation structures, or other structures that result in the removal of one or more portions of a semiconductor substrate, which are subsequently refilled with the same or a different material or otherwise incorporated to electrically and / or optically isolate individual components) can result in defects that can negatively impact the performance of semiconductor devices, such as image sensors. For example, as pixels included in image sensors decrease in size (e.g., as manufacturing processes improve to allow for smaller feature sizes, increased space utilization efficiency, or the like), the effects of defects or traps introduced by the formation of isolation structures (such as plasma etching for trench formation) can lead to an increase in dark current and white pixel noise, a key metric that characterizes image sensors and is associated with the current generated by a pixel while the image sensor is not exposed. Consequently, a reduction in white pixels can lead to an increase in the signal-to-noise ratio and, therefore, a higher dynamic range for the image sensor.

[0019] To passivate defects and / or traps introduced by the formation of isolation structures, ion implantation can be used to dope regions of the semiconductor substrate proximate to the isolation structures. However, such passivation has been found to negatively impact random noise, the threshold voltage control of adjacent or nearby pixel transistors (e.g., source-follower transistors, reset transistors, double floating diffusion transistors, or any other transistors proximate to a passivated isolation structure), and potentially reduce full-well capacity. In other words, the passivation of defects / traps can have both positive and negative effects on semiconductor device performance.

[0020] It has been discovered that by forming an asymmetric doping profile around or otherwise proximate to an isolation structure, white pixel noise can be reduced while mitigating the negative consequences of passivation. The asymmetric doping profile enables selective doping of regions of the semiconductor substrate with different implant doses depending on their relative position to other components of the semiconductor device. For example, regions of the semiconductor substrate proximate to an isolation structure and the sidewalls of a floating diffusion region or photodiode can be doped at a higher dose (e.g., to passivate defect / trap sites), while other regions of the semiconductor substrate proximate to the sidewalls of an isolation structure and a gate electrode of a transistor can be doped at a lower concentration (e.g., to mitigate random noise and / or control an increase in threshold voltage) or not doped at all. Furthermore, doping can surround the isolation structure, allowing both the sidewalls and bottom surface of the isolation structure to be passivated, thereby more effectively enhancing the performance of the semiconductor device. Thus, an asymmetric doping profile can be extended around one or more isolation structures to advantageously reduce white pixel noise, mitigate an increase in noise, mitigate any reduction in full well capacity, and control the threshold voltage of transistors, which can improve the performance of semiconductor devices (e.g., image sensors). It should be understood that while embodiments of the present invention will be discussed in the context of pixels and / or image sensors, such embodiments are non-limiting, and in other embodiments, the asymmetric doping profiles described herein can be advantageously used in devices other than pixels and / or image sensors. It should be further understood that in many embodiments, an asymmetric doping profile can be formed by implanting regions having different doping concentrations, such implanted regions being disposed on opposite sides of a given isolation structure or otherwise proximate to such opposite sides. However, in accordance with the teachings of the present invention, the implanted regions need not be directly opposite each other. Rather, depending on a configuration of the pixel (e.g., the pixel layout, which describes the relative orientation and shape of the photodiode, floating diffusion region, isolation structure and / or gate electrode) and / or the cross-sectional plane through which the structure is viewed, implant regions having different doping concentrations may be positioned relative to each other and relative to the isolation structure in different configurations (e.g., in some embodiments, implant regions having different doping concentrations may be positioned proximate to adjacent sides of a given isolation structure).

[0021] FIG1A illustrates a top view 100 of an exemplary pixel 101 included in an image sensor having an asymmetric passivation isolation structure, according to an embodiment of the present invention. Exemplary pixel 101 includes a semiconductor substrate 105, a photodiode 110, a transfer gate electrode 115 of a transfer transistor, a source-follower gate electrode 117 of a source-follower transistor, a reset gate electrode 119 of a reset transistor, a floating diffusion region 125, and isolation structures 130, including isolation structures 130-1, 130-2, and 130-3. In embodiments of the present invention, semiconductor substrate 105 includes silicon, a silicon-germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, any other alloy formed from III-V compounds, combinations thereof, or a bulk substrate thereof, or is formed from the foregoing materials. In some embodiments, semiconductor substrate 105 is a pure semiconductor (e.g., undoped), while in other embodiments, semiconductor substrate 105 is an impure semiconductor (e.g., semiconductor substrate 105 is a p-type semiconductor or an n-type semiconductor, where "p" and "n" indicate a conductivity type of semiconductor substrate 105). In some embodiments, semiconductor substrate 105 includes an epitaxial layer grown thereon, for forming photodiode 110 therein. In one or more embodiments, semiconductor substrate 105 can be described as having a bulk dopant concentration corresponding to a background or baseline doping characteristic of semiconductor substrate 105 (e.g., the bulk dopant concentration can describe a baseline pure or impure doping characteristic). In the same or other embodiments, the bulk dopant concentration can correspond to the dopant concentration of the epitaxial layer grown on semiconductor substrate 105. It should be further understood that the term "semiconductor substrate" throughout this disclosure can correspond to a portion or the entirety of a semiconductor wafer (e.g., formed from one or more of the aforementioned materials). Photodiode 110 is a photosensitive element (e.g., a pinned photodiode) comprising one or more doped regions of semiconductor substrate 105. These doped regions, collectively and / or in conjunction with semiconductor substrate 105, form a PN junction within semiconductor substrate 105 capable of photogenerating charge carriers in response to the intensity of light incident on photodiode 110. As illustrated, photodiode 110 of pixel 101 has a shape corresponding to a square with one corner removed (i.e., a regular polygon with five sides). However, in the same or other embodiments, photodiode 110 (or other instances thereof) may assume a rectangular, triangular, trapezoidal, pentagonal, hexagonal, heptagonal, octagonal, prismatic, or other shapes such as regular or irregular polygons.

[0022] Transfer gate electrode 115, source-follower gate electrode 117, and reset gate electrode 119 form the transfer transistor, source-follower transistor, and reset transistor, respectively, of pixel 101 for reading out photogenerated charge carriers generated by photodiode 110 in response to incident light. In one embodiment, transfer gate 115 is coupled to transfer photogenerated charge carriers accumulated in photodiode 110 to floating diffusion region 125. In the same or another embodiment, the reset gate is coupled to reset floating diffusion region 125 and / or photodiode 110 (e.g., to a predetermined charge level or voltage), while source-follower gate 117 is coupled to amplify the charge accumulated in floating diffusion region 125 and output a voltage indicative of the amplified charge. It should be understood that in the illustrated embodiment, the transfer gate electrode 115, the source-follower gate electrode 117, and the reset gate electrode 119 can be used to operate the pixel 101 similarly to a 4T pixel. It should further be understood that not all gate electrodes included in the pixel 101 need be illustrated. For example, the pixel 101 may include additional gate electrodes for a column of select transistors, transistors included in the conversion gain circuitry (e.g., a double floating diffusion), transistors coupled to memory elements, and other transistors (e.g., for 3T, 5T, 6T, or other higher transistor count pixel architectures). In some embodiments, the gate electrodes (e.g., the transfer gate electrode 115, the source follower gate electrode 117, the reset gate electrode 119, or other gate electrodes included in the pixel 101) may be formed of polysilicon (impure or pure), metal (e.g., one or more of Al, Cu, Au, Ag, Ti, Ta, Nb), metal alloys (e.g., TaN, WNx, other metal nitrides, RuOx, or other metal oxide gate electrode materials), or combinations thereof.

[0023] Disposed proximate to the gate electrodes of pixel 101 (e.g., transfer gate electrode 115, source-follower gate electrode 117, and reset gate electrode 119) is isolation structure 130. Isolation structure 130 may be one or more interconnected or physically distinct and separate structures positioned to electrically and / or optically isolate adjacent elements included in pixel 101 (e.g., isolation structure 130-1 is shaped and positioned to isolate floating diffusion region 125 from source-follower gate electrode 117). As illustrated in FIG. 1A , isolation structure 130-1, isolation structure 130-2, and isolation structure 130-3 are dependent and independent isolation structures. However, in other embodiments, isolation structure 130-1, isolation structure 130-2, and isolation structure 130-3 extend from one another or are otherwise coupled together to form a monolithic isolation structure. Therefore, and in some embodiments, reference to one of isolation structure 130-1, isolation structure 130-2, or isolation structure 130-3 may correspond to a portion of a larger monolithic isolation structure included in pixel 101. Isolation structure 130 may be a shallow trench isolation structure or a deep trench isolation structure. In most embodiments, isolation structure 130 corresponds to a shallow trench isolation structure. In some embodiments, isolation structure 130 may be formed from a trench filled with a dielectric material, or may otherwise include silicon dioxide, other dielectric materials (e.g., HfO2 or other insulating materials with a dielectric constant greater than a corresponding dielectric constant of silicon dioxide), polysilicon, or a combination thereof.

[0024] In the illustrated embodiment, isolation structure 130-1 is disposed proximate to and below transfer gate electrode 115 and / or source follower gate electrode 117, isolation structure 130-2 is disposed proximate to and below transfer gate electrode 115 and reset gate electrode 119, and isolation structure 130-3 is disposed proximate to and below source follower gate electrode 117, as illustrated in Figures 1A to 1E. Advantageously, the configuration of the photodiode 110, gate electrodes (e.g., transfer gate electrode 115, source-follower gate electrode 117, reset gate electrode 119, or other gate electrodes included in pixel 101), floating diffusion region 125, and isolation structure 130 promotes efficient use of space within or near semiconductor substrate 105 (e.g., to increase the fill factor of pixel 101). However, the close proximity of certain components may increase dark current, white pixels, and / or noise. For example, sidewalls of isolation structure 130 proximate to photodiode 110 (e.g., sidewalls of portions of isolation structures 130-1 and 130-2 disposed beneath transfer gate electrode 115, or sidewalls of other portions of isolation structure 130 disposed proximate to photodiode 110) may have an increased trap density, which may be charged and increase dark current. To mitigate this effect, the sidewalls of the trench used to form the isolation structure 130, or more specifically, the region of the semiconductor substrate 105 where the trench sidewalls are formed, can be passivated by implanting one or more dopants (e.g., B, As, P, other Group III or V elements, or combinations thereof). However, it has been found that uniform doping of the sidewalls of the isolation structure 130 can negatively impact random noise and unintentionally modulate the threshold voltage of transistors associated with the gate electrode 130 (e.g., the source-follower transistor associated with the source-follower gate electrode 117 and the reset transistor associated with the remaining gate electrode 119 of the pixel 101). This is particularly true for regions of the semiconductor substrate 105 that are positioned proximate to the isolation structure 130 that are also located beneath a gate electrode (e.g., the source-follower gate electrode 117, the reset gate electrode 119, or other gate electrodes included in the pixel 101). To achieve the benefits of trap / defect passivation while reducing random noise, embodiments of the pixel 101 described herein include one or more asymmetric doping profiles for regions of the semiconductor substrate 105 proximate to the isolation structure 130. The one or more asymmetric doping profiles have been developed to balance the benefits of isolation structure passivation, reducing dark current and / or white pixels while mitigating the increase in noise associated with isolation structure passivation and further providing transistor threshold voltage control.

[0025] In the following description of FIG. 1B through FIG. 1E , which provide additional views of the pixel 101 illustrated in FIG. 1A , implant regions 132 and 134 are discussed. Implant regions 132 and 134 extend from or are otherwise disposed proximate to sidewalls of the isolation structure 130 while at least partially underlying one or more gate electrodes (e.g., the transfer gate electrode 115 , the source-follower gate electrode 117 , the remaining gate electrode 119 , or other gate electrodes included in the pixel 101 ). It should be understood that implant regions 132 and 134 correspond to regions of the semiconductor substrate 105 having different dopant concentrations relative to one another (e.g., the dopant concentration of implant region 132 is greater than the dopant concentration of implant region 134 ), which may be due to differences in implant dose. For example, implant region 132 may have a dopant concentration that is at least one or two orders of magnitude greater than a corresponding dopant concentration of implant region 134 . Generally, implant region 132 is positioned to passivate traps present in semiconductor substrate 105 proximate photodiode 110 caused by the formation of isolation structure 130, while implant region 134 is positioned to control the threshold voltage associated with transistors included in pixel 101 and reduce noise during readout.

[0026] In the following figures (e.g., 101-AA' of FIG. 1B, 101-BB' of FIG. 1C, 101-CC' of FIG. 1D, and 101-DD' of FIG. 1E), implant regions 132 and 134 will be suffixed with a number (e.g., 1, 2, or 3) to indicate from which of the isolation structures 130 (e.g., 130-1, 130-2, or 130-3) the implant region extends, and with a letter (e.g., A, B, C, D) to indicate to which line (e.g., AA', BB', CC', or DD' illustrated in FIG. 1A) the implant region is associated. However, it should be understood that the doping concentrations of similarly labeled implant regions are not necessarily identical (e.g., implant region 132-1A illustrated in FIG. 1B may not necessarily have exactly the same dopant concentration as implant region 132-1B illustrated in FIG. 1C). Additionally, it should be noted that, due to the distance dependence of dopant concentration, the dopant concentration of implanted regions 132 and 134 may not be uniform within a given view (e.g., the dopant concentration of implanted region 132-1B illustrated in FIG. 1C is not necessarily the same as the dopant concentration of implanted region 132-1D illustrated in FIG. 1E ). Thus, terms such as "asymmetric doping profile" correspond to a doping concentration of a given region that is examined at a common distance from a reference point when compared (e.g., with reference to FIG. 1B , the dopant concentration of implanted region 132-1A may be examined at a first distance from sidewall 130-1S1, while the dopant concentration of implanted region 134-1A may be examined at a second distance from sidewall 130-1S2 when the first distance is equal to the second distance). However, it should be understood that, in general, the dopant concentration of implanted region 132 is greater than the dopant concentration of implanted region 134.

[0027] FIG1B illustrates a cross-sectional view 101-AA′ of an exemplary pixel 101 along line AA′ shown in FIG1A , according to an embodiment of the present invention. As illustrated, semiconductor substrate 105 includes a first side 107 (e.g., a front side or a back side) and a second side 109 (e.g., a back side or a front side) opposite first side 107. Cross-sectional view 101-AA′ further illustrates photodiode 110 disposed between first side 107 and second side 109 and extending at least partially beneath transfer gate electrode 115, such that photodiode 110 is disposed between transfer gate electrode 115 and second side 109. The photodiode 110 has a first conductivity type (e.g., p-type or n-type) opposite to the conductivity type (e.g., n-type or p-type) of the semiconductor substrate 105 and / or a corresponding conductivity type of a well (not illustrated) formed in the semiconductor substrate 105, in which the photodiode 110 resides (e.g., in some embodiments, the photodiode 110 may be disposed within or surrounded by a well formed by doping a corresponding region of the semiconductor substrate 105). In the illustrated embodiment, a pinning layer 112 is formed in the semiconductor substrate 105 between the first side 107 of the semiconductor substrate 105 and the photodiode 110 to collectively form a pinned photodiode (i.e., the pinning layer 112 is combined with the photodiode 110 and / or one or more wells formed in the semiconductor substrate 105).

[0028] The illustrated view of FIG1B further includes transfer gate electrode 115, source-follower gate electrode 117, floating diffusion region 125, gate dielectric 127, isolation structure 130-1, and isolation structure 130-3. In some embodiments, gate dielectric 127 corresponds to one or more insulating materials used to form transistors included in pixel 101 (e.g., a transfer transistor associated with transfer gate electrode 115, a source-follower transistor associated with source-follower gate electrode 117, a reset transistor associated with reset gate electrode 119, or any other transistor associated with or otherwise included in pixel 101, as illustrated in FIG1A or described in embodiments of the present invention). In some embodiments, gate dielectric 127 includes at least one of silicon dioxide, hafnium oxide, or other dielectric materials. In the illustrated embodiment, isolation structure 130-1 and isolation structure 130-3 are surrounded by or otherwise disposed proximate to implant regions 132 and 134 (eg, implant regions 132-1A, 132-3A, 134-1A, and 134-3A) of semiconductor substrate 105.

[0029] In some embodiments, implant regions 132 and 134 directly contact one or more sidewalls of isolation structure 130 (e.g., implant region 132-1A directly contacts sidewall 130-1S1, and implant region 134-3A directly contacts sidewall 130-3S1). It should be understood that direct contact may occur due to fabrication methods resulting from an ion implantation process (e.g., as illustrated in FIG. 3 ). However, in other embodiments, and depending on the implantation process (e.g., the ion implantation energy), implant regions 132 and 134 may not directly contact one or more sidewalls of isolation structure 130. However, it should be understood that due to the implantation process, implant regions 132 and 134 will be positioned proximate to one or more sidewalls of isolation structure 130, through which implant regions 132 and 134 are formed (i.e., implant regions 132 and 134 are formed through the sidewalls of a trench that is subsequently filled to form isolation structure 130, and the aforementioned sidewalls of the trench become the sidewalls of isolation structure 130, which is positioned proximate to implant regions 132 and 134). In the same or other embodiments, implant regions 132 and 134 may interface with or otherwise directly contact one another (e.g., implant region 132-1A contacts implant region 134-1A at interface 136). In other embodiments, implant regions 132 and 134 may not interface with one another. In certain embodiments, adjacent implant regions may interface with one another (e.g., implant region 134-1A may interface with or otherwise extend into implant region 134-3A). As illustrated, implant regions 134-1A and 134-3A are disposed between implant regions 132-1A and 132-3A. Implant region 132-1A is disposed between implant region 134-1A and floating diffusion region 125. In some embodiments, implant region 132-1A extends toward, and in some cases contacts, floating diffusion region 125.

[0030] In some embodiments, implanted regions 132 and 134 may be doped regions of semiconductor substrate 105 (e.g., with ions of B, As, P, other Group III or Group V elements, or combinations thereof) that have a common conductivity type (e.g., p-type or n-type) as photodiode 110, which is opposite to a conductivity type of pinned layer 112 and / or the bulk conductivity type of semiconductor substrate 105. In one embodiment, floating diffusion region 125 has a common conductivity type as one or more of implanted regions 132 and 134. In the same or other embodiments, implanted regions 132 and 134 have a common conductivity type. In some embodiments, one or more of implanted regions 132 or 134 may be optional or may be omitted. For example, in one embodiment, a portion of the semiconductor substrate 105 corresponding to the implanted region 134 may be undoped, but may have a dopant concentration corresponding to the bulk characteristic dopant concentration of the semiconductor substrate 105 (i.e., the implanted region 134 has a dopant concentration corresponding to the bulk dopant concentration of the semiconductor substrate 105). In either case (e.g., whether the implanted region 134 is doped above the bulk dopant concentration of the semiconductor substrate 105), the dopant concentration of the implanted region 132 is greater (e.g., on the order of atoms / cm 3 ) than the dopant concentration of the implanted region 134 to form an asymmetric doping profile around one or more of the isolation structures 130 (e.g., isolation structure 130-1, isolation structure 130-3, or any other isolation structure included in the isolation structure 130 of an embodiment of the present invention that is specifically illustrated or otherwise described). In some embodiments, floating diffusion 125 and one of implanted regions 132 or 134 (e.g., 132-1A) have substantially similar dopant concentrations (e.g., within 10%) and conductivity types (e.g., both are p-type or n-type). In other embodiments, the dopant concentration of floating diffusion region 125 is greater than the dopant concentration of one or more of implanted regions 132 and 134. It will be appreciated that the asymmetric doping profile is due to the different doses used when performing the ion implantation. Thus, in some embodiments, a first implant dose used to form implanted region 132 is at least one order of magnitude, two orders of magnitude, or more greater than a second implant dose used to form implanted region 134.

[0031] As illustrated, one or more of the implanted regions 134 (e.g., implanted regions 134-1A and 134-3A) are at least partially disposed below the source-follower gate electrode 117 (e.g., such that at least one of the implanted regions 134 is disposed between the source-follower gate electrode 117 and the second side 109 of the semiconductor substrate 105). Depending on the dopant type and concentration, this can be used to adjust or mitigate threshold voltage modulation of a source-follower transistor associated with the source-follower gate electrode 117, reduce noise, or the like. It should be understood that the implanted regions 134 can be implanted to form a channel region associated with the source-follower transistor below the source-follower gate electrode 117 of the source-follower transistor, proximate to the source-follower transistor, for adjusting or mitigating threshold voltage modulation of other transistors (e.g., a reset transistor) included in the pixel 101, reducing noise, or the like through dopant concentration adjustment according to embodiments of the present invention. Disposed between the photodiode 110 and one or more of the isolation structures 130 (e.g., isolation structure 130-1) is one of the implanted regions 132 (e.g., implanted region 132-1A), which is positioned to passivate defects or traps that could negatively impact the operation of the pixel 101 (e.g., by generating dark current and / or producing a white pixel when the traps are charged). It should be appreciated that the proximity of the implanted region 132 (e.g., 132-1A) (e.g., see FIG1C for implanted regions 132-1B and / or 132-2B in FIG1A ) to the floating diffusion region 125 and / or the photodiode 110 can provide the beneficial effect of passivating trap sites proximate to the isolation structure 130 that would otherwise have an adverse effect on photogenerated charge carriers, increase dark current, or otherwise adversely impact the operation and / or performance of the pixel 101.

[0032] In the illustrated embodiment, isolation structures 130-1 and 130-3 are disposed within semiconductor substrate 105 and extend from first side 107 toward second side 109. Source-follower gate electrode 117 is disposed proximate to first side 107 of semiconductor substrate 105. Isolation structures 130-1 and 130-3 are at least partially disposed between source-follower gate electrode 117 and second side 109 of the semiconductor substrate. Contacting, extending from, or otherwise proximate to isolation structures 130-1 and 130-3 are implanted regions 132 and 134 (e.g., implanted regions 132-1A and 134-1A are proximate to isolation structure 130-1, and implanted regions 132-3A and 134-3A are proximate to isolation structure 130-3). As illustrated, isolation structure 130-1 and isolation structure 130-3 are respectively disposed between edge 129 of source-follower gate electrode 117 and second side 109 of semiconductor substrate 105, such that source-follower gate electrode 117 does not extend over respective portions of isolation structure 130-1 and isolation structure 130-3 (i.e., source-follower gate electrode 117 does not completely cover isolation structures 130-1 and 130-3, and further does not extend over at least a portion of implant regions 132-1A and 132-3A).

[0033] Cross-sectional view 101-AA' in FIG1B shows the respective sidewalls and bottom surfaces included in isolation structures 130-1 and 130-3. Specifically, isolation structure 130-1 includes bottom surface 130-1B, sidewall 130-1S1, and sidewall 130-1S2, while isolation structure 130-3 includes bottom surface 130-3B, sidewall 130-3S1, and sidewall 130-3S2. As illustrated, sidewall 130-1S1 opposes sidewall 130-1S2, while bottom surface 130-1B is coupled to sidewalls 130-1S1 and 130-1S2. Similarly, sidewall 130-3S1 opposes sidewall 130-3S2, while bottom surface 130-3B is coupled to sidewalls 130-3S1 and 130-3S2. In the illustrated view, implant region 132-1A extends from sidewall 130-1S1 of isolation structure 130-1 toward photodiode 110, and implant region 134-1A extends from sidewall 130-1S2 and is positioned further away from photodiode 110 than implant region 132-1A. In other words, implant region 132-1A is positioned between photodiode 110 and sidewall 130-1. Furthermore, isolation structures 130-1 and 130-3 are both positioned between photodiode 110 and implant region 132-3A. Furthermore, implant region 132-1A is positioned between photodiode 110 and implant region 134-1A.

[0034] In some embodiments, and as illustrated in FIG. 1B , implant region 132-1A contacts both sidewalls 130-1S1 and bottom surface 130-1B of isolation structure 130-1 without contacting sidewalls 130-1S2 of isolation structure 130-1. Implant region 134-1A contacts both sidewalls 130-1S2 and bottom surface 130-1B of isolation structure 130-1 without contacting sidewalls 130-1S1 of isolation structure 130-1. Thus, bottom surface 130-1B is disposed between first side 107 of semiconductor substrate 105 and both implant regions 132-1A and 134-1A. Similarly, implant region 132-3A contacts both sidewalls 130-3S2 and bottom surface 130-3B of isolation structure 130-3 without contacting sidewalls 130-3S1 of isolation structure 130-3. Implanted region 134-3A contacts both sidewalls 130-3S1 and bottom surface 130-3B of isolation structure 130-3, but does not contact sidewalls 130-3S2 of isolation structure 130-3. Thus, bottom surface 130-3B is disposed between first side 107 of semiconductor substrate 105 and two of implanted regions 132-3A and 134-3A. In some embodiments, implanted regions 134-1A and 134-3A, respectively formed or positioned opposite implanted regions 132-1A and 132-3A in semiconductor substrate 105, have respective dopant concentrations corresponding to the bulk dopant concentration of semiconductor substrate 105. In other embodiments, implanted regions 134-1A and 134-3A have respective dopant concentrations that are greater than the bulk dopant concentration of semiconductor substrate 105 but less than the corresponding dopant concentrations of implanted regions 132-1A and 132-3A. It will be appreciated that the asymmetric doping profile, due at least in part to the difference in dopant concentration between implanted regions 132 and 134, provides the benefit of passivating one or more regions of semiconductor substrate 105 proximate to isolation structure 130 (e.g., to mitigate the effects of traps or other defects), while also enabling control of the threshold voltage of one or more transistors and mitigating increases in noise.

[0035] FIG1C illustrates a cross-sectional view 101-BB' of an exemplary pixel 101 along line BB' shown in FIG1A , in accordance with an embodiment of the present invention. Specifically, when viewed against the backdrop of FIG1A , cross-sectional view 101-BB' in FIG1C shows that regions of isolation structures 130 (e.g., 130-1 and 130-2) proximate to photodiode 110 (e.g., where defects or traps may have been introduced due to the fabrication of isolation structures 130) are passivated by one or more implanted regions (e.g., 132-1B and 132-2B illustrated in FIG1C ). Specifically, one or more regions of semiconductor substrate 105 disposed between photodiode 110 and isolation structure 130 are doped to form implanted regions of semiconductor substrate 105 (e.g., implanted regions 132-1B and 132-2B illustrated in FIG1C ). As illustrated, when FIG. 1C is viewed in the context of FIG. 1A , implant regions 132-1B and 132-2B extend from respective sidewalls of isolation structure 130 (e.g., 130-1S4 and 130-2S1, respectively) toward photodiode 110. In other words, implant regions 132-1B and 132-2B are disposed between photodiode 110 and corresponding sidewalls of isolation structure 130 (i.e., 130-1S4 and 130-2S1, respectively).

[0036] 1C , isolation structure 130-1 and isolation structure 130-2 are disposed within semiconductor substrate 105 and extend from first side 107 toward second side 109. Transfer gate electrode 115 and reset gate electrode 119 are disposed proximate to first side 107 of semiconductor substrate 105. In the illustrated view, both isolation structure 130-1 and isolation structure 130-2 are disposed between transfer gate electrode 115 and second side 109 of semiconductor substrate 105, while isolation structure 130-2 is further disposed between reset gate electrode 119 and second side 109 of semiconductor substrate 105. Contacting isolation structure 130-1 and isolation structure 130-2, or otherwise disposed proximate to isolation structure 130-1 and isolation structure 130-2, are implant regions 132 and 134 (e.g., implant regions 132-1B and 134-1B are proximate to isolation structure 130-1, and implant regions 132-2B and 134-2B are proximate to isolation structure 130-2). As illustrated, isolation structure 130-1 and isolation structure 130-2 are disposed between edge 137 of transfer gate electrode 115 and second side 109 of semiconductor substrate 105, such that transfer gate electrode 115 does not extend over respective portions of isolation structure 130-1 and isolation structure 130-2 (i.e., transfer gate electrode 115 does not completely cover isolation structures 130-1 and 130-2, and further does not extend over at least a portion of implant regions 134-1A and 134-2B). Similarly, the isolation structure 130-2 is disposed between the edge 135 of the reset gate electrode 119 and the second side 109 of the semiconductor substrate 105, such that the reset gate electrode 119 does not extend over respective portions of the isolation structure 130-2 (i.e., the reset gate electrode 119 does not completely cover the isolation structure 130-2 and further does not extend over at least a portion of the implanted region 132-2B).

[0037] Cross-sectional view 101-BB' in FIG1C shows the respective sidewalls and bottom surfaces included in isolation structures 130-1 and 130-2. Specifically, isolation structure 130-1 includes bottom surface 130-1B, sidewall 130-1S3, and sidewall 130-1S4, while isolation structure 130-2 includes bottom surface 130-2B, sidewall 130-2S1, and sidewall 130-2S2. As illustrated, bottom surface 130-1B is coupled to sidewalls 130-1S3 and 130-1S4. Similarly, bottom surface 130-2B is coupled to sidewalls 130-2S1 and 130-2S2.

[0038] As illustrated, implant regions 132-1B and 132-2B are formed proximate to respective sidewalls of isolation structure 130 (e.g., 130-1S4 and 130-2S1, respectively) and below the transfer gate electrode 115 of the transfer transistor associated with pixel 101. In some embodiments, and as illustrated in FIG1C , implant region 132-1B contacts both sidewall 130-1S4 and bottom surface 130-1B of isolation structure 130-1 without contacting sidewall 130-1S3 of isolation structure 130-1. Implant region 134-1B is implanted and formed proximate to sidewall 130-1S3 of isolation structure 130-1 that is not located below transfer gate electrode 115. Implant region 134-2B is implanted and formed below the reset gate electrode 119 of the reset transistor. Implant region 134-1B contacts both sidewalls 130-1S3 and bottom surface 130-1B of isolation structure 130-1, but not sidewalls 130-1S4 of isolation structure 130-1. Thus, bottom surface 130-1B is disposed between first side 107 of semiconductor substrate 105 and both implant regions 132-1B and 134-1B. Similarly, implant region 132-2B contacts both sidewalls 130-2S1 and bottom surface 130-2B of isolation structure 130-2, but not sidewalls 130-2S2 of isolation structure 130-2. Implant region 134-2B contacts both sidewalls 130-2S2 and bottom surface 130-2B of isolation structure 130-2, but not sidewalls 130-2S1 of isolation structure 130-2. Thus, bottom surface 130-2B is disposed between first side 107 of semiconductor substrate 105 and two of implanted regions 132-2B and 134-2B. In the illustrated view, implanted regions 134-1B and 134-2B may have respective dopant concentrations corresponding to the bulk dopant concentration of semiconductor substrate 105. In other embodiments, implanted regions 134-1B and 134-2B have respective dopant concentrations that are greater than the bulk dopant concentration of semiconductor substrate 105 but less than the corresponding dopant concentrations of implanted regions 132-1B and 134-2B. It will be appreciated that an asymmetric doping profile, at least in part due to the dopant concentration difference between implanted regions 132 and 134, provides the benefit of passivating one or more regions of semiconductor substrate 105 proximate to isolation structure 130 (e.g., to mitigate the effects of traps or other defects), while also enabling control of the threshold voltage of one or more transistors and mitigating increases in noise.

[0039] FIG1D illustrates a cross-sectional view 101-CC' of an exemplary pixel 101 along line CC' shown in FIG1A according to an embodiment of the present invention. Specifically, when viewed in the context of FIG1A , cross-sectional view 101-CC' of FIG1D shows that regions of isolation structure 130 (e.g., 130-1 and 130-3) are disposed below source-follower gate electrode 117 and / or are disposed proximate to floating diffusion region 125. In the illustrated view of FIG1D are implanted regions 132-1C, 132-3C, 134-1C, and 134-3C. It should be understood that implant region 132-1C is disposed between isolation structure 130-1 and floating diffusion region 125 (e.g., to passivate defects or traps that could adversely affect image charge readout from floating diffusion region 125), while implant regions 134-1C and 134-3C are disposed proximate to respective sidewalls of isolation structures 130-1 and 130-3 beneath source-follower gate electrodes 117. Implant regions 134-1C and 134-3C can adjust the threshold voltage of the source-follower transistor and / or mitigate an increase in noise during operation of the source-follower transistor). As illustrated, implant regions 132-1C, 132-3C, 134-1C, and 134-3C extend from respective sidewalls of isolation structure 130 (e.g., 130-1S1, 130-3S3, 130-1S2, and 130-3S1, respectively). In the illustrated view, implant regions 134-1C and 134-3C are disposed between implant regions 132-1C and 132-3C. Additionally, bottom surface 130-1B is disposed between first side 107 of semiconductor substrate 105 and both of implant regions 132-1C and 134-1C. Similarly, bottom surface 130-3B is disposed between first side 107 of semiconductor substrate 105 and both of implant regions 132-3C and 134-3C.

[0040] Cross-sectional view 101-CC' of FIG1D shows the respective sidewalls and bottom surfaces included in isolation structures 130-1 and 130-3. Specifically, isolation structure 130-1 includes bottom surface 130-1B, sidewall 130-1S1, and sidewall 130-1S2, while isolation structure 130-3 includes bottom surface 130-3B, sidewall 130-3S1, and sidewall 130-3S3. As illustrated, bottom surface 130-1B is coupled to sidewalls 130-1S1 and 130-1S2, and bottom surface 130-3B is coupled to sidewalls 130-3S1 and 130-3S3. As illustrated, isolation structure 130-1 and isolation structure 130-3 are disposed between edge 129 of source-follower gate electrode 117 and second side 109 of semiconductor substrate 105, such that source-follower gate electrode 117 does not extend over respective portions of isolation structure 130-1 and isolation structure 130-3 (i.e., source-follower gate electrode 117 does not completely cover isolation structures 130-1 and 130-2 and does not further extend over respective portions of implanted regions 132-1C and 132-3C). In some embodiments, implanted regions 134-1C and 134-3C have respective dopant concentrations corresponding to the bulk dopant concentration of semiconductor substrate 105. In other embodiments, implanted regions 134-1C and 134-3C have respective dopant concentrations that are greater than the bulk dopant concentration of semiconductor substrate 105 but less than the corresponding dopant concentrations of implanted regions 132-1C and 132-3C. It will be appreciated that an asymmetric doping profile, due at least in part to the difference in dopant concentration between implanted regions 132 and 134, provides the benefit of passivating one or more regions of semiconductor substrate 105 proximate to isolation structure 130 (e.g., to mitigate the effects of traps or other defects), while also enabling control of the threshold voltage of one or more transistors and mitigating increases in noise.

[0041] It should be understood that when viewing isolation structure 130-2 in the context of at least FIG. 1A and FIG. 1C , it can be seen that isolation structure 130-2 extends at least partially beneath transfer gate electrode 115 (i.e., a gate electrode) and reset gate electrode 119 (i.e., a second gate electrode). Consequently, an implanted region extending from a sidewall of isolation structure 130-2 (e.g., a first implanted region corresponding to 132-2B extending from a first sidewall corresponding to 130-2S1) is disposed between isolation structure 130-2 and photodiode 110 (e.g., as shown when viewing FIG. 1C in the context of FIG. 1A ). Furthermore, a second sidewall of isolation structure 130-2 (e.g., sidewall 130-2S2 illustrated in FIG. 1C ) is disposed between reset gate electrode 119 and second side 109 of semiconductor substrate 105.

[0042] FIG1E illustrates a cross-sectional view 101-DD' of an exemplary pixel 101 along line DD' shown in FIG1A , according to an embodiment of the present invention. Specifically, when viewed in the context of FIG1A , cross-sectional view 101-DD' of FIG1E shows that regions of isolation structure 130-1 proximal to photodiode 110 (e.g., where defects or traps may have been introduced due to the fabrication of isolation structure 130-1) are passivated by one or more implanted regions (e.g., 132-1 illustrated in FIG1E ). One or more regions of semiconductor substrate 105 disposed between photodiode 110 and isolation structure 130-1 are doped to form implanted regions of semiconductor substrate 105 (e.g., implanted region 132-1D illustrated in FIG1E ). As illustrated, implant region 132-1D extends from sidewall 130-155 of isolation structure 130-1 toward photodiode 110, and implant region 134-1D extends from sidewall 130-156 of isolation structure 130-1 and is disposed further away from the photodiode region of photodiode 110.

[0043] In the illustrated embodiment, isolation structure 130-1 is disposed within semiconductor substrate 105 and extends from first side 107 toward second side 109. Transfer gate electrode 115 is disposed proximate to first side 107 of semiconductor substrate 105. In the illustrated view, isolation structure 130-1 is disposed between transfer gate electrode 115 and second side 109 of semiconductor substrate 105. Contacting isolation structure 130-1 or otherwise disposed proximate to isolation structure 130-1 are implant regions 132 and 134 (e.g., implant regions 132-1D and 134-1D are proximate to isolation structure 130-1). As illustrated, the isolation structure 130-1 is disposed between one of the edges 137 of the transfer gate electrode 115 and the second side 109 of the semiconductor substrate 105 such that the transfer gate electrode 115 does not extend over a portion of the isolation structure 130-1 (i.e., the transfer gate electrode 115 does not completely cover the isolation structure 130-1 and does not further extend over at least a portion of the implant region 134-1D).

[0044] Cross-sectional view 101-DD' of FIG1E shows the individual sidewalls and bottom surfaces included in isolation structure 130-1. Specifically, isolation structure 130-1 includes bottom surface 130-1B, sidewall 130-1S5, and sidewall 130-1S6. As illustrated, sidewall 130-1S5 opposes sidewall 130-1S6, while bottom surface 130-1B is coupled to sidewalls 130-1S5 and 130-1S6. Similarly, sidewall 130-3S1 opposes sidewall 130-3S2, while bottom surface 130-3B is coupled to sidewalls 130-3S1 and 130-3S2.

[0045] In some embodiments, and as illustrated in FIG. 1E , implant region 132-1D contacts both sidewall 130-155 and bottom surface 130-1B of isolation structure 130-1 without contacting the opposing sidewall (e.g., sidewall 130-156) of isolation structure 130-1. Implant region 134-1D contacts both sidewall 130-156 and bottom surface 130-1B of isolation structure 130-1 without contacting the opposing sidewall (e.g., sidewall 130-155) of isolation structure 130-1. Thus, bottom surface 130-1B is disposed between first side 107 of semiconductor substrate 105 and both implant regions 132-1D and 134-1D. In some embodiments, in the illustrated view, implanted region 134-1D, disposed on a sidewall of isolation structure 130-1 (e.g., sidewall 130-186), opposite implanted region 132-1D, has a respective dopant concentration corresponding to the bulk dopant concentration of semiconductor substrate 105. In other embodiments, implanted region 134-1D has a respective dopant concentration that is greater than the bulk dopant concentration of semiconductor substrate 105 but less than a corresponding dopant concentration of implanted region 132-1D. It will be appreciated that an asymmetric doping profile, at least in part due to the dopant concentration difference between implanted regions 132 and 134, provides the benefit of passivating one or more regions of semiconductor substrate 105 proximate to isolation structure 130 (e.g., to mitigate the effects of traps or other defects), while also enabling control of the threshold voltage of one or more transistors and mitigating increases in noise.

[0046] It should be further understood that additional details of embodiments of the present invention can be inferred when considering the context provided by the various figures disclosed herein. For example, it should be understood that when isolation structure 130-1 is viewed in the context of at least FIG. 1A , FIG. 1B , and FIG. 1E , it can be seen that isolation structure 130-1 extends at least partially beneath transfer gate electrode 115 (i.e., a gate electrode) and source-follower gate electrode 117 (i.e., a second gate electrode). Consequently, an implanted region extending from a sidewall of isolation structure 130-1 (e.g., a first implanted region corresponding to 132-1D extending from a first sidewall corresponding to 130-1S5 illustrated in FIG. 1E ) is disposed between isolation structure 130-1 and photodiode 110. Furthermore, another sidewall of isolation structure 130-1 (e.g., a second sidewall corresponding to sidewall 130-1S2 illustrated in FIG. 1B ) is disposed between source-follower gate electrode 117 and second side 109 of semiconductor substrate 105. Furthermore, isolation structure 130-1 is disposed between photodiode 110 and isolation structure 130-3 (i.e., a second isolation structure). Thus, a sidewall of isolation structure 130-1 (e.g., a second sidewall corresponding to sidewall 130-1S2 illustrated in FIG. 1B ) is disposed between a sidewall of isolation structure 130-3 (e.g., a third sidewall of the second isolation structure corresponding to sidewall 130-3S1 illustrated in FIG. 1B ) and an implanted region (e.g., a first implanted region extending from first sidewall 130-1S5 illustrated in FIG. 1E , corresponding to implanted region 132-1D). As illustrated in FIG1B , a sidewall (e.g., a third sidewall) of isolation structure 130-3 is disposed between source-follower gate electrode 117 (i.e., the second gate electrode) and second side 109 of semiconductor substrate 105. It should be understood that additional implanted regions (e.g., one or more second implanted regions corresponding to implanted regions 134-1A and 134-3A illustrated in FIG1B ) are disposed between source-follower gate electrode 117 (i.e., the second gate electrode) and second side 109 of semiconductor substrate 105. Thus, the additional implanted regions contact at least one of isolation structure 130-3 (e.g., the third sidewall of the second isolation structure corresponding to sidewall 130-3S1 illustrated in FIG1B ) or isolation structure 130-1 (e.g., the second sidewall of the isolation structure corresponding to sidewall 130-1S2 illustrated in FIG1B ).As previously discussed, the additional implanted regions (e.g., one or more second implanted regions corresponding to implanted regions 134-1A and 134-3A illustrated in FIG. 1B ) have a corresponding dopant concentration (i.e., a second dopant concentration) that is greater than the bulk dopant concentration of semiconductor substrate 105 but less than the bulk dopant concentration of an implanted region extending from a different sidewall of isolation structure 130-1 (e.g., the first implanted region corresponding to 132-1D extending from the first sidewall corresponding to 130-1S5 illustrated in FIG. 1E , or any other implanted regions included in embodiments of the present invention labeled 132-1, 132-2, or 132-3).

[0047] In some embodiments, transfer gate electrode 115 corresponds to a first gate electrode, and source-follower gate electrode 117 or reset gate electrode 119 corresponds to a second gate electrode. In such embodiments, one or more implanted regions disposed between transfer gate electrode 115 and second side 109 of semiconductor substrate 105 (e.g., 132-1B and 132-2B illustrated in FIG. 1C and 132-1D illustrated in FIG. 1E ) may correspond to a first implanted region, while one or more other implanted regions opposite the first implanted region (e.g., 134-1B and 134-2B illustrated in FIG. 1C and 134-1D illustrated in FIG. 1E ) may correspond to a second implanted region not disposed under the gate electrode (i.e., transfer gate electrode 115).

[0048] It should be understood that embodiments of the present invention may include one or more dielectric or insulating materials (eg, isolation structure 130, gate dielectric 127, etc.), which may have a component that includes one or more dielectric materials. In some embodiments, the one or more dielectric materials may include oxides, nitrides, and / or silicates, such as silicon dioxide (SiO 2 ), hafnium oxide (HfO 2 ), hafnium silicate (HfSi xO y ), hafnium silicate nitride (HfSiON), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), praseodymium oxide (Pr 2 O 3 ), cerium oxide (CeO 2 ), neodymium oxide (Nd 2 O 3 ), bismuth oxide (Pm 2 O 3 ), samarium oxide (Sm 2 O 3 ), europium oxide (Eu 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), zirconium oxide (Tb 2 O 3 ), and / or bismuth oxide (CeO 2 ).

[0014] The present invention also provides a method for preparing a semiconductor material comprising: preparing a semiconductor material comprising: a bismuth oxide (bismuth oxide), ...

[0049] FIG2A illustrates a cross-sectional view of an isolation structure 230 having an asymmetric passivation portion according to an embodiment of the present invention. Isolation structure 230 is disposed within semiconductor substrate 105 and extends from first side 107 toward second side 109. As illustrated, isolation structure 230 includes sidewall 230-S1 and sidewall 230-S2 opposite sidewall 230-S1. Isolation structure 230 further includes a bottom surface 230-B coupled to sidewall 230-S1 and sidewall 230-S2. Contacting isolation structure 230 or otherwise disposed proximate to it are implanted regions 232 and 234. More specifically, implanted region 232 contacts or extends from both sidewall 230-S1 and bottom surface 230-B without contacting sidewall 230-S2. Additionally, implanted region 234 contacts both sidewall 230-S2 and bottom surface 230-B, or extends from both without contacting sidewall 230-S1. Thus, bottom surface 230-B is disposed between first side 107 of semiconductor substrate 105 and both implanted regions 232A and 234. As illustrated, implanted regions 232 and 234 also interface with each other at interface 236 (and, in some embodiments, partially overlap). However, in other embodiments, implanted regions 232 and 234 may not interface with each other. In the illustrated embodiment, implanted regions 232 and 234 are regions of semiconductor substrate 105 having different dopant concentrations to form an asymmetric doping profile. In most embodiments, the dopant concentration of implanted region 232 is greater than the dopant concentration of implanted region 234. In one embodiment, the average dopant concentration of implanted region 232 is greater than the average dopant concentration of implanted region 234. In some embodiments, an average dopant concentration of the implanted region 234 is greater than a dopant concentration (eg, bulk dopant concentration) of the semiconductor substrate 105. In some embodiments, the dopant concentration of the implanted region 234 corresponds to the bulk dopant concentration of the semiconductor substrate 105.

[0050] It should be understood that isolation structure 230 illustrated in FIG2A may correspond to or otherwise describe features of any of the isolation structures 130 illustrated in FIG1A through FIG1E . In other words, isolation structure 230 is one possible implementation of isolation structures 130-1, 130-2, and / or 130-3. Similarly, implant regions 232 and 234 are possible implementations of similarly named implant regions illustrated in FIG1A through FIG1E (e.g., one or more of implant regions 132 and 134, respectively), and thus may have the same or similar features, dopant concentrations, and the like. Therefore, it should be understood that the asymmetric doping profile formed by implant regions 232 and 234 may similarly describe the asymmetric doping profiles formed by the various embodiments of implant regions 132 and 134 illustrated in FIG1A through FIG1E . In other words, the asymmetric doping profiles associated with implanted regions 232 and 234 may be similar to the asymmetric doping profiles formed by implanted regions 132 and 134 illustrated in Figures 1A-1E.

[0051] FIG2B illustrates a graph 250 representing an example doping profile along line XX' of the example isolation structure shown in FIG2A , according to an embodiment of the present invention. It should be understood that graph 250 is an idealized graph in which the distance from a given point along line XX' to the nearest surface point of isolation structure 230 is equal across the length of line XX'. It should be understood that the dopant concentration from ion implantation is highly dependent on the implantation energy, the distance into semiconductor substrate 105, and generally has a Gaussian distribution as measured successively deeper into the semiconductor substrate from a surface point of isolation structure 230. For ease of illustration and explanation, line XX' is equidistant from isolation structure 230 and / or otherwise corresponds to a location within semiconductor substrate 105 (or, more specifically, within implant regions 232 and 234) where the dopant concentration corresponds to a local maximum.

[0052] Referring back to FIG. 2B , graph 250 illustrates locations along the distance axis labeled X, X1, X2, XINT, X3, and X' ("DIST.") and dopant concentrations annotated by level ("DOPANT CONC.") along the dopant concentration axis labeled 252, 254, 256, and 258. Locations X and X' correspond to locations within semiconductor substrate 105 along line XX' outside of implanted regions 232 and 234, which have a dopant concentration corresponding to level 252, which is the bulk dopant concentration of semiconductor substrate 105. Distance location X1, which is near where line XX' enters implanted region 234, increases from the bulk dopant concentration of semiconductor substrate 105 (i.e., level 252) to a peak dopant concentration in implanted region 234 corresponding to level 254. However, it should be understood that in other embodiments, the dopant concentration of implanted region 234 may correspond to the bulk dopant concentration of semiconductor substrate 105, as indicated by dashed line 262. In this embodiment, the dopant concentration along line XX' remains substantially at the bulk dopant concentration of semiconductor substrate 105 (i.e., at level 252) until reaching position X2, which corresponds to or is otherwise close to where line XX' enters implanted region 232. XINT corresponds to the interface where implanted regions 234 and 232 interface. In some embodiments, implanted regions 234 and 232 may overlap, resulting in a local peak 260 in dopant concentration occurring at level 258. It should be understood that local peak 260 may not occur in all embodiments, such as when there is no overlap between implanted regions 234 and 232 and / or when the dopant concentration of implanted region 234 corresponds to the bulk dopant concentration of semiconductor substrate 105. It should further be understood that the transition in dopant concentration between implanted regions 232 and 234 may be gradual. From distance position XINT toward position X3, the dopant concentration corresponds to a peak dopant concentration of implanted region 232 corresponding to level 256. Finally, as positions along line XX' leave implanted region 232 and enter semiconductor substrate 105, the dopant concentration from X3 to X' decreases to the bulk dopant concentration of semiconductor substrate 105.

[0053] It should be understood that the dopant concentrations represented by levels 252, 254, and 256 can differ from one another by one or more orders of magnitude, two or more orders of magnitude, or more. For example, the dopant concentration of implanted region 232 (e.g., at level 256) can be one, two, or more orders of magnitude greater than the dopant concentration of implanted region 234 (e.g., at levels 254 or 252). Similarly, the dopant concentration of implanted region 234 can be one, two, or more orders of magnitude greater than the bulk dopant concentration of semiconductor substrate 105 (e.g., at level 252). In some embodiments, the dopant concentration of implanted region 232 can be referred to as a first dopant concentration, and the dopant concentration of implanted region 234 can be referred to as a second dopant concentration (e.g., the first dopant concentration is greater than the second dopant concentration). It should be appreciated that the asymmetric doping profile illustrated in FIG. 2B for implant regions 232 and 234 illustrated in FIG. 2A can reduce white pixels and dark current without reducing RTS noise at pixel transitions (e.g., when implant region 232 is positioned close to a photodiode or floating diffusion and implant region 234 is close to the gate of a source-follower transistor or other pixel transistor, such as a reset transistor or a column select transistor).

[0054] FIG3 illustrates a method 300 for forming an isolation structure with an asymmetric passivation portion according to an embodiment of the present invention. It should be understood that method 300 is one possible manner in which isolation structures 130 and 230 illustrated in FIG1A through FIG2A may be formed or otherwise fabricated. It should be understood that while the process blocks of method 300 illustrated in FIG3 are provided in a particular order, in other embodiments, a different order of blocks 301, 303, 305, 307, 309, and 311 may be utilized. Furthermore, process blocks may be added to or removed from method 300 according to embodiments of the present invention. The process blocks illustrated in method 300 may utilize conventional semiconductor device processing and microfabrication techniques known to those skilled in the art, including, but not limited to, photolithography, ion implantation, chemical vapor deposition, physical vapor deposition, thermal evaporation, sputter deposition, reactive ion etching, plasma etching, wafer bonding, chemical mechanical planarization, and the like. It should be understood that the described techniques are merely illustrative and not exhaustive, and that other techniques may be utilized to create one or more components of the various embodiments of the present invention.

[0055] Block 301 illustrates providing a semiconductor substrate (e.g., semiconductor substrate 105 illustrated in Figures 1A-2A) that can be used to form an image sensor or other complementary metal oxide semiconductor device. It should be understood that the semiconductor substrate can be provided to one or more machines or other equipment for fabrication (e.g., for application of one or more conventional semiconductor device processing and microfabrication techniques). In some embodiments, the semiconductor substrate can be a pure or impure semiconductor wafer or a wafer substrate having an epitaxial layer grown thereon. The epitaxial layer can be pre-populated with one or more components (e.g., photodiodes), structures (e.g., wells), or the like.

[0056] Block 303 shows forming one or more photodiodes (e.g., see photodiode 110 illustrated in FIG. 1A , FIG. 1B , and FIG. 1E ) within a semiconductor substrate between a first side and a second side of the semiconductor substrate by one or more ion implantation processes having various ion implantation energies to form one or more photodiodes having a specific doping profile. It should be understood that in some embodiments, the first side and the second side, which are opposite to each other, may correspond to a front side and a back side of the semiconductor substrate, respectively, or vice versa.

[0057] Block 305 illustrates forming one or more trenches disposed within the semiconductor substrate. In certain embodiments, the one or more trenches extend from a first side into the semiconductor substrate and toward a second side. At least one trench included in the one or more trenches is formed proximate to at least one of the one or more photodiodes. It should be understood that in most embodiments, the trenches do not extend completely through the semiconductor substrate. However, in other embodiments, the trenches may extend completely through the semiconductor substrate. It should be understood that the one or more trenches may form an initial cavity from which one or more isolation structures (e.g., isolation structures 130 and / or 230 illustrated in Figures 1A-2A) are formed.

[0058] Block 307 shows implanting dopants from the first side of the semiconductor substrate into one or more of the trenches at a non-normal angle (e.g., see Figures 4C and 4D). It should be understood that block 307 may include one or more implants to form one or more implant regions (e.g., implant regions 132 and 134 of Figures 1A-1E and implant regions 232 and 234 of Figure 2A). Thus, block 307 may include implanting a dopant from a first side of the semiconductor substrate into one or more trenches and through each trench at a non-normal angle to form a first implant region (e.g., implant regions 132 and 232 in Figures 1A-2A) in the substrate region of the semiconductor substrate proximate to each of the trenches, and implanting a second dopant from the first side of the semiconductor substrate into the one or more trenches and through each trench at a second non-normal angle to form a second implant region (e.g., implant regions 134 and 234 in Figures 1A-2A) proximate to a sidewall of each trench of the semiconductor substrate. In some embodiments, the second non-normal angle is different from the non-normal angle. In one or more embodiments, a second dopant concentration in the second implant region is greater than the bulk dopant concentration of the semiconductor substrate but less than the first dopant concentration in the first implant region. In the same or other embodiments, the first dopant concentration in the first implant region is greater than the bulk dopant concentration of the semiconductor substrate. It should be understood that implanting the dopant and the second dopant can be achieved by ion implantation having a predetermined dose rate. In some embodiments, a dopant is implanted at a first dose rate to form a first implant region, and a second dopant is implanted at a second dose rate to form a second implant region. In the same or other embodiments, the first dose rate is one, two, or more orders of magnitude greater than the second dose rate. It should be understood that the first and second implant regions can provide an asymmetric doping profile around the sidewalls and bottom of a trench associated with one or more isolation structures (e.g., surrounded by, encapsulated by, or otherwise positioned proximate to such sidewalls and bottom) to provide advantages within the present invention (e.g., trap passivation proximate to a photodiode or floating diffusion to reduce white pixels and dark current without degrading RTS noise of the pixel transistor).

[0059] Block 309 illustrates filling one or more trenches with a trench fill material (e.g., a dielectric material) to form one or more isolation structures (e.g., isolation structures 130 and 230 illustrated in Figures 1A-2A) disposed within the semiconductor substrate and extending from a first side toward a second side. In some embodiments, at least one of the one or more isolation structures includes a first sidewall, a second sidewall, and a bottom surface coupled to the first sidewall and the second sidewall. In some embodiments, the first sidewall is opposite the second sidewall. However, in other embodiments, the first sidewall and the second sidewall may be coupled to each other or otherwise disposed adjacent to each other. In some embodiments, the first implant region is disposed between one or more of the photodiodes and the first sidewall.

[0060] Block 311 shows forming one or more gate electrodes (e.g., transfer gate electrode 115, source follower gate electrode 117, reset gate electrode 119, or other gate electrodes associated with a transistor included in an image sensor or as illustrated in FIG. 1A through FIG. 1E ) disposed proximate to a first side of a semiconductor substrate. In some embodiments, at least one of one or more isolation structures is at least partially disposed between one of the gate electrodes and a second side of the semiconductor substrate.

[0061] 4A-4D illustrate examples of angled implants for forming an isolation structure with an asymmetric passivation according to embodiments of the present invention. It should be understood that the angled implant examples illustrated in FIG4A-4D show non-limiting implementation details for forming implant regions (e.g., implant regions 132, 134, 232, 234) illustrated and / or discussed with respect to FIG1A-2B and / or the implant regions discussed in method 300 illustrated in FIG3. It should be understood that other orientations of ion implants may be utilized and that the exemplary embodiments are not exhaustive.

[0062] Figures 4A-4B illustrate an intermediate step in forming the example pixel 101 illustrated in Figure 1A and include a number of similarly labeled elements, such as the photodiode 110. Figures 4A and 4B illustrate trenches 430, trench 430-1, trench 430-2, and trench 430-3, which can subsequently be used to form the isolation structure 130 illustrated in Figure 1A according to the method 300 illustrated in Figure 3. Furthermore, it should be understood that not all elements are labeled (e.g., gate electrodes, floating diffusion regions, and the like) or illustrated because such elements may be formed after the implanted regions or may otherwise obscure certain features of the diagram. For example, it should be understood that in most embodiments, ion implantation of the implanted regions occurs before forming the gate electrodes and backfilling the trenches that will form the isolation structure 130 (e.g., see the method 300 illustrated in Figure 3). 4A-4B further illustrate a coordinate system 472, which shows an XY plane corresponding to the top view of pixel 100 illustrated in FIG1A and directions 401, 406, 408, 421, 422, and 424 illustrating the directionality of ion implantation used to form implanted regions having different implant doses and / or implant energies. It should be understood that the width of directions 401, 406, 408, 421, 422, and 424 indicates the implant dose. It should be understood that in most, if not all, embodiments, directions 401, 406, 408, 421, 422, and 424 are directed into the page at a non-normal angle (e.g., see FIG4C-4D).

[0063] Referring back to FIG. 4A , it can be seen that the ion implantation dose along direction 401 (e.g., to form the implanted regions 132 and 232 illustrated in FIG. 1A-2B ) is greater than the implantation dose along direction 421 (e.g., to form the implanted regions 134 and 234 illustrated in FIG. 1A-2B ). Furthermore, in the illustrated embodiment, the projections of directions 401 and 421 on the XY plane are parallel to each other but in opposite directions, with the projections being perpendicular to an edge 432 of the photodiode 110. It should be understood that the edge 432 of the photodiode 110 is the edge of the photodiode closest to one or more of the floating diffusion region 125 and / or the gate electrode (e.g., source-follower gate electrode 117) formed in subsequent steps, to provide the benefits of the asymmetric doping profile discussed herein. However, in other embodiments, the projections of directions 401 and 421 on the XY plane may not be parallel to the edge 432 of the photodiode 110. In the illustrated embodiment, the projections of directions 401 and 421 onto the XY plane also make an angle θ1 with respect to an edge 431 of trench 430-1, which is proximate to or otherwise desirably disposed below source-follower gate electrode 117. In some embodiments, θ1 is approximately 135 degrees relative to the X-axis, but it will be appreciated that θ1 can be other values ​​and depends at least in part on the misorientation between edge 432 of photodiode 110 and edge 431 of trench 430-1, both of which are selected to achieve the benefits of the asymmetric doping profile provided by the implanted region.

[0064] FIG4B illustrates additional or alternative implantation steps in which more than two ion implantation steps than those illustrated in FIG4A may be used to form implanted regions. Specifically, FIG4B shows that any number of ion implantation steps can be used to form an asymmetric doping profile and, therefore, the orientation of pixel components (e.g., photodiodes, gate electrodes, isolation structures, floating diffusion regions, and the like) is not restricted. As illustrated, FIG4B shows directions 406, 408, 422, and 424 that can be used to form one, two, or more implanted regions having different dopant concentrations based at least in part on implant angle, implant dose, and / or implant energy. As illustrated, the implant dose in directions 406 and 408 is greater than the implant dose in directions 422 and 424. In the illustrated embodiment, the projections of directions 406 and 422 onto the XY plane are parallel to each other but in opposite directions. Similarly, the projections of directions 408 and 424 onto the XY plane are parallel to each other but in opposite directions, and are also orthogonal to the projections of directions 406 and 422, respectively. It should be understood that the directionality, implantation dose, and implantation energy of directions 406, 408, 422, and 424 can be configured to implant through trench 430 to form the implanted regions illustrated in various embodiments of the present invention. In addition, it should be understood that more or fewer implantation steps than those explicitly illustrated can be utilized when forming the implanted regions.

[0065] FIG4C illustrates a side view 485 of an intermediate step illustrated in FIG4A , wherein ion implantation is directed through isolation structure 430 along direction 401, in accordance with an embodiment of the present invention. Specifically, side view 485 of FIG4C corresponds to a cross-section taken along the z-direction (i.e., along the XY projection of direction 401) of coordinate system 472 illustrated in FIG4A . As illustrated, implanting dopants at a non-normal angle θ2 relative to a normal axis 496 to the surface of first side 107 of semiconductor substrate 105 results in implanted region 432 contacting both first sidewall 430-S1 and bottom surface 430-B of trench 430 without contacting second sidewall 430-S2 of isolation structure 430, at least in part due to angle θ2 and a shielding effect of mask 492.

[0066] FIG4D illustrates a side view 490 of the intermediate step illustrated in FIG4A , wherein ion implantation is directed through isolation structure 430 along direction 421, in accordance with an embodiment of the present invention. Specifically, side view 490 of FIG4D corresponds to a cross-section taken along the z-direction (i.e., the XY projection along direction 421) of coordinate system 472 illustrated in FIG4A . As illustrated, implanting dopants at a non-normal angle θ3 relative to axis 496 normal to the surface of first side 107 of semiconductor substrate 105 results in implanted region 434 contacting both second sidewall 430-S2 and bottom surface 430-B of trench 430 without contacting first sidewall 430-S1 of isolation structure 430, at least in part due to angle θ3 and a shielding effect of mask 492. It should be understood that in some embodiments, θ2 and θ3 are relative to one another (e.g., if θ2 is -X degrees relative to the surface normal, θ3 is +X degrees relative to the surface normal).

[0067] FIG5 illustrates an exemplary imaging system 502 including an image sensor 500 having one or more isolation structures with asymmetric passivation, according to embodiments of the present invention. According to embodiments of the present invention, image sensor 500 may include a plurality of pixels, each corresponding to an example of pixel 101 illustrated in FIG1A-1E , as further described in FIG2A-2B . Imaging system 502 includes image sensor 500 that generates an electrical signal or image signal in response to incident radiation 570, an objective lens 565 having an adjustable optical power to focus on one or more points of interest within an external scene 503, and a controller 550 that controls, among other things, the operation of image sensor 500 and objective lens 565. Image sensor 500 shows a simplified schematic diagram of semiconductor material 501 having a plurality of photodiodes 505, a plurality of color filters 510, and a plurality of microlenses 515 disposed within respective portions of semiconductor material 501. The controller 550 includes one or more processors 552 , memory 554 , control circuitry 556 , readout circuitry 558 , and function logic 560 .

[0068] Controller 550 includes logic and / or circuitry to control the operation of various components of imaging system 502 (e.g., before, after, and during the in-situ phases of image and / or video acquisition). Controller 550 can be implemented as hardware logic (e.g., an application-specific integrated circuit, a field programmable gate array, a system-on-a-chip, etc.), software / firmware logic executed on a general-purpose microcontroller or microprocessor, or a combination of both hardware and software / firmware logic. In one embodiment, controller 550 includes a processor 552 coupled to a memory 554 that stores instructions executed by controller 550 and / or one or more other components of imaging system 502. When executed, the instructions may cause imaging system 502 to perform operations associated with various functional modules, logic blocks, or circuitry of imaging system 502, including any one or a combination of control circuitry 556, readout circuitry 558, function logic 560, image sensor 500, objective lens 565, and any other components of imaging system 502 (illustrated or otherwise). A memory system is a non-transitory computer-readable medium that may include, but is not limited to, a volatile (e.g., RAM) or non-volatile (e.g., ROM) storage system readable by controller 550. It should be further understood that controller 550 may be a monolithic integrated circuit, one or more discrete interconnected electrical components, or a combination thereof. Furthermore, in some embodiments, one or more electrical components may be coupled together to collectively function as controller 550 for orchestrating the operations of imaging system 502.

[0069] Control circuitry 556 can control the operating characteristics of photodiode array 505 (e.g., exposure duration, when to capture digital images or video, and the like). Readout circuitry 558 reads or otherwise samples analog signals from individual photodiodes (e.g., reading out the electrical signals generated by each of the plurality of photodiodes 505 in response to incident light to generate image signals used to capture an image frame, and the like) and may include amplification circuitry, analog-to-digital (ADC) circuitry, image buffers, or other components. In the illustrated embodiment, readout circuitry 558 is included in controller 550, but in other embodiments, readout circuitry 558 may be separate from controller 550. Function logic 560 is coupled to readout circuitry 558 to receive image data, de-mosaic the image data, and generate one or more image frames. In some embodiments, the electronic signals and / or image data may be manipulated or otherwise processed by function logic 560 (e.g., applying post-image effects such as cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or other).

[0070] For ease of description, spatially relative terms (such as "below," "beneath," "above," "beneath," "above," "upper," "top," "bottom," "left," "right," "center," "middle," and the like) may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or turned over, an element described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" encompass both orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. It should also be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or one or more intervening elements may also be present.

[0071] The procedures explained above can be implemented using software and / or hardware. The techniques described may constitute machine-executable instructions embodied in a tangible or non-transitory machine-readable (e.g., computer) storage medium. When executed by a machine (e.g., controller 550 in FIG. 5 ), the machine-executable instructions cause the machine to perform the described operations. Alternatively, the procedures may be embodied in hardware, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other.

[0072] A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible by a machine (e.g., a computer, a network device, a personal digital assistant, a manufacturing tool, any device with one or more processors, etc.). For example, a machine-readable storage medium includes recordable and non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0073] The above description of the illustrated examples of the present invention, including those described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention are described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the invention.

[0074] Such modifications may be made to the invention in light of the above detailed description. The terminology used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in this specification. Rather, the scope of the invention is to be determined entirely by the appended claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0075] 101:Pixels / Instance Pixels 101-AA': Cross-section 101-BB': Cross-section 101-CC': Cross-section 101-DD': Cross-section 105:Semiconductor substrate 107: First side 109: Second side 110: Photodiode 112: Pinning layer 115: transfer gate / transfer gate electrode 117: Source follower gate electrode 119: Gate electrode / reset gate electrode 125: floating diffusion part / floating diffusion area 127: Gate dielectric 129: Edge 130-1: Isolation Structure 130-1B: bottom surface 130-1S1: Side wall 130-1S2: Sidewall 130-1S3: Side wall 130-1S4: Side wall 130-1S5: Side wall 130-1S6: Side wall 130-2: Isolation Structure 130-2B: bottom surface 130-2S1: Side wall 130-2S2: Sidewall 130-3: Isolation Structure 130-3B: bottom surface 130-3S1: Side wall 130-3S2: Sidewall 130-3S3: Sidewall 132-1A: Implantation Area 132-1B: Implantation Area 132-1C: Implantation Area 132-1D: Implantation Area 132-2B: Implantation Area 132-3A: Implantation Area 132-3C: Implantation Area 134-1A: Implantation Area 134-1B: Implantation Area 134-1C: Implantation Area 134-1D: Implantation Area 134-2B: Implantation Area 134-3A: Implantation Area 134-3C: Implantation Area 135: Edge 136: Interface 137: Edge 230: Isolation Structure 230-B: bottom surface 230-S1: Side wall 230-S2: Sidewall 232: Implantation area 234: Implantation area 236: Interface 250: Chart 252: Level / Dopant Concentration 254: Level / Dopant Concentration 256: Level / Dopant Concentration 258: Level / Dopant Concentration 260: Local peak 262: Dashed Line 300: Method 301: Block 303: Block 305: Block 307: Block 309: Block 311: Block 401: Direction 406: Direction 408: Direction 421: Direction 422: Direction 424: Direction 430: Trench / Isolation Structure 430-1: Ditch 430-2: Ditch 430-3: Ditch 430-B: bottom surface 430-S1: First side wall 430-S2: Second side wall 431: Edge 432: Edge 434: Implantation area 472: Coordinate System 485: Side view 490: Side view 492:Mask 496: Normal axis 500: Image sensor 501:Semiconductor Materials 502: Imaging System / Exemplary Imaging System 503:External scene 505: Photodiode / Photodiode Array 510: Color filter 515: Microlens 550: Controller 552: Processor 554:Memory 556: Control circuit system 558: Readout circuit system 560: Functional Logic 565:Objective lens A-A': line B-B': line C-C': line D-D': line X: Position / Axis X-X': line X': Position X 1: Position X 2: Position X 3: Position X INT: Position θ 1: Angle θ 2: Angle / Non-normal angle θ 3: Angle

Claims

1. A pixel for an image sensor, the pixel comprising: A photodiode disposed within a semiconductor substrate between a first side and a second side of the semiconductor substrate, the second side being opposite to the first side; an isolation structure disposed within the semiconductor substrate and extending from the first side toward the second side, wherein the isolation structure includes a first sidewall, a second sidewall, and a bottom surface coupled to the first sidewall and the second sidewall; a gate electrode disposed close to the first side of the semiconductor substrate, wherein the isolation structure is at least partially disposed between the gate electrode and the second side of the semiconductor substrate; and a first implantation region of the semiconductor substrate disposed close to the first sidewall of the isolation structure, wherein the first implantation region is further disposed between the photodiode and the first sidewall, and wherein a first dopant concentration in the first implantation region is greater than the bulk dopant concentration in the semiconductor substrate.

2. The pixel of claim 1, wherein the first implantation region is further positioned close to the bottom surface of the isolation structure without contacting the second sidewall of the isolation structure, such that the bottom surface is positioned between the first implantation region and the first sidewall of the semiconductor substrate.

3. The pixel of claim 2, wherein a portion of the semiconductor substrate opposite to and close to the second sidewall has a conductivity type like that of the first implantation region and a specific dopant concentration corresponding to the bulk dopant concentration of the semiconductor substrate.

4. The pixel of claim 3, wherein the first dopant concentration is at least one order of magnitude greater than the individual dopant concentration of the portion of the semiconductor substrate, such that an asymmetric doping distribution exists around the isolation structure based on a doping concentration difference between the first dopant concentration and the bulk dopant concentration.

5. The pixel of claim 2 further includes a second implantation region of the semiconductor substrate adjacent to the second sidewall of the isolation structure, wherein the first implantation region is disposed between the photodiode and the second implantation region, and wherein the second dopant concentration of the second implantation region is greater than the bulk dopant concentration of the semiconductor substrate but less than the first dopant concentration of the first implantation region.

6. As in request 5, wherein the second implantation region contacts both the second sidewall and the bottom surface of the isolation structure without contacting the first sidewall of the isolation structure.

7. The pixel of claim 5, wherein the first dopant concentration is one or more orders of magnitude greater than the second dopant concentration, such that an asymmetric doping distribution exists around the isolation structure based on a doping concentration difference between the first dopant concentration and the second dopant concentration.

8. The pixel of claim 1, wherein the first implantation region is at least partially disposed between the gate electrode and the second side of the semiconductor substrate.

9. The pixel of claim 8 further includes a second implantation region of the semiconductor substrate adjacent to one of the second sidewalls of the isolation structure, wherein the first implantation region is further disposed between the photodiode and the second implantation region, wherein the isolation structure is further disposed between one edge of the gate electrode and the second side of the semiconductor substrate, such that the gate electrode does not extend over at least a portion of the second implantation region.

10. The pixel of claim 9, wherein the first implanted region contacts both the first sidewall and the bottom surface of the isolation structure but not the second sidewall of the isolation structure, wherein the second implanted region contacts both the second sidewall and the bottom surface of the isolation structure but not the first sidewall of the isolation structure, and wherein the second dopant concentration of one of the second implanted regions is greater than the bulk dopant concentration of the semiconductor substrate but less than the first dopant concentration of one of the first implanted regions.

11. The pixel of claim 1 further includes a second gate electrode disposed close to the first side of the semiconductor substrate, wherein the second sidewall of the isolation structure is disposed between the second gate electrode and the second side of the semiconductor substrate.

12. The pixel of claim 11, wherein the gate electrode corresponds to a transmission gate electrode of a transmission transistor that couples the photodiode to a floating diffusion portion disposed in the semiconductor substrate, and wherein the second gate electrode corresponds to a reset gate electrode of a reset transistor or a source follower gate electrode of a source follower transistor.

13. The pixel of claim 11, wherein the first implantation region contacts both the first sidewall and the bottom surface of the isolation structure but not the second sidewall of the isolation structure, and wherein a portion of the semiconductor substrate opposite to the first implantation region and in contact with the second sidewall has a respective dopant concentration corresponding to the bulk dopant concentration of the semiconductor substrate.

14. The pixel of claim 11 further includes a second implantation region of the semiconductor substrate disposed close to the second sidewall of the isolation structure, wherein the first implantation region is disposed between the photodiode and the second implantation region, wherein the second dopant concentration of the second implantation region is greater than the bulk dopant concentration of the semiconductor substrate but less than the first dopant concentration of the first implantation region, and wherein the second implantation region is disposed between the second gate electrode and the second sidewall of the semiconductor substrate.

15. The pixel of claim 11 further includes a second isolation structure disposed within the semiconductor substrate and extending from the first side toward the second side, wherein the isolation structure is disposed between the photodiode and the second isolation structure, wherein the second sidewall of the isolation structure is disposed between a third sidewall of the second isolation structure and the first implantation region, and wherein the third sidewall is disposed between the second gate electrode and the second side of the semiconductor substrate.

16. The pixel of claim 15 further includes a second implantation region of the semiconductor substrate disposed between the second gate electrode and the second side of the semiconductor substrate, wherein the second implantation region contacts the second sidewall of the isolation structure or the third sidewall of the second isolation structure, and wherein a second dopant concentration in one of the second implantation regions is greater than the bulk dopant concentration of the semiconductor substrate but less than the first dopant concentration in the first implantation region.

17. The pixel of claim 1, wherein the gate electrode corresponds to a transfer gate electrode of a transfer transistor that couples the photodiode to a floating diffusion portion disposed in the semiconductor substrate, a reset gate electrode of a reset transistor, or a source follower gate electrode of a source follower transistor that operates to read image charge from the photodiode.

18. A method for forming a pixel of an image sensor, the method comprising: A photodiode is formed within a semiconductor substrate, located between a first side and a second side of the semiconductor substrate, wherein the first side and the second side are opposite to each other. A trench is formed in the semiconductor substrate, the trench extending from the first side toward the second side; a dopant is implanted from the first side of the semiconductor substrate into the trench at an illegal angle to form a first implantation region of the semiconductor substrate adjacent to the trench; and the trench is filled to form an isolation structure disposed in the semiconductor substrate and extending from the first side toward the second side, the isolation structure including a first sidewall, a second sidewall, and a bottom surface coupled to the first sidewall and the second sidewall, wherein the first implantation region is disposed between the photodiode and the first sidewall, and wherein the concentration of a first dopant in the first implantation region is greater than the concentration of a bulk dopant in the semiconductor substrate.

19. The method of claim 18, wherein the illegal orientation angle of implanting the dopants causes the first implantation region to contact both the first sidewall and the bottom surface of the isolation structure without contacting the second sidewall of the isolation structure.

20. The method of claim 19, further comprising implanting a second dopant from the first side of the semiconductor substrate into the trench at a second non-directional angle to form a second implantation region of the semiconductor substrate, wherein the second non-directional angle is different from the non-directional angle, and wherein implanting the second dopant causes the second implantation region to contact both the second sidewall and the bottom surface of the isolation structure without contacting the first sidewall of the isolation structure, and wherein the concentration of the second dopant in the second implantation region is greater than the bulk dopant concentration of the semiconductor substrate but less than the first dopant concentration in the first implantation region.

21. The method of claim 20, wherein implanting the dopants to form the first implantation region occurs at a first dose rate, and implanting the second dopants to form the second implantation region occurs at a second dose rate, wherein the first dose rate is at least an order of magnitude greater than the second dose rate.

22. The method of claim 18, further comprising forming a gate electrode disposed close to the first side of the semiconductor substrate, wherein the isolation structure is at least partially disposed between the gate electrode and the second side of the semiconductor substrate.

23. A pixel for an image sensor, the pixel comprising: A photodiode disposed within a semiconductor substrate between a first side and a second side of the semiconductor substrate, the second side being opposite to the first side; an isolation structure disposed within the semiconductor substrate and extending from the first side toward the second side, wherein the isolation structure includes a first sidewall, a second sidewall, and a bottom surface coupled to the first sidewall and the second sidewall; a gate electrode disposed close to the first side of the semiconductor substrate, wherein the isolation structure is at least partially disposed between the gate electrode and the second side of the semiconductor substrate; a first implantation region of the semiconductor substrate disposed between the photodiode and the first sidewall; a second implantation region disposed close to the second sidewall, wherein a first dopant concentration in the first implantation region is greater than a second dopant concentration in the second implantation region.

24. The pixel of claim 23, wherein the first implantation region is disposed between the gate electrode and the second side of the semiconductor substrate, or the second implantation region is disposed between the gate electrode and the second side of the semiconductor substrate.

25. The pixel of claim 23, wherein the bottom surface of the isolation structure is disposed between the first side of the semiconductor substrate and at least one of the first implantation region or the second implantation region.

26. The pixel of claim 23 further includes a second gate electrode disposed close to the first side of the semiconductor substrate, wherein the second sidewall of the isolation structure is disposed between the second gate electrode and the second side of the semiconductor substrate, wherein the first implantation region is disposed between the gate electrode and the second side of the semiconductor substrate, and wherein the second implantation region is disposed between the second gate electrode and the second side of the semiconductor substrate.

Images