Semiconductor device

Abstract

A semiconductor device includes: a substrate; a bit line extending on the substrate in a first direction; a first active pattern and a second active pattern located on the bit line; a back gate electrode located between the first active pattern and the second active pattern and extending across the bit line in a second direction perpendicular to the first direction; a first word line extending in the second direction on one side of the first active pattern; a second word line extending in the second direction on the other side of the second active pattern; and a contact pattern connected to each of the first active pattern and the second active pattern, wherein the contact pattern sequentially includes an epitaxial growth layer, a doped polycrystalline silicon layer, and a silicide layer.

Description

Semiconductor Device [Cross - reference to Related Applications] This application is based on and claims priority to Korean Patent Application No. 10 - 2022 - 0106351, filed with the Korean Intellectual Property Office on August 24, 2022, the disclosure of which is incorporated herein by reference in its entirety. The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical - channel transistor. To meet excellent performance and economic feasibility, it is necessary to increase the integration degree of semiconductor devices. Specifically, the integration degree of memory devices is an important factor determining the economic feasibility of products. The integration degree of two - dimensional memory devices is mainly determined by the area occupied by a unit memory cell, and thus depends to a large extent on the level of fine - pattern formation technology. However, expensive equipment is required to form fine patterns, and the area of a chip die is limited. Therefore, although the integration degree of two - dimensional memory devices has been continuously increasing, it is still limited. The present inventive concept provides a semiconductor device including a vertical - channel transistor with improved integration degree and electrical characteristics. The problems to be solved by the technical idea of the present inventive concept are not limited to the above - mentioned problems, and those of ordinary skill in the art can clearly understand other unmentioned problems from the following description. According to one aspect of the present inventive concept, a semiconductor device includes: a substrate; a first bit line extending in a first direction on the substrate; a first active pattern and a second active pattern located on the first bit line; a back - gate electrode located between the first active pattern and the second active pattern and extending across the first bit line in a second direction perpendicular to the first direction; a first word line extending in the second direction, wherein the first active pattern is disposed between the first word line and the back - gate electrode; a second word line extending in the second direction, wherein the second active pattern is disposed between the second word line and the back - gate electrode; and a contact pattern connected to each of the first active pattern and the second active pattern. The contact pattern includes an epitaxial growth layer, a doped polysilicon layer, and a silicide layer stacked on top of each other in a vertical direction perpendicular to the upper surface of the substrate. According to another aspect of the inventive concept, a semiconductor device includes: a substrate; bit lines extending in a first direction on the substrate; a first active pattern and a second active pattern located on the bit lines; a back gate electrode located between the first active pattern and the second active pattern and extending across the bit lines in a second direction perpendicular to the first direction; a first word line extending in the second direction at a first side of the first active pattern; a second word line extending in the second direction at a second side of the second active pattern; and contact patterns connected to each of the first active pattern and the second active pattern. The contact patterns include an undoped epitaxial growth layer, a doped epitaxial growth layer, and a silicide layer stacked on top of each other in a vertical direction perpendicular to the upper surface of the substrate. According to another aspect of the inventive concept, a semiconductor device includes: a substrate; a first bit line extending in a first direction on the substrate; a second bit line adjacent to the first bit line; a spacer structure disposed in a space between the first bit line and the second bit line and extending in the first direction; a first active pattern and a second active pattern arranged alternately in the first direction on the first bit line; a back gate electrode located between the first active pattern and the second active pattern and extending across the first bit line in a second direction perpendicular to the first direction; a first word line adjacent to the first active pattern and extending in the second direction; a second word line adjacent to the second active pattern and extending in the second direction; a gate insulating pattern located between the first active pattern and the second active pattern and the first word line and the second word line; a back gate insulating pattern located between the back gate electrode and each of the first active pattern and the second active pattern; contact patterns connected to each of the first active pattern and the second active pattern; a landing pad located on the contact patterns; and a data storage pattern connected to the landing pad. The contact patterns include: an undoped epitaxial growth layer; a doped epitaxial growth layer located on the undoped epitaxial growth layer and having a gradually increasing doping concentration; a doped polysilicon layer disposed on the doped epitaxial growth layer and doped at a concentration higher than that of the doped epitaxial growth layer; and a metal silicide layer located on the doped polysilicon layer. Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. FIG. 1 is a perspective view showing a part of a semiconductor device 10 according to an embodiment, FIG. 2 is a layout showing the semiconductor device 10 according to an embodiment, FIG. 3 shows cross-sectional views of the semiconductor device 10 shown in FIG. 2 taken along lines A-A' and B-B', and FIG. 4 is an enlarged cross-sectional view of part IV of the semiconductor device 10 shown in FIG. 3. However, for ease of explanation, FIG. 1 only shows some components included in the semiconductor device 10. Referring to FIGS. 1 to 4, the semiconductor device 10 according to an embodiment may include memory cells, each of which includes a vertical-channel transistor (VCT) and a capacitor. The bit lines BL may be spaced apart from each other in a first direction D1 on the substrate 200. The bit lines BL may be spaced apart from each other in the first direction D1 and extend in a second direction D2 intersecting the first direction D1. The first direction D1 and the second direction D2 may be parallel to the upper surface of the substrate 200. The substrate 200 may include a material having semiconductor characteristics (e.g., silicon (Si) or germanium (Ge)), an insulating material (e.g., glass or quartz), or a semiconductor or conductor covered with an insulating material or may be formed of a material having semiconductor characteristics (e.g., silicon (Si) or germanium (Ge)), an insulating material (e.g., glass or quartz), or a semiconductor or conductor covered with an insulating material. Each of the bit lines BL may include a polysilicon pattern 161P, a metal pattern 163P, and a hard mask pattern 165P stacked in sequence. Herein, the hard mask pattern 165P in each of the bit lines BL may be in contact with the substrate 200. The metal pattern 163P may include a conductive metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) or a metal (e.g., tungsten (W), titanium (Ti), or tantalum (Ta)) or may be formed of a conductive metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) or a metal (e.g., tungsten (W), titanium (Ti), or tantalum (Ta)). Alternatively, the metal pattern 163P may include a metal silicide (e.g., titanium silicide (TiSi), cobalt silicide (CoSi), and nickel silicide (NiSi)) or may be formed of a metal silicide (e.g., titanium silicide (TiSi), cobalt silicide (CoSi), and nickel silicide (NiSi)). The hard mask pattern 165P may include an insulating material (e.g., silicon nitride and silicon oxynitride) or may be formed of an insulating material (e.g., silicon nitride and silicon oxynitride). Unless otherwise indicated in the context, the term "contact" as used herein refers to a direct connection (i.e., touching). In some embodiments, the semiconductor device 10 may include a gap structure 173 located between the bit lines BL. Each of the gap structures 173 may be surrounded by line insulating layers 171 and 175. The gap structures 173 may extend parallel to each other in the second direction D2. The gap structures 173 may be disposed between the line insulating layer 171 and the line insulating layer 175, and the upper surface of the gap structure 173 may be positioned at a level lower than the upper surface of the bit line BL. In some embodiments, the gap structure 173 may comprise a conductive material and include an air gap or void within the gap structure 173. In other embodiments, the air gap may be surrounded by the gap structure 173 and the line insulating layers 171 and 175. The gap structure 173 may reduce the coupling noise between adjacent bit lines BL. For example, the gap structure 173 may include a shield line made of a conductive material. The phrase "air gap" will be understood to include a gap formed by air (e.g., a pocket) or a gap (e.g., a pocket) formed by a gas other than air (e.g., other atmospheric gases and chamber gases that may be present during manufacturing). An "air gap" may also constitute a space that does not have or substantially does not have gas or other materials therein. The first active pattern AP1 and the second active pattern AP2 may be alternately located on each of the bit lines BL in the second direction D2. Each of the first active patterns AP1 may be spaced apart from each other by a specific distance in the first direction D1, and each of the second active patterns AP2 may be spaced apart from each other by a specific distance in the first direction D1. In other words, the first active pattern AP1 and the second active pattern AP2 may be arranged two-dimensionally in the first direction D1 and the second direction D2 that intersect each other. In some embodiments, the first active pattern AP1 and the second active pattern AP2 may comprise or be formed of a single-crystalline semiconductor material. For example, the first active pattern AP1 and the second active pattern AP2 may comprise or be formed of single-crystalline Si. Each of the first active pattern AP1 and the second active pattern AP2 may have a length in the first direction D1, a width in the second direction D2, and a height in a third direction D3 perpendicular to the upper surface of the substrate 200. Each of the first active pattern AP1 and the second active pattern AP2 may have a substantially uniform width. That is, each of the first active pattern AP1 and the second active pattern AP2 may have substantially the same width on the first surface S1 and the second surface S2. Terms such as "same", "equal", "planar", "uniform", or "coplanar" as used herein encompass approximate sameness, including variations that may occur, for example, due to the manufacturing process. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. Each of the first active pattern AP1 and the second active pattern AP2 may have a first surface S1 and a second surface S2 facing each other in a direction perpendicular to the first direction D1 and the second direction D2. For example, the first surface S1 of the first active pattern AP1 and the first surface S1 of the second active pattern AP2 may be in contact with the polysilicon pattern 161P of the bit line BL or may be in contact with the metal pattern 163P when the polysilicon pattern 161P is omitted. Each of the first active pattern AP1 and the second active pattern AP2 may have a first side surface SS1 and a second side surface SS2 facing each other in the second direction D2. The first side surface SS1 of the first active pattern AP1 may be adjacent to the first word line WL1, and the second side surface SS2 of the second active pattern AP2 may be adjacent to the second word line WL2. Each of the first active pattern AP1 and the second active pattern AP2 may include a first dopant region SDR1 adjacent to the bit line BL, a second dopant region SDR2 adjacent to the contact pattern BC, and a channel region CHR located between the first dopant region SDR1 and the second dopant region SDR2. The first dopant region SDR1 and the second dopant region SDR2 are regions doped with dopants in each of the first active pattern AP1 and the second active pattern AP2, and the dopant concentration in the first dopant region SDR1 and the second dopant region SDR2 may be greater than the dopant concentration in the channel region CHR. For example, the first dopant region SDR1 may be referred to as a source region, and the second dopant region SDR2 may be referred to as a drain region. When the semiconductor device 10 operates, the channel regions CHR of the first active pattern AP1 and the second active pattern AP2 may be controlled by the first word line WL1, the second word line WL2, and the back gate electrode BG. Since the first active pattern AP1 and the second active pattern AP2 include or are formed of a single crystal semiconductor material, the leakage current characteristics may be improved when the semiconductor device 10 operates. Each of the back gate electrodes BG may be spaced apart from each other by a specific distance in the second direction D2 on the bit line BL. The back gate electrode BG may extend across the bit line BL and extend in the first direction D1. Each of the back gate electrodes BG may be located between the first active pattern AP1 and the second active pattern AP2 adjacent to each other in the second direction D2. In other words, the first active pattern AP1 may be located at one side of each of the back gate electrodes BG, and the second active pattern AP2 may be located at the other side of each of the back gate electrodes BG. In the third direction D3, the back gate electrode BG may have a height smaller than that of the first active pattern AP1 and the second active pattern AP2. The back gate electrode BG may include, for example, doped polycrystalline silicon, a conductive metal nitride (e.g., TiN or TaN), a metal (e.g., W, Ti, or Ta), a conductive metal silicide, a conductive metal oxide, or a combination thereof, or may be formed of, for example, doped polycrystalline silicon, a conductive metal nitride (e.g., TiN or TaN), a metal (e.g., W, Ti, or Ta), a conductive metal silicide, a conductive metal oxide, or a combination thereof. When the semiconductor device 10 operates, a negative voltage may be applied to the back gate electrode BG, thereby increasing the threshold voltage of the VCT. That is, deterioration of leakage current characteristics due to a decrease in the threshold voltage according to miniaturization of the VCT can be prevented. A first insulating pattern 111 may be provided between the first active pattern AP1 and the second active pattern AP2 adjacent to each other in the second direction D2. The first insulating pattern 111 may be located between the second dopant regions SDR2 of the first active pattern AP1 and the second active pattern AP2. The first insulating pattern 111 may extend parallel to the back gate electrode BG in the first direction D1. The distance between the second surface S2 of each of the first active pattern AP1 and the second active pattern AP2 and the back gate electrode BG may vary depending on the thickness of the first insulating pattern 111. The first insulating pattern 111 may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, or may be formed of, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. A back gate insulating pattern 113 may be provided between each back gate electrode BG and the first active pattern AP1 and the second active pattern AP2, and between the back gate electrode BG and the first insulating pattern 111. The back gate insulating pattern 113 may include a vertical portion covering opposite side surfaces of the back gate electrode BG and a horizontal portion connecting the vertical portions. The horizontal portion of the back gate insulating pattern 113 may be closer to the contact pattern BC than the bit line BL and cover the top surface of the back gate electrode BG. The back gate insulating pattern 113 may include, for example, a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer, or a combination thereof, or may be formed of, for example, a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer, or a combination thereof. A back gate capping pattern 115 may be provided between the bit line BL and the back gate electrode BG. The back gate capping pattern 115 may include or be formed of an insulating material, and the lower surface of the back gate capping pattern 115 may contact the polysilicon pattern 161P of each of the bit lines BL. The back gate capping pattern 115 may be located between the vertical portions of the back gate insulating pattern 113. The thickness of the back gate capping pattern 115 located between the bit lines BL may be different from the thickness of the back gate capping pattern 115 located on the bit lines BL. The first word line WL1 and the second word line WL2 may extend on the bit line BL in a first direction D1 and may be alternately arranged in a second direction D2. The first word line WL1 may be located at one side of the first active pattern AP1, and the second word line WL2 may be located at the other side of the second active pattern AP2. The first word line WL1 and the second word line WL2 may be spaced apart from the bit line BL and the contact pattern BC in a vertical direction. In other words, in a front view, the first word line WL1 and the second word line WL2 may be located between the bit line BL and the contact pattern BC. The first word line WL1 and the second word line WL2 may have a width in the second direction D2, and the width of each of the first word line WL1 and the second word line WL2 located on the bit line BL may be different from the width of each of the first word line WL1 and the second word line WL2 located on the gap structure 173. Some portions of the first word line WL1 may be respectively located between the first active patterns AP1 adjacent to each other in the first direction D1, and some portions of the second word line WL2 may be respectively located between the second active patterns AP2 adjacent to each other in the first direction D1. The first word line WL1 and the second word line WL2 may include or be formed of, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The first word line WL1 and the second word line WL2 adjacent to each other may have corresponding sidewalls facing each other. In a third direction D3, the first word line WL1 and the second word line WL2 may have a height smaller than that of the first active pattern AP1 and the second active pattern AP2. In the third direction D3, the height of the first word line WL1 and the second word line WL2 may be less than or equal to the height of the back gate electrode BG. Gate insulating patterns GOX may be respectively provided between the first word line WL1 and the second word line WL2 and the first active pattern AP1 and the second active pattern AP2. The gate insulating patterns GOX may extend in parallel with the first word line WL1 and the second word line WL2 in the first direction D1. The gate insulating pattern GOX may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer, or a combination thereof. The high-k dielectric layer may include a metal oxide or a metal oxynitride. For example, the high-k dielectric layer that can be used for the gate insulating pattern GOX may include hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), or a combination thereof, but is not limited thereto. The gate insulating pattern GOX may cover the first side surface of the first active pattern AP1 and the second side surface of the second active pattern AP2. The gate insulating pattern GOX may have a substantially uniform thickness. Each of the gate insulating patterns GOX may include a vertical portion VP adjacent to each of the first active pattern AP1 and the second active pattern AP2 and a horizontal portion HP protruding from the vertical portion VP in the first direction D1. A second insulating pattern 143 may be provided between each of the horizontal portions HP of the gate insulating pattern GOX and the contact pattern BC. For example, the second insulating pattern 143 may include silicon oxide or may be formed of silicon oxide. A first etch stop layer 131 and a second etch stop layer 141 may be provided between the second insulating pattern 143 and each of the second dopant regions SDR2 of the first active pattern AP1 and the second active pattern AP2. On the gate insulating pattern GOX, the first word line WL1 and the second word line WL2 may be separated from each other by a third insulating pattern 155P. The third insulating pattern 155P may extend in the first direction D1 between the first word line WL1 and the second word line WL2. A first capping layer 153 may be provided between the third insulating pattern 155P and each of the first word line WL1 and the second word line WL2. The first capping layer 153 may have a substantially uniform thickness. The contact pattern BC can penetrate through the interlayer insulating layer 231 and the etching stop layer 210 and can be respectively connected to the first active pattern AP1 and the second active pattern AP2. In other words, the contact pattern BC can be respectively connected to the second dopant region SDR2 of the first active pattern AP1 and the second dopant region SDR2 of the second active pattern AP2. In the contact pattern BC, the lower width can be greater than the upper width. Adjacent contact patterns BC can be separated from each other by the isolation insulating pattern 255. In a top view, each of the contact patterns BC can have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, and a hexagonal shape. In the semiconductor device 10 according to the present embodiment, each of the contact patterns BC can have a stacked structure sequentially including an epitaxial growth layer 241, a doped polysilicon layer 243, and a silicide layer 245. The epitaxial growth layer 241 can be in contact with a corresponding one of the first active pattern AP1 and the second active pattern AP2. The epitaxial growth layer 241 can have a doping concentration DC that gradually changes in a third direction D3 perpendicular to the upper surface of the substrate 200. Specifically, the doping concentration DC inside the epitaxial growth layer 241 can gradually decrease as it moves away from the doped polysilicon layer 243. In other words, the doping concentration DC inside the epitaxial growth layer 241 can gradually increase as it moves away from the substrate 200. Additionally, the lower region of the epitaxial growth layer 241 in contact with each of the first active pattern AP1 and the second active pattern AP2 can be formed as an undoped underlap section. Due to the doping scheme of the epitaxial growth layer 241 to be described below, the dopant contained in the epitaxial growth layer 241 can be a dopant that moves from the doped polysilicon layer 243 by a thermal diffusion method. That is, the type of dopant in the epitaxial growth layer 241 can be the same as the type of dopant in the doped polysilicon layer 243. The dopant can be an n-type dopant (e.g., phosphorus or arsenic), but is not limited thereto. Additionally, the doping concentration DC of the epitaxial growth layer 241 can be about 3×10 20 / cm³, can gradually decrease, and can be about 2.5×10 19 / cm³. However, the doping concentration DC of the epitaxial growth layer 241 is not limited to the above values. For example, terms such as "about" or "approximately" can reflect quantities, sizes, orientations, or layouts that change only in a relatively small manner and / or in a manner that does not significantly change the operation, function, or structure of certain components. For example, a range from "about 0.1 to about 1" can encompass ranges such as a 0% to 5% deviation around 0.1 and a 0% to 5% deviation around 1, especially when such deviations maintain the same effect as the listed range. In addition, the epitaxial growth layer 241 can include a single-crystal Si epitaxial growth layer or a SiGe epitaxial growth layer or can be formed by a single-crystal Si epitaxial growth layer or a SiGe epitaxial growth layer, but is not limited thereto. The doped polysilicon layer 243 can be provided by forming polysilicon doped with a high concentration of an n-type dopant or a p-type dopant on the epitaxial growth layer 241. The doping concentration of the dopant in the doped polysilicon layer 243 can be high enough such that some of the dopants contained in the doped polysilicon layer 243 move to the epitaxial growth layer 241 and dope the epitaxial growth layer 241. The silicide layer 245 can include a metal silicide (e.g., CoSi, NiSi, or TiSi) or can be formed by a metal silicide (e.g., CoSi, NiSi, or TiSi). The silicide layer 245 can be formed by reacting a metal layer with the doped polysilicon layer 243 to form the silicide layer 245 and then removing the unreacted remainder of the metal layer. By performing an annealing process, some of the high-concentration dopants contained in the doped polysilicon layer 243 can move to the epitaxial growth layer 241 by a thermal diffusion method. Thus, the epitaxial growth layer 241 can have a doping concentration DC that gradually decreases as it moves away from the junction interface with the doped polysilicon layer 243. Thus, the epitaxial growth layer 241 can be formed to have a specific junction depth, which corresponds to the distance between the junction interface and the upper surface of the epitaxial growth layer 241. In some embodiments, the junction depth of the epitaxial growth layer 241 can be the maximum distance between the junction interface and the upper surface of the epitaxial growth layer 124. Lap pads LP can be respectively provided on the contact pattern BC. Specifically, each of the lap pads LP can be arranged to contact the silicide layer 245. In a top view, each of the lap pads LP can have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a rhombus shape, and a hexagonal shape. The isolation and insulation pattern 255 can be located between each of the bonding pads LP respectively. In a top view, each of the bonding pads LP can be arranged in a matrix form in a first direction D1 and a second direction D2. The upper surface of the bonding pad LP can be substantially coplanar with the upper surface of the isolation and insulation pattern 255. The bonding pad LP can comprise or be formed of the following materials: doped polysilicon, aluminum (Al), copper (Cu), Ti, Ta, ruthenium (Ru), W, molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), TiN, TaN, tungsten nitride (WN), niobium nitride (NbN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), TiSi, titanium silicon nitride (TiSiN), TaSi, tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), NiSi, CoSi, iridium oxide (IrO), ruthenium oxide (RuO), or a combination thereof, but not limited thereto. Data storage patterns DSP can be respectively provided on the bonding pads LP. The data storage patterns DSP can be electrically connected to the first active pattern AP1 and the second active pattern AP2 respectively. The data storage patterns DSP can be arranged in a matrix form in the first direction D1 and the second direction D2. The data storage patterns DSP can completely overlap or partially overlap the bonding pads LP respectively. The data storage patterns DSP can completely contact or partially contact the upper surface of the bonding pads LP respectively. In some embodiments, each of the data storage patterns DSP can be a capacitor and include a storage electrode 261, a plate electrode 265, and a capacitor dielectric layer 263 located between the storage electrode 261 and the plate electrode 265. In such a case, the storage electrode 261 can contact the bonding pad LP. In a top view, the storage electrode 261 can have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a rhombus shape, and a hexagonal shape. As another alternative, each of the data storage patterns DSP can be a variable resistance pattern, and the variable resistance pattern can be switched to two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP can comprise or be formed of a phase change material (such as a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, and an antiferromagnetic material) whose crystal structure changes according to the current amount. The present invention is not limited thereto. An upper insulating layer 270 can be provided on the data storage pattern DSP, and the unit contact plug PLG can be connected to the plate electrode 265 by passing through the upper insulating layer 270. Although not shown, peripheral circuit transistors may be provided in the peripheral circuit region of the substrate 200. In the peripheral circuit region, the active layer may include the same single-crystalline semiconductor material as the first active pattern AP1 and the second active pattern AP2 or may be formed of the same single-crystalline semiconductor material as the first active pattern AP1 and the second active pattern AP2. The active layer may have a first surface in contact with the substrate 200 and a second surface opposite to the first surface. The first surface of the active layer may be substantially coplanar with the first surface S1 of the first active pattern AP1 and the first surface S1 of the second active pattern AP2. The peripheral circuit transistors may be located on the second surface of the active layer. That is, a peripheral gate insulating layer may be provided on the second surface of the active layer, and a peripheral gate electrode may be provided on the peripheral gate insulating layer. The peripheral gate electrode may include a peripheral conductive pattern, a peripheral metal pattern, and a peripheral capping pattern. The semiconductor device 10 according to the technical idea of the inventive concept includes a stacked structure in a structure including a VCT. The stacked structure includes an epitaxially grown doped layer 241 in each of the contact patterns BC that electrically connect the first active pattern AP1 and the second active pattern AP2 to the data storage pattern DSP. Thereby, a specific junction depth between the first active pattern AP1 and the second active pattern AP2 and the contact pattern BC can be ensured. In addition, an undoped underlap section may be provided in the lower region of the epitaxially grown layer 241, thereby reducing gate induced drain leakage (GIDL). Finally, the semiconductor device 10 according to the technical idea of the inventive concept has the effect of improving integration and electrical characteristics. FIGS. 5 and 6 are cross-sectional views showing semiconductor devices 20 and 30 according to other embodiments. Most of the components constituting the semiconductor devices 20 and 30 to be described below and the materials forming these components are substantially the same as or similar to the components and materials described with reference to FIGS. 1 to 4. Therefore, differences from the above-described semiconductor device 10 will be mainly described for convenience of explanation. Referring to FIG. 5, the semiconductor device 20 according to an embodiment may include memory cells, each of which includes a VCT. In the semiconductor device 20 according to the present embodiment, each of the contact patterns BC2 may sequentially include an epitaxially grown layer 341 and a silicide layer 345. The epitaxial growth layer 341 can be in contact with each of the first active pattern AP1 and the second active pattern AP2 and is formed such that the doping concentration DC gradually changes in the third direction D3. Specifically, the doping concentration DC inside the epitaxial growth layer 341 can be adjusted by a gas phase doping (GPD) process or a plasma assisted doping (PLAD) process. The doping process for the epitaxial growth layer 341 can be performed in-situ during a selective epitaxial growth (SEG) process. That is, a self-aligned junction can be formed between the first active pattern AP1 and the second active pattern AP2 and the contact pattern BC2 by a GPD process or a PLAD process, and the self-aligned junction can determine a specific junction depth. The silicide layer 345 can include a metal silicide (e.g., CoSi, NiSi, or TiSi) or can be formed of a metal silicide (e.g., CoSi, NiSi, or TiSi). The silicide layer 345 can be formed by reacting a metal layer with the doped epitaxial growth layer 341 to form the silicide layer 345 and then removing the unreacted remainder of the metal layer. Referring to FIG. 6, the semiconductor device 30 according to an embodiment can include memory cells, each of which includes a VCT. In the semiconductor device 30 according to the present embodiment, each of the contact patterns BC3 can sequentially include an epitaxial growth layer 441, a doped polysilicon layer 443, and a silicide layer 445. The epitaxial growth layer 441 can be in contact with each of the first active pattern AP1 and the second active pattern AP2. The epitaxial growth layer 441 can have a doping concentration DC that gradually changes in the third direction D3. The epitaxial growth layer 441 can have a width W1 in the second direction D2. The doped polysilicon layer 443 can be provided by forming polysilicon doped with a high concentration of an n-type dopant or a p-type dopant on the epitaxial growth layer 441. The width W3 of the doped polysilicon layer 443 in the second direction D2 can be greater than the width W1 of the epitaxial growth layer 441. The silicide layer 445 can be formed by reacting a metal layer with the doped polysilicon layer 443 to form the silicide layer 445 and then removing the unreacted remainder of the metal layer. The width W5 of the silicide layer 445 in the second direction D2 can be greater than the width W3 of the doped polysilicon layer 443. That is, the contact pattern BC3 can have a tapered shape with a gradually decreasing width downward. FIGS. 7 to 30 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment in a process order. Specifically, each of FIGS. 7 to 30 shows a cross-section taken along lines A-A' and B-B' shown in FIG. 2. Referring to FIG. 7, a first substrate 100 including a buried insulating layer 101 and an active layer 110 may be prepared. The first substrate 100 may be a wafer including Si. Alternatively, the first substrate 100 may be a wafer including a semiconductor element (e.g., Ge) and a compound semiconductor. The compound semiconductor may include silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Additionally, the first substrate 100 may have a silicon on insulator (SOI) structure. The buried insulating layer 101 may include or may be formed of, for example, a buried oxide. Alternatively, the buried insulating layer 101 may be an insulating layer formed by chemical vapor deposition (CVD). The buried insulating layer 101 may include or may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant dielectric material. The active layer 110 may include or may be formed of a single crystal semiconductor material. The active layer 110 may have a first surface and a second surface opposite to each other. The second surface may be in contact with the buried insulating layer 101. A first mask pattern MP1 may be formed on the first surface of the active layer 110. The first mask pattern MP1 may have a linear opening portion extending in a first direction D1. The first mask pattern MP1 may include a buffer layer B10, a first mask layer M10, a second mask layer M20, and a third mask layer M30 stacked in sequence. Herein, the third mask layer M30 may include or may be formed of a material having an etching selectivity with respect to the second mask layer M20. The first mask layer M10 may include or may be formed of a material having an etching selectivity with respect to the buffer layer B10 and the second mask layer M20. In some embodiments, the buffer layer B10 and the second mask layer M20 may include or may be formed of silicon oxide, and the first mask layer M10 and the third mask layer M30 may include or may be formed of silicon nitride. Thereafter, the active layer 110 can be anisotropically etched by using the first mask pattern MP1 as an etching mask. Accordingly, a first trench T1 extending in the first direction D1 can be formed in the active layer 110. The first trench T1 can expose the buried insulating layer 101 passing through the first trench T1 and can be spaced apart from each other by a specific distance in the second direction D2. Referring to FIG. 8, first insulating patterns 111 that respectively fill the lower portions of the first trenches T1 can be formed. The first insulating patterns 111 can be formed by forming an insulating material to fill the first trenches T1 and then etching the insulating material. Each first insulating pattern 111 can expose a part of the sidewall of the corresponding first trench T1. After the first insulating patterns 111 are formed, a back gate insulating pattern 113 and a back gate electrode BG can be respectively formed inside the first trenches T1. Specifically, after the first insulating patterns 111 are formed, a gate insulating layer that conformally covers the inner walls of the first trenches T1 can be formed, and a gate conductive layer can be formed to fill the first trenches T1 on which the gate insulating layer is formed above. Thereafter, the back gate electrodes BG can be respectively formed inside the first trenches T1 by etching the gate conductive layer. The third mask layer M30 can be removed while the back gate electrodes BG are formed. In some embodiments, before the back gate insulating pattern 113 is formed, the active layer 110 exposed through the inner walls of the first trenches T1 can be doped with impurities by performing a GPD process or a PLAD process. Referring to FIG. 9, back gate cap patterns 115 can be respectively formed inside the first trenches T1 in which the back gate electrodes BG are formed. The back gate cap patterns 115 can be formed by forming an insulating layer to fill the first trenches T1 in which the back gate electrodes BG are formed and then planarizing the insulating layer to expose the upper surface of the first mask layer M10. When the back gate cap patterns 115 include the same material as the second mask layer M20 or are formed of the same material as the second mask layer M20, the second mask layer M20 can be removed by the planarization process for forming the back gate cap patterns 115. Before the back gate cap patterns 115 are formed, the active layer 110 can be doped with impurities through the first trenches T1 in which the back gate electrodes BG are formed by performing a GPD process or a PLAD process. After the back gate cap patterns 115 are formed, the first mask layer M10 can be removed so that the back gate cap patterns 115 protrude upward from the upper surface of the buffer layer B10. Thereafter, a spacer layer 120 may be formed to cover the upper surface of the buffer layer B10, the sidewalls of the back gate insulating patterns 113, and the upper surface of the back gate cap patterns 115 with a uniform thickness. The width of each of the active patterns of the VCT may be determined depending on the thickness of the spacer layer 120. The spacer layer 120 may comprise or may be formed of an insulating material. The spacer layer 120 may comprise, for example, silicon oxide, silicon oxynitride, silicon nitride, SiC, or a combination thereof, or may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride, SiC, or a combination thereof. Referring to FIG. 10, an anisotropic etching process may be performed on the spacer layer 120 to form a pair of spacers 121 on the sidewalls of each of the back gate insulating patterns 113. Thereafter, an anisotropic etching process may be performed on the active layer 110 by using the spacers 121 as an etching mask. Accordingly, a pair of preliminary active patterns PAP spaced apart from each other may be formed at opposite sides of each of the back gate insulating patterns 113. The buried insulating layer 101 may be exposed by forming the preliminary active patterns PAP. The preliminary active patterns PAP may have a linear shape extending parallel to the back gate electrode BG in a first direction D1, and a second trench T2 may be formed between the preliminary active patterns PAP adjacent to each other along a second direction D2. Referring to FIG. 11, a first etch stop layer 131 conformally covering the inner walls of the second trench T2 may be formed and a first sacrificial layer 133 filling the second trench T2 having the first etch stop layer 131 formed thereon may be formed. The first etch stop layer 131 may be formed of an insulating material (e.g., silicon oxide). The first sacrificial layer 133 may fill the second trench T2 and have a substantially flat upper surface. The first sacrificial layer 133 may be formed of an insulating material having an etching selectivity with respect to the first etch stop layer 131. In some embodiments, the first sacrificial layer 133 may include or may be formed of any one of a silicon oxide layer formed using a spin on glass (SOG) technique and an insulating material. Referring to FIG. 12, a second mask pattern MP2 may be formed on the first sacrificial layer 133. The second mask pattern MP2 may be formed of a material having an etching selectivity with respect to the first sacrificial layer 133 and have a linear shape extending in the second direction D2. In other embodiments, the second mask pattern MP2 may have a linear shape extending in a diagonal direction with respect to the first direction D1 and the second direction D2. Thereafter, the opening OP can be formed by etching the first sacrificial layer 133 and the first etch stop layer 131 in sequence using the second mask pattern MP2 as an etch mask, and some parts of the preliminary active pattern PAP are exposed through the opening OP. The opening OP can expose the upper surface of the buried insulating layer 101. During the etching process of the first sacrificial layer 133 and the first etch stop layer 131, the spacers 121 exposed through the second mask pattern MP2 can be removed. Referring to FIG. 13, the first active pattern AP1 and the second active pattern AP2 can be formed at opposite sides of the back gate insulating pattern 113 by anisotropically etching the preliminary active pattern PAP exposed through the opening OP (see FIG. 12). The first active pattern AP1 can be formed on the first sidewall of the back gate electrode BG and be spaced apart from each other in the first direction D1, and the second active pattern AP2 can be formed on the second sidewall of the back gate electrode BG and be spaced apart from each other in the first direction D1. In other embodiments, when the second mask pattern MP2 extends in the diagonal direction, the first active pattern AP1 and the second active pattern AP2 can be arranged to face each other in the diagonal direction. After forming the first active pattern AP1 and the second active pattern AP2, the second sacrificial layer 135 can fill the opening OP (see FIG. 12). The second sacrificial layer 135 can be formed of an insulating material having an etch selectivity relative to the first etch stop layer 131. In some embodiments, the second sacrificial layer 135 can be formed of the same material as the first sacrificial layer 133. After forming the second sacrificial layer 135, the second mask pattern MP2 can be removed and a planarization process can be performed on the first sacrificial layer 133 and the second sacrificial layer 135 to expose the upper surface of the back gate capping pattern 115. Referring to FIG. 14, the first sacrificial layer 133 and the second sacrificial layer 135 (see FIG. 13) can be removed, and the first etch stop layer 131 can be exposed between the first active pattern AP1 and the second active pattern AP2 facing each other along the second direction D2. Thereafter, the second etch stop layer 141 can be formed with a uniform thickness in the third trench T3 on which the first etch stop layer 131 is formed. Specifically, the second etch stop layer 141 can be formed on some parts of the first etch stop layer 131, some parts of the back gate insulating pattern 113, some parts of the back gate capping pattern 115, and some parts of the buried insulating layer 101. The second etch stop layer 141 can be formed of a material having an etch selectivity relative to the first etch stop layer 131. The second insulating pattern 143 can be formed to fill a part of the third trench T3 in which the second etch stop layer 141 is formed. The second insulating pattern 143 can be formed by using the SOG technique to form an insulating layer that fills the third trench T3 and then etching the insulating layer. The second insulating pattern 143 can include fluorinated silicate glass (FSG), SOG, tonen silazene (TOSZ), or similar materials or can be formed of FSG, SOG, TOSZ, or similar materials. The level of the upper surface of the second insulating pattern 143 can vary depending on the etching process. In some embodiments, the upper surface of the second insulating pattern 143 can be positioned at a level higher than the lower surface of the back gate electrode BG. As an alternative, the upper surface of the second insulating pattern 143 can be positioned at a level lower than the lower surface of the back gate electrode BG. Referring to FIG. 15, the first active pattern AP1 and the second active pattern AP2 can be exposed in the third trench T3 by etching the first etch stop layer 131 and the second etch stop layer 141 exposed by the second insulating pattern 143. Thereafter, a gate insulating layer 151 can be formed that conformally covers the sidewalls of the first active pattern AP1 and the second active pattern AP2, the upper surface of the back gate cap pattern 115, and the upper surface of the second insulating pattern 143. Any one of physical vapor deposition (PVD), thermal CVD, low pressure CVD, plasma enhanced CVD (PE-CVD), and atomic layer deposition (ALD) can be used to form the gate insulating layer 151. Referring to FIG. 16, after the gate insulating layer 151 is formed, a first word line WL1 and a second word line WL2 can be formed on the sidewalls of the first active pattern AP1 and the second active pattern AP2. Forming the first word line WL1 and the second word line WL2 can include forming a gate conductive layer that conformally covers the gate insulating layer 151 and then performing an anisotropic etching process on the gate conductive layer. Herein, the thickness of the gate conductive layer can be less than half of the width of the third trench T3. The gate conductive layer can define a gap region in the third trench T3 and can be formed on the gate insulating layer 151. During the time of performing an anisotropic etching process on the gate conductive layer, the gate insulating layer 151 can be used as an etch stop layer or the gate insulating layer 151 can be over-etched such that the second insulating pattern 143 is exposed. The first word line WL1 and the second word line WL2 can have various shapes according to the anisotropic etching process performed on the gate conductive layer. The upper surface of the first word line WL1 and the upper surface of the second word line WL2 can be positioned at a level lower than the upper surfaces of the first active pattern AP1 and the second active pattern AP2. After forming the first word line WL1 and the second word line WL2, a GPD process or a PLAD process can be performed to dope the active layer 110 with impurities through the gate insulating layer 151 exposed by the first word line WL1 and the second word line WL2. Referring to FIG. 17, a first capping layer 153 and a third insulating layer 155 can be sequentially formed in a third trench T3 (see FIG. 16) in which the first word line WL1 and the second word line WL2 are formed. Specifically, the first capping layer 153 can be conformally formed over the entire surface of the first substrate 100. The first capping layer 153 can include, for example, silicon nitride, silicon oxynitride, SiC, or a combination thereof or can be formed of, for example, silicon nitride, silicon oxynitride, SiC, or a combination thereof. The first capping layer 153 can cover the surfaces of the first word line WL1 and the second word line WL2. Thereafter, a third insulating layer 155 can be formed to fill the third trench T3 (see FIG. 16) in which the first capping layer 153 is formed. Herein, the third insulating layer 155 can include an insulating material different from the material of the first capping layer 153 or can be formed of an insulating material different from the material of the first capping layer 153. Thereafter, a planarization process can be performed on the third insulating layer 155 and the first capping layer 153 to expose the upper surface of the back gate capping pattern 115. Thus, the upper surfaces of the first active pattern AP1 and the second active pattern AP2 can be exposed. Referring to FIG. 18, a polysilicon layer 161 can be formed over the entire surface of the first substrate 100. The polysilicon layer 161 can contact the upper surfaces of the first active pattern AP1 and the second active pattern AP2. Thereafter, a metal layer 163 and a hard mask layer 165 can be sequentially formed on the polysilicon layer 161. The metal layer 163 can be formed of a conductive metal nitride or a metal (e.g., W, Ti, or Ta). The hard mask layer 165 can be formed of an insulating material (e.g., silicon nitride and silicon oxynitride). Referring to FIG. 19, a mask pattern (not shown) having a linear shape extending in the second direction D2 can be formed on the hard mask layer 165, and the hard mask layer 165, the metal layer 163, and the polysilicon layer 161 can be anisotropically etched in sequence using the mask pattern. Therefore, bit lines BL that are spaced apart from each other in the first direction D1 and extend in the second direction D2 can be formed. When forming the bit lines BL, some portions of the back gate capping pattern 115 can be etched together. Referring to FIG. 20, after forming the bit lines BL, a third insulating layer 171 that defines a gap region between the bit lines BL can be formed. The third insulating layer 171 can have a substantially uniform thickness and can be formed over the entire surface of the first substrate 100. The thickness of the third insulating layer 171 can be less than half of the gap between adjacent bit lines BL. By forming the third insulating layer 171, a gap region can be defined between the bit lines BL by the third insulating layer 171. The gap region can extend parallel to the bit lines BL in the second direction D2. After forming the third insulating layer 171, a shielding line formed of a conductive material or a gap structure 173 including an insulating material can be formed in the gap region of the third insulating layer 171. The gap structures 173 can be formed between the respective bit lines BL. In some embodiments, forming the gap structure 173 can include forming a shielding layer on the third insulating layer 171 to fill the gap region and forming grooves in the upper surface of the shielding layer. The upper surface of the gap structure 173 can be positioned at a level lower than the upper surface of the bit lines BL. The gap structure 173 can include a metal (e.g., W, Ti, Ni, or cobalt (Co)) or can be formed of a metal (e.g., W, Ti, Ni, or cobalt (Co)). In other embodiments, the gap structure 173 can include a carbon-containing conductive material (e.g., graphene) or can be formed of a carbon-containing conductive material (e.g., graphene). The gap structure 173 can include a low dielectric constant dielectric material having a dielectric constant lower than that of the third insulating layer 171 or can be formed of a low dielectric constant dielectric material having a dielectric constant lower than that of the third insulating layer 171. After forming the gap structure 173, capping insulating patterns 175 can be formed on the gap structures 173, respectively. Forming the capping insulating patterns 175 can include forming a capping insulating layer that fills the gap regions in which the gap structures 173 are respectively formed and performing a planarization process on the capping insulating layer and the third insulating layer 171 to expose the upper surface of the bit lines BL (i.e., the upper surface of the hard mask layer 165). Referring to FIG. 21, a first substrate 100 having a back gate electrode BG, a first word line WL1, a second word line WL2, a first active pattern AP1, a second active pattern AP2, and a bit line BL formed thereon can be bonded to a substrate 200. The substrate 200 can be bonded to the upper surface of the bit line BL (i.e., the upper surface of the hard mask layer 165 and the upper surface of the top cover insulating pattern 175). The substrate 200 can include, for example, single crystal Si, glass, or quartz, or can be formed of, for example, single crystal Si, glass, or quartz. Referring to FIG. 22, after bonding the substrate 200, a rear lapping process for removing the first substrate 100 (see FIG. 21) can be performed. Removing the first substrate 100 (see FIG. 21) can include exposing the buried insulating layer 101 by sequentially performing a grinding process and a wet etching process. Referring to FIG. 23, the buried insulating layer 101 can be removed to expose the first active pattern AP1, the second active pattern AP2, the first insulating pattern 111, and the back gate insulating pattern 113. Thereafter, a third etch stop layer 211 and a fourth etch stop layer 213 can be sequentially formed. The third etch stop layer 211 can be formed of silicon oxide and can be formed on the first active pattern AP1, the second active pattern AP2, the first insulating pattern 111, and the back gate insulating pattern 113. The fourth etch stop layer 213 can be formed of a material (e.g., silicon nitride) having an etch selectivity with respect to the third etch stop layer 211. An interlayer insulating layer 231 and an etch stop layer 233 can be formed. The etch stop layer 233 can be formed of an insulating material having an etch selectivity with respect to the interlayer insulating layer 231. Referring to FIG. 24, contact holes BCH passing through the interlayer insulating layer 231 and the etch stop layer 233 and exposing the first active pattern AP1 and the second active pattern AP2, respectively, can be formed. The contact holes BCH can be formed to expose the upper surfaces of the first active pattern AP1 and the second active pattern AP2, respectively. The contact holes BCH can be spaced apart from each other in a first direction D1 and a second direction D2. In addition, the contact holes BCH can expose the upper surfaces of the third etch stop layer 211 and the fourth etch stop layer 213 adjacent to the first active pattern AP1 and the second active pattern AP2, as well as the side surfaces of the interlayer insulating layer 231 and the side surfaces of the etch stop layer 233. In a top view, the contact holes BCH can have shapes such as a circular shape, an elliptical shape, a polygonal shape, and a rounded polygonal shape. In some embodiments, the contact holes BCH can be arranged in a grating shape in a top view. In other embodiments, the contact holes BCH can be arranged in a honeycomb shape in a top view. Referring to FIG. 25, an epitaxial growth layer 241 may be formed to fill a part of each of the contact holes BCH (see FIG. 24). The epitaxial growth layer 241 may be formed from each of the upper surface of the first active pattern AP1 and the upper surface of the second active pattern AP2 by using a SEG process. The epitaxial growth layer 241 may be formed in an undoped state or in a state doped with a low concentration. Additionally, the epitaxial growth layer 241 may include a single crystal Si epitaxial growth layer or a SiGe epitaxial growth layer or may be formed of a single crystal Si epitaxial growth layer or a SiGe epitaxial growth layer, but is not limited thereto. Additionally, a process of effectively controlling the thickness distribution of the epitaxial growth layer 241 by forming a sacrificial layer (not shown) on the epitaxial growth layer 241 and then removing the sacrificial layer may be further included. Referring to FIG. 26, a doped polycrystalline silicon layer 243 may be formed to locally fill each of the contact holes BCH (see FIG. 24). The doped polycrystalline silicon layer 243 may be provided by forming polycrystalline silicon doped with a high concentration of an n-type dopant or a p-type dopant on the epitaxial growth layer 241. The doping concentration of the dopant in the doped polycrystalline silicon layer 243 may be high enough such that some of the dopants contained in the doped polycrystalline silicon layer 243 move to the epitaxial growth layer 241 and dope the epitaxial growth layer 241. Referring to FIG. 27, a silicide layer 245 may be formed to completely fill the other parts of each of the contact holes BCH (see FIG. 24). The silicide layer 245 may include a metal silicide (e.g., CoSi, NiSi, or TiSi) or may be formed of a metal silicide (e.g., CoSi, NiSi, or TiSi). The silicide layer 245 may be formed by forming a metal layer that fills each of the contact holes BCH (see FIG. 24) on the doped polycrystalline silicon layer 243, reacting the metal layer with the doped polycrystalline silicon layer 243 to form the silicide layer 245, and then removing the unreacted remaining portion of the metal layer. By performing an annealing process, some of the high concentration dopants contained in the doped polycrystalline silicon layer 243 may move to the epitaxial growth layer 241. Therefore, the epitaxial growth layer 241 may have a doping concentration that gradually decreases as it moves away from the junction interface with the doped polycrystalline silicon layer 243. Therefore, the epitaxial growth layer 241 may have a specific junction depth. Then, contact patterns BC each including the epitaxial growth layer 241 that is gradually doped, the doped polycrystalline silicon layer 243 doped with a high concentration, and the silicide layer 245 may be formed in the contact holes BCH (see FIG. 24), respectively. Referring to FIG. 28, a conductive layer 250 may be formed to cover the entire upper surface of the contact pattern BC and the upper surface of the etch stop layer 233. The conductive layer 250 may include or may be formed of a material for forming the landing pad LP described below. For example, the conductive layer 250 may include a metal (such as Ti, Ta, and W) or may be formed of a metal (such as Ti, Ta, and W). Referring to FIG. 29, landing pads LP respectively connected to the contact pattern BC may be formed by patterning the conductive layer 250 (see FIG. 28). Forming the landing pads LP may include forming groove regions by anisotropically etching the etch stop layer 233 (see FIG. 28) and the interlayer insulating layer 231 located between the conductive layer 250 (see FIG. 28) and the contact pattern BC by using a mask pattern, and forming isolation insulating patterns 255 by burying insulating materials in the groove regions, respectively. Herein, during the time period of forming the groove regions, some portions of the contact pattern BC may be etched. The upper surface of the isolation insulating pattern 255 may be substantially coplanar with the upper surface of the landing pad LP. Referring to FIG. 30, capacitors of the data storage pattern DSP may be formed on the landing pads LP, respectively. Specifically, storage electrodes 261 may be formed on the landing pads LP, respectively, and a capacitor dielectric layer 263 may be formed to conformally cover the surface of the storage electrodes 261. Thereafter, a plate electrode 265 may be formed on the capacitor dielectric layer 263. Referring back to FIG. 3, a semiconductor device 10 according to the inventive concept may be manufactured by forming an upper insulating layer 270 on the data storage pattern DSP and forming a unit contact plug PLG connected to the plate electrode 265 through the upper insulating layer 270. Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it should be understood that various changes in form and detail may be made thereto without departing from the spirit and scope of the following claims. 10, 20, 30: Semiconductor device 100: First substrate 101: Buried insulating layer 110: Active layer 111: First insulating pattern 113: Back gate insulating pattern 115: Back gate capping pattern 120: Spacer layer 121: Spacer 131: First etch stop layer 133: First sacrificial layer 135: Second sacrificial layer 141: Second etch stop layer 143: Second insulating pattern 151: Gate insulating layer 153: First capping layer 155: Third insulating layer 155P: Third insulating pattern 161: Polysilicon layer 161P: Polysilicon pattern 163: Metal layer 163P: Metal pattern 165: Hard mask layer 165P: Hard mask pattern 171: Third insulating layer / wire insulating layer 173: Gap structure 175: Capping insulating pattern / wire insulating layer 200: Substrate 210, 233: Etch stop layer 211: Third etch stop layer 213: Fourth etch stop layer 231: Interlayer insulating layer 241, 341, 441: Epitaxial growth layer 243, 443: Doped polysilicon layer 245, 345, 445: Silicide layer 250: Conductive layer 255: Isolation insulating pattern 261: Storage electrode 263: Capacitor dielectric layer 265: Plate electrode 270: Upper insulating layer A - A', B - B': Line AP1: First active pattern AP2: Second active pattern B10: Buffer layer BC, BC2, BC3: Contact pattern BCH: Contact hole BG: Back gate electrode BL: Bit line CHR: Channel region D1: First direction D2: Second direction D3: Third direction DC: Doping concentration DSP: Data storage pattern GOX: Gate insulating pattern HP: Horizontal part IV: Part LP: Lapping pad M10: First mask layer M20: Second mask layer M30: Third mask layer MP1: First mask pattern MP2: Second mask pattern OP: Opening PAP: Preliminary active pattern PLG: Unit contact plug S1: First surface S2: Second surface SS1: First side surface SS2: Second side surface SDR1: First dopant region SDR2: Second dopant region T1: First trench T2: Second trench T3: Third trench VP: Vertical part W1, W3, W5: Width WL1: First word line WL2: Second word line Embodiments of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a perspective view showing a part of a semiconductor device according to an embodiment. FIG. 2 is a layout showing a semiconductor device according to an embodiment. FIG. 3 shows a cross-sectional view of the semiconductor device shown in FIG. 2 taken along lines A-A' and B-B'. FIG. 4 is an enlarged cross-sectional view of part IV of the semiconductor device shown in FIG. 3. FIGS. 5 and 6 are cross-sectional views showing semiconductor devices according to other embodiments. FIGS. 7 to 30 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment in a process sequence. 10: Semiconductor device 111: First insulating pattern 113: Back gate insulating pattern 115: Back gate capping pattern 131: First etch stop layer 141: Second etch stop layer 143: Second insulating pattern 153: First capping layer 155P: Third insulating pattern 161P: Polysilicon pattern 163P: Metal pattern 165P: Hard mask pattern 171: Third insulating layer / wire insulating layer 173: Gap structure 175: Capping insulating pattern / wire insulating layer 200: Substrate 211: Third etch stop layer 213: Fourth etch stop layer 231: Interlayer insulating layer 241: Epitaxial growth layer 243: Doped polysilicon layer 245: Silicide layer 255: Isolation insulating pattern 261: Storage electrode 263: Capacitor dielectric layer 265: Plate electrode 270: Upper insulating layer A-A', B-B': Lines AP1: First active pattern AP2: Second active pattern BC: Contact pattern BG: Back gate electrode BL: Bit line D1: First direction D2: Second direction D3: Third direction DSP: Data storage pattern GOX: Gate insulation pattern IV: Portion LP: Lapping pad PLG: Unit contact plug WL1: First word line WL2: Second word line

Claims

1. A semiconductor device, comprising: substrate; The first element line extends in a first direction on the substrate; The first active pattern and the second active pattern are located on the first bit line; The back gate electrode is located between the first active pattern and the second active pattern and extends across the first bit line in a second direction perpendicular to the first direction. A first character line extends in the second direction, wherein the first active pattern is disposed between the first character line and the back gate electrode; The second character line extends in the second direction, wherein the second active pattern is disposed between the second character line and the back gate electrode; And a contact pattern connected to each of the first active pattern and the second active pattern, wherein the contact pattern comprises an epitaxial growth layer, a doped polycrystalline silicon layer and a silicide layer stacked on each other in a vertical direction perpendicular to the upper surface of the substrate, and wherein the epitaxial growth layer has a doping concentration that gradually varies in the vertical direction.

2. The semiconductor device of claim 1, wherein each of the first active pattern and the second active pattern comprises a single-crystal semiconductor material, wherein the epitaxial growth layer of the contact pattern is in contact with the first active pattern and the second active pattern.

3. The semiconductor device of claim 2, wherein the doping concentration of the epitaxial growth layer gradually decreases with distance from the doped polycrystalline silicon layer.

4. The semiconductor device of claim 3, wherein the lower region of the epitaxial growth layer contacts each of the first active pattern and the second active pattern, and wherein the lower region of the epitaxial growth layer is an undoped region.

5. The semiconductor device of claim 3, wherein the type of dopant in the epitaxial growth layer is the same as the type of dopant in the doped polycrystalline silicon layer.

6. The semiconductor device of claim 5, wherein the epitaxial growth layer is a silicon (Si) epitaxial growth layer, and wherein the dopant of the epitaxial growth layer is an n-type dopant.

7. The semiconductor device of claim 1, wherein each of the first active pattern and the second active pattern comprises: Source / drain regions are adjacent to the contact pattern; And a channel region adjacent to the first word line and the second word line, wherein the doping concentration of the source / drain region is greater than the doping concentration of the channel region.

8. The semiconductor device as claimed in claim 1, further comprising: The data storage pattern is connected to the contact pattern; And an overlap pad, disposed between the contact pattern and the data storage pattern.

9. The semiconductor device of claim 8, wherein the overlap pad contacts the silicon layer of the contact pattern.

10. The semiconductor device as claimed in claim 1, further comprising: The second bit line is adjacent to the first bit line; A gap structure is provided in the space between the first bit line and the second bit line; An insulating pattern is located between the gap structure and the first bit line, wherein the gap structure comprises a conductive material.

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