Electronic device and method for manufacturing the same

Abstract

This disclosure relates to an electronic device, comprising: a substrate; a first metal layer disposed on the substrate; a dielectric layer disposed on the first metal layer, wherein the dielectric layer includes an upper surface, a lower surface, and a through-hole, the upper surface and the lower surface facing each other, the first metal layer being exposed by the through-hole, and the through-hole having a sidewall; and a second metal layer disposed on the upper surface and extending to the sidewall of the through-hole and the first metal layer for electrical connection with the first metal layer; wherein the thickness of the second metal layer located on the sidewall and adjacent to the lower surface is less than the thickness of the second metal layer located on the sidewall and adjacent to the upper surface. This disclosure further relates to a method for fabricating the aforementioned electronic device.

Description

Electronic Device and Method for Preparing the Same The present disclosure relates to an electronic device and a method for preparing the same, and particularly to an electronic device and a method for preparing the same in which the metal layer in the through hole has different thicknesses. In the preparation of an electronic device, a semi-additive method such as a sputtering and electroplating or chemical plating and electroplating process followed by an etching process can be used to form a patterned metal layer, and the metal layers above and below the dielectric layer are electrically connected through the through holes and the patterned metal layer of the dielectric layer. However, when the through holes of the dielectric layer have a high aspect ratio, the etching process may cause the metal layer on the bottom or side walls of the through holes to be thinner, resulting in an increase in resistance value and even a disconnection phenomenon. In view of this, there is an urgent need to develop a novel electronic device and a method for preparing the same to overcome the foregoing problems. The present disclosure provides an electronic device, including: a substrate; a first metal layer disposed on the substrate; a dielectric layer disposed on the first metal layer, wherein the dielectric layer includes an upper surface, a lower surface and a through hole, the upper surface and the lower surface are opposite to each other, the through hole exposes a part of the first metal layer, and the through hole has a side wall; and a second metal layer disposed on the upper surface and extending to the side wall of the through hole and the first metal layer to be electrically connected to the first metal layer; wherein, the thickness of the second metal layer on the side wall and adjacent to the lower surface is less than the thickness of the second metal layer on the side wall and adjacent to the upper surface. In addition, the present disclosure further provides a method for preparing an electronic device, including the following steps: providing a substrate, a first metal layer is disposed on the substrate, and a dielectric layer is disposed on the first metal layer, wherein the dielectric layer includes an upper surface, a lower surface and a through hole, the upper surface and the lower surface are opposite to each other, the through hole exposes a part of the first metal layer, and the through hole has a side wall; forming a second metal layer on the upper surface of the dielectric layer and extending to the side wall of the through hole and the first metal layer to be electrically connected to the first metal layer; and forming an anti-etching unit, wherein the anti-etching unit is disposed corresponding to the through hole; wherein, the thickness of the second metal layer on the side wall and adjacent to the lower surface is less than the thickness of the second metal layer on the side wall and adjacent to the upper surface. The following specifically illustrates the implementation manners of the present disclosure through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed according to different viewpoints and applications without departing from the spirit of this creation. It should be noted that, in this text, unless otherwise specified, an element with "a" does not necessarily mean only one such element, but may include one or more such elements. Furthermore, the ordinal numbers such as "first" and "second" used in the specification and claims are used to modify the elements of the claims. By themselves, they do not imply or represent that there is any previous ordinal number for the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish one claimed element with a certain name from another claimed element with the same name. Throughout this specification and the appended claims, certain terms will be used to refer to specific elements. Those skilled in the art should understand that electronic equipment manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, terms such as "comprising", "containing", "having", etc. are open-ended terms, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of this disclosure uses the terms "comprising", "containing", and / or "having", it specifies the existence of the corresponding features, regions, steps, operations, and / or components, but does not exclude the existence of one or more corresponding features, regions, steps, operations, and / or components. In the text, the terms "about", "approximately", "substantially", "essentially" generally mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meaning of "about", "approximately", "substantially", "essentially" can still be implied even without specifically stating "about", "approximately", "substantially", "essentially". In addition, the phrase "ranging from a first value to a second value", "ranging between a first value and a second value" means that the range includes the first value, the second value, and other values therebetween. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein. In addition, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another element. It is understood that if the device in the drawing is flipped so that it is upside down, the element described on the "below" side will become the element on the "above" side. When a corresponding member (such as a film layer or region) is referred to as "on another member", it can be directly on another member, or there may be other members between the two. On the other hand, when a member is referred to as "directly on another member", there are no members between the two. In addition, when a member is referred to as "on another member", there is an up-and-down relationship between the two in the top-down direction, and this member can be above or below another member, and this up-and-down relationship depends on the orientation of the device. Furthermore, terms regarding joining and connection such as "connect", "interconnect" and their similar terms, unless specifically defined, may refer to two structures in direct contact, or may also refer to two structures not in direct contact, with other structures provided between the two structures. Terms regarding joining and connection may also include the situation where both structures can move, or both structures are fixed. In addition, the terms "electrically connected" and "coupled" include any direct and indirect electrical connection means. In the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable means can be used to measure the depth, thickness, width or height of each element, or the spacing or distance between elements. In addition, there may be a certain error between any two values or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees. In this disclosure, the electronic device may include, but is not limited to, a display device, a backlight device, an antenna device, a sensing device, or a splicing device. The electronic device may be a foldable or flexible electronic device. The display device may be a non-self-emitting display device or a self-emitting display device. The antenna device may be an antenna device in a liquid crystal form or a non-liquid crystal form. The sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasonic waves, but is not limited thereto. Electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a mini light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. In addition, the outer shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a processing system, a driving system, a control system, a light source system, a shelf system, etc. to support the display device or the splicing device. It should be noted that the technical solutions provided in different embodiments hereinafter may be mutually replaced, combined, or mixed used to constitute another embodiment without violating the spirit of this disclosure. Figures 1A to 1F show schematic cross-sectional views of the manufacturing process of the second metal layer of an electronic device according to an embodiment of this disclosure. As shown in Figure 1A, first, a substrate 11 is provided. Among them, the material of the substrate 11 may include quartz, glass, wafer, sapphire, resin, epoxy resin, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), other plastic materials, or a combination thereof, but this disclosure is not limited thereto. Then, a first metal layer 12 is formed on the substrate 11. Among them, the material of the first metal layer 12 may include gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, zinc, their alloys, or a combination thereof, but this disclosure is not limited thereto. In addition, the first metal layer 12 may be formed by sputtering, chemical plating, electroplating, metal film pasting, or a combination thereof, but this disclosure is not limited thereto. Next, a dielectric layer 13 is formed on the first metal layer 12. Among them, the material of the dielectric layer 13 may include organic materials, inorganic materials, or a combination thereof. Suitable inorganic materials may include, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or a combination thereof, but the present disclosure is not limited thereto. Suitable organic materials may include, for example, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polybenzoxazole (PBO), benzocyclobutene (ECB), polyfluoroalkoxy (PFA), epoxy resin, photoresist, polymer, or a combination thereof, but the present disclosure is not limited thereto. In addition, the dielectric layer 13 can be formed by a coating method, film pasting, or a combination thereof. The coating method can be, for example, dip coating, spin coating, roller coating, blade coating, spray coating, or a combination thereof. As shown in FIG. 1B, a via hole 131 is formed in the dielectric layer 13. Among them, the via hole 131 can be formed by etching or drilling. The drilling can be, for example, laser drilling, mechanical drilling, or a combination thereof. After the foregoing steps, a substrate 11 can be obtained. A first metal layer 12 is provided on the substrate 11, a dielectric layer 13 is provided on the first metal layer 12, and the dielectric layer 13 includes an upper surface 132, a lower surface 133, and a via hole 131. The upper surface 132 and the lower surface 133 are opposite to each other. The via hole 131 exposes a part of the first metal layer 12, and the via hole 131 has a side wall 1311. As shown in FIG. 1C, a seed layer 14a is formed on the dielectric layer 13. For example, the seed layer 14a extends from the upper surface 132 of the dielectric layer 13 to the side wall 1311 of the via hole 131, is provided on the first metal layer 12, and is electrically connected to the first metal layer 12. Here, the seed layer 14a can be formed by sputtering, electroless plating, or a combination thereof. Among them, the thickness T1 of the seed layer 14a can be between 0.1 μm and 2 μm (0.1 μm ≦ T1 ≦ 2 μm). For example, it can be greater than 0.1 μm and less than 2 μm (0.1 μm < T1 < 2 μm). When the thickness T1 of the seed layer 14a is within the foregoing range, it is beneficial to the electroplating of the subsequent metal layer. Here, the thickness T1 of the seed layer 14a refers to the maximum thickness of the seed layer 14a on the upper surface 132 of the dielectric layer 13 in the normal direction of the substrate 11 (i.e., the Z direction). As shown in FIG. 1D, an electroplating photoresist 15 is formed on the seed layer 14a. Among them, the electroplating photoresist 15 can be formed through a yellow light development process. Then, a metal is deposited on the seed layer 14a to obtain a second metal layer 14, as shown in FIG. 1E. Thereafter, as shown in FIG. 1F, the electroplating photoresist 15 is removed. Here, the metal can be deposited on the seed layer 14a by electroplating, and the deposited metal can include gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, zinc, their alloys or their combinations, but the present disclosure is not limited thereto. In some embodiments of the present disclosure, since the seed layer 14a is quite thin, the seed layer 14a can hardly be observed; or since the seed layer 14a is the same as the metal deposited thereon, the seed layer 14a and the metal deposited thereon can hardly be distinguished, thus forming the second metal layer 14. After the foregoing steps, a second metal layer 14 can be formed on the upper surface 132 of the dielectric layer 13, and the second metal layer 14 extends into the through hole 131 to be electrically connected to the first metal layer 12. Specifically, the second metal layer 14 is disposed on the upper surface 132 of the dielectric layer 13, on the side wall 1311 of the through hole 131, and on the first metal layer 12, thereby being electrically connected to the first metal layer 12. FIGS. 2A to 2C show schematic cross-sectional views of the manufacturing process of an electronic device according to an embodiment of the present disclosure. After the steps shown in FIG. 1F, as shown in FIG. 2A, an anti-etching unit 16 is formed, wherein the anti-etching unit 16 is disposed corresponding to the through hole 131. More specifically, the anti-etching unit 16 is disposed inside the through hole 131. Here, the anti-etching unit 16 can be formed by a suitable method, for example, spraying, screen printing or their combination, but the present disclosure is not limited thereto. In addition, the material of the anti-etching unit 16 can include photoresist, but the present disclosure is not limited thereto. Furthermore, there is no special limitation on the height at which the anti-etching unit 16 fills the through hole 131, as long as the effect of protecting the second metal layer 14 at the bottom of the through hole 131 can be achieved. For example, the second metal layer 14 has a first surface 141, and the height H1 from the first surface 141 to the substrate 11 is greater than the height H2 from the surface 161 of the anti-etching unit 16 to the substrate 11. Here, the so-called height H1 refers to the maximum height from the first surface 141 of the second metal layer 14 to the substrate 11 in the normal direction of the substrate 11 (i.e., the Z direction), especially the maximum height from the first surface 141 of the second metal layer 14 adjacent to the through hole 131 to the substrate 11. In addition, the so-called height H2 refers to the maximum height of the surface 161 of the anti-etching unit 16 in the normal direction of the substrate 11 (i.e., the Z direction). As shown in FIG. 2B, the second metal layer 14 is patterned, and then the circuit production of the second metal layer 14 is completed, wherein the second metal layer 14 located on the side wall 1311 of the through hole 131 has a stepped structure. Here, the second metal layer 14 can be patterned through an etching process. As shown in FIG. 2C, the anti-etching unit 16 is removed; through the foregoing process, the electronic device of this embodiment can be obtained. However, in another embodiment of the present disclosure, if the anti-etching unit 16 does not affect the properties of the electronic device, the anti-etching unit 16 may not need to be removed. As shown in FIG. 2C, the electronic device of this embodiment includes: a substrate 11; a first metal layer 12 disposed on the substrate 11; a dielectric layer 13 disposed on the first metal layer 12, wherein the dielectric layer 13 includes an upper surface 132, a lower surface 133, and a through hole 131. The upper surface 132 and the lower surface 133 are opposite to each other. The through hole 131 exposes a part of the first metal layer 12, and the through hole 131 has a side wall 1311; and a second metal layer 14 disposed on the upper surface 132 and extending into the through hole 131 to be electrically connected to the first metal layer 12; wherein, the thickness T2 of the second metal layer 14 on the side wall 1311 and adjacent to the lower surface 133 is less than the thickness T3 of the second metal layer 14 on the side wall 1311 and adjacent to the upper surface 132. In addition, in this embodiment, the thickness of the second metal layer 14 on the side wall 1311 increases from the lower surface 133 to the upper surface 132 of the dielectric layer 13. Here, the so-called thickness T2 and thickness T3 respectively refer to the thickness of the second metal layer 14 in the direction perpendicular to the side wall 1311. FIG. 2D is a partial enlarged view of the electronic device of FIG. 2C. As shown in FIGS. 2C and 2D, in this embodiment, the second metal layer 14 on the side wall 1311 of the through hole 131 has a stepped structure. More specifically, the second metal layer 14 on the side wall 1311 of the through hole 131 has a first side wall 142 and a second side wall 143. The second side wall 143 is located between the first side wall 142 and the side wall 1311. There is a first thickness T4 between the side wall 1311 and the first side wall 142, and a second thickness T5 between the side wall 1311 and the second side wall 143, and the thickness difference (ΔT1) between the first thickness T4 and the second thickness T5 is between 0.1 μm and 2 μm (0.1 μm ≦ ΔT1 ≦ 2 μm). For example, the thickness difference (ΔT1) between the first thickness T4 and the second thickness T5 is 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 1.3 μm, 1.5 μm, 1.8 μm, 2 μm, or a numerical range composed of any of the foregoing values. Here, the so-called first thickness T4 and second thickness T5 respectively refer to the thickness of the second metal layer 14 in the direction perpendicular to the side wall 1311. In addition, as shown in FIG. 2D, in this embodiment, the second metal layer 14 on the sidewall 1311 of the through hole 131 further has a first connection wall 144. The first connection wall 144 connects the first sidewall 142 and the second sidewall 143, wherein there is a first included angle θ1 between the extension line of the second sidewall 143 and the first connection wall 144, and the first included angle θ1 is between 40 degrees and 70 degrees (40° ≤ θ1 ≤ 70°). Furthermore, as shown in FIG. 2C, in this embodiment, the electronic device does not include an anti-etching unit; however, in another embodiment of the present disclosure, the electronic device may optionally further include an anti-etching unit 16, and the anti-etching unit 16 can be disposed in the through hole 131, as shown in FIG. 2B. FIGS. 3A to 3C show cross-sectional schematic views of the manufacturing process of an electronic device according to another embodiment of the present disclosure. After the steps shown in FIG. 1F, as shown in FIG. 3A, an anti-etching unit 16 is formed, wherein the anti-etching unit 16 is disposed corresponding to the through hole 131. More specifically, the anti-etching unit 16 is disposed on the second metal layer 14 corresponding to the through hole 131, rather than in the through hole 131. Here, the anti-etching unit 16 can be formed by attaching a dry film photoresist to the second metal layer 14 corresponding to the through hole 131, but the present disclosure is not limited thereto. As shown in FIG. 3B, the second metal layer 14 is patterned, and then the circuit of the second metal layer 14 is completed. The second metal layer 14 on the upper surface 132 of the dielectric layer 13 has a stepped structure. Here, the second metal layer 14 can be patterned through an etching process. In addition, as shown in FIG. 3B, the width W1 of the anti-etching unit 16 needs to be greater than the opening width W2 of the through hole 131, so as to achieve the purpose of protecting the second metal layer 14 in the through hole 131. Furthermore, the width W1 of the etching unit 16 can be less than the width W3 of the portion to be retained after etching the second metal layer 14, so as to avoid affecting the circuit formed after etching the second metal layer 14 subsequently. As shown in FIG. 3C, the anti-etching unit 16 is removed; through the foregoing process, the electronic device of this embodiment can be obtained. However, in another embodiment of the present disclosure, if the anti-etching unit 16 does not affect the properties of the electronic device, the anti-etching unit 16 may not need to be removed. In addition to the stepped structure of the second metal layer 14, the structure of the electronic device of this embodiment shown in FIG. 3C is similar to the structure of the electronic device shown in FIG. 2C. FIG. 3D is a partial enlarged view of the electronic device in FIG. 3C. As shown in FIGS. 3C and 3D, in this embodiment, the second metal layer 14 located on the upper surface 132 of the dielectric layer 13 has a stepped structure. More specifically, the second metal layer 14 located on the upper surface 132 of the dielectric layer 13 has a first surface 145 and a second surface 146. The second surface 146 is located between the upper surface 132 and the first surface 145. There is a third thickness T6 between the upper surface 132 and the first surface 145, and a fourth thickness T7 between the upper surface 132 and the second surface 146. The thickness difference (ΔT2) between the third thickness T6 and the fourth thickness T7 is between 0.1 μm and 2 μm (0.1 μm ≦ ΔT2 ≦ 2 μm). For example, the thickness difference (ΔT2) between the third thickness T6 and the fourth thickness T7 is 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 1.3 μm, 1.5 μm, 1.8 μm, 2 μm, or a numerical range composed of any of the foregoing values. Here, the so-called third thickness T6 and fourth thickness T7 respectively refer to the thicknesses of the stepped structure of the second metal layer 14 in the normal direction of the substrate 11 (i.e., the Z direction). In addition, as shown in FIG. 3D, in this embodiment, the second metal layer 14 located on the upper surface 132 of the dielectric layer 13 further has a second connection wall 147 and a third connection wall 148. The second connection wall 147 connects the upper surface 132 and the second surface 146, and the third connection wall 148 connects the second surface 146 and the first surface 145. The second connection wall 147 and the upper surface 132 have a second included angle θ2, and the third connection wall 148 and the extension line of the second surface 146 have a third included angle θ3. The second included angle θ2 is between 40 degrees and 70 degrees (40° ≦ θ2 ≦ 70°), and the third included angle θ3 is between 40 degrees and 70 degrees (40° ≦ θ3 ≦ 70°). Among them, the second included angle θ2 and the third included angle θ3 may be the same or different. In this embodiment, the second included angle θ2 and the third included angle θ3 may be the same, but the present disclosure is not limited thereto. Furthermore, as shown in FIG. 3C, in this embodiment, the electronic device does not include an anti-etching unit; however, in another embodiment of the present disclosure, the electronic device may optionally further include an anti-etching unit 16, and the anti-etching unit 16 may be disposed on the second metal layer 14 corresponding to the through hole 131, as shown in FIG. 3B. FIGS. 3A' to 3B' show cross-sectional schematic diagrams of the manufacturing process of an electronic device according to still another embodiment of the present disclosure. The manufacturing of the electronic device in this embodiment is similar to that in FIGS. 3A to 3B, except for the following differences. As shown in FIG. 3A’, in this embodiment, the anti-etching unit 16 is disposed corresponding to the through hole 131. More specifically, the anti-etching unit 16 is disposed on the second metal layer 14 corresponding to the through hole 131 and further disposed in the through hole 131. Here, the anti-etching unit 16 can be formed by a suitable method, for example, dip coating, spin coating, roller coating, doctor blade coating, spraying or a combination thereof, but the present disclosure is not limited thereto. In addition, the material of the anti-etching unit 16 may include photoresist, but the present disclosure is not limited thereto. Then, as shown in FIG. 3B’, perform the step of patterning the second metal layer 14 similar to that in FIG. 3B, and then the circuit fabrication of the second metal layer 14 is completed. The second metal layer 14 located on the upper surface 132 of the dielectric layer 13 has a stepped structure. In this embodiment, the patterning step in FIG. 3B’ is similar to that in FIG. 3B, so it will not be described in detail. Next, the step of removing the anti-etching unit 16 can be performed to form an electronic device as shown in FIG. 3C. Therefore, the structure of the electronic device formed through the processes of FIGS. 3A’ and 3B’ is similar to the structure of the electronic device shown in FIG. 3C, which will not be described in detail here. In addition, in another embodiment of the present disclosure, the electronic device may optionally further include an anti-etching unit 16, and the anti-etching unit 16 can be disposed on the second metal layer 14 corresponding to the through hole 131 and further disposed in the through hole 131, as shown in FIG. 3B’. In the preparation of conventional electronic devices, a seed layer can be formed by sputtering or chemical plating, and then a metal layer can be formed through an electroplating process. When the aspect ratio of the through holes in the dielectric layer increases, especially when the aspect ratio of the through holes is greater than 1 (for example, as shown in FIG. 3B, when the depth H3 of the through hole 131 is greater than the opening width W2 (H3 / W2 > 1)), when etching the metal layer on the dielectric layer to form a circuit, the metal layer on the sidewall or bottom of the through hole may become thinner, resulting in an increase in resistance value and even a disconnection phenomenon. In the foregoing embodiments of the present disclosure, by forming an anti-etching unit corresponding to the through hole, the metal layer in the through hole can be protected, preventing the metal layer in the through hole from being etched simultaneously when etching the metal layer on the dielectric layer, and preventing the metal layer from becoming thinner or disconnected, thereby improving the yield of the electronic device. The above specific embodiments should be construed as merely illustrative and not in any way limiting the rest of the present disclosure, and the features between different embodiments can be mixed and used as long as they do not conflict with each other. 11: Substrate 12: First metal layer 13: Dielectric layer 131: Via hole 1311: Side wall 132: Upper surface 133: Lower surface 14: Second metal layer 14a: Seed layer 141: First surface 142: First side wall 143: Second side wall 144: First connection wall 145: First surface 146: Second surface 147: Second connection wall 148: Third connection wall 15: Electroplating photoresist 16: Etching resistance unit 161: Surface H1, H2: Height H3: Depth T1, T2, T3: Thickness T4: First thickness T5: Second thickness T6: Third thickness T7: Fourth thickness W1, W3: Width W2: Opening width θ1: First included angle θ2: Second included angle θ3: Third included angle X, Y, Z: Coordinates Figures 1A to 1F show schematic cross-sectional views of the preparation process of the second metal layer of an electronic device according to an embodiment of the present disclosure. Figures 2A to 2C show schematic cross-sectional views of the preparation process of an electronic device according to an embodiment of the present disclosure. Figure 2D is a partial enlarged view of the electronic device in Figure 2C. Figures 3A to 3C show schematic cross-sectional views of the preparation process of an electronic device according to another embodiment of the present disclosure. Figure 3D is a partial enlarged view of the electronic device in Figure 3C. Figures 3A' to 3B' show schematic cross-sectional views of the preparation process of an electronic device according to still another embodiment of the present disclosure. None. 11: Substrate 12: First metal layer 13: Dielectric layer 131: Via hole 1311: Side wall 132: Upper surface 133: Lower surface 14: Second metal layer T2,T3: Thickness X,Y,Z: Coordinates

Claims

1. An electronic device comprising: One substrate; A first metal layer is disposed on the substrate; A dielectric layer is disposed on the first metal layer, wherein the dielectric layer includes an upper surface, a lower surface, and a through-hole, the upper surface being opposite to the lower surface, the through-hole exposing a portion of the first metal layer, and the through-hole having a sidewall; and a second metal layer is disposed on the upper surface and extends to the sidewall of the through-hole and the first metal layer for electrical connection with the first metal layer, wherein the second metal layer has a stepped structure; wherein the thickness of the second metal layer located on the sidewall and adjacent to the lower surface is less than the thickness of the second metal layer located on the sidewall and adjacent to the upper surface.

2. The electronic device as claimed in claim 1, wherein the thickness of the second metal layer located on the sidewall increases from the lower surface of the dielectric layer toward the upper surface.

3. The electronic device as claimed in claim 1, wherein the stepped structure is located on the sidewall of the through hole, the second metal layer on the sidewall has a first sidewall and a second sidewall, the second sidewall is located between the first sidewall and the sidewall, the sidewall and the first sidewall have a first thickness, the sidewall and the second sidewall have a second thickness, and the thickness difference between the first thickness and the second thickness is between 0.1 μm and 2 μm.

4. The electronic device of claim 1, wherein the stepped structure is located on the upper surface of the dielectric layer, the second metal layer on the upper surface has a first surface and a second surface, the second surface is located between the upper surface and the first surface, the upper surface and the first surface have a third thickness, the upper surface and the second surface have a fourth thickness, and the thickness difference between the third thickness and the fourth thickness is between 0.1 μm and 2 μm.

5. The electronic device as claimed in claim 1 further includes an etch-resistant unit corresponding to the through-hole.

6. The electronic device of claim 5, wherein the etch-resistant unit is disposed within the via, on the second metal layer corresponding to the via, or within the via and on the second metal layer corresponding to the via.

7. A method for fabricating an electronic device, comprising the following steps: providing a substrate, wherein a first metal layer is disposed on the substrate, and a dielectric layer is disposed on the first metal layer, wherein the dielectric layer includes an upper surface, a lower surface, and a via, the upper surface and the lower surface being opposite each other, the via exposing a portion of the first metal layer, and the via having a sidewall; forming a second metal layer on the upper surface of the dielectric layer and extending to the sidewall of the via and the first metal layer for electrical connection with the first metal layer; forming an etch resist unit, wherein the etch resist unit is disposed corresponding to the via; and patterning the second metal layer such that the second metal layer located on the sidewall or the second metal layer located on the upper surface has a stepped structure; wherein... The thickness of the second metal layer located on the sidewall and adjacent to the lower surface is less than the thickness of the second metal layer located on the sidewall and adjacent to the upper surface.

8. The fabrication method as claimed in claim 7, wherein after the step of patterning the second metal layer, a further step is included: removing the etch resist unit.

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