Semiconductor memory devices

Abstract

The present invention provides a semiconductor memory device that achieves high performance and high integration density, and has the effect of configuring semiconductor dies, including vertically volatile memory structures and vertically non-volatile memory structures, on a peripheral circuit structure. The provided semiconductor memory device includes: a semiconductor substrate; a back gate structure having a cylindrical shape and extending vertically on the semiconductor substrate, and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer; a plurality of semiconductor patterns, each having an annular horizontal segment surrounding the back gate structure and spaced apart from each other in the vertical direction; and a first conductive line, a second conductive line, and a third conductive line surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction.

Description

Semiconductor Memory Device [Cross - Reference to Related Applications] Aspects of the present inventive concept relate to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a capacitor - less semiconductor memory device and a method of manufacturing the same. This application is based on and claims priority to Korean Patent Application No. 10 - 2022 - 0141766, filed with the Korean Intellectual Property Office on October 28, 2022, the disclosure of which is incorporated herein by reference in its entirety. Due to the need for miniaturized, multi - functional, and high - performance electronic products, there is a need for high - capacity semiconductor memory devices, and it is necessary to increase the integration degree to provide high - capacity semiconductor memory devices. Therefore, there is a need for semiconductor memory devices with high integration degree and high capacity. Among these semiconductor memory devices, dynamic random access memory (DRAM) generally includes a capacitor, but it is difficult to reduce the size of the capacitor for implementing the memory function, thus imposing a limitation on high integration degree. Aspects of the present inventive concept provide a capacitor - less semiconductor memory device capable of achieving high performance and high integration degree. Aspects of the present inventive concept provide a method of manufacturing a capacitor - less semiconductor memory device capable of achieving high performance and high integration degree. The problems solved by the technical spirit of the present inventive concept are not limited to the problems mentioned above, and those skilled in the art will clearly understand other problems not mentioned based on the following description. According to an aspect of the present inventive concept, there is provided a semiconductor memory device, the semiconductor memory device including: a semiconductor substrate; a back - gate structure having a cylindrical shape and extending on the semiconductor substrate in a vertical direction, and including a back - gate electrode layer and a back - gate insulating layer surrounding the back - gate electrode layer; a plurality of semiconductor patterns, each having an annular horizontal section surrounding the back - gate structure and spaced apart from each other in the vertical direction; a first conductive line, a second conductive line, and a third conductive line surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction; and a front - gate insulating layer disposed to continuously surround between the semiconductor pattern and the second conductive line, on an upper surface of the second conductive line, and on a lower surface of the second conductive line, wherein a region of the semiconductor pattern facing the first conductive line and the third conductive line is doped with impurities of a first conductivity type, and wherein a region of the semiconductor pattern facing the second conductive line is doped with impurities of a second conductivity type opposite to the impurities of the first conductivity type. According to another aspect of the inventive concept, there is provided a semiconductor memory device including: a semiconductor substrate having a cell region and a stepped extension region; a back gate structure having a cylindrical shape and extending in a vertical direction over the semiconductor substrate in the cell region and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer; a plurality of semiconductor patterns each having an annular horizontal section surrounding the back gate structure and spaced apart from each other in the vertical direction; a source line, a word line, and a bit line surrounding the semiconductor patterns and spaced apart from each other in the vertical direction; a front gate insulating layer continuously disposed between the semiconductor patterns and the word line, on an upper surface of the word line, and on a lower surface of the word line; and a first interconnect electrically connected to the back gate structure on an upper portion of the cell region; and a second interconnect electrically connected to the source line, the word line, and the bit line on an upper portion of the extension region, wherein regions of the semiconductor patterns facing the source line and the bit line are doped with impurities of a first conductivity type, and wherein regions of the semiconductor patterns facing the word line are doped with impurities of a second conductivity type opposite to the impurities of the first conductivity type. According to another aspect of the inventive concept, there is provided a semiconductor memory device including: a semiconductor substrate; a peripheral circuit structure disposed on the semiconductor substrate; a volatile memory structure and a non-volatile memory structure disposed on the peripheral circuit structure, wherein the volatile memory structure is a vertical dynamic random access memory (DRAM) and includes: a back gate structure having a cylindrical shape and extending in a vertical direction over the semiconductor substrate and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer; a plurality of semiconductor patterns each having an annular horizontal section surrounding the back gate structure and spaced apart from each other in the vertical direction; a source line, a word line, and a bit line surrounding the semiconductor patterns in a horizontal direction and spaced apart from each other in the vertical direction; and a front gate insulating layer continuously disposed between the semiconductor patterns and the word line, on an upper surface of the word line, and on a lower surface of the word line, wherein the non-volatile memory structure is a vertical NAND. Hereinafter, embodiments of the technical idea of the inventive concept will be described in detail with reference to the accompanying drawings. FIG. 1 is a perspective view showing a semiconductor memory device according to an embodiment of the inventive concept, FIG. 2 is a perspective view illustrating a cell region of FIG. 1, FIG. 3 is a plan view illustrating the cell region of FIG. 1, and FIG. 4 is an enlarged perspective view of region IV of FIG. 2. For ease of explanation, some components (e.g., the first interconnect and the second interconnect) are shown in a transparent manner inside. Referring to FIGS. 1 to 4 together, the semiconductor memory device 10 may include a memory cell MC array structure, and the memory cell MC array structure includes a cell region CR and an extended region ER. The cell region CR may be a region in which volatile memory cells MC having a vertical structure are provided, and the volatile memory cells MC form an array. The extended region ER may be a region in which a trapezoidal connection portion is formed, and the connection portion is used for an electrical connection between the memory cell MC array formed in the cell region CR and the peripheral circuit formed in a peripheral circuit region (not shown). The semiconductor substrate 101 may include, for example, silicon (Si) or be formed of, for example, silicon (Si). As an alternative, the semiconductor substrate 101 may include the following materials or be formed of the following materials: another semiconductor element, such as germanium (Ge); or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). As an alternative, the semiconductor substrate 101 may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate 101 may include a buried oxide (BOX) layer. A plurality of line insulating layers 110 may be disposed on the semiconductor substrate 101 at regular intervals in the vertical direction (Z direction). The plurality of line insulating layers 110 may be formed of a material including, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. Each of the plurality of line insulating layers 110 may be composed of: a single layer made of one insulating film, a bilayer made of two insulating films, or a multilayer made of a combination of at least three insulating films. Each of the plurality of first conductive lines 131, second conductive lines 132, and third conductive lines 133 may be disposed on a corresponding one of the line insulating layers 110 at regular intervals in the vertical direction (Z direction). The plurality of first conductive lines 131, second conductive lines 132, and third conductive lines 133 may include or be formed of at least one of the following: a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). A detailed description of the first conductive lines 131, second conductive lines 132, and third conductive lines 133 will be described later. The multiple back gate structures BG may be spaced apart from each other on the semiconductor substrate 101 in a first horizontal direction (X direction) and a second horizontal direction (Y direction) and may extend in a vertical direction (Z direction) (e.g., along the length direction). The multiple back gate structures BG may be disposed in vertical openings that penetrate the multiple line insulating layers 110 and the multiple first conductive lines 131, second conductive lines 132, and third conductive lines 133 in the cell region CR. In some embodiments, each of the multiple back gate structures BG may have a circular rod shape, such as a cylindrical rod shape. In other embodiments, different from that shown in the drawings, each of the multiple back gate structures BG may be tapered. For example, the width of each of the multiple back gate structures BG in the horizontal direction (X direction and Y direction) may become smaller in the vertical direction closer to the semiconductor substrate 101. The multiple back gate structures BG may include: a back gate insulating layer 123 disposed on the inner wall of the vertical opening; and a back gate electrode layer 125 filling the interior of the vertical opening on the back gate insulating layer 123. In the drawings, the multiple back gate structures BG are illustrated as having a circular horizontal cross-section, but are not limited thereto. The back gate insulating layer 123 may comprise, for example, silicon oxide or be formed of, for example, silicon oxide. In some embodiments, a back gate barrier layer (not shown) may be formed between the back gate insulating layer 123 and the back gate electrode layer 125. For example, each of the back gate electrode layer 125 and the back gate barrier layer (not shown) may comprise at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound or be formed of at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound. The fill insulating layer 150 may pass through the multiple line insulating layers 110 and the multiple first conductive lines 131, second conductive lines 132, and third conductive lines 133. The fill insulating layer 150 may divide the memory cell MC array into multiple unit blocks. For example, the semiconductor substrate 101 may be disposed on the lower surface of the fill insulating layer 150. For example, the fill insulating layer 150 may be formed on the semiconductor substrate. In some embodiments, the fill insulating layers 150 may be spaced apart from each other in a first horizontal direction (X direction) and extend along a second horizontal direction (Y direction). The fill insulating layer 150 may be disposed to be spaced apart from the multiple back gate structures BG. The fill insulating layer 150 may be formed of, for example, silicon oxide, silicon nitride, or a combination thereof. A plurality of semiconductor patterns 121 may be spaced apart from each other on each sidewall of the plurality of back gate structures BG in the vertical direction (Z direction). The plurality of semiconductor patterns 121 may have an annular horizontal cross-section surrounding the sidewall of each back gate structure BG. In some embodiments, the radius R1 of the semiconductor pattern 121 may be greater than the radius R2 of the back gate structure BG. The semiconductor pattern 121 may be made of doped semiconductor material. In some embodiments, the semiconductor pattern 121 may be formed of doped polysilicon. The plurality of semiconductor patterns 121 and the plurality of channel isolation insulating layers 151 may be alternately disposed on the sidewalls of the back gate structure BG. For example, the plurality of channel isolation insulating layers 151 may surround the sidewall portions of the back gate structure BG that are not covered by the semiconductor patterns 121. For example, each of the plurality of channel isolation insulating layers may contact the back gate insulating layer 123. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or being "on" another element, the one element may be directly connected or directly coupled to the other element or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or being "contacting / in contact with" another element, there are no intervening elements at the point of contact. The first conductive line 131, the second conductive line 132, and the third conductive line 133 may be positioned around a semiconductor pattern 121. The first conductive line 131, the second conductive line 132, and the third conductive line 133 are adjacent to one end of a semiconductor pattern 121, extend in the first horizontal direction (X direction), and may be spaced apart from each other in the vertical direction (Z direction). Line insulating layers 110 may be respectively disposed between the first conductive line 131, the second conductive line 132, and the third conductive line 133 that are adjacent in the vertical direction (Z direction). Each of the first conductive line 131, the second conductive line 132, and the third conductive line 133 may be formed of any one of doped semiconductor material, conductive metal nitride, metal, and metal semiconductor compound. The plurality of first conductive lines 131, second conductive lines 132, and third conductive lines 133 include a plurality of first conductive lines 131, a plurality of second conductive lines 132, and a plurality of third conductive lines 133. The regions of the plurality of semiconductor patterns 121 that contact the plurality of first conductive lines 131 may be source regions 121S. Each of the first conductive lines 131 may be a source line. Each source region 121S may include semiconductor material doped with impurities of a first conductivity type at a high concentration. In some embodiments, the first conductivity type may be N-type, and for example, the source region 121S may be an N+ region heavily doped with N-type impurities. The front gate insulating layer 140 may be disposed to surround the plurality of second conductive lines 132, and the regions of the plurality of semiconductor patterns 121 facing the plurality of second conductive lines 132 may be channel regions 121C. Each of the second conductive lines 132 may be a front gate electrode layer or a word line. Each channel region 121C may include semiconductor material doped with impurities of a second conductivity type at a low concentration, the second conductivity type being opposite to the first conductivity type. Here, the second conductivity type may be P-type, and for example, the channel region 121C may be a P region lightly doped with P-type impurities. The regions of the plurality of semiconductor patterns 121 that contact the plurality of third conductive lines 133 may be drain regions 121D. Each of the third conductive lines 133 may be a drain line or a bit line. Each drain region 121D may include semiconductor material doped with impurities of a first conductivity type at a high concentration. For example, the drain region 121D may be an N+ region heavily doped with N-type impurities. For example, in the semiconductor memory device 10 according to an embodiment of the present invention, the source region 121S and the drain region 121D may be formed of the same conductivity type (e.g., N-type), and the channel region 121C may be formed of a conductivity type opposite to the conductivity types of the source region 121S and the drain region 121D (e.g., P-type), but the concept of the present invention is not limited thereto. Thus, in the semiconductor memory device 10 according to an embodiment of the present invention, the semiconductor pattern 121 may be used as the channel and the source / drain of the memory cell MC. According to the electrical operation between the back gate including the back gate electrode layer 125 and the front gate including the word line, a plurality of carriers (e.g., holes) may accumulate in a portion of the back gate insulating layer 123 adjacent to the channel region 121C. The semiconductor pattern 121 is sequentially composed of a source region 121S, a channel region 121C, and a drain region 121D in the vertical direction (Z direction), and the length of each of the source region 121S, the channel region 121C, and the drain region 121D in the vertical direction (Z direction) can be greater than the thickness of each of the corresponding first conductive line 131, second conductive line 132, and third conductive line 133 in the vertical direction (Z direction). This is due to the replacement process of the first sacrificial layer SL1, the second sacrificial layer SL2, and the third sacrificial layer SL3 (see FIG. 6) corresponding to the first conductive line 131, the second conductive line 132, and the third conductive line 133. The channel isolation insulating layer 151 can be disposed, for example, in the vertical direction between adjacent semiconductor patterns 121 among the plurality of semiconductor patterns 121. The channel isolation insulating layer 151 includes: a horizontal portion 151A having a first thickness (e.g., in the vertical direction); and an edge portion 151B having a second thickness greater than the first thickness (e.g., in the vertical direction), and the plurality of semiconductor patterns 121 can be electrically separated / insulated from each other by the edge portion 151B. The upper surface and the lower surface of the edge portion 151B of the channel isolation insulating layer 151 have a circular shape 151R (e.g., in a cross-sectional view) due to a wet etching process. For example, the circular shape 151R can be formed by a combination of the etchant of the wet etching process and the materials of the line insulating layer 110, the source region 121S, the drain region 121D, and / or the back gate insulating layer 123. At the point where the back gate structure BG intersects the first interconnect IC1 at the top of the cell region CR, a first via V1 is provided. The upper surface of the first via V1 can contact the first interconnect IC1, and the lower surface of the first via V1 can be arranged to contact the back gate electrode layer 125. For example, the lower surface of the first via V1 may not contact the semiconductor pattern 121. In the extension region ER, the horizontal lengths of the first conductive line 131, the second conductive line 132, and the third conductive line 133 constituting one memory cell MC can be different from each other. For example, the first conductive line 131 can be longer than the second conductive line 132, and the second conductive line 132 can be longer than the third conductive line 133. For example, in the extension region ER, the first conductive line 131, the second conductive line 132, and the third conductive line 133 can have a trapezoidal shape. The first interconnect IC1 and the second interconnect IC2 of the present disclosure can be interconnecting lines for electrically connecting the components of the semiconductor memory device of the present disclosure. For example, each of the interconnecting lines IC1 and IC2 can be a conductor line formed of a conductive material. Therefore, in the extension region ER, the vertical lengths of the first conductive wire 131, the second conductive wire 132, and the third conductive wire 133 that form a memory cell MC connected to the second vias V2 of the second interconnect IC2 can be different from each other. For example, the second via V2 connected to the first conductive wire 131 can be longer than the second via V2 connected to the second conductive wire 132, and the second via V2 connected to the second conductive wire 132 can be longer than the second via V2 connected to the third conductive wire 133. Moreover, in the semiconductor memory device 10, the first interconnect IC1 and the second interconnect IC2 may not be electrically connected to each other. Therefore, the semiconductor memory device 10 according to an embodiment of the present invention can operate in a manner of storing data in the memory cell MC by using majority carriers accumulated in the back gate insulating layer 123. For example, the semiconductor memory device 10 can serve as and / or can be a dynamic random access memory (DRAM) capable of performing read / write operations without using a separate capacitor structure. For example, each group can be a memory cell and can store 1 bit of data without using a capacitor as the memory cell. In this way, a capacitorless semiconductor memory device 10 can be implemented. Since the semiconductor memory device 10 according to the technical concept of the present invention concept can have a high integration degree and high scalability and can significantly increase the read / write operation speed by a capacitorless vertical memory cell MC array structure to achieve high performance, the semiconductor memory device 10 can have excellent competitiveness and high reliability. As used herein, components described as "electrically connected" are configured such that electrical signals can be transmitted from one component to another (although the intensity of such electrical signals may attenuate when they are transmitted and such electrical signals can be selectively transmitted). FIG. 5 is a flowchart illustrating a method of manufacturing a semiconductor memory device according to an embodiment. Referring to FIG. 5, the method S10 of manufacturing a semiconductor memory device may include a process sequence of a first operation S110 to a ninth operation S190. When a certain embodiment can be implemented in a different manner, a specific process sequence can be implemented in an order different from the described order. For example, two consecutive processes can be implemented substantially simultaneously, or can be implemented in an order opposite to the described order. The method S10 for manufacturing a semiconductor memory device according to an aspect of the technical concept of the present invention may include: a first operation S110 of alternately stacking a line insulating layer and first to third sacrificial layers on a semiconductor substrate; a second operation S120 of forming a circular opening by removing some portions of the plurality of line insulating layers and some portions of the plurality of first to third sacrificial layers, and forming a back gate structure filling the circular opening; a third operation S130 of forming a line opening by removing other portions of the plurality of line insulating layers and other portions of the plurality of first to third sacrificial layers; a fourth operation S140 of forming a first horizontal space by removing the first sacrificial layer; a fifth operation S150 of doping a conductive impurity on sidewalls of the semiconductor pattern layer exposed by the first horizontal space and forming a conductive material filling the first horizontal space (e.g., completely filling the first horizontal space); a sixth operation S160 of forming a second horizontal space by removing the second sacrificial layer; a seventh operation S170 of conformally forming a front gate electrode layer on an inner wall of the second horizontal space and forming a conductive material filling an interior of the second horizontal space (e.g., completely filling the interior of the second horizontal space); an eighth operation S180 of forming a third horizontal space by removing a portion of the third sacrificial layer and a portion of the semiconductor pattern layer; and a ninth operation S190 of forming a filling insulating layer filling the line opening and the third horizontal space. Technical characteristics of each of the first operation S110 to the ninth operation S190 will be described in detail below with reference to FIGS. 6 to 14. FIGS. 6 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a process sequence according to an embodiment. For ease of explanation, the cell region CR (see FIG. 2) of the semiconductor memory device will be focused on for description. Referring to FIG. 6, a line insulating layer 110 and first, second, and third sacrificial layers SL1, SL2, and SL3 may be alternately stacked on a semiconductor substrate 101. First, a line insulating layer (e.g., a first line insulating layer) 110 and a third sacrificial layer SL3 may be formed on the semiconductor substrate 101. Next, a line insulating layer (e.g., a second line insulating layer) 110 and a first sacrificial layer SL1 may be formed on the third sacrificial layer SL3. Next, a line insulating layer (e.g., a third line insulating layer) 110 and a second sacrificial layer SL2 may be formed on the first sacrificial layer SL1. Next, a line insulating layer (e.g., a fourth line insulating layer) 110 and a first sacrificial layer SL1 may be formed on the second sacrificial layer SL2. Such a layered structure may be provided sequentially and repeatedly. The multiple wire insulation layers 110 and the multiple first sacrificial layers SL1, second sacrificial layers SL2, and third sacrificial layers SL3 can be formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD) processes, respectively, but the concept of the present invention is not limited thereto. In some embodiments, each of the multiple wire insulation layers 110 and the multiple first sacrificial layers SL1, second sacrificial layers SL2, and third sacrificial layers SL3 can be formed of materials having an etching selectivity relative to each other. For example, the multiple wire insulation layers 110 can be formed using silicon oxide, and each of the multiple first sacrificial layers SL1, second sacrificial layers SL2, and third sacrificial layers SL3 can be formed using different silicon-based materials. Each of the multiple wire insulation layers 110 and the multiple first sacrificial layers SL1, second sacrificial layers SL2, and third sacrificial layers SL3 can have a thickness of about several tens of nanometers (nm), but the concept of the present invention is not limited thereto. Referring to FIG. 7, a mask pattern (not shown) is formed on the uppermost wire insulation layer 110, and the mask pattern is used as an etching mask so that a circular opening 120H penetrating through the multiple wire insulation layers 110 and the multiple first sacrificial layers SL1, second sacrificial layers SL2, and third sacrificial layers SL3 can be formed. The circular opening 120H can expose the upper surface of the semiconductor substrate 101. In some embodiments, the circular openings 120H can be spaced apart from each other in the horizontal direction (X direction and Y direction) and extend in the vertical direction (Z direction) (e.g., along the length direction). Each circular opening 120H is illustrated as having the same horizontal width throughout its entire height, but can have a tapered shape in which the horizontal width decreases toward the semiconductor substrate 101. Each circular opening 120H is illustrated as having a circular horizontal cross-section (see FIG. 3), but is not limited thereto. First, a semiconductor pattern 121 can be formed on the inner wall of the circular opening 120H. The semiconductor pattern 121 can be formed using at least one of a thermal oxidation process, CVD, PECVD, or ALD process. The semiconductor pattern 121 can be formed to cover the two inner walls of the multiple wire insulation layers 110 and the inner walls of the multiple first sacrificial layers SL1, second sacrificial layers SL2, and third sacrificial layers SL3. In some embodiments, the semiconductor pattern 121 can be formed of polycrystalline silicon lightly doped with P-type impurities. Next, a back gate insulating layer 123 can be formed on the inner wall of the semiconductor pattern 121. The back gate insulating layer 123 can be formed using at least one of a thermal oxidation process, CVD, PECVD, or ALD process. In some embodiments, the back gate insulating layer 123 can be formed of silicon oxide. Next, a back gate electrode layer 125 can be formed to fill the remaining portion of the circular opening 120H. In some embodiments, the back gate electrode layer 125 can be formed of a metal or a metal compound. Referring to FIG. 8, a mask pattern (not shown) is formed on the uppermost line insulating layer 110, and the mask pattern is used as an etching mask so that line openings 130H can be formed by removing some portions of the plurality of line insulating layers 110 and some portions of the plurality of first sacrificial layers SL1, second sacrificial layers SL2, and third sacrificial layers SL3. Each line opening 130H can expose the upper surface of the semiconductor substrate 101. The line openings 130H can be formed to be spaced apart from the circular opening 120H in a first horizontal direction (X direction). In some embodiments, the line openings 130H can be spaced apart from each other in the first horizontal direction (X direction) / along the first horizontal direction (X direction) and can extend along a second horizontal direction (Y direction). In FIG. 8, each line opening 130H is illustrated as having the same horizontal width throughout its entire height, but can have a tapered shape in which the horizontal width decreases in a direction closer to the semiconductor substrate 101. Referring to FIG. 9, a plurality of first horizontal spaces 131S that communicate with and are connected to the line openings 130H can be formed by removing the first sacrificial layer SL1 (e.g., by removing all of the first sacrificial layer SL1 (see FIG. 8) exposed through the line openings 130H). Since the first horizontal spaces 131S are formed by removing the first sacrificial layer SL1 (see FIG. 8) exposed through the line openings 130H, the thickness occupied by the first horizontal spaces 131S can be substantially the same as the thickness of the first sacrificial layer SL1 (see FIG. 8). In this document, for ease of explanation, spatial relative terms such as "beneath", "below", "lower", "above", "upper", "downward", "upward", etc. may be used to describe the relationship between one element or feature illustrated in the figures and another (other) element or feature. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device in the figure is flipped, an element described as being "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" can encompass both upward and downward orientations. The device can have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are accordingly interpreted. Referring to FIG. 10, the portions of the sidewalls of the semiconductor pattern 121 exposed by the first horizontal space 131S (see FIG. 9) are heavily doped with impurities of the first conductivity type to form a source region 121S and a drain region 121D. Here, the first conductivity type can be N-type, and for example, the source region 121S and the drain region 121D can be N+ regions heavily doped with N-type impurities. In some embodiments, the doping process of the impurities of the first conductivity type can be implemented by a vapor doping process or a plasma doping process. Therefore, a channel region 121C can be formed between the source region 121S and the drain region 121D. The channel region 121C can be a region lightly doped with impurities of the second conductivity type. Here, the second conductivity type can be P-type, and for example, the channel region 121C can be a P region lightly doped with P-type impurities. As described above, the doping process of the impurities of the second conductivity type can be implemented together during the formation of the semiconductor pattern 121. Next, a conductive material can be formed to fill the first horizontal space 131S, for example, completely fill the first horizontal space 131S (see FIG. 9). The conductive material can be formed of a metal (e.g., tungsten) or a metal compound. In some embodiments, the conductive material facing the source region 121S can be the first conductive line 131 or the source line, and the conductive material facing the drain region 121D can be the third conductive line 133, the drain line, or the bit line. Referring to FIG. 11, a plurality of second horizontal spaces 132S connected to and communicating with the line opening 130H can be formed by removing the second sacrificial layer SL2 (e.g., by removing all of the second sacrificial layer SL2 exposed through the line opening 130H (see FIG. 10)). Since the second horizontal space 132S is formed by removing the second sacrificial layer SL2 (see FIG. 10) exposed through the via opening 130H, the thickness occupied by the second horizontal space 132S can be substantially the same as the thickness of the second sacrificial layer SL2 (see FIG. 10). Terms such as "same", "equal", "planar", or "coplanar" as used herein encompass equality or near equality including possible variations such as may occur due to the manufacturing process. The term "substantially" may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. Referring to FIG. 12, a front gate insulating layer 140 is conformally formed on the inner wall of the second horizontal space 132S (see FIG. 9), and a conductive material may be formed to fill the remaining interior of the second horizontal space 132S, such as completely filling the remaining interior of the second horizontal space 132S (see FIG. 9). The front gate insulating layer 140 may be formed of silicon oxide. The front gate insulating layer 140 may be conformally formed along the inner wall of the second horizontal space 132S (see FIG. 9). The conductive material may be formed of a metal (e.g., tungsten) or a metal compound. In some embodiments, the conductive material facing the channel region 121C may be the second conductive line 132, the front gate electrode layer, or the word line. Through this process, the plurality of front gate electrode layers may be formed to be spaced apart from each other in the vertical direction (Z direction) such that the plurality of front gate electrode layers correspond to one back gate electrode layer 125. Referring to FIG. 13, a plurality of third horizontal spaces 133S connected to and communicating with the via opening 130H may be formed by removing the third sacrificial layer SL3 (e.g., by removing all of the third sacrificial layer SL3 (see FIG. 12) exposed through the via opening 130H). Since the third horizontal space 133S is formed by removing the third sacrificial layer SL3 (see FIG. 12) exposed through the via opening 130H, the thickness occupied by the third horizontal space 133S can be substantially the same as the thickness of the third sacrificial layer SL3 (see FIG. 12). In addition, a third vertical space 133T connected to and communicating with the third horizontal space 133S may be formed by removing the portion of the semiconductor pattern 121 exposed through the third horizontal space 133S. For example, in a cross-sectional view, the upper and lower portions of the third vertical space 133T may have a circular shape 133R. This may be due to the wet etching process used to form the third vertical space 133T. For example, the circular shape 133R may be formed by a combination of an etchant of the wet etching process and the materials of the line insulating layer 110, the semiconductor pattern 121, and / or the back gate insulating layer 123. Referring to FIG. 14, a fill insulating layer 150 may be formed to fill the line opening 130H, the third horizontal space 133S, and the third vertical space 133T. The fill insulating layer 150 may be formed of, for example, silicon oxide, silicon nitride, or a combination thereof. Here, the fill insulating layer 150 that fills the third horizontal space 133S and the third vertical space 133T may be a channel isolation layer 151. For example, the channel isolation insulating layer 151 may include a horizontal portion 151A that fills the third horizontal space 133S and an edge portion 151B that fills the third vertical space 133T. Returning to FIGS. 1 and 2, a semiconductor memory device 10 according to the technical concept of the present invention concept is completed by forming a first interconnect IC1 on top of the plurality of memory cells MC formed as described above. FIG. 15 is a conceptual diagram illustrating a semiconductor die 20 including a semiconductor memory device according to an embodiment. Referring to FIG. 15, the semiconductor die 20 may include a volatile memory structure 220 and a non-volatile memory structure 230 located on a peripheral circuit region 210. The volatile memory structure 220 and the non-volatile memory structure 230 may be embedded in a substrate including the peripheral circuit region 210, or may be mounted on the substrate as a form of semiconductor wafers (e.g., a volatile memory wafer 220 and a non-volatile memory wafer 230). Circuit elements required to drive the memory devices included in the volatile memory structure 220 and the non-volatile memory structure 230 may be provided in the peripheral circuit region 210. The circuit elements may be, for example, a read circuit or a write circuit, but are not limited thereto. In the volatile memory structure 220, a semiconductor memory device 10 according to the technical concept of the present invention concept (see FIG. 1) may be provided. For example, the volatile memory structure 220 may be a vertical capacitor-less DRAM. The non-volatile memory structure 230 may include vertical memory cells having the same or a similar structure as the structure of the semiconductor memory device 10 (see FIG. 1) according to an embodiment or a technical concept of the present invention concept. For example, the non-volatile memory structure 230 may be a vertical anti-ferroelectric flash memory. Therefore, according to an embodiment or technical concept of the present invention, by forming a volatile memory structure 220 and a non-volatile memory structure 230 having a similar structure to each other in a peripheral circuit region 210, the memory hierarchy can be reduced, enabling high speed, and at the same time, some of the manufacturing processes are the same, so that a hybrid memory that can be produced at low cost can be manufactured. FIG. 16 is a configuration diagram of a system including a semiconductor memory device according to an embodiment. Referring to FIG. 16, the system 1000 includes a controller 1010, an input / output device 1020, a storage device 1030, an interface 1040, and a bus 1050. The system 1000 may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card. The controller 1010 is used to control executable programs in the system 1000 and may include a microprocessor, a digital signal processor, a microcontroller, or a similar device. The input / output device 1020 can be used to input data into the system 1000 or output data from the system 1000. The system 1000 can be electrically connected to an external device (e.g., a personal computer or a network) using the input / output device 1020 and can exchange data with the external device. The input / output device 1020 can be, for example, a touch screen, a touch pad, a keyboard, and / or a display. The storage device 1030 can store data for operating the controller 1010 or data processed by the controller 1010. The storage device 1030 can include the semiconductor memory device 10 according to an embodiment of the technical concept of the present invention described above. The interface 1040 can be a data transmission path between the system 1000 and an external device. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 can communicate with each other via the bus 1050. Even though different figures illustrate variations of exemplary embodiments and different embodiments disclose different features from each other, these figures and embodiments are not necessarily intended to be mutually exclusive. More precisely, when considering the figures and the related descriptions of the embodiments as a whole, the features illustrated in different figures and / or described above in different embodiments can be combined with other features of other figures / embodiments to produce additional variations of the embodiments. For example, the components and / or features of the different embodiments described above can be interchangeably or additionally combined with the components and / or features of other embodiments to form additional embodiments, unless the context otherwise indicates. While aspects of the inventive concept have been particularly shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made to the aspects of the inventive concept without departing from the spirit and scope of the following claims. 10: Semiconductor memory device 20: Semiconductor die 101: Semiconductor substrate 110: Line insulating layer 120H: Circular opening 121: Semiconductor pattern 121C: Channel region 121D: Drain region 121S: Source region 123: Back gate insulating layer 125: Back gate electrode layer 130H: Line opening 131: First conductive line 131S: First horizontal space 132: Second conductive line 132S: Second horizontal space 133: Third conductive line 133R, 151R: Shape of circle 133S: Third horizontal space 133T: Third vertical space 140: Front gate insulating layer 150: Filling insulating layer 151: Channel isolation insulating layer / channel isolation layer 151A: Horizontal portion 151B: Edge portion 210: Peripheral circuit region 220: Volatile memory structure / volatile memory die 230: Non-volatile memory structure / non-volatile memory die 1000: System 1010: Controller 1020: Input / output device 1030: Storage device 1040: Interface 1050: Bus BG: Back gate structure CR: Cell region ER: Extension region IC1: First interconnect / interconnect line IC2: Second interconnect / interconnect line MC: Memory cell IV: Region / area R1, R2: Radius S10: Method / fabrication method S110: First operation S120: Second operation S130: Third operation S140: Fourth operation S150: Fifth operation S160: Sixth operation S170: Seventh operation S180:第八操作 S190:第九操作 SL1: First sacrificial layer SL2: Second sacrificial layer SL3: Third sacrificial layer V1: First via V2: Second via X: First horizontal direction / direction Y: Second horizontal direction / direction Z: Vertical direction / direction Embodiments of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a perspective view illustrating a semiconductor memory device according to an embodiment. FIG. 2 is a perspective view illustrating the cell region of FIG. 1. FIG. 3 is a plan view illustrating the cell region of FIG. 1. FIG. 4 is an enlarged perspective view of region IV of FIG. 2. FIG. 5 is a flowchart illustrating a method of manufacturing a semiconductor memory device according to an embodiment. FIGS. 6 to 14 are cross-sectional views illustrating a method of sequentially manufacturing a semiconductor memory device according to an embodiment of the inventive concept. FIG. 15 is a conceptual diagram illustrating a semiconductor die including a semiconductor memory device according to an embodiment. FIG. 16 is a configuration diagram illustrating a system including a semiconductor memory device according to an embodiment. 10: Semiconductor memory device 101: Semiconductor substrate 131: First conductive line 132: Second conductive line 133: Third conductive line 151: Channel isolation insulating layer / Channel isolation layer CR: Cell region ER: Extension region IC1: First interconnect / Interconnect line IC2: Second interconnect / Interconnect line V1: First via hole V2: Second via hole X: First horizontal direction / Direction Y: Second horizontal direction / Direction Z: Vertical direction / Direction

Claims

1. A semiconductor memory device, comprising: Semiconductor substrate; A back gate structure having a cylindrical shape and extending vertically on the semiconductor substrate, and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer; a plurality of semiconductor patterns, each having an annular horizontal segment surrounding the back gate structure and spaced apart from each other in the vertical direction; a first conductive line, a second conductive line, and a third conductive line surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction; a front gate insulating layer disposed continuously surrounding the semiconductor pattern and the second conductive line, on the upper surface of the second conductive line, and on the lower surface of the second conductive line; and a channel isolation insulating layer disposed between adjacent semiconductor patterns among the plurality of semiconductor patterns, wherein the regions of the semiconductor patterns facing the first conductive line and the third conductive line are doped with impurities of a first conductivity type, and wherein the regions of the semiconductor patterns facing the second conductive line are doped with impurities of a second conductivity type opposite to the impurities of the first conductivity type.

2. The semiconductor memory device as claimed in claim 1, wherein the semiconductor pattern is each composed of a source region, a channel region, and a drain region arranged sequentially in the vertical direction, wherein the source region faces the first conductive line and is doped with an N-type impurity, wherein the channel region faces the second conductive line and is doped with a P-type impurity, and wherein the drain region faces the third conductive line and is doped with an N-type impurity.

3. The semiconductor memory device of claim 2, wherein the length of each of the source region, the channel region, and the drain region along the vertical direction is greater than the thickness of each of the corresponding first conductive line, the second conductive line, and the third conductive line.

4. The semiconductor memory device of claim 1, wherein the channel isolation insulating layer includes a horizontal portion having a first thickness and an edge portion having a second thickness greater than the first thickness, wherein the plurality of semiconductor patterns are electrically separated from each other by the edge portion of the channel isolation insulating layer.

5. The semiconductor memory device as claimed in claim 4, wherein the upper and lower surfaces of the edge portion of the channel isolation insulating layer have a circular shape.

6. The semiconductor memory device as claimed in claim 1, further comprising: Multiple wire insulation layers are disposed between the first conductive wire, the second conductive wire and the third conductive wire, below the first conductive wire and above the third conductive wire.

7. The semiconductor memory device of claim 6, wherein the sidewall of each of the first conductive line and the third conductive line contacts the semiconductor pattern, wherein the sidewall of the second conductive line contacts the front gate insulating layer.

8. The semiconductor memory device of claim 1, wherein a plurality of the second conductive lines are arranged to face a back gate structure, wherein the semiconductor memory device is configured such that holes accumulate in the region of the back gate insulating layer facing the second conductive lines for a preset time.

9. The semiconductor memory device of claim 1, wherein a linear first interconnect is provided on the back gate structure, and a first via is provided at the point where the back gate structure and the first interconnect intersect.

10. The semiconductor memory device of claim 9, wherein the upper surface of the first via contacts the first interconnect, and the lower surface of the first via contacts the back gate electrode layer.

Images