Molded direct bonded and interconnected stack

Abstract

This invention relates to dies and / or wafers that are stacked and bonded in various configurations, including stacks, and may be covered with a molding compound to facilitate handling, packaging, and similar operations. In various examples, the molding compound may more or less cover a stack to facilitate connectivity with devices on the stack, enhance thermal management, and so on.

Description

Molded directly bonded and interconnected stacks The following description relates to the processing of integrated circuits ("ICs"). More specifically, the following description relates to techniques for packaging dies or wafers and other microelectronic components. [Cross-reference to Priority Claims and Related Applications] This application claims the benefit of U.S. Non-Provisional Application No. 16 / 460,068, filed on July 2, 2019, and U.S. Provisional Application No. 62 / 694,845, filed on July 6, 2018, which are incorporated herein by reference in their entirety. Microelectronic components typically consist of a thin or thick block of semiconductor material (such as silicon or gallium arsenide), which is often referred to as a semiconductor wafer. Wafers can be formed to include multiple integrated chips or dies on the surface of the wafer and / or partially embedded within the wafer. Dies separated from the wafer are typically provided as individual pre-packaged units. In some packaging designs, the die are mounted to a substrate or wafer carrier, which is in turn mounted on a circuit board such as a printed circuit board (PCB). For example, many dies are arranged in a package suitable for surface mounting. Packaged semiconductor dies may also be provided in a "stacked" configuration, where one package is disposed on, for example, a circuit board or other carrier, and another package is adhered on top of the first package. These configurations can allow several different dies or devices to be adhered within a single footprint on a circuit board, and can further facilitate high-speed operation by providing short interconnects between packages. Typically, this interconnect distance may be only slightly greater than the thickness of the die itself. For interconnections to be achieved within a stack of die packages, interconnect structures for mechanical and electrical connections may be provided on both sides (e.g., faces) of each die package (except the topmost package). Additionally, dies or wafers can be stacked in three-dimensional configurations as part of various microelectronic packaging solutions. This can include stacking one or more layers of dies, devices, and / or wafers on a larger base die, device, wafer, substrate, or the like, stacking multiple dies or wafers in vertical or horizontal configurations, and various combinations of both. The die or wafers can be bonded in a stacked configuration using a variety of bonding techniques, including direct dielectric bonding, adhesiveless techniques such as ZiBond®, or hybrid bonding techniques such as DBI®, all available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), Xperi Corporation. Direct dielectric bonding techniques involve a spontaneous covalent bonding process that occurs under ambient conditions without the need for adhesives or intervening materials when two prepared dielectric surfaces are bonded together, while hybrid bonding techniques add metal-to-metal bonding of corresponding metal bond pads at the bonding surfaces of the corresponding die or wafers, also without the need for intervening materials, to form a unified conductive structure (see, e.g., U.S. Patent Nos. 6,864,585 and 7,485,968, which are incorporated herein by reference in their entirety). Heat annealing of the metal bond pads can be used to strengthen the metal-to-metal bond. The corresponding mating surfaces of the bonded dies or wafers typically include embedded conductive interconnect structures (which may be metal) or the like. In some examples, the bonding surfaces are configured and aligned so that the conductive interconnect structures from the corresponding surfaces bond during bonding. The bonded interconnect structures form a continuous conductive interconnect (for signals, power, etc.) between the stacked dies or wafers. Implementing stacked die and wafer configurations can present various challenges. When using direct or hybrid bonding techniques to bond stacked die or wafers, the surfaces of the die or wafers to be bonded generally require extremely flat, smooth, and clean surfaces. For example, these surfaces should generally have very low surface topological deviations (i.e., nanometer-scale deviations) so that they can mate tightly together to form a continuous bond. Double-sided dies or wafers can be formed and prepared for stacking and bonding, where both sides of the die or wafer will be bonded to other substrates, wafers, or dies, such as in multiple die-to-die or die-to-wafer applications. Preparing both sides of the die or wafer includes surface treatment of both surfaces to meet dielectric roughness specifications and metal layer (e.g., copper) recess specifications. Hybrid surfaces can be prepared using chemical mechanical polishing (CMP) processes, plasma processes, wet and dry cleaning methods, or the like for bonding to another die, wafer, or other substrate. It may be desirable to package stacked and bonded dies and wafers in various configurations for connectivity diversity, performance optimization, and enhanced thermal management. A first aspect of the present invention is a microelectronic assembly comprising: a first substrate having a first bonding surface and a first microelectronic circuit element embedded in the first substrate, a portion of the first circuit element of the first substrate being exposed at the first bonding surface of the first substrate; a second substrate having a first bonding surface and the first microelectronic circuit element embedded in the second substrate, a portion of the first circuit element of the second substrate being exposed at the first bonding surface of the second substrate, the first bonding surface of the second substrate being hybrid-bonded to the first bonding surface of the first substrate without an adhesive such that the first circuit element of the second substrate is electrically coupled to the first circuit element of the first substrate, wherein side edges of the first substrate are misaligned relative to side edges of the second substrate; and a molding covering at least the side edges of the second substrate. The microelectronic assembly of the first aspect further includes a first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate. In a first aspect of the microelectronic assembly, the first substrate includes a second surface opposite the first bonding surface, and wherein the first conductive via extends to the second surface of the first substrate and provides electrical connectivity from the first bonding surface of the first substrate to the second surface of the first substrate. The microelectronic assembly of the first aspect further comprises a terminal connector coupled to the second surface of the first substrate and electrically coupled to the first conductive via. In the first aspect of the microelectronic assembly, the second substrate includes a second bonding surface opposite to the first bonding surface and a second microelectronic circuit element embedded in the second substrate, with a portion of the second circuit element of the second substrate exposed at the second bonding surface of the second substrate. The microelectronic assembly of the first aspect further comprises a second conductive via electrically coupled to the first circuit element and the second circuit element of the second substrate and extending at least partially through the second substrate, the second conductive via providing electrical connectivity from the first bonding surface of the second substrate to the second bonding surface of the second substrate. In the first aspect of the microelectronic assembly, the second conductive via provides electrical connectivity from the second surface of the first substrate to the second bonding surface of the second substrate, the second surface of the first substrate being opposite the first bonding surface of the first substrate. The microelectronic assembly of the first aspect further comprises a third substrate having a first bonding surface and a first microelectronic circuit element embedded in the third substrate, a portion of the first circuit element of the third substrate being exposed at the first bonding surface of the third substrate, the first bonding surface of the third substrate being bonded to the second bonding surface of the second substrate such that the first circuit element of the third substrate is electrically coupled to the second circuit element of the second substrate. In the first aspect of the microelectronic assembly, a side edge of the third substrate is misaligned with respect to the front side edge of the second substrate or the front side edge of the first substrate. In the first aspect of the microelectronic assembly, the molding covers the front side edge of the first substrate, the front side edge of the second substrate, and the front side edge of the third substrate. In the microelectronic assembly of the first aspect, the molding covers the front side edge of the second substrate and the front side edge of the third substrate, but does not cover the front side edge of the first substrate. In the first aspect of the microelectronic assembly, the molding covers a second surface of the third substrate opposite to the first bonding surface of the third substrate. In a first aspect of the microelectronic assembly, the molding covers a second surface of the second substrate opposite to the first bonding surface of the first substrate. A second aspect of the various aspects of the present invention is a microelectronic component comprising a plurality of microelectronic components of the first aspect. In a second aspect of the microelectronic assembly, the footprints of the first, second, and third substrates are non-uniform, and wherein an outer side edge of the molding extending from the first substrate to the third substrate is planar. A third aspect of the present invention is a microelectronic assembly comprising: a plurality of stacks of molded microelectronic elements, each stack comprising: a first substrate having a first bonding surface and a first microelectronic circuit element embedded in the first substrate, a portion of the first circuit element of the first substrate being exposed at the first bonding surface of the first substrate, and a first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate; a second substrate having a first bonding surface and the first microelectronic circuit element embedded in the second substrate, the first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate; A first circuit element of each substrate is partially exposed at the first bonding surface of the second substrate, a second conductive via is electrically coupled to the first circuit element of the second substrate and extends at least partially through the second substrate, the first bonding surface of the second substrate is hybrid-bonded to the first bonding surface of the first substrate without an adhesive, such that the first circuit element of the second substrate is electrically coupled to the first circuit element of the first substrate, wherein side edges of the first substrate are misaligned relative to side edges of the second substrate; and a molding covering at least the aforementioned side edges of the second substrate. In a third aspect of the microelectronic assembly, the first substrate includes a second surface opposite the first bonding surface, and wherein the first conductive via extends to the second surface of the first substrate and provides electrical connectivity from the first bonding surface of the first substrate to the second surface of the first substrate. In a third aspect of the microelectronic assembly, the second substrate includes a second bonding surface opposite the first bonding surface and a second microelectronic circuit element embedded in the second substrate, a portion of the second circuit element of the second substrate is exposed at the second bonding surface of the second substrate, and wherein the second conductive through-hole is electrically coupled to the second circuit element of the second substrate. In a third aspect of the microelectronic assembly, at least one of the first bonding surface and the second bonding surface of the second substrate includes an intentional recess at a peripheral edge of the second substrate. In a third aspect of the microelectronic component, the molded article comprises a first low-viscosity compound without particles, the first low-viscosity compound penetrates the recess at the peripheral edge of the second substrate, and a second compound with particles covers the first low-viscosity compound. The microelectronic assembly of the third aspect further comprises a laminate and / or an interposer, and wherein the plurality of molded microelectronic elements are stacked and hybrid-bonded to the laminate or the interposer without adhesives or interposer materials. The microelectronic assembly of the third aspect further comprises at least one wire bond pad on the surface of the laminate and / or on the surface of the interposer. In the microelectronic assembly of a third aspect, the laminate is coupled to the interposer using wires coupled at wire bond pads on a surface of the laminate and at wire bond pads on a surface of the interposer. The microelectronic assembly in a third aspect further comprises a non-molded die hybrid-bonded to the laminate and / or the interposer without an adhesive. In a third aspect of the microelectronic assembly, at least the second substrate includes a solid-state memory device. A fourth aspect of the present invention is a method of forming a microelectronic assembly, comprising: forming a microelectronic stack, comprising: providing a first substrate having a front side and a back side, the back side having a bonding surface comprising a non-conductive bonding layer and an exposed electrically conductive first circuit element, the first substrate having a first conductive via, the first conductive via being electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate; providing a second substrate having a front side and a back side, the front side comprising a non-conductive bonding layer and an exposed electrically conductive first circuit element; coupling the front side of the second substrate to the back side of the first substrate by contacting the non-conductive bonding layer of the first substrate with the non-conductive bonding layer of the second substrate, side edges of the first substrate being misaligned relative to side edges of the second substrate, and contacting the first circuit element of the first substrate with the first circuit element of the second substrate; and covering at least the aforementioned side edges of the second substrate with a molding. The method of the fourth aspect further comprises covering the back side of the second substrate with the molding. In a fourth aspect of the method, the back side of the second substrate includes a second non-conductive bonding layer and an exposed electrically conductive second circuit element, the second substrate having a second conductive via electrically coupling the first circuit element and the second circuit element of the second substrate. The method of the fourth aspect further includes: providing a third substrate having a front side and a back side, the front side including a non-conductive bonding layer and an exposed electrically conductive first circuit element; coupling the front side of the third substrate to the back side of the second substrate by contacting the non-conductive bonding layer of the third substrate with the non-conductive bonding layer of the second substrate, side edges of the third substrate being misaligned relative to side edges of the second substrate and / or side edges of the first substrate, and contacting the first circuit element of the third substrate with the second circuit element of the second substrate; and covering the aforementioned side edges of the third substrate with the molding. The method of the fourth aspect further includes forming a recess at the bonding layer of the first substrate at a periphery of the first substrate and / or at the bonding layer of the second substrate at a periphery of the second substrate, and filling at least the recess with a low-viscosity compound before covering the side edges of the first substrate and the side edges of the second substrate with the molded object. The method of the fourth aspect further comprises hybrid bonding the microelectronic stack to a semiconductor interposer having at least one wire bond contact pad. The method of the fourth aspect further includes coupling the interposer to a laminate having a second wirebond contact pad, and bonding the at least one wirebond contact pad of the interposer to the second wirebond contact pad of the laminate with a wire. In a fourth aspect of the method, forming the microelectronic assembly includes forming a plurality of microelectronic stacks. A fifth aspect of the various aspects of the present invention is a microelectronic assembly comprising: a first die having a first bonding surface and a first microelectronic circuit element embedded in the first die, a portion of the first circuit element being exposed at the first bonding surface of the first die; and a second die having a first bonding surface and a first microelectronic circuit element embedded in the second die, a portion of the first circuit element of the second die being exposed at the first bonding surface of the second die, the first bonding surface of the first die being hybrid-bonded to the first bonding surface of the second die such that the first die is electrically coupled to the second die without an adhesive layer, wherein a side edge of the first die comprises a mold layer that is thinner than a mold layer disposed on the side edge of the second die. A sixth aspect of the various aspects of the present invention is a microelectronic assembly comprising: a first die having a first bonding surface comprising a first microelectronic circuit element; a second die having a first bonding surface comprising a second microelectronic circuit element; the first bonding surface of the first die being hybrid-bonded to the first bonding surface of the second die such that the first die is electrically coupled to the second die without requiring an adhesive layer; and a molding layer disposed on side edges of the first die and side edges of the second die, wherein a thickness of the molding layer on the first die is different from a thickness of the molding layer on the second die. The microelectronic assembly of the sixth aspect further comprises a first conductive via electrically coupled to the first circuit element of the first die and extending at least partially through the first die. In the microelectronic assembly of a sixth aspect, the first bonding surface of the first die or the first bonding surface of the second die includes a plurality of circuit elements having a pitch less than 20 microns. In the microelectronic assembly of a sixth aspect, the first bonding surface of the first die or the first bonding surface of the second die includes a plurality of circuit elements having a pitch less than 1 micron. Overview Representative techniques and devices are disclosed, including process steps for stacking and bonding dies and / or wafers, including hybrid bonding of die-to-die, die-to-wafer, and wafer-to-wafer without adhesives. In various embodiments, the dies and / or wafers are stacked and bonded in various configurations, including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various embodiments, the molding may more or less cover a stack to facilitate connectivity with the stacked devices, enhance thermal management, and so on. Various implementations and configurations are discussed with reference to electrical and electronic components and varying carriers. Although reference is made to specific components (i.e., die, wafers, integrated circuit (IC) chip dies, substrates, etc.), this is not intended to be limiting, but rather for ease of discussion and convenience of illustration. The techniques and devices discussed with reference to wafers, die, substrates, or the like are applicable to any type or number of electrical components, circuits (e.g., integrated circuits (ICs), hybrid circuits, ASICS, memory devices, processors, etc.), groups of components, passive components, Micro-Electro Mechanical Systems (MEMS) components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), and the like, which can be integrated and coupled to interface with each other, external circuits, systems, carriers, and the like. Each of these different components, circuits, groups, packages, structures, and the like may be generally referred to as a "microelectronic component." For simplicity, a component joined to another component will be referred to herein as a "die," unless otherwise specified. Illustrative Specific Examples FIG1 is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and molded article according to one embodiment. In the illustrated example, stack 100 (or microelectronic assembly 100) is formed by stacking and bonding (e.g., hybrid bonding without adhesive) a plurality of dies 102 (e.g., any desired number of dies 102). In an alternative embodiment, stack 100 is formed by stacking and bonding (e.g., hybrid bonding without adhesive) a plurality of wafers, which are subsequently singulated into the dies 102 shown in FIG1 . In one embodiment, as shown in FIG1 , the dies 102 in stack 100 may not be perfectly aligned. In other words, the edges of the dies 102 are not precisely aligned, and there is some error or misalignment "e" from one die 102 to another in stack 100. In various examples, the misalignment "e" may be attributable to accuracy tolerances of pick-and-place tools or the like. A die 102 (or wafer) can be formed using various techniques to include a base substrate 104 and one or more insulating or dielectric layers 106. For example, the die 102 shown in FIG. 1 may represent a double-sided die 102 having insulating layers 106 on both surfaces of the base layer 104. As also shown in FIG. 1 , a die 102 ′ may also be included, which may be a single-sided or double-sided primary die or primary wafer. A single-sided die 102 or 102 ′ may be positioned in the stack 100 as the top die 102, the bottom die 102, or as any other die 102 in the stack 100 where direct bonding connections to both sides of the die 102 are not required. Unless otherwise specified, reference to a “die 102” as used herein includes both single-sided and double-sided dies and wafers. The base substrate 104 may include silicon, germanium, glass, quartz, a dielectric surface, a direct or indirect bandgap semiconductor material or layer, or another suitable material. The insulating layer 106 is deposited or formed over the substrate 104 and may include a layer of an inorganic dielectric material such as an oxide, nitride, oxynitride, oxycarbide, carbide, carbonitride, diamond, diamond-like material, glass, ceramic, glass-ceramic, and the like. The bonding surface 108 of the die 102 may include conductive features 110, such as TSVs, traces, pads, and interconnect structures, which are embedded in the insulating layer 106, for example, and are configured so that during bonding, conductive features 110 from corresponding bonding surfaces 108 of opposing devices can be optionally matched and combined. The combined conductive features 110 can form a continuous conductive interconnect (for signal, power, ground, etc.) between the stacked devices. A damascene process (or similar process) can be used to form embedded conductive features 110 in the insulating layer 106. The conductive features 110 can include metal (e.g., copper, etc.) or other conductive materials or combinations of materials and include structures, traces, pads, patterns, and the like. In some examples, a barrier layer can be deposited in the cavity for the conductive features 110 prior to depositing the material for the conductive features 110, such that the barrier layer is disposed between the conductive features 110 and the insulating layer 106. The barrier layer can include a tantalum layer, a titanium layer, a tungsten layer, or a combination thereof (e.g., or another conductive material) with their respective compounds or alloys to prevent or reduce diffusion of the material of the conductive features 110 into the insulating layer 106. After forming the conductive features 110, the exposed surface of the device wafer 102 (including the insulating layer 106 and the conductive features 110) can be planarized (e.g., via CMP) to form a planar bonding surface 108. Forming bonding surface 108 involves treating surface 108 to meet dielectric roughness specifications and, if required, metal layer (e.g., copper) recess specifications, thereby preparing surface 108 for hybrid bonding. In other words, bonding surface 108 is formed to be as flat and smooth as possible, with minimal (nanoscale) surface topological deviations. Various conventional processes, such as chemical mechanical polishing (CMP), dry or wet etching, etc., can be used to achieve low surface roughness. This process provides a flat and smooth surface 108 that produces a reliable bond. Embedded conductive traces 112 in the dielectric substrate 106, extending partially below the prepared surface 108, can be used to electrically couple conductive features 110 to desired components through the die 102. For example, the conductive features 110 can be coupled to conductive (e.g., copper) through-silicon vias (TSVs) 114 or the like, which extend partially or completely through the die 102 to form an electrical connection through the thickness of the die 102. For example, depending on the thickness of the die 102, the TSVs 114 can extend approximately 50 microns in some cases. The figures show examples of the die 102 having various configurations of conductive features 110, traces 112, and TSVs 114, which are not intended to be limiting. In various embodiments, some of the conductive features 110 , traces 112 , and TSVs 114 may not be present in the die 102 (or wafer), and in other embodiments, additional conductive features 110 , traces 112 , and TSVs 114 may be present, or other circuit components and the like may be present. Die 102 can be hybrid bonded to other dies 102 having metal pads 110, traces 112, and / or TSVs 114, for example, without adhesive, to form the necessary electrical connections through the die 102 when forming the stack 100. Hybrid bonding includes direct dielectric-to-dielectric bonding (e.g., ZIBOND®) of the respective insulating layers 106 of each die 102 without adhesive or other intervening materials, and direct metal-to-metal bonding (e.g., DBI®) of the respective conductive features 110 of each die 102, also without intervening materials. Dielectric-to-dielectric bonding occurs spontaneously when the respective bonding surfaces 108 are brought together at ambient temperature. Metal-to-metal bonding, which may include diffusion between the metals of the conductive features 110, can occur with or without pressure and by heating. As shown in FIG1 , electrical connectivity can be established from the top surface of the top die 102 of the stack 100 (e.g., via conductive features 110), through the die 102 (any number of dies 102) of the stack 100 (e.g., via conductive features 110, traces 112, and TSVs 114), and to the bottom surface of the bottom die 102 of the stack 100 (e.g., via TSVs 114). In the example of FIG1 , conductive features 110 provide connectivity to the top surface of the stack 100, and TSVs 114 having at least one electrical coupling pad 116 provide connectivity to the bottom surface of the bottom die 102 of the stack 100 (in some cases, a titanium layer (not shown) or the like can couple TSVs 114 to pads 116). In alternative embodiments, one or both of the top and bottom surfaces of the stack 100 may have no connectivity, or different means than shown may provide connectivity to either the top or bottom surface of the stack 100. For example, in some embodiments, the stack 100 may not include the conductive features 110 at the top surface of the stack 100 , or the TSVs 114 in the top die 102 , or the TSVs 114 and liner 116 in the bottom die 102 . In some embodiments, one or more of the TSVs 114 provide thermal connectivity between the dies 102. For example, the TSVs can help dissipate or transfer heat from some dies 102 to other dies 102 and / or to the external environment. In some embodiments, the TSVs 114 comprise a thermally conductive material and may include a thermally conductive barrier layer (not shown). In some examples, the TSVs 114 can be sized for optimal heat dissipation based on the function of the associated die 102 (e.g., heat generation). FIG2 is a cross-sectional view of a microelectronic assembly 200 that includes multiple stacks 100 of die 102. In some embodiments, each stack 100 includes the same number of die 102. In other embodiments, some stacks 100 may include a different number of die 102 than other stacks 100 of assembly 200. In one embodiment, as shown in FIG2 , the die 102 are not perfectly aligned within the stack 100. In other words, the edges of the die 102 are not precisely aligned within the stack 100, and there is some edge error or misalignment from die 102 to die 102. In some embodiments, the stacks 100 are singulated from a plurality of wafers that have been stacked and bonded as discussed above. In one embodiment, the bottom set of dies 102' comprises the main wafer 202 for stack 100. In one embodiment, the dies 102 can be stacked onto the main wafer 202, which is then singulated, if desired, at the boundaries of the stack 100. In other embodiments, the main wafer 202, if present, can be singulated at a different step in the process. As shown in Figure 2, one or more of the stacks 100 of components 200 may be covered in a molding 204 comprising a seal or the like. In various embodiments, the molding 204 may comprise a high-strength, high-thermal-stress (high-heat-resistant) seal material that may also have high heat dissipation characteristics. In addition, the molding 204 may need to have a coefficient of thermal expansion (CTE) of less than 20 to help control warpage. For example, HITACHI® offers such a seal or "epoxy molding compound," which is referred to as "CEL." Other similar products are also available. In one embodiment, the component 200 is covered with the molding 204, and then the component 200 is divided into multiple stacks 100. The individual stacks 100 may be covered with additional seals 204 as needed. In other embodiments, stack 100 is molded after the formation of stack 100, which includes stacking and bonding individual dies 102 into stack 100 or singulation of wafers to form dies 102 and stack 100. For example, mold 204 can be deposited before or after singulation of dies 102. In either case, mold 204 can cover the entire stack 100 of dies 102 or selected dies 102. For example, in one embodiment, main wafer 202 (and die 102') may not be covered with mold 204. This may be due to the manufacturing process or by design. For all embodiments disclosed herein, the molding 204 may comprise a single layer of sealant covering over and / or surrounding some or all of the die 102 in the stack 100, or the molding 204 may comprise multiple layers of sealant (e.g., a laminate) of the same or different materials. Furthermore, in one embodiment, the molding 204 comprises particles within the sealant, and the molding 204 has a progressive particle density, from a low or no particle state at either the top or bottom of the stack 100 to a higher particle density at the other of the top or bottom of the stack 100. In one example, particles, when present, may be present at varying densities in the multiple layers of the sealant. In various embodiments, the molding 204 comprises an inorganic housing or the like. In some examples, a molding 204 is added to the stack 100 and / or assembly 200 of die 102 to provide final packaging for the stack 100 or assembly 200. The stacking solution allows for ease of handling and assembly during processing, as well as deployment in applications. The molding 204 provides protection for the die 102 and stack 100, as well as the assembly 200 and any discrete components that may be packaged with the die 102. In one embodiment, as shown in FIG2 , the top surface of one or more of the stacks 100 (or all of the stacks 100 ) may be free of molding 204 . The bare top surface of the top die 102 can be used for further interconnection of the top die 102 of the stack 100 with other circuits, devices (e.g., optical, radio frequency (RF), analog, digital, logic, memory, or other devices), or the like, including, for example, additional dies 102 or the like of the component 200 (e.g., when conductive features 110 are present on the top surface of the top die 102 ). Alternatively or additionally, the top surface of the top die 102 may be covered to enhance heat dissipation. For example, heat can be more easily and efficiently dissipated from the die 102 without requiring encapsulation 204 on the top surface of the top die 102 of the component 200 . In such cases, the conductive features 110 (and traces 112 ) may not be present on the top surface of the top die 102 . For example, TSVs 114 may be present if they are used to help dissipate heat through the top surface. In one embodiment, component 200 includes one or more electrical contacts or terminals 206 at a surface (e.g., a bottom surface) of component 200. Terminals 206 can be used to electrically couple the component to another circuit, device, printed circuit board (PCB), or the like. As shown in FIG2 , terminals 206 can be electrically coupled to TSVs 114 (or other interconnects) of a die 102 (e.g., the bottom-most die 102) of a stack 100 of component 200 via pads 116. For example, component 200 can include electrical connectivity from the top die 102 of one or more of the stack 100 (e.g., in some cases, the top surface of the top die 102) through the die 102 of the stack 100 to terminals 206. In some embodiments, additional layers, circuit components, vias, and the like may also be incorporated into the stack 100 and / or assembly 200 as desired. In alternative embodiments, the TSVs 114 may be optional in some dies 102 and / or in some stacks 100. In one embodiment, as shown in FIG3 , the top surface of one or more of the stacks 100 (or all of the stacks 100) may include a molding 204. In one embodiment, the molding 204 at the top surfaces of the stacks 100 and components 200 protects the stacks 100 and components 200 during handling, assembly, deployment, and the like. In one embodiment, each of the stacks 100 is covered with molding 204, including the top and sides of the stacks 100. In one embodiment, the main wafer 202 (and die 102′) may not be covered with molding 204. As shown in the example of FIG3 , in some embodiments, when electrical connections are not formed at the top surfaces of the die 102 and components 200, the top die 102 of the component 200 may not include conductive features 110 (or traces 112 and / or TSVs 114). For example, these components may be optional when they serve other purposes (eg, when circuit components are disposed on or within the upper insulating layer 106, or the like). As also shown in the example of FIG3 , in some applications, the die 102 may have various configurations and arrangements of components. For example, as shown in FIG3 , the die 102″ may include TSVs 114 that are directly coupled to conductive pads 110 on adjacent die 102 to provide connectivity with adjacent bonded die 102. For example, end surfaces of the TSVs 114 may be exposed at the bonding surface 108 of the die 102″, thereby forming contact surfaces that bond with the conductive pads 110 on the adjacent die 102. In other specific examples, also shown in FIG3 , the die 102″ may include conductive pads 110 at the bonding surface, wherein the TSVs 114 are directly coupled to the conductive pads 110. These conductive pads 110 may be bonded to conductive pads 110 (or other conductive structures) on the adjacent die 102. In one embodiment, as shown in Figures 4 and 5, the entire stack 100, including the main wafer 202 and the die 102', can be covered with a molding 204. In one embodiment, the main wafer 202 can be singulated into the die 102' prior to the sealing step, thereby facilitating the main wafer to be covered with the molding 204. Multiple dies 102 can be stacked (in groups or one at a time) onto the main die 102' to form the stack 100, which can then be covered with the molding 204. Alternatively, the molding 204 can be applied to the assembly 200 after all the dies 102 are stacked and bonded into the stack 100. In any case, the molding 204 can be present on the sides of the stack 100. Furthermore, after the molding step in alternative embodiments, the stack 100 of the assembly 200 can be separated from each other. As shown, FIG4 illustrates an exemplary component 200 in which the top surfaces (i.e., backside) of the component 200 and stack 100 are free of molding 204. In one embodiment, molding 204 can be deposited over the component 200 and subsequently removed from the top surface of the stack 100. In various embodiments, molding 204 can be removed from the top surface of the stack 100 to provide interconnection with the top die 102 for improved heat dissipation or the like. FIG5 illustrates a case where the top surface (i.e., backside) is covered with molding 204. As shown in Figures 6 and 7, the die 102 of the stack 100 may not be uniform in size (e.g., size, area, footprint, thickness, etc.). Die 102 having different footprints or thicknesses, for example, may be stacked and bonded to form the stack 100. Without the molding 204, the stack 100 of non-uniform die 102 exhibits uneven side edges and / or varying heights of the stack 100. Covering the stack 100 with the molding 204 can present a uniform package (in side edges / surfaces and height) such as the stack 100 and / or the component 200. The example illustrated at FIG6 shows an embodiment in which the die 102 is covered with the molding 204, but the main wafer (main die 102′) is not covered with the molding 204. In some embodiments, the thickness of the molding layer 204 on the side edges of the top die 102 is thicker than the thickness of the molding layer 204 disposed on the side edges of the second die 102 below. The example of FIG7 shows an embodiment in which the die 102 and the main die 102′ are all covered with the molding 204, as discussed above. As shown in Figures 8 and 9, in some embodiments, the stack 100 may include dies 102 that have interconnects on one side and no interconnects on the other side. For example, as shown in the diagram, the top die 102 may not have interconnects to the top surface of the die 102. In such cases, no interconnects may be required on the top (e.g., back) surface of the stack 100 or component 200. In alternative embodiments, other dies 102 may include interconnects on only one side. In some embodiments, TSVs 114 may also be optionally used for the top die 102; however, the TSVs 114 may be used for heat dissipation. In some examples, as shown in Figures 8 and 9, a heat sink 802 or other components 902 (e.g., sensors, optical components, etc.) can be included in the stack 100. For example, the heat sink 802 can be located at the top of the stack 100 to help dissipate heat from one or more dies 102 in the stack 100 to the environment. In some cases, thermally conductive TSVs 114 can help transfer excess heat from some dies 102 to other dies 102 and to the heat sink 802. In alternative embodiments, the heat sink 802 or other components 902 can be located somewhere within the stack 100 or somewhere at the bottom of the stack 100, depending on their application and performance requirements. 8 and 9 , when the heat sink 802 or other component 902 is located at the top of the stack 100, the top of the stack 100 (e.g., the top or "back" surface of the die 102) may be free of molding 204. In some cases, some of the stacks 100 of the assembly 200 may include molding 204 entirely around and including at the top surface of the stack 100, while other stacks 100 (e.g., stacks 100 including the heat sink 802 or other component 902) may be free of molding 204 at the top surface while having molding 204 at the sides of the stack 100. As shown in Figures 10 and 11, in some embodiments, uniform and / or non-uniform dies 102 can be stacked and bonded to form a stack 100, wherein multiple dies 102 are laterally positioned on a single level within a component 200 package. For example, as shown in Figure 10, the main wafer 202 may not be singulated at each of the stacks 100. Thus, more than one stack 100 can be bonded to a single main die 102'. For example, in the example of Figure 10, the second and third stacks 100 are bonded to a single main die 102', and the fourth and fifth stacks 100 are bonded to another main die 102'. As shown in FIG10 , groups of stacks 100 bonded to a master die 102′ can be collectively encased in a mold 204. For example, in one example, the second and third stacks 100 can be collectively encased in a mold 204 (e.g., typically sealed), and the fourth and fifth stacks 100 can be collectively encased in a mold 204 (e.g., typically sealed). Alternatively, or in combination, the molds 204 of some groups of stacks 100 bonded to a common master die 102′ can be separated, with separate molds 204 surrounding each stack 100. The master die 102′ (or wafer) can be free of a mold, as shown in the example. Alternatively, the master die 102′ (or wafer) can be covered with a mold 204. As shown in FIG11 , in some embodiments, additional dies 102 can be stacked in a lateral configuration on a single level of the device 200, thereby forming one or more common stacks or partial common stacks 1100. For example, FIG11 shows an example of a partial common stack 1100. In this example, the first row of dies 102 bonded to the main die 102′ may not be singulated at each of the stacks 100. Thus, more than one stack 100 can be bonded to a single main die 102′ and a single “first row” of dies 102. For example, in the example of FIG11 , the second and third stacks 100 include a single first row of dies 102 bonded to a single main die 102′. Subsequent rows of dies 102 in the second and third stacks 100 are bonded to the single first row of dies 102. Accordingly, the second and third stacks 100 share a common main die 102′ and a common first row of dies 102. When some dies 102 are shared by multiple stacks 100, this creates a partially shared stack 1100. In other embodiments, additional rows of dies 102 may be shared by the second and third stacks 100. For example, if all rows of dies 102 in multiple stacks 100 are shared by multiple stacks 100, this would create a shared stack 1100. 11 , the fourth and fifth stacks 100 also include a single first row of dies 102 bonded to a single main die 102′. Subsequent rows of dies 102 of the fourth and fifth stacks 100 are bonded to the single first row of dies 102. Accordingly, the fourth and fifth stacks 100 share a common main die 102′ and a common first row of dies 102, thereby creating a partial common stack 1100. As shown in Figures 10 and 11, the first stack 100 is covered with molding 204 (except for the main die 102'), and each of the partial co-stacks 1100 is also covered with molding 204 (except for the main die 102'). However, as shown in Figures 10 and 11, one or more partial co-stacks 1100 may include molding 204 at the top surface of the die 102 of the partial co-stack 1100, and one or more partial co-stacks 1100 may be free of molding 204 at the top surface of the die 102 of the partial co-stack 1100. As discussed above, removing molding 204 at the top surface of the top die 102 (or not depositing molding 204) can allow interconnectivity with the top die 102, can allow improved heat dissipation from the top die 102, and so on. Additional Embodiments 12 and 13 illustrate exemplary embodiments of an assembly 200 in which one or more stacks 100 of bonded dies 102 are bonded to a main wafer 202. In some embodiments, the main wafer 202 may be singulated into main dies 102' (not shown). In various embodiments as shown, the dies 102 may be double-sided dies having conductive features 110 embedded within an insulating layer 106 on either side of a base layer 104. Some details such as traces 112 and TSVs 114 may be assumed to be present in some embodiments, but are not illustrated for clarity of the drawings. In one embodiment, as shown in Figures 12 and 13, one or more of the insulating layers 106 may be etched at the perimeter edge of the die 102 (see 1202), thereby removing some of the insulating layer 106 at the perimeter. Perimeter etching 1202 may be intentional based on device, packaging, processing, or similar specifications. In one embodiment, etching 1202 may occur on one or more sides or edges of the die 102. In some cases, etching 1202 includes removing a portion of the insulating layer 106 at the perimeter and exposing the underlying base layer 104. In other cases, etching 1202 does not expose the base layer 104, or etching 1202 also removes some of the base layer 104. FIG14 is an additional illustration of a die 102 having an etched perimeter edge (recess 1202) according to one embodiment. In one exemplary embodiment, the illustration of FIG14 more closely shows the relative dimensions of the recess 1202 relative to the base layer 104 and the insulating layer 106. In other embodiments, other proportions may exist. In some cases, the mold compound 204 may be particle-filled, as discussed above. For example, particles may be added to the mold compound 204 to alter the coefficient of thermal expansion (CTE) of the mold compound 204. This can help reduce package warpage, for example, by equalizing the CTE across the package (e.g., component 200). However, in some cases, the particles in the mold compound 204 may be too large to fit within the smaller recess 1202 formed by the perimeter etch. Any voids left after the mold compound 204 is applied to the stack 100 can cause "popcorn" failures in components of the package (e.g., component 200). In various embodiments, as shown in FIG13 , multiple layers of molding 204 can be used to reduce potential failures rather than excluding particles from molding 204 (and not receiving the benefits of doing so). For example, a first low-viscosity compound 1302 can be applied around stack 100, thereby forming a layer of compound 1302 that surrounds stack 100 and penetrates etched recesses 1202. Layer 1302 can then be followed by a layer of molding 204. In one embodiment, the first layer of compound 1302 may not include fillers or particles. For example, due to its low viscosity, the primary purpose of compound 1302 may be to fill etched recesses 1302 in die 102. However, compound 1302 may also form a layer over the vertical walls of die 102 in stack 100. After applying the first layer of compound 1302, stack 100 and / or component 200 may be covered with molding 204. In alternative embodiments, additional layers may also be used to cover stack 100 and / or component 200. In other embodiments, the first layer (low-viscosity) compound 1302 (or resin) may include submicron particles or even nanoparticles small enough to be incorporated into the recess 1202. The submicron or nanoparticles may include silica, silicon, a silica / silicon compound, or the like. The nanoparticles may in some cases average 20 nm in size (e.g., diameter), and in other cases may be smaller or larger. In one embodiment, a first layer of compound 1302 (including submicron or nanometer-sized filler particles) forms a layer over the vertical walls of die 102 and recesses 1202. In some embodiments, it is preferred that the submicron or nanometer-sized particle content of first layer of compound 1302 be greater than 5%. Molding layer 204 typically includes reinforcing particles, typically containing greater than 50% particles, and it may be preferred that the particle content of molding layer 204 be higher than the particle content of first layer of compound 1302 within recesses 1202. Similarly, in some applications, it may be preferred that the nominal size of the particles in molding layer 204 be greater than the nominal size of the particles in first layer of compound 1302. Referring to Figures 15 and 16 , in common practice, memory dies are coupled to other memory dies using ball-grid arrays (BGAs) and other similar technologies. In those cases, the memory die-to-memory die pitch is typically about 45 microns. Using similar technologies, the logic die-to-interposer pitch is about 90 to 100 microns. However, in some embodiments, it is possible and practical to assemble a stack of memory dies (such as stack 100 ) separately with a finer pitch and then stack it on the logic die. It should be noted that in some cases, the logic die may not be larger than the memory die. Figures 15 and 16 illustrate an example of a "high-bandwidth memory" component 200 comprising a stack 100 of memory dies 102 (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc.) coupled to a logic die 1502. In various embodiments, the dies 102 are hybrid bonded (DBI®) to form the stack 100, as discussed above. As shown in Figure 15 , the stack 100 (or the bottom die 102) can be hybrid bonded to the logic die 1502. The logic die 1502 can include terminals 206 for coupling the component 200 to a circuit, PCB, device, or the like, as discussed above. Using direct or hybrid bonding techniques, the distance between the dies 102 and between the dies 102 and the logic die 1502 is significantly reduced (due to the die thickness compared to current technology, where the distance is the die thickness plus the height of the Cu pillars and solder balls). In one embodiment, circuit elements (such as conductive features 110 or the like) at the bonding surface of one or more of the bonded dies 102 are less than 20 microns and in other applications less than 5 microns or even less than 1 micron. As shown in FIG16 , flip chip technology or the like can alternatively be used to couple stack 100 to logic die 1502. For example, flip chip terminals 1602 can be coupled to the bottom side of bottom die 102, which interfaces with terminals 1602 at the top surface of logic die 1502. Accordingly, a combination of hybrid bonding and flip chip technology can be used with assembly 200. In alternative embodiments, other coupling technologies can also be used as desired to couple the hybrid bonded stack 100 to logic die 1502, an interposer, or the like. 16 is a molding 1604 that covers the flip chip terminals 1602 and fills the gap between the stack 100 and the logic die 1502. In some embodiments, the assembly 200 may also be covered with a molding 204 for handling, packaging, etc., as desired. Figures 17 through 20 illustrate additional embodiments of using the stack 100 and / or assembly 200 in various applications. For example, Figure 17 shows an assembly 1700 comprising various dies 102, the assembly comprising the stack 100 hybrid-bonded to an interposer 1702. In one embodiment, the interposer 1702 comprises a semiconductor, such as silicon. The drawings are simplified for clarity. In various embodiments, as shown in FIG17 , some dies 102 may be molded and other dies 102 may be unmolded. A heat sink or other cooling device 1704 (e.g., a fan, etc.) is coupled to the unmolded die 102 to cool the die 102 (which may include high-power components such as a processor or the like). The interposer 1702 includes hybrid bond pads 110 and at least one wire bond pad 1706. 18 , wire bond pads 1706 can be used to couple distal components (e.g., components coupled to (or passing through) or integral with laminate 1802) to liner 1706 via wires 1804. In one embodiment shown, laminate 1802 is hybrid bonded to insert 1702. Alternatively, laminate 1802 can be coupled to insert 1702 by another bonding technique. For example, as shown in Figure 19, laminate 1802 can be coupled to interposer 1702 via BGA technology, another surface mount technology, or the like. In one embodiment, as shown in Figure 19, laminate 1802 can include one or more wire bond pads 1902 that can be used with wires 1804 to couple to wire bond pads 1706 or the like. In one embodiment, as shown in FIG19 , assembly 200 or stack 100 may be packaged with another component 1904, which may be hybrid-bonded to insert 1702. Component 1904 and assembly 200 or stack 100 may be covered in a molding 1906, which may optionally include a seal (or other encapsulation). Encapsulation or stack 100 and component 1904 may be hybrid-bonded to insert 1702. Cooling device 1704 may be coupled to component 1904 and / or stack 100, as shown in FIG19 . Alternatively, filler 1604 may be used to cover terminals 206 and fill gaps between insert 1702 and laminate 1802. Alternatively, insert 1702 may be sealed together with or separately from the other components. As shown in FIG20 , the stack 100 may be covered with a molding 204, and other dies 102 and / or components may not be covered with the molding. A heat sink or other cooling device 1704 (e.g., a fan, etc.) is coupled to the unmolded die 102 to cool the die 102 (which may include high power components such as a processor or the like). Additional cooling devices may also be coupled to the stack 100, which may not include a molding 204 at the top surface of the stack 100. The insert 1702 includes a hybrid bond pad 110 and at least one wire bond pad 1706. As shown, the insert 1702 may be coupled to the laminate 1802 via a BGA configuration or other coupling technology. Exemplary Process FIG21 is a flow chart illustrating an exemplary process 2100 for forming a stacked and bonded microelectronic assembly (such as microelectronic assembly 200) comprising a die stack (such as stack 100 of die 102). In some embodiments, the die stack may be covered with a molding (such as molding 204) for handling, processing, application, and the like. Process 2100 refers to FIG1 through FIG20. The order in which the processes are described is not intended to be construed as limiting, and any number of the described process blocks in a process may be combined in any order to implement the process or an alternative process. Alternatively, individual blocks may be deleted from the process without departing from the spirit and scope of the subject matter described herein. Furthermore, the processes may be implemented with any suitable hardware, software, firmware, or combination thereof without departing from the scope of the subject matter described herein. In alternative embodiments, other technologies may be included in various combinations in the process and remain within the scope of the present invention. At block 2102, the process includes forming a microelectronic stack (such as stack 100 of dies 102). In an alternative embodiment, the process includes forming a plurality of microelectronic stacks. In one embodiment, forming a microelectronic stack includes the following blocks: At block 2104, the process includes providing a first substrate (such as first die 102) having a front side and a back side. The back side has a bonding surface including a non-conductive bonding layer and an exposed electrically conductive first circuit element. The first substrate has a first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate. At block 2106, the process includes providing a second substrate having a front side and a back side. The front side includes a non-conductive bonding layer and an exposed electrically conductive first circuit element. At block 2108, the process includes coupling the front side of the second substrate to the back side of the first substrate by contacting the non-conductive bonding layer of the first substrate and the non-conductive bonding layer of the second substrate. In one embodiment, the side edges of the first substrate are misaligned relative to the side edges of the second substrate. The coupling includes contacting the first circuit element of the first substrate with the first circuit element of the second substrate (e.g., hybrid bonding). At block 2110, the process includes covering the side edges of the first substrate and the side edges of the second substrate with a molding (such as molding 204). In one embodiment, the process includes covering the backside of the second substrate with the molding. In various embodiments, the molding includes more than one layer or more than one material or compound. In some embodiments, at least one of the plurality of molding layers includes particles to help equalize the CTE of the device, thereby preventing device warping. In one embodiment, the back side of the second substrate includes a second non-conductive bonding layer and an exposed electrically conductive second circuit element. In one embodiment, the second substrate has a second conductive via that electrically couples the first circuit element and the second circuit element of the second substrate. In one embodiment, a process includes providing a third substrate having a front side and a back side, the front side including a non-conductive bonding layer and an exposed electrically conductive first circuit element. The process includes coupling the front side of the third substrate to the back side of the second substrate by contacting the non-conductive bonding layer of the third substrate with the non-conductive bonding layer of the second substrate. In one embodiment, side edges of the third substrate are misaligned relative to side edges of the second substrate and / or side edges of the first substrate. The coupling includes contacting the first circuit element of the third substrate with the second circuit element of the second substrate (e.g., hybrid bonding). In one embodiment, the process includes forming a recess at the bonding layer of the first substrate and / or the bonding layer of the second substrate at the periphery of the first substrate and / or the periphery of the second substrate, and filling at least the recess with a low-viscosity compound before covering the side edges of the first substrate and the side edges of the second substrate with a mold. In another embodiment, the process includes covering the side edges of the third substrate with a molding. In yet another embodiment, the process includes covering the back side of the third substrate with a molding. In one embodiment, the process includes hybrid bonding the microelectronic stack to a semiconductor interposer having at least one wirebond contact pad. In another embodiment, the process includes coupling the interposer to a laminate having a second wirebond contact pad and bonding the at least one wirebond contact pad of the interposer to the second wirebond contact pad of the laminate using wire bonding. For example, the interposer may be hybrid bonded to the laminate. In other embodiments, various portions of the microelectronic assembly are covered with one or more molding layers, while other portions are not covered with molding. Although various implementations and examples are discussed herein, other implementations and examples may be possible by combining features and elements of individual implementations and examples. In various embodiments, some process steps may be modified or eliminated compared to those described herein. The techniques, components, and devices described herein are not limited to the illustrations of Figures 1-21 and may be applied to other designs, types, configurations, and constructions, including other electrical components, without departing from the scope of the invention. In some cases, additional or alternative components, techniques, sequences, or processes may be used to implement the techniques described herein. Furthermore, the components and / or techniques may be configured and / or combined in various combinations while causing similar or substantially the same results. Conclusion Although the embodiments of the present invention have been described in language specific to structural features and / or methodological acts, it is to be understood that the embodiments are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing example devices and techniques. Each claim herein constitutes a separate embodiment, and the combination of embodiments of different claims and / or different embodiments is within the scope of the invention and will be apparent to those skilled in the art after reviewing this disclosure. 100: Stack / Microelectronic Assembly 102: Die 102': Die 102": Die 104: Base Substrate 106: Insulating Layer / Dielectric Layer 108: Bonding Surface 110: Conductive Feature 112: Conductive Trace 114: Conductive TSV 116: Electrical Coupling Pad / Liner 200: Microelectronic Assembly 202: Main Wafer 204: Molding 206: Electrical Contact / Terminal 802: Heat Sink 902: Other Components 1100: Co-Stack / Partial Co-Stack 1202: Etching / Recess 1302: First Low-Viscosity Compound 1502: Logic Die 1602: Flip Chip Terminal 1604: Molding 1700: Component 1702: Interposer 1704: Heat Sink / Cooling Device 1706: Wire Bond Pad 1802: Laminate 1804: Wiring 1902: Wire Bond Pad 1904: Component 1906: Molding 2100: Process 2102: Block 2104: Block 2106: Block 2108: Block 2110: Block e: Error / Misalignment Detailed description is provided with reference to the accompanying drawings. In the drawings, one or more left-most digits of an element symbol identify the drawing in which the element symbol first appears. The use of the same element symbol in different drawings indicates similar or identical items. For this discussion, the devices and systems illustrated in the drawings are shown as having a large number of components. As described herein, various embodiments of the devices and / or systems may include fewer components and remain within the scope of the present invention. Alternatively, other embodiments of the devices and / or systems may include additional components or various combinations of the described components and remain within the scope of the present invention. [Figure 1] is a cross-sectional profile of an exemplary die-to-wafer and / or die-to-die stack and molded article according to one embodiment. [Figure 2] is a cross-sectional profile of an exemplary die-to-wafer and / or die-to-die stack and molded article according to one embodiment, in which the top of the stack is not covered. [Figure 3] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and mold according to one embodiment, in which the top of the stack is covered. [Figure 4] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and mold according to one embodiment, in which the top of the stack is not covered and the mold extends to the bottom of the stack. [Figure 5] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and mold according to one embodiment, in which the top of the stack is covered and the mold extends to the bottom of the stack. [Figure 6] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and mold with unequally sized die according to one embodiment, in which the top of the stack is covered. [Figure 7] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and molding having unequally sized die according to one embodiment, in which the molding covers the top of the stack and extends to the bottom of the stack. [Figure 8] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and molding according to one embodiment, in which the top die of the stack does not have interconnects on one side. [Figure 9] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and molding according to one embodiment, in which the top die of the stack does not have interconnects on one side and the molding extends to the bottom of the stack. [Figure 10] is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and molding including some lateral placement of die on a single level according to one embodiment. FIG11 is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and molded article including some lateral placement of the die and wafer on a single level according to one embodiment. FIG12 is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack including some etching of the die edge according to one embodiment.FIG13 is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die stack and molded article including some etching of the die edge according to one embodiment. FIG14 is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die hybrid bonded stack including some etching of the die edge according to another embodiment. FIG15 is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die memory stack according to one embodiment. FIG16 is a cross-sectional view of an exemplary die-to-wafer and / or die-to-die hybrid bonded stack including flip-chip termination according to one embodiment. FIG17-20 show cross-sectional views of exemplary die-to-wafer and / or die-to-die hybrid bonded stacks including various combinations on a substrate according to various embodiments. FIG21 is a flow chart illustrating an exemplary process for forming stacked and bonded structures according to one embodiment. 100: Stacking / Microelectronics Assembly 102: Grain 102': Grain 104: Base substrate 106: Insulation layer / dielectric layer 108:Joint surface 110:Conduction characteristics 112: Conductive trace 114: Conductive silicon vias 116: Electrical coupling pad / gasket e: Error / misalignment

Claims

1. A microelectronic component comprising: a substrate; a first die and a first bonding layer on the first die, the first bonding layer being directly bonded to the substrate without adhesive; a second die having microelectronic circuit elements formed therein and disposed above the first die, the first die being directly bonded to the second bonding layer on the second die without adhesive; a first sealing layer disposed adjacent to a sidewall of the second die; and a second sealing layer deposited on the first sealing layer and laterally adjacent to the first sealing layer, the second sealing layer comprising an inorganic material.

2. The microelectronic assembly according to claim 1, wherein the first sealing layer and the second sealing layer have different material compositions.

3. The microelectronic assembly according to claim 1, wherein the side edge of the second die is laterally offset from the side edge of the first die.

4. The microelectronic assembly according to claim 1, wherein the first sealing layer and the second sealing layer have different coefficients of thermal expansion (CTE).

5. The microelectronic component according to claim 1, wherein the first sealing layer comprises silicon dioxide.

6. The microelectronic component according to claim 1, further comprising a conductive feature at the surface of the second grain opposite the second bonding layer, the conductive feature being configured to be electrically connected to another component.

7. The microelectronic assembly according to claim 6, wherein the surface of the second die is free of the first sealing material.

8. The microelectronic component according to claim 6, further comprising a plurality of through-substrate vias (TSVs) in the second die.

9. The microelectronic component according to claim 1, wherein the substrate has a first lateral occupancy area that is larger than the second lateral occupancy area of ​​the first die, and wherein the second lateral occupancy area of ​​the first die is smaller than the third lateral occupancy area of ​​the second die.

10. The microelectronic component of claim 9, wherein the first die includes a first plurality of pads, wherein the plurality of substrates in the second die are through-connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

11. The microelectronic component according to claim 9, wherein the first lateral occupancy area of ​​the substrate is greater than the third lateral occupancy area of ​​the second die.

12. The microelectronic component according to claim 1, wherein the first grain area of ​​the first grain is smaller than the second grain area of ​​the second grain.

13. The microelectronic assembly according to claim 1, wherein the first die and the second bonding layer on the second die are directly bonded through dielectric-to-dielectric and metal-to-metal direct bonding.

14. The microelectronic component according to claim 1, wherein the first die includes a memory die.

15. The microelectronic assembly according to claim 1, wherein the first sealing layer comprises a plurality of layers.

16. The microelectronic assembly of claim 1, wherein the first sealing layer comprises a molding compound.

17. The microelectronic assembly according to claim 1, wherein a portion of the first sealing layer is disposed over a portion of the first die.

18. A microelectronic component, comprising: substrate; A first die and a first bonding layer on the first die, the first bonding layer being directly bonded to the substrate without adhesive, the first die comprising a memory die; a second die having microelectronic circuit elements formed therein and disposed above the first die, the first die being mixed with a second bonding layer bonded to the second die; a first sealing layer disposed adjacent to a sidewall of the second die; and a second sealing layer deposited on the first sealing layer and laterally adjacent to the first sealing layer, the second sealing layer comprising an inorganic material, wherein the surface of the second die opposite to the second bonding layer includes conductive features configured to be electrically connected to another component, the surface of the second die not having the first sealing layer.

19. The microelectronic assembly according to claim 18, wherein the first sealing layer and the second sealing layer have different material compositions.

20. The microelectronic assembly according to claim 18, wherein the first sealing layer comprises a plurality of layers.

21. The microelectronic component according to claim 18, wherein the first sealing layer comprises silicon dioxide.

22. The microelectronic component according to claim 18, wherein the first sealing layer comprises an inorganic material.

23. The microelectronic assembly according to claim 18, wherein the first sealing layer comprises a molding compound.

24. The microelectronic component according to claim 18, further comprising a plurality of substrate through-holes in the second die.

25. The microelectronic assembly of claim 24, wherein the first die includes a first plurality of pads, wherein the plurality of substrates in the second die are through-connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

26. The microelectronic component according to claim 18, wherein the substrate has a first lateral occupancy area that is larger than the second lateral occupancy area of ​​the first die, and wherein the second lateral occupancy area of ​​the first die is smaller than the third lateral occupancy area of ​​the second die.

27. The microelectronic assembly according to claim 26, wherein the first lateral occupancy area of ​​the substrate is greater than the third lateral occupancy area of ​​the second die.

28. A microelectronic component, comprising: A substrate having a first lateral occupying area; A first die and a first bonding layer on the first die, the first bonding layer being directly bonded to the substrate without adhesive, the first die including a memory die having a second lateral occupying area smaller than the first lateral occupying area; A second die having microelectronic circuit elements formed therein and disposed above the first die, the first die being mixed-bonded to a second bonding layer on the second die, the second die having a third lateral occupying area smaller than the first lateral occupying area and larger than the second lateral occupying area; and a first sealing layer disposed adjacent to the sidewall of the second die.

29. The microelectronic component according to claim 28, further comprising a second sealing layer deposited on the first sealing layer and disposed laterally adjacent to the first sealing layer.

30. The microelectronic assembly of claim 29, wherein the first sealing layer and the second sealing layer comprise at least two different materials.

31. The microelectronic component according to claim 28, wherein the first sealing layer comprises an inorganic material.

32. The microelectronic component of claim 28, further comprising a plurality of substrate through-holes in the second die, wherein the first die includes a first plurality of pads, wherein the plurality of substrate through-holes in the second die are connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

33. The microelectronic assembly according to claim 28, wherein at least two side edges of the first die are disposed within the third lateral occupied area of ​​the second die.

34. The microelectronic component according to claim 28, wherein the second die includes a logic die.

35. A microelectronic component, comprising: substrate; A first grain and a first bonding layer on the first grain, the first bonding layer being directly bonded to the substrate without adhesive; A second die having microelectronic circuit elements formed therein and disposed above the first die, the first die being directly bonded to a second bonding layer on the second die without adhesive; and a first compound disposed adjacent to the sidewall of the first die. And a second compound, which is deposited on and laterally adjacent to the first compound, the second compound comprising an inorganic material.

36. The microelectronic component according to claim 35, wherein the first compound and the second compound have different material compositions.

37. The microelectronic assembly of claim 35, wherein the side edge of the second die is laterally offset from the side edge of the first die.

38. The microelectronic component according to claim 35, wherein the first compound and the second compound have different coefficients of thermal expansion (CTE).

39. The microelectronic component according to claim 35, wherein the second compound comprises silicon dioxide.

40. The microelectronic component according to claim 35, wherein the first compound comprises an inorganic material.

41. The microelectronic component according to claim 35, further comprising a conductive feature at the surface of the second grain opposite the second bonding layer, the conductive feature being configured to be electrically connected to another component.

42. The microelectronic component according to claim 41, wherein the surface of the second grain does not contain the first compound.

43. The microelectronic component according to claim 41, further comprising a plurality of substrate through-holes (TSVs) in the second die.

44. The microelectronic assembly of claim 43, wherein the first die includes a first plurality of pads, wherein the plurality of substrates in the second die are through-connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

45. The microelectronic component according to claim 35, wherein the substrate has a first lateral occupancy area that is larger than the second lateral occupancy area of ​​the first die, and wherein the second lateral occupancy area of ​​the first die is smaller than the third lateral occupancy area of ​​the second die.

46. ​​The microelectronic assembly according to claim 45, wherein the first lateral occupancy area of ​​the substrate is greater than the third lateral occupancy area of ​​the second die.

47. The microelectronic component according to claim 35, wherein the first grain area of ​​the first grain is smaller than the second grain area of ​​the second grain.

48. The microelectronic component of claim 35, wherein the first die and the second bonding layer on the second die are directly bonded through dielectric-to-dielectric and metal-to-metal direct bonding.

49. The microelectronic component according to claim 35, wherein the first die includes a memory die.

50. The microelectronic assembly according to claim 35, wherein the first sealing layer comprises a plurality of layers.

51. The microelectronic assembly according to claim 35, wherein the first sealing layer comprises a molding compound.

52. The microelectronic assembly of claim 35, wherein a portion of the first sealing layer is disposed over a portion of the first die.

53. The microelectronic component of claim 35, wherein the first compound is also deposited adjacent to the sidewall of the second grain, and wherein the second compound is also deposited on a portion of the first compound deposited adjacent to the sidewall of the second grain and laterally adjacent to the portion of the first compound.

54. A microelectronic component, comprising: substrate; A first die and a first bonding layer on the first die, the first bonding layer being directly bonded to the substrate without adhesive, the first die comprising a memory die; a second die having microelectronic circuit elements formed therein and disposed above the first die, the first die being mixed-bonded to a second bonding layer on the second die; a first compound disposed adjacent to the sidewall of the first die, the first compound comprising an inorganic material. And a second compound, the second compound being deposited on and laterally adjacent to the first compound, wherein the surface of the second grain opposite to the second bonding layer includes conductive features configured to be electrically connected to another component, and the surface of the second grain is free of the first compound.

55. The microelectronic component according to claim 54, wherein the first compound and the second compound have different material compositions.

56. The microelectronic component according to claim 54, wherein the second compound comprises silicon dioxide.

57. The microelectronic component according to claim 54, wherein the second compound comprises an inorganic material.

58. The microelectronic component according to claim 54, further comprising a plurality of substrate through-holes (TSVs) in the second die.

59. The microelectronic assembly of claim 58, wherein the first die includes a first plurality of pads, wherein the plurality of substrates in the second die are through-connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

60. The microelectronic component according to claim 54, wherein the substrate has a first lateral occupancy area that is larger than the second lateral occupancy area of ​​the first die, and wherein the second lateral occupancy area of ​​the first die is smaller than the third lateral occupancy area of ​​the second die.

61. The microelectronic component according to claim 60, wherein the first lateral occupancy area of ​​the substrate is greater than the third lateral occupancy area of ​​the second die.

62. A microelectronic component, comprising: A substrate having a first lateral occupying area; A first die and a first bonding layer on the first die, the first bonding layer being directly bonded to the substrate without adhesive, the first die including a memory die having a second lateral occupying area smaller than the first lateral occupying area; A second die having microelectronic circuit elements formed therein and disposed above the first die, the first die being mixed-bonded to a second bonding layer on the second die, the second die having a third lateral occupying area smaller than the first lateral occupying area and larger than the second lateral occupying area; and an inorganic housing disposed adjacent to the sidewall of the first die.

63. The microelectronic assembly according to claim 62, wherein the inorganic housing comprises a plurality of layers.

64. The microelectronic component according to claim 63, wherein the plurality of layers includes a first layer and a second layer comprising two different materials.

65. The microelectronic component of claim 62, further comprising a plurality of substrate through-holes (TSVs) in the second die, wherein the first die includes a first plurality of pads, wherein the plurality of substrate through-holes in the second die are connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

66. The microelectronic assembly according to claim 62, wherein at least two side edges of the first die are disposed within the third lateral occupied area of ​​the second die.

67. The microelectronic component according to claim 62, wherein the second die includes a logic die.

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