Semiconductor device

Abstract

A semiconductor device is disclosed, comprising: an active pattern located on a substrate and surrounded by a device isolation pattern; a character line extending in a first direction and located on the active pattern and the device isolation pattern in a first direction parallel to the bottom surface of the substrate; a bit line extending on the active pattern in a second direction intersecting the first direction; a storage node contact located on the active pattern; an overlap pad including a lower overlap pad and an upper overlap pad sequentially disposed on the storage node contact, with an interface between the lower overlap pad and the upper overlap pad; and a fence pattern located on the lateral surfaces of the character line and the overlap pad. The top surface of the fence pattern has a height greater than the height of the top surface of the lower overlap pad.

Description

Technical Field

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims priority to Korean Patent Application No. 10-2023-0091042 filed on July 13, 2023 in the Korean Intellectual Property Office, and the disclosure of the Korean patent application is hereby incorporated by reference in its entirety into this application.

[0003] The present invention relates to a semiconductor, and more particularly to a semiconductor device. Prior Art

[0004] Semiconductor devices play an important role in the electronics industry due to their small size, high functionality, and / or low manufacturing cost. Semiconductor devices can be classified as any of semiconductor memory devices that store logic data, semiconductor logic devices that process operations on logic data, and hybrid semiconductor devices that have both memory elements and logic elements.

[0005] Recently, the high speed and low power consumption of electronic products may require that semiconductor devices embedded in the electronic products should have high operating speed and / or low operating voltage. To meet the above requirements, semiconductor devices have been more highly integrated. The high integration of semiconductor devices may lead to reduced reliability of semiconductor devices. Therefore, various research studies have been conducted to enhance the reliability of semiconductor devices. Summary of the invention

[0006] Some embodiments of the inventive concept provide semiconductor devices with improved productivity.

[0007] The subject matter of the present invention is not limited to the above contents, and based on the following description, those skilled in the art will clearly understand other subjects not mentioned above.

[0008] According to some embodiments of the inventive concept, a semiconductor device may include: an active pattern located on a substrate and surrounded by a device isolation pattern in a plan view; a word line extending in a first direction and located on the active pattern and the device isolation pattern, the first direction being parallel to a bottom surface of the substrate; a bit line extending in a second direction on the active pattern, the second direction intersecting the first direction; a storage node contact located on the active pattern; a landing pad including a lower landing pad and an upper landing pad stacked on the storage node contact, an interface existing between the lower landing pad and the upper landing pad; and a fence pattern located on a lateral surface of the word line and the landing pad. A top surface of the fence pattern may be higher than a top surface of an interface between the lower landing pad and the upper landing pad adjacent to the lower landing pad relative to the substrate.

[0009] According to some embodiments of the inventive concept, a semiconductor device may include: an active pattern located on a substrate and surrounded by a device isolation pattern in a plan view; a word line extending in a first direction and located on the active pattern and the device isolation pattern, the first direction being parallel to a bottom surface of the substrate; a bit line extending in a second direction on the active pattern, the second direction intersecting the first direction; a storage node contact located on the active pattern; a strap pad located on the storage node contact; and a fence pattern located on a lateral surface of the word line and the strap pad. The fence pattern may include: a lower fence pattern located on a lateral surface of the bit line; and an upper fence pattern located on the lower fence pattern and protruding beyond the lower fence pattern in the first direction.

[0010] According to some embodiments of the inventive concept, a semiconductor device may include: an active pattern located on a substrate and surrounded by a device isolation pattern in a plan view; a word line extending in a first direction and located on the active pattern and the device isolation pattern, the first direction being parallel to a bottom surface of the substrate; a bit line extending in a second direction on the active pattern, the second direction intersecting the first direction; a storage node contact located on the active pattern; a landing pad located on the storage node contact; a fence pattern located on a lateral surface of the word line and the landing pad; and a filling pattern located on the bit line and extending in the second direction. A top surface of the fence pattern may be substantially at the same height as a top surface of the filling pattern. Simple diagram description

[0011] FIG. 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. 2A , 2B and 2C are cross-sectional views respectively taken along line AA′, line BB′ and line CC′ shown in FIG. 1 . FIG. 3 shows a cross-sectional view taken along line AA′ shown in FIG. 1 . 4A and 4B are cross-sectional views respectively taken along line AA′ and line CC′ shown in FIG. 1 . 5 , 6A, 6B, 6C, 7 , 8A, 8B, 8C, 9 , 10A, 10B and 10C are plan views and cross-sectional views illustrating methods of fabricating a semiconductor device according to some embodiments of the inventive concept. 11 and 12 are cross-sectional views illustrating methods of fabricating a semiconductor device according to some embodiments of the inventive concept. 13 and 14 are cross-sectional views illustrating methods of fabricating a semiconductor device according to some embodiments of the inventive concept. Implementation

[0012] Semiconductor devices according to some embodiments of the inventive concept will be discussed hereinafter with reference to the accompanying drawings.

[0013] Fig. 1 is a plan view showing a semiconductor device according to some embodiments of the inventive concept. Fig. 2A, Fig. 2B and Fig. 2C are cross-sectional views respectively taken along line AA', line BB' and line CC' shown in Fig. 1 .

[0014] 1 to 2C , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0015] A device isolation pattern STI defining an active pattern ACT may be disposed on the substrate 100. A plurality of active patterns ACT may be disposed. For example, the active pattern ACT may include a portion of the substrate 100 surrounded by the device isolation pattern STI. For ease of explanation, unless otherwise specifically stated in the present disclosure, the substrate 100 may be defined to indicate another portion other than the portion of the substrate 100.

[0016] Each active pattern ACT may be parallel to the bottom surface of the substrate 100 and may be spaced apart from each other in the first direction D1 and the second direction D2 intersecting each other. The active patterns ACT may have island shapes separated from each other and may each have a strip shape elongated in a third direction D3 parallel to the bottom surface of the substrate 100. The first direction D1, the second direction D2, and the third direction D3 may intersect each other. The active pattern ACT may have a shape protruding in a fourth direction D4 perpendicular to the bottom surface of the substrate 100.

[0017] The device isolation pattern STI may include a dielectric material, such as at least one of silicon oxide (SiO 2) and / or silicon nitride (SiN). The device isolation pattern STI may be a single layer formed of a single material or a multilayer including two or more materials. In the present disclosure, each of the sentences "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may include one of the elements listed in a corresponding one of the above-mentioned expressions or any possible combination of the elements.

[0018] The active pattern ACT may include a first edge portion EA1 and a second edge portion EA2 spaced apart from each other in the third direction D3, and may also include a center portion CA located between the first edge portion EA1 and the second edge portion EA2. The first edge portion EA1 and the second edge portion EA2 may be opposite ends of the active pattern ACT in the third direction D3. The center portion CA may be a portion of the active pattern ACT sandwiched between the first edge portion EA1 and the second edge portion EA2, and may be, for example, a portion of the active pattern ACT sandwiched between a pair of word lines WL to be discussed below. The first edge portion EA1 and the second edge portion EA2 and the center portion CA may be doped with impurities (e.g., n-type impurities or p-type impurities).

[0019] The word line WL may extend across the active pattern ACT and the device isolation pattern STI, extend on the active pattern ACT and the device isolation pattern STI, or be located on the active pattern ACT and the device isolation pattern STI. A plurality of word lines WL may be provided. The word lines WL may be spaced apart from each other in the second direction D2. For example, a pair of word lines WL adjacent to each other in the second direction D2 may extend across one active pattern ACT in a direction perpendicular to the substrate 100 or overlap the one active pattern ACT. The word line WL may be correspondingly positioned in the trench region TR provided in the active pattern ACT and the device isolation pattern STI.

[0020] Each of the word lines WL may include a gate electrode GE, a gate dielectric pattern GI, and a gate cap pattern GC. The gate electrode GE may penetrate the active pattern ACT and the device isolation pattern STI in the first direction D1. The gate dielectric pattern GI may be sandwiched between the gate electrode GE and the active pattern ACT and between the gate electrode GE and the device isolation pattern STI. A gate cap pattern GC covering the top surface of the gate electrode GE or overlapping the top surface of the gate electrode GE may be provided on the gate electrode GE. The gate electrode GE may include a conductive material. For example, the gate electrode GE may be a single layer formed of one material or a multilayer formed of two or more materials. For example, the gate dielectric pattern GI may include at least one of silicon oxide (SiO 2) and / or a high dielectric constant (high-k) dielectric material. In the present disclosure, a high dielectric constant dielectric material may be defined as a material indicating a dielectric constant greater than that of silicon oxide. For example, the gate cap pattern GC may include silicon nitride (SiN).

[0021] A buffer pattern BP may be disposed on the substrate 100. The buffer pattern BP may cover the active pattern ACT and the device isolation pattern STI or overlap the active pattern ACT and the device isolation pattern STI. The buffer pattern BP may be a single layer or multiple layers. For example, the buffer pattern BP may include at least one of silicon oxide (SiO 2), silicon nitride (SiN) and / or silicon oxynitride (SiON).

[0022] A first groove RS1 may be formed on an upper portion of the active pattern ACT and an upper portion of the device isolation pattern STI adjacent to an upper portion of each of the active patterns ACT.

[0023] A bit line contact DC may be provided in the first recess RS1. The bit line contact DC may be sandwiched between the central portion CA of the active pattern ACT and the bit line BL to be discussed below. A plurality of bit line contacts DC may be provided. Each bit line contact DC may be spaced apart from each other in the first direction D1 and the second direction D2. The bit line contact DC may electrically connect the corresponding bit line BL to the central portion CA of the corresponding active pattern ACT. For example, the bit line contact DC may include at least one of polycrystalline silicon doped with impurities, polycrystalline silicon not doped with impurities, and / or a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0024] A bit line BL may be disposed on the bit line contact DC. The bit line BL may extend in the second direction D2 on the bit line contact DC. A plurality of bit lines BL may be disposed. The bit lines BL may be spaced apart from each other in the first direction D1. For example, the bit line BL may include a metallic material such as Ti, Mo, W, Cu, Al, Ta, Ru, or Ir. The bit line BL may include a material having grains formed in the same crystal direction. For example, the bit line BL may include a material having a single crystal, but the inventive concept is not limited thereto. For example, the bit line BL includes a polycrystalline material having a plurality of grains, and the crystal orientations of the plurality of grains may be similar or substantially identical.

[0025] A first barrier pattern (not shown) may be further interposed between the bit line BL and the bit line contact DC and between the bit line BL and the polysilicon pattern PP to be discussed below. The first barrier pattern may prevent diffusion of materials between the bit line BL and the bit line contact DC and between the bit line BL and the polysilicon pattern PP to be discussed below. For example, the first barrier pattern may include a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0026] A polysilicon pattern PP may be provided between the bit line BL and the buffer pattern BP and between the bit line contacts DC adjacent to each other in the second direction D2. A plurality of polysilicon patterns PP may be provided. For example, each polysilicon pattern PP may be spaced apart from each other in the first direction D1 and the second direction D2. A top surface of the polysilicon pattern PP and a top surface of the bit line contact DC may be located at substantially the same level or height relative to a top surface of the substrate 100 and may be coplanar with each other. The polysilicon pattern PP may include, for example, polysilicon doped with impurities.

[0027] A bit line cap pattern BCP may be provided on the bit line BL. The bit line cap pattern BCP may extend in the second direction D2 together with the bit line BL. A plurality of bit line cap patterns BCP may be provided. The bit line cap patterns BCP may be spaced apart from each other in the first direction D1. The bit line cap pattern BCP may vertically overlap the bit line BL. The bit line cap pattern BCP may be formed of a single layer or a plurality of layers. The bit line cap pattern BCP may include a first cap pattern, a second cap pattern, and a third cap pattern stacked in sequence. For example, each of the first cap pattern to the third cap pattern may include silicon nitride (SiN). In some embodiments, the bit line cap pattern BCP may include four or more stacked cap patterns.

[0028] A bit line spacer BSP may be disposed on the lateral surface of the bit line contact DC, the lateral surface of the bit line BL, and the lateral surface of the bit line cap pattern BCP. The bit line spacer BSP may extend in the second direction D2 on the lateral surface of the bit line BL. The bit line spacer BSP may fill the first groove RS1 or be located in the first groove RS1, and may extend in the fourth direction D4 on the lateral surface of the bit line cap pattern BCP. A plurality of bit line spacers BSP may be disposed. Each bit line spacer BSP may be spaced apart from each other in the first direction D1. For example, the bit line spacer BSP may include at least one of silicon oxide (SiO 2), silicon nitride (SiN), silicon carbonitride (SiCN), and / or silicon oxycarbonitride (SiOCN).

[0029] The bit line spacer BSP may include one spacer or a plurality of spacers. For example, a first spacer to a third spacer may be sequentially disposed on the lateral surface of the bit line BL. The second spacer may include an air gap separating the first spacer and the third spacer from each other.

[0030] A storage node contact BC may be provided between the bit lines BL adjacent to each other in the first direction D1. A plurality of storage node contacts BC may be provided. Each storage node contact BC may be spaced apart from each other in the first direction D1 and the second direction D2. Storage node contacts BC adjacent to each other in the first direction D1 may be spaced apart from each other across the bit line BL. Storage node contacts BC adjacent to each other in the second direction D2 may be spaced apart from each other across the fence pattern FN to be discussed below. Each of the storage node contacts BC may fill the second groove RS2 in a corresponding one of the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT and may be connected to the corresponding edge portion. For example, the storage node contact BC may include at least one of polycrystalline silicon doped with impurities, polycrystalline silicon not doped with impurities, and / or a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0031] A fence pattern FN may be sandwiched between bit lines BL adjacent to each other in a first direction D1 on a word line WL. The fence pattern FN may be sandwiched between storage node contacts BC adjacent to each other in a second direction D2 on the word line WL. A plurality of fence patterns FN may be provided. Each fence pattern FN may be spaced apart from each other in the first direction D1 and the second direction D2. Fence patterns FN adjacent to each other in the first direction D1 may be spaced apart from each other across the bit line BL. Fence patterns FN adjacent to each other in the second direction D2 may be spaced apart from each other across the storage node contacts BC. The fence pattern FN may include, for example, at least one of silicon oxide (SiO 2), silicon nitride (SiN), silicon carbonitride (SiCN), and / or silicon oxycarbonitride (SiOCN).

[0032] The fence pattern FN may include a lower fence pattern FNx and an upper fence pattern FNy that are distinguished from each other without an interface. The upper fence pattern FNy may protrude more than the lower fence pattern FNx in the first direction D1. A bottom surface FNxb of the upper fence pattern FNy may contact a top surface BSPa of the bit line spacer BSP.

[0033] The fence pattern FN may have a first lateral surface FNS1 pointing in the first direction D1, a second lateral surface FNS2 pointing in the second direction D2 or in the opposite direction of the second direction D2, and a third lateral surface FNS3 opposite to the first lateral surface FNS1. The first lateral surface FNS1 of the fence pattern FN may include a first lateral surface FNxS1 of a lower fence pattern FNx and a first lateral surface FNyS1 of an upper fence pattern FNy. The second lateral surface FNS2 of the fence pattern FN may include a second lateral surface FNxS2 of the lower fence pattern FNx and a second lateral surface FNyS2 of the upper fence pattern FNy. The third lateral surface FNS3 of the fence pattern FN may include a third lateral surface FNxS3 of the lower fence pattern FNx and a third lateral surface FNyS3 of the upper fence pattern FNy. The first lateral surface FNyS1 of the upper fence pattern FNy may protrude more than the first lateral surface FNxS1 of the lower fence pattern FNx in the first direction D1.

[0034] The second barrier pattern (not shown) may conformally cover the bit line spacer BSP and the storage node contact BC or overlap the bit line spacer BSP and the storage node contact BC. For example, the second barrier pattern may include a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir). An ohmic pattern (not shown) may be further interposed between the second barrier pattern and the storage node contact BC. For example, the ohmic pattern may include a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0035] A landing pad LP may be disposed on the storage node contact BC and may be electrically connected to one of the first edge portion EA1 and the second edge portion EA2 of the corresponding active pattern ACT through the corresponding storage node contact BC.

[0036] The landing pad LP may include a lower landing pad LPx and an upper landing pad LPy sequentially disposed on the storage node contact BC. The lower landing pad LPx and the upper landing pad LPy may be distinguished from each other by an interface and may contact each other.

[0037] The lower landing pad LPx may be disposed on the second lateral surface FNxS2 of the lower fence pattern FNx. The lower landing pad LPx may be sandwiched between the bit line cap patterns BCP adjacent to each other in the first direction D1. The lower landing pad LPx may be sandwiched between the lower fence patterns FNx adjacent to each other in the second direction D2. A plurality of lower landing pads LPx may be provided. Each lower landing pad LPx may be spaced apart from each other in the first direction D1 and the second direction D2. The lower landing pads LPx adjacent to each other in the first direction D1 may be spaced apart from each other across the bit line cap pattern BCP. The lower landing pads LPx adjacent to each other in the second direction D2 may be spaced apart from each other across the lower fence pattern FNx. The top surface LPxa of the lower landing pad LPx may be located at a level lower than the top surface FNya of the upper fence pattern FNy and substantially the same level as the bottom surface FNyb of the upper fence pattern FNy. In other words, the top surface LPxa of the lower landing pad LPx may be located at a height lower than the top surface FNya of the upper fence pattern FNy relative to the top surface of the substrate 100 and substantially the same height as the bottom surface FNyb of the upper fence pattern FNy. The lower landing pad LPx may have a uniform width in the second direction D2. For example, the width of the lower landing pad LPx in the second direction D2 may be substantially constant or may decrease in the downward direction.

[0038] The upper lap pad LPy may be disposed on the second lateral surface FNyS2 of the upper fence pattern FNy. The upper lap pad LPy and the upper fence pattern FNy may be adjacent to each other in the second direction D2. The upper lap pad LPy may be located at a level higher than that of the bit line cap pattern BCP. The upper lap pad LPy may be sandwiched between the fill patterns FIL adjacent to each other in the first direction D1 described later. The upper lap pad LPy may be sandwiched between the upper fence patterns FNy adjacent to each other in the second direction D2. A plurality of upper lap pads LPy may be provided. Each upper lap pad LPy may be spaced apart from each other in the first direction D1 and the second direction D2. The upper lap pads LPy adjacent to each other in the first direction D1 may be spaced apart from each other across the fill pattern FIL or there may be a fill pattern FIL between the upper lap pads LPy adjacent to each other in the first direction D1. The upper landing pads LPy adjacent to each other in the second direction D2 may be spaced apart from each other across the upper fence pattern FNy. When viewed in a plane, the upper landing pads LPy may be linearly disposed along the first direction D1 between the word lines WL adjacent to each other in the second direction D2. The upper landing pads LPy may be linearly disposed along the second direction D2 between the fill patterns FIL adjacent to each other in the first direction D1.

[0039] The top surface LPya of the upper landing pad LPy may be located at substantially the same level or height as the top surface FNya of the upper fence pattern FNy relative to the top surface of the substrate. The upper landing pad LPy may protrude more than the lower landing pad LPx in the first direction D1.

[0040] For example, both the lower lap pad LPx and the upper lap pad LPy may not be recessed in the second direction D2 relative to the fill pattern FIL to be discussed below. When viewed in the second direction D2, the bottom surface of the upper lap pad LPy may have a width substantially the same as the width of the top surface LPxa of the lower lap pad LPx. When viewed in the second direction D2, the upper lap pad LPy may vertically overlap with the top surface LPxa of the lower lap pad LPx and completely cover the top surface LPxa of the lower lap pad LPx or completely overlap with the top surface LPxa of the lower lap pad LPx. Therefore, a large contact area may be provided between the top surface LPxa of the lower lap pad LPx and the bottom surface of the upper lap pad LPy. Therefore, electrical connection may be easily achieved between the upper lap pad LPy and the corresponding lower lap pad LPx of the upper lap pad LPy and the electrical properties of the semiconductor device may be improved.

[0041] The lapping pad LP may have a first lateral surface LPS1 pointing in the first direction D1, a second lateral surface LPS2 pointing in the second direction D2 or in the opposite direction of the second direction D2, and a third lateral surface LPS3 opposite to the first lateral surface LPS1. The first lateral surface LPS1 of the lapping pad LP may include a first lateral surface LPxS1 of a lower lapping pad LPx and a first lateral surface LPyS1 of an upper lapping pad LPy. The second lateral surface LPS2 of the lapping pad LP may include a second lateral surface LPxS2 of the lower lapping pad LPx and a second lateral surface LPyS2 of the upper lapping pad LPy. The third lateral surface LPS3 of the lapping pad LP may include a third lateral surface LPxS3 of the lower lapping pad LPx and a third lateral surface LPyS3 of the upper lapping pad LPy.

[0042] The second lateral surface LPxS2 of the lower landing pad LPx may contact the second lateral surface FNxS2 of the lower fence pattern FNx. The second lateral surface LPxS2 of the lower landing pad LPx may be continuously connected to the second lateral surface LPyS2 of the upper landing pad LPy. The second lateral surface LPxS2 of the lower landing pad LPx may be flat. For example, the second lateral surface LPxS2 of the lower landing pad LPx may not be recessed.

[0043] The first lateral surface LPyS1 and the third lateral surface LPyS3 of the upper lap pad LPy may each be in contact with the second lateral surface LPyS2 of the upper lap pad LPy. For example, the first lateral surface LPyS1 and the third lateral surface LPyS3 of the upper lap pad LPy may each be in contact with the second lateral surface LPyS2 of the upper lap pad LPy, and at the same time, a corner may be formed between the second lateral surface LPyS2 and each of the first lateral surface LPyS1 and the third lateral surface LPyS3. The corner may be angled or may have a curvature.

[0044] A filling pattern FIL may be interposed between upper landing pads LPy adjacent to each other in the first direction D1. The filling pattern FIL may extend in the second direction D2 on the bit line BL. A top surface FILa of the filling pattern FIL may be located at substantially the same level as a top surface LPya of the upper landing pad LPy and a top surface FNya of the fence pattern FN. The filling pattern FIL may be adjacent to the landing pad LP and the fence pattern FN in the first direction D1.

[0045] A plurality of filling patterns FIL may be provided. The plurality of filling patterns FIL may be spaced apart from each other in the first direction D1. The filling patterns FIL adjacent to each other in the first direction D1 may be spaced apart from each other across the upper lap pad LPy or the upper fence pattern FNy. One of a pair of filling patterns FIL adjacent to each other in the first direction D1 may be in contact with the first lateral surface LPyS1 of the upper lap pad LPy and the first lateral surface FNyS1 of the upper fence pattern FNy. The other of the pair of filling patterns FIL adjacent to each other in the first direction D1 may be in contact with the third lateral surface LPyS3 of the upper lap pad LPy and the third lateral surface FNyS3 of the upper fence pattern FNy. For example, the filling pattern FIL may include at least one of silicon nitride (SiN), silicon oxide (SiO 2) and / or silicon oxynitride (SiON).

[0046] A data storage pattern DSP may be disposed on the landing pad LP. A plurality of data storage patterns DSP may be disposed, and the plurality of data storage patterns DSP may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the data storage patterns DSP may vertically overlap at least a portion of the corresponding landing pad LP. For example, each of the data storage patterns DSP may vertically overlap the entirety of the corresponding landing pad LP in a direction perpendicular to the top surface of the substrate 100. In some embodiments, each of the data storage patterns DSP may be offset more than the landing pad LP in the first direction D1 or in a direction opposite to the first direction D1, and may vertically overlap a portion of the landing pad LP. The data storage pattern DSP may be electrically connected to one of the first edge portion EA1 and the second edge portion EA2 of the corresponding active pattern ACT via the corresponding landing pad LP and the corresponding storage node contact BC.

[0047] The data storage pattern DSP may be, for example, a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device according to the concept of the present invention may be a dynamic random access memory (DRAM). For another example, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor device according to the concept of the present invention may be a magnetic random access memory (MRAM). For another example, the data storage pattern DSP may include a phase change material or a variable resistance material. In this case, the semiconductor device according to the concept of the present invention may be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). However, this is only an example and the concept of the present invention is not limited thereto. The data storage pattern DSP may include various structures and / or materials capable of storing data.

[0048] 3 to 4B, a semiconductor device according to some embodiments of the present inventive concept will be described below. For the sake of brevity, the explanation of components that are repeated with the components discussed above will not be repeated, and the differences will be discussed in detail.

[0049] FIG. 3 shows a cross-sectional view taken along line AA′ shown in FIG. 1 .

[0050] 3 , a first seed pattern SD1 may be interposed between the bit line contact DC and the active pattern ACT. In this case, the bit line contact DC may include a metallic material, such as Ti, Mo, W, Cu, Al, Ta, Ru, or Ir. When manufacturing a semiconductor device, the bit line contact DC may be grown from the first seed pattern SD1 used as a seed. The first seed pattern SD1 may increase the contact resistance between the bit line contact DC and the active pattern ACT. For example, the first seed pattern SD1 may include a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir). For example, unlike what is shown, the polysilicon pattern PP may not be provided.

[0051] 4A and 4B are cross-sectional views respectively taken along line AA′ and line CC′ shown in FIG. 1 .

[0052] 4A and 4B , a second seed pattern SD2 may be interposed between the bit line BL and the bit line contact DC. In this case, the bit line contact DC may include silicon doped with impurities or silicon not doped with impurities. The second seed pattern SD2 may be further interposed between the bit line BL and the polysilicon pattern PP. When manufacturing a semiconductor device, the bit line BL may be grown from the second seed pattern SD2 used as a seed. The second seed pattern SD2 may increase the contact resistance between the bit line BL and the bit line contact DC. For example, the second seed pattern SD2 may include a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0053] 5 to 14, the following will describe methods for making semiconductor devices according to some embodiments of the present inventive concept. For the sake of brevity, the explanation of components that are repeated with the components discussed above will not be repeated, and the differences will be discussed in detail.

[0054] 5 to 10C are plan views and cross-sectional views illustrating methods of manufacturing semiconductor devices according to some embodiments of the present inventive concept. FIG. 5, FIG. 7, and FIG. 9 are plan views illustrating methods of manufacturing semiconductor devices according to some embodiments of the present inventive concept. FIG. 6A, FIG. 8A, and FIG. 10A illustrate cross-sectional views taken along lines AA' shown in FIG. 5, FIG. 7, and FIG. 9, respectively. FIG. 6B, FIG. 8B, and FIG. 10B illustrate cross-sectional views taken along lines BB' shown in FIG. 5, FIG. 7, and FIG. 9, respectively. FIG. 6C, FIG. 8C, and FIG. 10C illustrate cross-sectional views taken along lines CC' shown in FIG. 5, FIG. 7, and FIG. 9, respectively.

[0055] 5 and 6A to 6C, a substrate 100 may be provided. A device isolation pattern STI may be formed in an upper portion of the substrate 100 and buried in the upper portion of the substrate 100. The formation of the device isolation pattern STI may include: performing a patterning process to partially remove the upper portion of the substrate 100 and filling the removed area with the device isolation pattern STI. An active pattern ACT may be defined to indicate an area of ​​the substrate 100 surrounded by the device isolation pattern STI (e.g., an upper portion of the substrate 100 that is not removed). An impurity region may be formed in the active pattern ACT. The formation of the impurity region may include: performing an ion implantation process to implant impurities into the active pattern ACT.

[0056] The word line WL may be formed in a trench formed on an upper portion of the substrate 100. The formation of the word line WL may include: forming a mask pattern (not shown) on the active pattern ACT and the device isolation pattern STI; performing an anisotropic etching process using the mask pattern to form the trench; and partially or completely filling the trench with the word line WL.

[0057] For example, filling the trench with the word line WL may include: conformally depositing a gate dielectric pattern GI on the inner surface of the trench; filling the trench with a conductive layer so that the conductive layer can undergo an etch-back process and / or a grinding process to form a gate electrode GE; and forming a gate cap pattern GC on the gate electrode GE to fill the unoccupied portion of the trench.

[0058] The buffer pattern BP and the poly-silicon pattern PP may be sequentially formed on the substrate 100. The buffer pattern BP and the poly-silicon pattern PP may be formed to cover or overlap the active pattern ACT and the device isolation pattern STI.

[0059] A first groove RS1 may be formed on the active pattern ACT and the device isolation pattern STI. When forming the first groove RS1, the buffer pattern BP and the polysilicon pattern PP may be partially removed. A bit line contact layer DCL may be formed to fill the first groove RS1.

[0060] A first bit line mask layer BMP1L may be formed on the front surface of the substrate 100. The first bit line mask layer BMP1L may include a dielectric material having an etching selectivity relative to surrounding components (e.g., a bit line spacer BSP and a storage node contact BC to be discussed below). For example, the first bit line mask layer BMP1L may include at least one of silicon oxide (SiO 2) and / or silicon oxycarbide (SiOC). A first barrier layer (not shown) may be further formed between the first bit line mask layer BMP1L and the bit line contact layer DCL.

[0061] A second bit line mask pattern BMP2 may be formed on the first bit line mask layer BMP1L. The second bit line mask pattern BMP2 may extend in the second direction D2. A plurality of second bit line mask patterns BMP2 may be provided and may be spaced apart from each other in the first direction D1.

[0062] 7 and 8A to 8C, a bit line contact DC and a first bit line mask pattern BMP1 may be formed by using the second bit line mask pattern BMP2 as an etching mask to remove a portion of the bit line contact layer DCL and a portion of the first bit line mask layer BMP1L. The portion of the bit line contact layer DCL that is not removed may constitute or may be the bit line contact DC. The portion of the first bit line mask layer BMP1L that is not removed may constitute or may be the first bit line mask pattern BMP1. The first bit line mask pattern BMP1 may be formed on the bit line contact DC. The first bit line mask pattern BMP1 may extend in the second direction D2 on the active pattern ACT. The first bit line mask patterns BMP1 may be spaced apart from each other in the first direction D1.

[0063] The bit line spacer BSP may be formed to fill the unoccupied portion of the first recess RS1 and cover or overlap the lateral surface of the bit line contact DC and the lateral surface of the first bit line mask pattern BMP1. The formation of the bit line spacer BSP may include forming a plurality of spacers. For example, the first to third spacers may be sequentially formed on the lateral surface of the first bit line mask pattern BMP1.

[0064] A storage node contact BC may be formed between the first bit line mask patterns BMP1 adjacent to each other in the first direction D1. The formation of the storage node contact BC may include: performing a removal process on a portion of the bit line spacer BSP; forming a second recess RS2 by removing a portion of the buffer pattern BP, a portion of each of the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT, and a portion of the device isolation pattern STI; forming a storage node contact layer (not shown) to fill the space between the second recess RS2 and the first bit line mask pattern BMP1 and cover or overlap the top surface of the first bit line mask pattern BMP1; and removing the storage node contact layer on the top surface of the first bit line mask pattern BMP1 to separate the storage node contacts BC adjacent to each other in the first direction D1 from each other. A chemical mechanical polishing (CMP) process may be performed to remove the storage node contact layer on the top surface of the first bit line mask pattern BMP1.

[0065] 9 and 10A to 10C, a bit line BL may be formed on a bit line contact DC. For example, the formation of the bit line BL may include: removing a first bit line mask pattern BMP1 on the bit line contact DC; and forming the bit line BL in a portion of each of the regions where the first bit line mask pattern BMP1 is removed. The bit line BL may be formed by selective epitaxial growth. Selective epitaxial growth may be one of deposition methods that grows a specific material only on a specific region.

[0066] According to the present invention, the bit line BL can be formed by selective epitaxial growth. Therefore, the bit line BL can be formed to have grains with the same crystal orientation. Therefore, the resistance of the bit line BL can be reduced and the electrical properties of the semiconductor device can be improved.

[0067] A bit line cap pattern BCP may be formed on the bit line BL. For example, the formation of the bit line cap pattern BCP may include: forming a bit line cap layer (not shown) to fill the unoccupied portion of the region where the first bit line mask pattern BMP1 is removed and to cover or overlap the top surface of the storage node contact BC; and removing the bit line cap layer on the top surface of the storage node contact BC to separate the bit line cap patterns BCP adjacent to each other in the first direction D1 from each other. For example, a chemical mechanical polishing (CMP) process may be performed to remove the bit line cap layer on the top surface of the storage node contact BC.

[0068] According to the concept of the present invention, a bit line BL and a bit line cap pattern BCP may be sequentially formed in a region where the first bit line mask pattern BMP1 is removed. Therefore, an etching process for forming the bit line BL and the bit line cap pattern BCP may not be performed separately. Instead, the bit line contact DC, the bit line BL, and the bit line cap pattern BCP may be formed by separate etching processes. In this case, the bit line cap pattern BCP may be used as an etching mask, and the bit line cap pattern BCP may be formed to have a greater height than when the bit line cap pattern BCP is not used as an etching mask. Therefore, the bit line cap pattern BCP may have a high aspect ratio, and thus when an etching process is performed on each of the bit line contact DC, the bit line BL, and the bit line cap pattern BCP, collapse may occur at each of the bit line contact DC, the bit line BL, and the bit line cap pattern BCP. Therefore, the manufacturing process of forming the bit line BL and the bit line cap pattern BCP using the first bit line mask pattern BMP1 may be easier than the manufacturing process of performing an etching process to form each of the bit line BL and the bit line cap pattern BCP, which may improve the productivity of semiconductor devices.

[0069] A lower landing pad LPx may be formed on the storage node contact BC. For example, the formation of the lower landing pad LPx may include: removing an upper portion of each of the storage node contacts BC; forming a lower landing pad layer to fill the region where the upper portion of each of the storage node contacts BC is removed and cover or overlap the top surface of the bit line cap pattern BCP; and removing the lower landing pad layer on the top surface of the bit line cap pattern BCP to form lower landing pads LPx adjacent to each other in the first direction D1. A chemical mechanical polishing (CMP) process may be performed to remove the lower landing pad layer on the top surface of the first bit line cap pattern BCP. The top surface LPxa of the lower landing pad LPx and the top surface of the bit line cap pattern BCP may be located at substantially the same level or height and may be coplanar with each other.

[0070] The fence mask pattern FMP may be formed to extend in the first direction D1 on the lower landing pad LPx. A plurality of fence mask patterns FMP may be provided. The plurality of fence mask patterns FMP may be spaced apart from each other in the second direction D2. The fence mask pattern FMP may include a dielectric material having an etching selectivity relative to surrounding components (e.g., a fence pattern FN to be discussed below). For example, the fence mask pattern FMP may include at least one of silicon oxide (SiO 2) and / or silicon oxycarbide (SiOC).

[0071] The fence pattern FN may be formed between the bit lines BL adjacent to each other in the first direction D1 and between the fence mask patterns FMP adjacent to each other in the second direction D2. For example, the formation of the fence pattern FN may include: using the fence mask pattern FMP as an etching mask to remove a portion of the storage node contact BC and a portion of the lower landing pad LPx; and forming the fence pattern FN to fill the region where the portion of the storage node contact BC and the portion of the lower landing pad LPx are removed and also fill the space between the fence mask patterns FMP. The lower fence pattern FNx may be defined as a portion of the fence pattern FN indicating that the region where the portion of the storage node contact BC and the portion of the lower landing pad LPx are removed is filled. The upper fence pattern FNy may be defined as another portion of the fence pattern FN indicating that the space between the fence mask patterns FMP is filled. The lower fence pattern FNx and the upper fence pattern FNy may constitute or may be the fence pattern FN. The lower fence pattern FNx may be formed to extend in the fourth direction D4 between the bit lines BL adjacent to each other in the first direction D1. The upper fence pattern FNy may be formed to extend in the first direction D1 between the fence mask patterns FMP adjacent to each other in the second direction D2. The top surface FNya of the upper fence pattern FNy may be located at a level or height higher than the level or height of the top surface LPxa of the lower landing pad LPx and substantially the same as the level or height of the top surface FMPa of the fence mask pattern FMP. The second lateral surface FNyS2 of the upper fence pattern FNy may contact the fence mask pattern FMP. When the fence pattern FN is formed, the fence pattern FN may separate one storage node contact BC into a plurality of storage node contacts BC spaced apart from each other in the second direction D2, and may separate one lower landing pad LPx into a plurality of lower landing pads LPx spaced apart from each other in the second direction D2.

[0072] 1 and 2A to 2C, an upper landing pad LPy may be formed on the lower landing pad LPx. For example, the formation of the upper landing pad LPy may include: removing the fence mask pattern FMP; forming an upper landing pad layer (not shown) to fill the area where the fence mask pattern FMP is removed and cover or overlap the top surface FNya of the fence pattern FN; and removing the upper landing pad layer on the top surface FNya of the fence pattern FN to separate the upper landing pads LPy spaced apart from each other in the second direction D2. The upper landing pad LPy may extend in the first direction D1 on the lower landing pad LPx together with the upper fence pattern FNy. The top surface LPya of the upper landing pad LPy and the top surface FNya of the fence pattern FN may be located at substantially the same level or height and may be coplanar with each other. The upper landing pads LPy adjacent to each other in the second direction D2 may be spaced apart from each other across the upper fence pattern FNy.

[0073] According to the inventive concept, an upper landing pad LPy can be formed between regions where the fence mask pattern FMP is removed (e.g., between upper fence patterns FNy adjacent to each other in the second direction D2). Therefore, a discrete patterning process for separating the upper landing pads LPy from each other in the second direction D2 can be omitted. In summary, the upper landing pad LPy can be easily formed and the productivity of the semiconductor device can be improved.

[0074] The filling pattern FIL may be formed to extend across the upper landing pad LPy and the upper fence pattern FNy or to be located on the upper landing pad LPy and the upper fence pattern FNy. The filling pattern FIL may be formed to extend in the second direction D2 on the bit line BL. When forming the filling pattern FIL, the filling pattern FIL may separate one upper fence pattern FNy into a plurality of upper fence patterns FNy spaced apart from each other in the first direction D1, and may separate one upper landing pad LPy into a plurality of upper landing pads LPy spaced apart from each other in the first direction D1. Thereafter, a data storage pattern DSP may be formed on each of the upper landing pads LPy.

[0075] 11 and 12 are cross-sectional views illustrating methods of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0076] 11, after the formation of the first groove RS1 discussed with reference to FIGS. 6A to 6C, a first seed layer SD1L may be formed in the first groove RS1. The first seed layer SD1L may be formed on the central portion CA of the active pattern ACT. For example, as shown, the first seed layer SD1L may cover the inner bottom surface of the first groove RS1, overlap with the inner bottom surface of the first groove RS1, or be located on the inner bottom surface of the first groove RS1. For another example, although not shown, the first seed layer SD1L may further cover the inner lateral surface of the first groove RS1.

[0077] Thereafter, a bit line contact layer DCL may be formed to fill the first recess RS1. The bit line contact layer DCL may be formed by a growth process using the first seed layer SD1L as a seed.

[0078] 12, the bit line contact DC may be formed by the manufacturing process discussed above. In this process, a portion of the first seed layer SD1L may be removed and the first seed pattern SD1 may be formed. Thereafter, the semiconductor device discussed with reference to FIG. 3 may be manufactured by the manufacturing process discussed above.

[0079] 13 and 14 are cross-sectional views illustrating methods of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0080] 13, the formation of the first seed layer SD1L discussed with reference to FIG. 11 may be omitted. After the formation of the bit line contact layer DCL discussed with reference to FIGS. 6A to 6C, a second seed layer SD2L may be formed on the front surface of the substrate 100. The second seed layer SD2L may be formed between the bit line contact layer DCL and the first bit line mask layer BMP1L.

[0081] 14, the bit line contact DC may be formed by the manufacturing process discussed above. In this process, a portion of the second seed layer SD2L may be removed and a second seed pattern SD2 may be formed. Thereafter, the semiconductor device discussed with reference to FIGS. 4A and 4B may be manufactured by the manufacturing process discussed above.

[0082] According to the concept of the present invention, a bit line can be formed by selective epitaxial growth. Therefore, the bit line can be formed to have grains with the same crystal orientation. Therefore, the resistance of the bit line can be reduced and the electrical properties of the semiconductor device can be improved.

[0083] According to the inventive concept, a bit line and a bit line cap pattern can be sequentially formed in a region where a first bit line mask pattern is removed. Therefore, etching processes for forming the bit line and the bit line cap pattern may not be performed separately. Therefore, the bit line and the bit line cap pattern can be easily formed and the productivity, performance or yield of a semiconductor device can be improved.

[0084] According to the inventive concept, an upper landing pad can be formed in a region where the fence mask pattern is removed (e.g., between upper fence patterns adjacent to each other in the second direction). Therefore, a discrete patterning process for separating the upper landing pads from each other in the second direction can be omitted. In summary, the upper landing pad can be easily formed and the productivity, performance, or yield of the semiconductor device can be improved.

[0085] The above description provides some embodiments to illustrate the concept of the present invention. Therefore, the concept of the present invention is not limited to the above embodiments, and those skilled in the art will understand that changes in form and detail can be made without departing from the spirit and characteristics of the concept of the present invention.

[0086] 100:Substrate A-A', B-B', C-C': Line ACT: Active Pattern BC: Storage node contact BCP: Bit Line Cap Pattern / First Bit Line Cap Pattern BL: Bit Line BMP1: First bit line mask pattern BMP1L: First bit line mask layer BMP2: Second bit line mask pattern BP: Buffer Pattern BSP: Bit Line Spacer BSPa, FILa, FMPa, FNya, LPxa, LPya: top surface CA:Central part D1: First direction D2: Second direction D3: Third direction D4: The fourth direction DC: Bit line contacts DCL: Bit Line Contact Layer DSP: Data storage pattern EA1: First edge section EA2: Second edge section FIL: Fill pattern FMP: Fence Mask Pattern FN: Fence pattern FNS1, FNxS1, FNyS1, LPS1, LPxS1, LPyS1: first lateral surface FNS2, FNxS2, FNyS2, LPS2, LPxS2, LPyS2: Second lateral surface FNS3, FNxS3, FNyS3, LPS3, LPxS3, LPyS3: third lateral surface FNx: Lower fence pattern FNxb: Bottom surface FNy: Upper fence pattern GC: Gate cap pattern GE: Gate Electrode GI: Gate dielectric pattern LP: Lap Pad LPx: Lower Lap Pad LPy: Upper Lap Pad PP: Polysilicon Pattern RS1: First groove RS2: Second groove SD1: First seed pattern SD1L: First seed layer SD2: Second seed pattern SD2L: Second seed layer STI: Device Isolation Pattern TR: Trench area WL: Character Line

Claims

1. A semiconductor device, comprising: Active pattern, located on the substrate and surrounded by device-isolated patterns in a plan view; A character line extending in a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to the bottom surface of the substrate; a bit line extending in a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact located on the active pattern; an overlap pad including a lower overlap pad and an upper overlap pad stacked on the storage node contact, with an interface between the lower overlap pad and the upper overlap pad; and a fence pattern located on the lateral surfaces of the character line and the overlap pad, wherein the top surface of the fence pattern is higher than the top surface of the interface between the lower overlap pad and the upper overlap pad relative to the substrate.

2. The semiconductor device of claim 1, wherein the top surface of the fence pattern is substantially at the same height relative to the top surface of the substrate and the upper overlap pad.

3. The semiconductor device of claim 1, wherein the fence pattern comprises a lower fence pattern and an upper fence pattern, the lower fence pattern and the upper fence pattern being distinct from each other without an interface, wherein the upper fence pattern protrudes beyond the lower fence pattern in the first direction.

4. The semiconductor device of claim 1, wherein the bit line comprises a material having grains having the same crystal orientation.

5. A semiconductor device, comprising: Active pattern, located on the substrate and surrounded by device-isolated patterns in a plan view; A character line extends in a first direction and is located on the active pattern and the device isolation pattern, wherein the first direction is parallel to the bottom surface of the substrate; a bit line extends in a second direction on the active pattern, wherein the second direction intersects the first direction; a storage node contact is located on the active pattern; and an overlap pad is located on the storage node contact. And a fence pattern located on the lateral surface of the character line and the overlapping pad, wherein the fence pattern includes: a lower fence pattern located on the lateral surface of the character line; And an upper fence pattern located on the lower fence pattern, wherein the upper fence pattern includes a protrusion that protrudes from the lower fence pattern in the first direction, and the protrusion is located on one side of the overlapping pad.

6. The semiconductor device of claim 5, wherein the overlap pad includes a lower overlap pad and an upper overlap pad stacked on the storage node contact, wherein the top surface of the upper overlap pad is substantially at the same height relative to the substrate and the top surface of the upper fence pattern.

7. The semiconductor device as claimed in claim 5, further comprising: A fill pattern is located on the bit line and extends in the second direction, wherein the top surface of the fill pattern is substantially at the same height relative to the substrate and the top surface of the upper fence pattern.

8. The semiconductor device of claim 7, wherein the upper gate pattern comprises: A first lateral surface, located in the first direction; and a second lateral surface located in the second direction, wherein the first lateral surface of the upper fence pattern contacts the filling pattern, and wherein the second lateral surface of the upper fence pattern contacts the overlapping pad.

9. A semiconductor device, comprising: Active pattern, located on the substrate and surrounded by device-isolated patterns in a plan view; Character lines extending in a first direction and located on the active pattern and the device isolation pattern, wherein the first direction is parallel to the bottom surface of the substrate; bit lines extending in a second direction on the active pattern, wherein the second direction intersects the first direction; storage node contacts located on the active pattern; overlap pads located on the storage node contacts; fence patterns located on the lateral surfaces of the character lines and the overlap pads. And a fill pattern, located on the bit line and extending in the second direction, wherein the top surface of the fence pattern is substantially at the same height relative to the substrate as the top surface of the fill pattern.

10. The semiconductor device of claim 9, wherein the overlap pad comprises: A first lateral surface, located in the first direction; and a second lateral surface located in the second direction, wherein the first lateral surface of the overlapping pad contacts the filling pattern, and wherein the second lateral surface of the overlapping pad contacts the fence pattern.

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