Transistor and semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same, with various embodiments. In one embodiment, the exemplary semiconductor structure includes a first transistor, the first transistor including a first gate structure, a first source / drain component, and a first semiconductor layer. The first gate structure surrounds a plurality of first nanostructures disposed above a substrate. The first source / drain component is electrically coupled to the topmost nanostructure of the first nanostructure and is separated from the bottommost nanostructure of the first nanostructure by a first dielectric layer. The first semiconductor layer is disposed between the first source / drain components of the substrate, wherein the first source / drain components are in direct contact with the top surface of the first semiconductor layer.

Description

Transistors, Semiconductor Structures, and Methods of Manufacturing the Same Embodiments of the present invention relate to semiconductor technology, and more particularly, to a transistor having a dielectric layer, a semiconductor structure, and a method of manufacturing the same. The semiconductor integrated circuit industry has experienced rapid growth. Technological advancements in integrated circuit materials and design have led to several generations of integrated circuits, with each generation of circuits being smaller and more complex than the previous one. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per unit chip area) generally increases while the geometric dimensions (i.e., the smallest element (or line) that can be produced using the process) decrease. This miniaturization process typically provides benefits in terms of increased production efficiency and reduced associated costs. However, this miniaturization is also accompanied by more complex designs and processes for integrating the integrated circuits into devices. The corresponding progress in the process enables more complex designs to be manufactured in an accurate and reliable manner. For example, as integrated circuit technology has advanced to smaller process generations (technology nodes), multi-gate devices have been introduced, which improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure or a portion thereof, and is disposed on more than one side of a channel. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors (both are also referred to as non-planar transistors) are examples of multi-gate devices and have become popular and promising candidate application devices for high performance and low leakage. A FinFET has a raised channel with more than one side covered by a gate (e.g., the gate covers the top and sidewalls of a semiconductor material "fin" extending from a substrate). A GAA transistor has a gate structure that can extend and partially or completely surround a channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be composed of nanowires, nanosheets, other nanostructures, and / or other suitable structures, and a GAA transistor can also be referred to as a nanostructure transistor. Since semiconductor integrated circuits typically include a variety of different device types with different performance requirements, providing multi-gate devices (e.g., GAA transistors) that can meet such diverse device performance requirements remains a challenge. Therefore, the prior art is not entirely satisfactory in various aspects. In an exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first transistor, the first transistor including a first gate structure, a first source / drain component, and a first semiconductor layer. The first gate structure surrounds a plurality of first nanostructures disposed above a substrate. The first source / drain component is electrically coupled to the topmost nanostructure of the first nanostructures and is separated from the bottommost nanostructure of the first nanostructures by a first dielectric layer. The first semiconductor layer is disposed between the substrate and the first source / drain component, wherein the first source / drain component is in direct contact with the top surface of the first semiconductor layer. In another exemplary aspect, the present disclosure relates to a transistor. The transistor includes a gate structure, an undoped semiconductor layer, a dielectric layer, and a source / drain component. The gate structure surrounds a plurality of nanostructures disposed above a substrate. The undoped semiconductor layer is located in and above the substrate, wherein the top surface of the undoped semiconductor layer is flush with or above the top surface of the bottommost nanostructure of the nanostructures. The dielectric layer is disposed between the undoped semiconductor layer and the bottommost nanostructure of the nanostructures. The source / drain component is adjacent to the nanostructures, wherein the bottom surface of the source / drain component is in direct contact with the top surface of the undoped semiconductor layer. In yet another exemplary aspect, the present disclosure relates to a method of manufacturing a semiconductor structure. The method includes forming a first fin-shaped active region extending from a substrate and including a plurality of channel layers interleaved by a plurality of sacrificial layers, forming a first gate stack above a first channel region of the first fin-shaped active region, recessing a first source / drain region of the first fin-shaped active region to form a first source / drain opening, forming a first semiconductor layer in the bottom of the first source / drain opening, forming a first dielectric layer on the first semiconductor layer and extending along a sidewall surface of an intermediate portion of the first source / drain opening, wherein an entire sidewall surface of the bottommost channel layer of the channel layers is covered by the first dielectric layer, forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer, forming a first source / drain component on the second semiconductor layer, and replacing the first gate stack and the sacrificial layers with a gate structure. The following disclosure provides numerous examples or embodiments for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is described that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations being discussed. Furthermore, spatially relative terms may be used, such as "beneath", "below", "lower", "above", "higher", etc., for the purpose of facilitating the description of the relationship between one or more components or parts in a diagram. Spatially relative terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after turning. In addition, when using terms such as "about", "approximate", etc. to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range, which is considered based on the variations inherently occurring in the manufacturing process as understood by those of ordinary skill in the art. For example, based on the known manufacturing tolerances for manufacturing components with characteristics related to that number, the quantity or range of numbers covers a reasonable range including the said number, such as within + / - 10% of the said number. For example, those of ordinary skill in the art know that the manufacturing tolerance related to a deposited material layer is + / - 15%, and a material layer with a thickness of "about 5 nanometers" can cover a size range from 4.25 nanometers to 5.75 nanometers. GAA transistors have a wide range of applications. In some embodiments (e.g., low-power devices), GAA transistors can be designed to provide low leakage current to reduce power consumption, while in some other embodiments (e.g., high-performance devices), GAA transistors can be designed to have high drive current and high speed. Generally, transistors with a smaller effective channel width (Weff) tend to have lower power consumption. For example, a logic hybrid cell can include high-performance transistors and low-power transistors. Manufacturing GAA transistors to meet different application requirements may involve complex processes and come with high costs. In addition, forming p-type GAA transistors with satisfactory strain performance while providing low leakage current remains a challenge. The present disclosure provides a hybrid nanoscale structure solution, which can form a semiconductor structure having both high-speed GAA transistors and low-power GAA transistors by configuring different numbers of effective channel layers (coupled to corresponding source / drain components). In one embodiment, the low-power GAA transistor can have a smaller number of channel layers, which are coupled to corresponding n-type / p-type source / drain components; while the high-speed GAA transistor can have a larger number of channel layers, which are coupled to corresponding n-type / p-type source / drain components. The low-power GAA transistor includes a vertical sidewall dielectric layer, which provides isolation between the source / drain components and the bottommost channel layer in, for example, the channel region. By implementing this hybrid nanoscale structure solution, GAA transistors with different electrical properties can be formed on the same substrate. In addition, forming this vertical sidewall dielectric layer to provide isolation allows the p-type source / drain components of the p-type lower-power GAA transistor to grow epitaxially from bottom to top, thereby maintaining satisfactory strain performance. Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, FIG. 1 is a flowchart showing a method 100 of forming a semiconductor structure according to an embodiment of the present disclosure. Method 100 will be described below in conjunction with FIG. 2 and FIGS. 3A to 16H, which are partial top view / cross-sectional views of a semiconductor structure 200 at various manufacturing stages according to an embodiment of method 100. FIG. 17 is a flowchart showing a method 300 of forming a semiconductor structure according to an embodiment of the present disclosure. Method 300 will be described below in conjunction with FIG. 2 and FIGS. 18A to 24H, which are partial top view / cross-sectional views of a semiconductor structure 400 / 400' at various manufacturing stages according to an embodiment of method 300. FIG. 25 is a flowchart showing a method 500 of forming a semiconductor structure according to an embodiment of the present disclosure. Method 500 will be described below in conjunction with FIG. 2 and FIGS. 26A to 29H, which are partial top view / cross-sectional views of a semiconductor structure 600 / 600' at various manufacturing stages according to an embodiment of method 500. Methods 100 / 300 / 500 are merely illustrative and are not intended to limit the present disclosure to the specifically described content. Additional steps may be provided before, during, and after methods 100 / 300 / 500, and some of the described steps may be replaced, deleted, or moved for additional embodiments of the methods. For brevity, not all steps are described in detail herein. To avoid controversy, the X, Y, and Z directions in FIGS. 2 to 16H, FIGS. 18A to 24H, and FIGS. 26A to 29H are perpendicular to each other and are consistently used throughout the present disclosure. In the present disclosure, unless otherwise stated, similar reference numerals represent similar components. Referring to FIGS. 1, 2, 3A-3H, method 100 includes block 102, where a semiconductor structure 200 including a first region 10 and a second region 20 is received. FIG. 2 is a partial top view of an exemplary semiconductor structure 200 at various manufacturing stages in method 100 of FIG. 1, according to various aspects of the present disclosure. FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H illustrate partial cross-sectional views of semiconductor structure 200 taken along lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H' in FIG. 2, respectively. As shown in FIGS. 3A-3H, semiconductor structure 200 includes a substrate 202. Substrate 202 can be an elemental (single-element) semiconductor, such as crystalline silicon (Si) or germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); a non-semiconductor material, such as soda-lime glass, fused silica, fused quartz, and / or calcium fluoride (CaF 2 ); and / or a combination of the foregoing. In one embodiment, substrate 202 is a silicon (Si) substrate. Substrate 202 can be homogeneous in composition or can include different film layers, some of which can be selectively etched to form fin-shaped active regions (e.g., fin-shaped active regions 204a-204b). These film layers can have similar or different compositions, and in various embodiments, some of the film layers of the substrate have non-uniform compositions to induce device strain and thereby adjust device performance. Exemplary layered substrates also include silicon-on-insulator (SOI) substrates 202. In some such examples, the insulator layer of substrate 202 includes a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and / or other suitable insulator materials. Doped regions, such as wells, can be formed in substrate 202. In the embodiment illustrated in FIG. 2, the portion of substrate 202 in the first region 10 is doped with a p-type dopant and can be referred to as a p-type well (not shown), and the portion of substrate 202 in the second region 20 is doped with an n-type dopant and can be referred to as an n-type well (not shown). P-type dopants can include boron (B), boron difluoride (BF 2), or indium (In). The n-type dopant may include phosphorus (P) or arsenic (As). The n-type well and the p-type well can be formed using ion implantation or thermal diffusion and can be regarded as part of the substrate 202. As will be further described below, the first region 10 is an n-type field effect transistor (NFET) region for forming NFETs with different numbers of nanostructures, and the second region 20 is a p-type field effect transistor (PFET) region for forming PFETs with different numbers of nanostructures. In the present disclosure, high-speed n-type devices and high-speed p-type devices will be formed in the first n-type device region 200N3 and the first p-type device region 200P3, respectively; low-power n-type devices and low-power p-type devices will be formed in the second n-type device region 200N2 and the second p-type device region 200P2, respectively. As will be further described below, compared with the source / drain components of the GAA transistors formed in the first n-type device region 200N3 / first p-type device region 200P3, the source / drain components of the GAA transistors formed in the second n-type device region 200N2 / second p-type device region 200P2 will be coupled to a smaller number of channel layers (i.e., nanostructures). Still referring to FIGS. 2 and 3A - 3H, the semiconductor structure 200 includes a plurality of fin - shaped active regions (e.g., fin - shaped active regions 204a, 204b) protruding from a substrate 202. In this embodiment, the first region 10 includes the fin - shaped active region 204a, and the second region 20 includes the fin - shaped active region 204b. The number of fin - shaped active regions depicted in FIG. 2 is merely illustrative, and the semiconductor structure 200 may include any suitable number of active regions. Each of the fin - shaped active regions 204a - 204b may be formed by the top 202t of the substrate 202 (shown in FIG. 3E) and a vertical stack 207 of alternating semiconductor layers disposed on the top surface of the substrate 202 (shown in FIG. 3E). In one embodiment, the vertical stack 207 includes a plurality of channel layers (e.g., channel layers 208b, 208m, 208t) interleaved by a plurality of sacrificial layers 206. The channel layers 208b, 208m, 208t may be referred to individually or collectively as the channel layer 208. Each channel layer 208 may include a semiconductor material, such as silicon, germanium, silicon carbide, silicon germanium, germanium tin (GeSn), silicon germanium tin (SiGeSn), silicon germanium carbon tin (SiGeCSn), other suitable semiconductor materials, or a combination of the foregoing, and the composition of each sacrificial layer 206 is different from that of the channel layer 208. In one embodiment, the channel layer 208 includes silicon (Si), and the sacrificial layer 206 includes silicon germanium (SiGe). Although the illustrated vertical stack 207 includes three channel layers 208b, 208m, 208t and three sacrificial layers 206, it should be understood that the vertical stack 207 may include any suitable number (e.g., 2 to 10) of channel layers and any suitable number of sacrificial layers. Next, the vertical stack 207 and the top 202t of the substrate 202 are patterned to form the fin - shaped active regions 204a - 204b. In some embodiments, the patterned top 202t of the substrate 202 may be referred to as a mesa structure 202t. Each of the fin - shaped active regions 204a - 204b extends longitudinally along the X - direction and is divided into a channel region 204C overlapping with a dummy gate stack 210 (to be described below) and a source / drain region 204SD not overlapping with the dummy gate stack 210. The source / drain region 204SD may refer to the source region or the drain region individually or collectively, depending on the context. Each channel region 204C is disposed between two source / drain regions 204SD along the X - direction. In one embodiment, each of the fin - shaped active regions 204a - 204b has a uniform width (e.g., width W1). The semiconductor structure 200 also includes isolation components 205 (as shown in FIGS. 3E to 3H) formed around the fin-shaped active regions 204a-204b to separate one fin-shaped active region from an adjacent fin-shaped active region. The isolation component 205 may include a shallow trench isolation (STI) component 205 and may include silicon oxide, silicon oxynitride, fluorinated silicate glass (FSG), a low dielectric constant (k) dielectric, a combination of the foregoing, and / or other suitable materials. The semiconductor structure 200 also includes dummy gate stacks 210. Each dummy gate stack 210 includes a dummy gate dielectric layer 210a, a dummy gate electrode layer 210b above the dummy gate dielectric layer 210a, and a gate top hard mask layer 210c above the dummy gate electrode layer 210b. The dummy gate dielectric layer 210a may include silicon oxide. The dummy gate electrode layer 210b may include polysilicon. The gate top hard mask layer 210c may include silicon oxide, silicon nitride, and / or other suitable materials. Suitable deposition processes, photolithography processes, and etching processes may be employed to form the dummy gate stacks 210. In this embodiment, a gate replacement process (or a post-gate process) is adopted, where the dummy gate stacks 210 serve as placeholders for functional gate structures (e.g., the metal gate structure 242 shown in FIGS. 15A to 15D). Other processes and configurations are also possible. Although only four dummy gate stacks 210 are illustrated in FIG. 2, the semiconductor structure 200 may include any appropriate number of dummy gate stacks 210. The semiconductor structure 200 also includes a gate spacer layer 212 over the substrate 202. The gate spacer layer 212 can be a single-layer structure or a multi-layer structure. In an exemplary process, a first spacer layer (not separately labeled) is conformally deposited over the semiconductor structure 200, and a second spacer layer (not separately labeled) is conformally deposited over the first spacer layer. The first spacer layer and the second spacer layer can be conformally deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. The term "conformally" can be used herein to facilitate the description of a film layer having a substantially uniform thickness over various regions of the semiconductor structure 200. The first spacer layer can include silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, carbon nitride, metal nitride, or other suitable dielectric materials. The second spacer layer can include silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, carbon nitride, metal nitride, or other suitable dielectric materials. The composition of the first spacer layer is different from the composition of the second spacer layer. In one embodiment, the second spacer layer includes silicon nitride (SiN). Referring to FIGS. 1 and 4A-4H, method 100 includes block 104, wherein the source / drain regions 204SD of the fin-shaped active regions 204a-204b are recessed to form source / drain openings 214. An etching process is performed to remove portions of the gate spacer layer 212 over the top-facing surface of the semiconductor structure 200 to form gate spacers 212a extending along the sidewalls of the dummy gate stack 210 and fin sidewall spacers 212b extending along the lower portions of the sidewalls of the fin-shaped active regions 204a-204b (as shown in FIGS. 4E-4H). In some embodiments, the source / drain regions 204SD of the fin-shaped active regions 204a-204b are anisotropically etched by plasma etching using a suitable etchant, such as an oxygen-containing etchant, a hydrogen-containing etchant, a fluorine-containing etchant (e.g., carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), difluoromethane (CH 2 F 2 ), fluoroform (CHF 3 ), and / or hexafluoroethane (C 2 F 6), chlorine etchant (e.g., chlorine gas (Cl 2 ), chloroform (CHCl 3 ), carbon tetrachloride (CCl 4 ), and / or boron trichloride (BCl 3 ), bromine etchant (e.g., hydrogen bromide (HBr) and / or hydrogen bromide (CHBR 3 ), iodine etchant, other suitable etchants, and / or combinations of the foregoing. In this embodiment, the source / drain opening 214 extends to the top 202t of the substrate 202. Referring to FIGS. 1 and 5A - 5D, method 100 includes block 106, where an inner spacer member (e.g., inner spacer members 216b, 216m, 216t) is formed. After forming the source / drain opening 214, the sacrificial layer 206 exposed in the source / drain opening 214 is selectively and partially etched to form an inner spacer recess (filled by inner spacer members 216b, 216m, 216t), while the exposed channel layer 208 is substantially unetched. In some embodiments, this selective etching may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree to which the sacrificial layer 206 is etched is controlled by the duration of the etching process. After forming the inner spacer recess, a conformal layer of inner spacer material is then deposited over the semiconductor structure 200 (including over and within the inner spacer recess) using CVD or ALD. The inner spacer material may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, silicon oxycarbide, silicon carbide, or silicon nitride oxide. The inner spacer material layer is then etchback to form the inner spacer members (e.g., inner spacer members 216b, 216m, and 216t), as shown in FIGS. 5A - 5D. In some embodiments, the composition of the inner spacer material layer is different from that of the gate spacer 212a and the fin sidewall spacer 212b, such that the etchback of the inner spacer material layer substantially does not etch the gate spacer 212a and the fin sidewall spacer 212b. In the illustrated embodiment, the bottommost inner spacer member 216b is disposed between the substrate 202 and the bottommost channel layer 208b, the middle inner spacer member 216m is disposed between the bottommost channel layer 208b and the middle channel layer 208m, and the topmost inner spacer member 216t is disposed between the middle channel layer 208m and the topmost channel layer 208t. The inner spacer members 216b, 216m, and 216t may be referred to individually or collectively as the inner spacer member 216. It should be understood that the number of inner spacer members 216 is a function of the number of sacrificial layers, and the semiconductor structure 200 may include any suitable number of inner spacer members. Referring now to FIGS. 1 and 6A-6D, method 100 includes block 108, where a first semiconductor layer 218 is formed in source / drain opening 214. In this embodiment, after forming the inner spacer member 216, the first semiconductor layer 218 is formed in the source / drain opening 214 by, for example, using an epitaxial process. Each first semiconductor layer 218 may be undoped or unintentionally doped. In some embodiments, the first semiconductor layer 218 may include undoped silicon (Si), undoped germanium (Ge), undoped silicon germanium (SiGe), or other suitable materials. In one embodiment, the first semiconductor layers 218 in device regions 200N3, 200N2, 200P3, and 200P2 are formed simultaneously by a conventional epitaxial process and include undoped silicon (Si). Referring now to FIGS. 1 and 7A-7D, method 100 includes block 110, where a first dielectric layer 220 is conformally deposited over the semiconductor structure 200. The first dielectric layer 220 may include silicon nitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, other suitable materials, or a combination of the foregoing. In this embodiment, the first dielectric layer 220 is conformally deposited over the semiconductor structure 200, including in the source / drain opening 214, by any suitable method, such as CVD, ALD, physical vapor deposition (PVD), or other suitable methods. The term "conformally" may be used herein to describe a film layer having a substantially uniform thickness over various regions of the semiconductor structure 200. The first dielectric layer 220 has a deposition thickness T1. As shown in FIGS. 7A-7D, the first dielectric layer 220 partially fills the source / drain opening 214. For ease of description, the portion of the first dielectric layer 220 that is in direct contact with the first semiconductor layer 218 but not in direct contact with the inner spacer member 216 or the channel layer 208 is referred to as the horizontal portion 220b; the portion of the first dielectric layer 220 that is in direct contact with the inner spacer member 216, the channel layer 208, and the gate spacer 212a is referred to as the vertical portion 220a; and the portion of the first dielectric layer 220 that is formed over the dummy gate stack 210 is referred to as the top 220t. Referring now to FIGS. 1 and 8A through 8D, method 100 includes block 112, wherein a patterned mask layer 222 is formed over semiconductor structure 200. The patterned mask layer 222 can include a patterned photoresist layer or a combination of a patterned hard mask layer and a patterned photoresist layer formed on the patterned hard mask layer. In an exemplary process, a photoresist layer is deposited over semiconductor structure 200 using spin coating or a suitable process. The photoresist layer is patterned using a photolithography process to form the patterned mask layer 222. In this embodiment, the patterned mask layer 222 has a first opening 222a (as shown in FIG. 8B) and a second opening 222b (as shown in FIG. 8D), the first opening 222a exposing a horizontal portion 220b of the first dielectric layer 220 in the second n-type device region 200N2, and the second opening 222b exposing a horizontal portion 220b of the first dielectric layer 220 in the second p-type device region 200P2. The patterned mask layer 222 covers other portions of the first dielectric layer 220 in semiconductor structure 200 (e.g., portions of the first dielectric layer 220 formed in the first n-type device region 200N3 and the first p-type device region 200P3). Referring now to FIG. 1 and FIGS. 9A-9D, method 100 includes block 114 where a first etching process 224 is performed to etch a first dielectric layer 220. When using the patterned mask layer 222 as an etching mask, the first etching process 224 is performed to etch the first dielectric layer 220 to remove the horizontal portions 220b of the first dielectric layer 220 exposed by the first opening 222a and the horizontal portions 220b of the first dielectric layer 220 exposed by the second opening 222b. In one embodiment, the first etching process 224 is an anisotropic etching process. After performing the first etching process 224, the patterned mask layer 222 can be selectively removed. As shown in FIGS. 9A-9D, the execution of the first etching process 224 removes the horizontal portions 220b of the first dielectric layer 220 in the second n-type device region 200N2 and the horizontal portions 220b of the first dielectric layer 220 in the second p-type device region 200P2. As a result, in the second n-type device region 200N2 and the second p-type device region 200P2, the portions of the top surface of the first semiconductor layer 218 covered by the horizontal portions 220b of the first dielectric layer 220 are now exposed in the source / drain openings 214. The top surfaces of the first semiconductor layer 218 in the first n-type device region 200N3 and the first p-type device region 200P3 are still covered by the first dielectric layer 220. In some embodiments, the execution of the first etching process 224 can also reduce the thickness of the vertical portions 220a of the first dielectric layer 220 in the second n-type device region 200N2 and the second p-type device region 200P2. After performing the first etching process 224, the vertical portions 220a of the first dielectric layer 220 in the second n-type device region 200N2 and the second p-type device region 200P2 have a thickness T2 (as shown in FIG. 9B), and the thickness T2 is less than the deposition thickness T1. In some embodiments, the thickness T2 ranges between about 1 nanometer (nm) and 4 nanometers. It is noted that the vertical portions 220a in the second n-type device region 200N2 and the second p-type device region 200P2 still directly contact a portion of the top surface of the first semiconductor layer 218. Referring now to FIGS. 1 and 10A-10D, method 100 includes block 116 where a second semiconductor layer 226 is formed on a first semiconductor layer 218 in a second n-type device region 200N2 and a second p-type device region 200P2. After partially exposing the top surface of the first semiconductor layer 218 in the second n-type device region 200N2 and the second p-type device region 200P2, the second semiconductor layer 226 is formed on the first semiconductor layer 218. In one embodiment, the second semiconductor layer 226 is formed using an epitaxial growth process and thus is selectively formed from bottom to top (i.e., in the Z direction) on the first semiconductor layer 218 in the second n-type device region 200N2 and the second p-type device region 200P2 without growing in the first n-type device region 200N3 and the first p-type device region 200P3. Each second semiconductor layer 226 may be undoped or unintentionally doped. In some embodiments, the second semiconductor layer 226 may include undoped silicon (Si), undoped germanium (Ge), undoped silicon germanium (SiGe), or other suitable materials. In one embodiment, the second semiconductor layers 226 in the second n-type device region 200N2 and the second p-type device region 200P2 are formed simultaneously and include undoped silicon (Si). In this embodiment, the top surface 226ts of the second semiconductor layer 226 is at least coplanar with the bottom surface of the intermediate spacer member 216m and is below or coplanar with the top surface of the intermediate spacer member 216m. For ease of description, in the second n-type device region 200N2 and the second p-type device region 200P2, the portion of the vertical portion 220a that is in direct contact with the second semiconductor layer 226 is referred to as the lower portion 220al of the first dielectric layer 220, and the portion of the vertical portion 220a that is not in direct contact with the second semiconductor layer 226 is referred to as the upper portion 220au of the first dielectric layer 220. As shown in FIGS. 10B and 10D, the upper portion 220au of the first dielectric layer 220 in the second n-type device region 200N2 and the second p-type device region 200P2 is exposed in the source / drain opening 214. Referring now to FIGS. 1 and 11A - 11H, method 100 includes block 118, where a second etching process 228 is performed to anisotropically etch a first dielectric layer 220. After a second semiconductor layer 226 is formed in the second n - type device region 200N2 and the second p - type device region 200P2, the second etching process 228 is applied to the semiconductor structure 200. In one embodiment, the second etching process 228 is an anisotropic etching process. Performing the second etching process 228 removes portions of the first dielectric layer 220 that are not covered / protected by the second semiconductor layer 226, such that a lower portion 220al of the first dielectric layer 220 surrounds the second semiconductor layer 226 in the second n - type device region 200N2 and the second p - type device region 200P2. After performing the second etching process 228, the lower portion 220al of the first dielectric layer 220 can be referred to as a sidewall dielectric layer 220al. As depicted herein, the sidewall dielectric layer 220al provides isolation between the bottom - most channel layer 208b and the second semiconductor layer 226. In this embodiment, to reduce the number of channel layers electrically coupled to source / drain components in the second n - type device region 200N2 and the second p - type device region 200P2, the top surface of the sidewall dielectric layer 220al is above or coplanar with the bottom surface of the middle inter - spacer member 216m, and below or coplanar with the top surface of the middle inter - spacer member 216m. The height H1 of the sidewall dielectric layer 220al can range between about 10 nanometers and about 20 nanometers. In this embodiment, the second etching process 228 selectively etches the first dielectric layer 220 without removing or substantially removing portions of the second semiconductor layer 226 and portions of the channel layer 208. As shown in FIGS. 11A, 11C, 11E, and 11G, after performing the second etching process 228, the top surfaces of the first semiconductor layer 218 in the first n - type device region 200N3 and the first p - type device region 200P3 are exposed in the source / drain openings 214. Referring now to FIGS. 1 and 12A-12D, method 100 includes block 120, where p-type source / drain components 232a and 232b are formed in source / drain openings 214 in a first p-type device region 200P3 and a second p-type device region 200P2, respectively. The source / drain components may refer to the source or the drain individually or collectively, depending on the context. After etching a first dielectric layer 220 to form sidewall dielectric layers 220al in a second n-type device region 200N2 and a second p-type device region 200P2 and expose the top surface of a first semiconductor layer 218 in a first n-type device region 200N3 and a first p-type device region 200P3, as shown in FIGS. 12A-12D, a patterned mask layer 230 is formed over semiconductor structure 200. The patterned mask layer 230 covers the first n-type device region 200N3 and the second n-type device region 200N2, while the first p-type device region 200P3 and the second p-type device region 200P2 are not covered. A epitaxial growth process is then performed, such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes, to form p-type source / drain components 232a and 232b in the first p-type device region 200P3 and the second p-type device region 200P2, respectively. Since the first semiconductor layer 218 is exposed through the source / drain opening 214 in the first p-type device region 200P3 and the second semiconductor layer 226 is exposed through the source / drain opening 214 in the second p-type device region 200P2, the p-type source / drain components 232a and 232b are allowed to grow from bottom to top (i.e., along the Z direction) to provide satisfactory strain performance. Exemplary p-type source / drain components 232a and 232b may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be doped in-situ (e.g., with boron or gallium) by introducing a p-type dopant during the epitaxial process or doped ex-situ using a junction implant process. In some embodiments, each of the p-type source / drain components 232a and 232b may include multiple semiconductor layers having different doping concentrations. In the first p-type device region 200P3, the p-type source / drain component 232a is coupled to all the channel layers of the channel region 204C (i.e., the channel layers 208b, 208m, and 208t). As shown in the cross-sectional view of FIG. 12C, the entire bottom surface of the p-type source / drain component 232a is in direct contact with the first semiconductor layer 218, and the p-type source / drain component 232a is in direct contact with all the channel layers of the channel region 204C (i.e., the channel layers 208b, 208m, and 208t) and the inner spacer components 216b, 216m, 216t. In the second p-type device region 200P2, the p-type source / drain component 232b is coupled to the upper part of the channel region 204C (e.g., the channel layers 208m and 208t), and is separated from the bottom of the channel region 204C (e.g., the bottommost channel layer 208b) by the sidewall dielectric layer 220al. As shown in the cross-sectional view of FIG. 12D, the bottom surface of the p-type source / drain component 232b is in direct contact with the top surface of the second semiconductor layer 226 and the top surface of the sidewall dielectric layer 220al. That is, the bottom surface of the p-type source / drain component 232b is located above the bottom surface of the p-type source / drain component 232a. In some embodiments, the volume of the p-type source / drain component 232a may be greater than the volume of the p-type source / drain component 232b. After forming the p-type source / drain components 232a and 232b, the patterned mask layer 230 may be selectively removed. Now referring to FIG. 1 and FIGS. 13A to 13D, method 100 includes block 122, wherein a second dielectric layer 234 is formed over the semiconductor structure 200. In this embodiment, the second dielectric layer 234 is formed on the top surface of the first semiconductor layer 218 in the first n-type device region 200N3, on the top surfaces of the sidewall dielectric layer 220al and the second semiconductor layer 226 in the second n-type device region 200N2, on the top surface of the p-type source / drain component 232a in the first p-type device region 200P3, and on the top surface of the p-type source / drain component 232b in the second p-type device region 200P2. In the exemplary process, to form the second dielectric layer 234, an insulating layer is first deposited over the semiconductor structure 200 by using a physical vapor deposition (PVD) process. The insulating layer may include silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, combinations of the foregoing, or other suitable materials. Due to the characteristics of the PVD process, the portion of the insulating layer formed on the top surface or flat surface is thicker than the portion formed on the sidewall surface. Next, the portions of the insulating layer formed on the top surface of the gate spacer 212a, the top surface of the dummy gate stack 210, and the sidewall surfaces of the plurality of components (e.g., the sidewall surfaces of the gate spacer 212a, the sidewall surfaces of the exposed channel region 204C, and the sidewall surfaces of the inner spacer component 216) are removed by a combination of planarization, deposition, photolithography, and / or etching processes, leaving the bottom of the insulating layer in the source / drain openings 214 in the first n-type device region 200N3 and the second n-type device region 200N2 and the bottom of the insulating layer on the p-type source / drain components 232a and 232b in the first p-type device region 200P3 and the second p-type device region 200P2. The bottoms of these insulating layers are referred to as the second dielectric layer 234. The second dielectric layer 234 in the first n-type device region 200N3 is formed in the source / drain opening 214 and is in direct contact with the first semiconductor layer 218. The bottom surface of the second dielectric layer 234 in the first n-type device region 200N3 is below or coplanar with the top surface of the bottommost inner spacer component 216b, such that the n-type source / drain component in the first n-type device region 200N3 will be electrically coupled to all channel layers in the channel region 204C. The second dielectric layer 234 in the second n-type device region 200N2 is formed in the source / drain opening 214 and is in direct contact with the sidewall dielectric layer 220al and the second semiconductor layer 226. In this embodiment, the bottom surface of the second dielectric layer 234 in the second n-type device region 200N2 is below or coplanar with the top surface of the middle inner spacer component 216m. The formation of the second dielectric layer 234 in the first n-type device region 200N3 and the second n-type device region 200N2 will substantially suppress and / or eliminate any parasitic transistors formed between the metal gate structure 242 (as shown in FIGS. 16A to 16D), the n-type source / drain components 236a / 236b (as shown in FIGS. 14A to 14B), and the underlying mesa structure 202t, thereby reducing and / or blocking the leakage current through the mesa structure 202t in the first n-type device region 200N3 and the second n-type device region 200N2. In some embodiments, when viewed in the X direction, the second dielectric layer 234 may also be formed on the top surface of the isolation component 205. Referring now to FIGS. 1 and 14A through 14D, method 100 includes block 124, in which n-type source / drain components 236a and 236b are formed in source / drain openings 214 in a first n-type device region 200N3 and a second n-type device region 200N2, respectively. The source / drain components may refer to the source or the drain individually or collectively, depending on the context. After forming the second dielectric layer 234, an epitaxial growth process, such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes, is then performed to form n-type source / drain components 236a and 236b in the first n-type device region 200N3 and the second n-type device region 200N2, respectively. Exemplary n-type source / drain components 236a and 236b may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be doped in-situ (e.g., with phosphorus, arsenic, or antimony) by introducing an n-type dopant during the epitaxial process, or doped ex-situ using a junction implant process. In some embodiments, each of the n-type source / drain components 236a and 236b may include multiple semiconductor layers having different doping concentrations. In the first n-type device region 200N3, the n-type source / drain component 236a is coupled to and in direct contact with all channel layers (i.e., channel layers 208b, 208m, and 208t) of the channel region 204C. As shown in the cross-sectional view of FIG. 14A, the entire bottom surface of the n-type source / drain component 236a is in direct contact with the second dielectric layer 234. In the second n-type device region 200N2, the n-type source / drain component 236b is coupled to the upper part of the channel region 204C (e.g., channel layers 208m and 208t), and is separated from the bottom (e.g., the bottommost channel layer 208b) of the channel region 204C by the sidewall dielectric layer 220al. As shown in the cross-sectional view of FIG. 14B, the entire bottom surface of the n-type source / drain component 236b is in direct contact with the second dielectric layer 234. Forming the second dielectric layer 234 in the first n-type device region 200N3 and the second n-type device region 200N2 blocks the conductive path between the n-type source / drain components 236a / 236b and the underlying mesa structure 202t. The bottom surface of the n-type source / drain component 236b is located above the bottom surface of the n-type source / drain component 236a. In some embodiments, the volume of the n-type source / drain component 236a may be greater than the volume of the n-type source / drain component 236b. Referring now to FIGS. 1 and 15A - 15D, method 100 includes block 126, where dummy gate stack 210 and sacrificial layer 206 are replaced with metal gate structure 242. Contact etch stop layer (CESL) 238 and first inter - layer dielectric (ILD) layer 240 are deposited over semiconductor structure 200. CESL 238 can include silicon nitride, silicon oxynitride, and / or other suitable materials, and can be formed by a plasma - enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. After depositing CESL 238, first ILD layer 240 is deposited over semiconductor structure 200 by a PECVD process or other suitable deposition techniques. First ILD layer 240 can include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. A planarization process, such as a chemical mechanical polishing (CMP) process, can be performed on semiconductor structure 200 to remove excess material, thereby exposing the top surface of dummy gate electrode layer 210b in dummy gate stack 210. A first etching process can be implemented to selectively remove dummy gate layer 210b and dummy gate dielectric layer 210a of dummy gate stack 210, while substantially not removing gate spacer 212a to form a gate trench. After removing dummy gate stack 210, sacrificial layer 206 in channel region 204C is selectively removed to release channel layer 208 as a nanostructure (or channel member) 208. The selective removal of sacrificial layer 206 forms a gate opening under the gate trench. After removing the dummy gate stack 210 and the sacrificial layer 206, a metal gate structure 242 is formed in the gate trenches and the gate openings. The formation of the metal gate structure 242 includes forming an interface layer to surround and be located above each nanostructure 208. The interface layer may include silicon oxide or other suitable materials. The interface layer can be formed using suitable methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, or other suitable methods. In one embodiment, the interface layer is formed by thermal oxidation and thus is formed only on the surface of the nanostructure 208. That is, the interface layer does not extend along the sidewall surface of the gate spacer 212a and does not extend along the sidewall surface of the inner spacer member 216. In another embodiment, the interface layer is formed via ALD and thus conformally formed on the surface of the semiconductor structure 200. That is, the interface layer also extends along the sidewall surface of the gate spacer 212a and the sidewall surface of the inner spacer member 216. After forming the interface layer, a dielectric layer is formed above the semiconductor structure 200 to surround and be located above each nanostructure 208. In one embodiment, the dielectric layer is conformally deposited above the semiconductor structure 200. The term "conformally" may be used herein to facilitate the description of a film layer having a substantially uniform thickness over various regions. In some embodiments, the dielectric layer is a high dielectric constant (k) dielectric layer, and its dielectric constant is greater than the dielectric constant of silicon dioxide (~3.9). In some embodiments, the dielectric layer may include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium silicon oxide (HfSiO 4 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO 3 ; STO), barium titanate (BaTiO 3 ; BTO), barium zirconate (BaZrO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba,Sr)TiO 3 ; BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations of the foregoing materials, or other suitable materials. The dielectric layer and the interface layer can be collectively referred to as the gate dielectric layer. The formation of the metal gate structure 242 also includes forming a gate electrode over the gate dielectric layer. The gate electrode can be a multi-layer structure including at least one work function layer and a metal fill layer. For example, at least one work function layer can include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal gate structure 242 formed in the first p-type device region 200P3 and the second p-type device region 200P2 can include at least a p-type work function layer. The p-type work function layer can include titanium nitride (TiN), tungsten carbonitride (WCN), tantalum nitride (TaN), or molybdenum nitride (MoN). The metal gate structure 242 formed in the first n-type device region 200N3 and the second n-type device region 200N2 can include at least an n-type work function layer. The n-type work function layer can include titanium aluminum-based metals such as titanium aluminum carbide (TiAlC) or titanium aluminum (TiAl). The metal fill layer can include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or combinations of the foregoing. In various embodiments, the gate electrode can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a planarization process such as a chemical mechanical polishing (CMP) process can be performed to remove excess material over the first ILD layer 240 to provide a substantially flat top surface and facilitate the execution of further processes. Referring now to FIGS. 1 and 16A - 16H, method 100 includes block 128 where a further process is performed. Such a further process may include forming an etch stop layer 244 and a second ILD layer 246 over the semiconductor structure 200. In terms of composition and formation process, the etch stop layer 244 may be similar to the contact etch stop layer 238, and the second ILD layer 246 may be similar to the first ILD layer 240. The etch stop layer 244 may indicate an etch stop point for forming a gate via opening over the metal gate structure 242. A source / drain contact opening (now filled with a silicide layer 250 and source / drain contacts 252) is formed using a combination of photolithography and etching processes to expose the p - type source / drain components 232a - 232b and / or n - type source / drain components 236a - 236b. In the illustrated process, a hard mask layer and photoresist are deposited over the semiconductor structure 200. The photoresist layer is then exposed to patterned radiation transmitted through or reflected from a photomask, baked during a post - development bake, developed in a developer solution, and then rinsed, thereby forming a patterned photoresist layer. The patterned photoresist layer is then applied as an etch mask to etch the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer is then applied as an etch mask to etch the second ILD layer 246, the etch stop layer 244, the first ILD layer 240, and the CESL 238 to form source / drain contact openings in the first p - type device region 200P3 and the second p - type device region 200P2. After forming the source / drain contact openings, a silicide layer 250 and source / drain contacts 252 are formed in the source / drain contact openings. The silicide layer 250 in the first n - type device region 200N3 and the second n - type device region 200N2 may include nickel silicide, titanium silicide, tantalum silicide, cobalt silicide, tungsten silicide, or other suitable materials. The silicide layer 250 in the first p - type device region 200P3 and the second p - type device region 200P2 may include nickel silicide, nickel germanide, nickel silicide, titanium silicide, titanium germanide, titanium silicide, tantalum silicide, cobalt silicide, cobalt germanide, cobalt silicide, tungsten silicide, tungsten germanide, and / or tungsten silicide, or other suitable materials. A source / drain contact 252 is then formed in the source / drain contact openings and on the silicide layer 250. The source / drain contact 252 may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo), or other suitable materials, and may be formed by any suitable process. Although not shown, in some embodiments, a barrier layer may be formed to extend along the sidewall surfaces of the source / drain contact 252. Such a further process may include forming gate vias and interconnect structures over the semiconductor structure 200.In some embodiments, the interconnect structure may include multiple intermetal dielectric (IMD) layers and multiple metal wires or contact vias in each IMD layer. In some cases, the IMD layers and the first ILD layer 240 may have similar compositions. The metal wires and contact vias in each IMD layer may be formed of a metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal wires and contact vias may be lined with a barrier layer to insulate the metal wires and contact vias from the IMD layer and prevent electro-migration. This further process may include forming the interconnect structure under the backside of the semiconductor structure 200. In some alternative embodiments, the electrical properties of the devices in the semiconductor structure 200 may be further adjusted. For example, the effective width of the nanostructure 208 along the X direction may be adjusted to provide, for example, improved drive current (DC) performance. FIG. 17 is a flowchart illustrating a method 300 of forming a semiconductor structure 400 / 400' according to one or more aspects of the present disclosure. Referring to FIG. 17, method 300 includes block 102, block 104, block 106, and block 108. In the present embodiment, the semiconductor structure 200 shown in FIGS. 6A-6D (including the first n-type device region 200N3 and the second n-type device region 200N2 and the first p-type device region 200P3 and the second p-type device region 200P2) may be referred to as the semiconductor structure 400, which includes the first n-type device region 400N3 and the second n-type device region 400N2 and the first p-type device region 400P3 and the second p-type device region 400P2. Referring to FIGS. 17 and 18A-18D, method 300 further includes block 310, where a patterned mask layer 410 is formed to cover components in the first n-type device region 400N3. As shown in FIGS. 18A-18D, the patterned mask layer 410 covers the channel layers (e.g., channel layers 208b, 208m, and 208t) in the first n-type device region 400N3, while the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2 are exposed. Referring to FIGS. 17 and 19A - 19D, method 300 further includes block 320, where an etching process 420 is performed to selectively recess the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n - type device region 200N2, the first p - type device region 200P3, and the second p - type device region 200P2. When using the patterned mask layer 410 as an etching mask, the etching process 420 is performed to selectively recess the channel layers not covered by the patterned mask layer 410. In this way, the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n - type device region 400N2, the first p - type device region 400P3, and the second p - type device region 400P2 are recessed and thus have a width W3 that is reduced compared to the width W2 of the channel layer in the first n - type element region 400N3 along the X - direction. The recessing of the channel layers (e.g., channel layers 208b, 208m, and 208t) forms openings 430 in the second n - type device region 400N2, the first p - type device region 400P3, and the second p - type device region 400P2. In some embodiments, the execution of the etching process 420 may also slightly etch the first semiconductor layer 218 in the second n - type device region 400N2, the first p - type device region 400P3, and the second p - type device region 400P2. As shown in FIGS. 19B - 19D, the top surface of the first semiconductor layer 218 in the second n - type device region 400N2, the first p - type device region 400P3, and the second p - type device region 400P2 curves inward. After the etching process 420 is performed, the patterned mask layer 410 can be selectively removed. Referring to FIGS. 17, 20A-20D, 21A-21D, and 22A-22D, method 300 further includes blocks 110 to 128. After etching the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2, the operations of blocks 110 to 128 of method 100 are performed to form the semiconductor structure 400. For example, with respect to FIGS. 20A-20D, the first dielectric layer 220 is conformally deposited over the semiconductor structure 400. The first dielectric layer 220 in the semiconductor structure 400 also fills the opening 430. Next, with respect to FIGS. 21A-21D, a second semiconductor layer 226 is formed in the second n-type device region 400N2 and the second p-type device region 400P2, and a portion of the first dielectric layer 220 is removed, leaving the sidewall dielectric layer 220al in the second n-type device region 400N2 and the second p-type device region 400P2. The sidewall dielectric layer 220al of the semiconductor structure 400 is similar to the sidewall dielectric layer 220al of the semiconductor structure 200, and one of the differences includes that each sidewall dielectric layer 220al of the semiconductor structure 400 further includes a portion that fills the opening 430, and thus is vertically disposed between the bottommost inner spacer member 216b and the middle inner spacer member 216m. In this way, the sidewall dielectric layer 220al has a non-uniform thickness from bottom to top. In one embodiment, the top and bottom of the sidewall dielectric layer 220al that is in direct contact with the sidewall surface of the inner spacer member has a thickness T2 in the range of about 1 nanometer to about 4 nanometers, and the middle portion of the sidewall dielectric layer 220al that is in direct contact with the bottommost channel layer 208b has a thickness T3 in the range of about 3 nanometers to about 7 nanometers. FIGS. 22A to 22D illustrate partial cross-sectional views of the final structure of the semiconductor structure 400. The final structure of the semiconductor structure 400 is similar to the semiconductor structure 200 illustrated in FIGS. 16A to 16D. One of the differences between the final structure of the semiconductor structure 400 and the semiconductor structure 200 includes the profile of the sidewall dielectric layer 220al. As described above, the sidewall dielectric layer 220al of the semiconductor structure 400 also includes a portion vertically disposed between the bottommost inner spacer member 216b and the middle inner spacer member 216m. Another difference between the final structure of the semiconductor structure 400 and the semiconductor structure 200 includes different channel widths in the semiconductor structure 400. More specifically, the widths W3 (as shown in FIG. 19B) of the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2 are smaller than the width W2 (as shown in FIG. 19A) of the channel layer (e.g., channel layers 208b, 208m, and 208t) in the first n-type device region 200N3. In the above-described embodiments described with reference to FIGS. 21A-21D and FIGS. 22A-22D, the entire sidewall surface of the second semiconductor layer 226 of the semiconductor structure 400 is lined with the sidewall dielectric layer 220al. The profile of the sidewall dielectric layer 220al can be further adjusted by controlling the etching duration of the first etching process 224 performed in block 114. In an alternative embodiment, the first etching process 224 is performed such that the vertical portion 220a of the first dielectric layer 220 extending along the sidewall surfaces of the inner spacer members 216b, 216m, and 216t can be substantially removed, leaving the portion of the first dielectric layer 220 formed in the opening 430. As shown in FIGS. 23A-23D, the sidewall surface of the second semiconductor layer 226 of the semiconductor structure 400' is in direct contact with the sidewall dielectric layer 220al, the bottommost inner spacer member 216b, and the inner spacer member (e.g., the middle inner spacer member 216m shown in this illustration) directly disposed above the bottommost inner spacer member 216b. FIGS. 24A-24H illustrate partial cross-sectional views of the final structure of the semiconductor structure 400'. The final structure of the semiconductor structure 400' shown in FIGS. 24A-24D is similar to the semiconductor structure 400 shown in FIGS. 22A-22D, and one of the differences between the semiconductor structure 400' and the semiconductor structure 400 includes the profile of the sidewall dielectric layer 220al and the relative positional relationship between the sidewall dielectric layer 220al and its surrounding components, as shown in FIGS. 24B and 24D. FIGS. 24E-24H illustrate cross-sectional views of an alternative final structure of the semiconductor structure 400' when viewed from the X direction. In the embodiment shown in FIGS. 24E-24H, when viewed from the X direction, the entire sidewall surface of the second semiconductor layer 226 is in direct contact with the fin sidewall spacer 212b. In the above-described embodiments described with reference to FIGS. 17 to 24H, the operations in blocks 310 and 320 of method 300 (e.g., the etching process 420 shown in FIGS. 19A to 19D) are performed after the operation in block 108 (e.g., forming the first semiconductor layer 218) and before the operation in block 110 (e.g., deposition of the first dielectric layer 220). In some alternative embodiments, the operations in blocks 310 and 320 are performed after the operation in block 118 to form another alternative semiconductor structure 600 / 600'. FIG. 25 is a flowchart showing a method 500 of forming a semiconductor structure 600 / 600' in accordance with one or more aspects of the present disclosure. Referring to FIG. 25 and FIGS. 26A to 26H, method 500 includes blocks 102, 104, 106, 108, 110, 112, 114, 116, and 118. In this embodiment, after the operation in block 118, for ease of description, the semiconductor structure 200 shown in FIGS. 11A to 11H may be referred to as semiconductor structure 600, which includes a first n-type device region 600N3 and a second n-type device region 600N2 and a first p-type device region 600P3 and a second p-type device region 600P2. As shown in FIGS. 11A to 11H, the semiconductor structure 600 includes sidewall dielectric layers 220al formed in the second n-type device region 600N2 and the second p-type device region 600P2. Referring to the detailed description of the sidewall dielectric layer 220al in FIGS. 1 to 11H above and not repeating it for brevity. Referring to FIG. 25 and FIGS. 26A to 26D, method 500 further includes block 310, where a patterned mask layer 410 is formed to cover components in the first n-type device region 600N3. The patterned mask layer 410 may be similar to the patterned mask layer 222 or the patterned mask layer 230. As shown in FIGS. 26A-26D, the patterned mask layer 410 covers all the channel layers (e.g., channel layers 208b, 208m, and 208t) in the first n-type device region 600N3. All the channel layers (e.g., channel layers 208b, 208m, and 208t) in the first p-type device region 600P3, the channel layers (e.g., channel layers 208m and 208t) in the second n-type device region 600N2 that are not covered by the sidewall dielectric layer 220al, and the channel layers (e.g., channel layers 208m and 208t) in the second p-type device region 600P2 that are not covered by the sidewall dielectric layer 220al are not protected by the patterned mask layer 410. Still referring to FIGS. 25 and 26A - 26D, method 500 further includes block 320, where an etching process 420 is performed to selectively recess the channel layers not protected by the patterned mask layer 410. When using the patterned mask layer 410 as an etching mask, the etching process 420 is performed to selectively recess the channel layers not covered by the patterned mask layer 410. In this way, the channel layers 208m and 208t in the second n - type device region 600N2, the channel layers 208b, 208m, and 208t in the first p - type device region 600P3, and the channel layers 208m and 208t in the second p - type device region 600P2 are recessed, and thus have a reduced width along the X direction. In addition, in the second n - type device region 600N2 and the second p - type device region 600P2, the widths of the channel layers 208m and 208t are less than the width of their respective bottom - most channel layer 208b that is not recessed during the execution of the etching process 420. The recessing of the channel layers forms openings 430 in the second n - type device region 600N2, the first p - type device region 600P3, and the second p - type device region 600P2. In this embodiment, the execution of the etching process 420 recesses the channel layers while substantially not etching the second semiconductor layer 226. Referring to FIGS. 25 and 27A - 27D, method 500 further includes block 120, block 122, block 124, block 126, and block 128. After performing the operations in block 320, the operations in blocks 120 to 128 of method 100 are performed to facilitate the formation of the final structure of the semiconductor structure 600. The semiconductor structure 600 is similar to the semiconductor structure 200 shown in FIGS. 16A - 16H, and some differences between the semiconductor structure 200 and the semiconductor structure 600 include: in the second n - type device region 600N2 and the second p - type device region 600P2, the channel layers 208t and 208m have a reduced width, and their respective source / drain components 236b / 232b include a first portion vertically disposed between the gate spacer 212a and the top - most inner spacer component 216t and a second portion vertically disposed between the top - most inner spacer component 216t and the middle inner spacer component 216m; in the first p - type device region 600P3, all channel layers (e.g., channel layers 208t, 208m, and 208b) have a reduced width, and the p - type source / drain component 232a includes a first portion vertically disposed between the gate spacer 212a and the top - most inner spacer component 216t, a second portion vertically disposed between the top - most inner spacer component 216t and the middle inner spacer component 216m, and a third portion vertically disposed between the middle inner spacer component 216m and the bottom - most inner spacer component 216b. In the embodiment shown in FIGS. 26A to 27D, the etching process 420 is configured to selectively recess the channel layer without substantially etching the second semiconductor layer 226. In another embodiment shown in FIGS. 28A to 28D, the etching process 420 is configured to recess the channel layer and the second semiconductor layer 226. As shown in FIGS. 28A to 28D, after performing the etching process 420, the top surface of the second semiconductor layer 226 of the semiconductor structure 600' is located below the top surface of the sidewall dielectric layer 220al. FIGS. 29A to 29H illustrate the final structure of this semiconductor structure 600'. The semiconductor structure 600' shown in FIGS. 29A to 29H is similar to the semiconductor structure 600 shown in FIGS. 27A to 27D, and some differences between these two semiconductor structures include: in the second n-type device region 600N2 of the semiconductor structure 600', according to the thickness of the second dielectric layer 234 and the recessed thickness of the second semiconductor layer 226, the second dielectric layer 234 is in direct contact with at least a part of the sidewall surface of the sidewall dielectric layer 220al, and may further be formed on and in direct contact with the top surface of the sidewall dielectric layer 220al; in the second p-type device region 600P2 of the semiconductor structure 600' shown in FIGS. 29D to 29H, the p-type source / drain component 232b includes a bottom extending between and in direct contact with the sidewall surfaces of the two sidewall dielectric layers 220al formed in the source / drain opening 214. That is, the volume of the p-type source / drain component 232b of the semiconductor structure 600' is larger than the volume of the p-type source / drain component 232b of the semiconductor structure 600. Similarly, the volume of the n-type source / drain component 236b of the semiconductor structure 600' is larger than the volume of the n-type source / drain component 236b of the semiconductor structure 600. For the sake of brevity, some components in FIGS. 29E to 29H are omitted. Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits for semiconductor structures and their formation. The present disclosure provides methods and structures for multi-gate devices that can provide multiple semiconductor channel layers selected based on preferred performance (e.g., low leakage current or high drive current) without sacrificing the strain performance of the p-type source / drain components of p-type multi-gate devices. This method can be applied to active regions with the same or different configurations (e.g., spacing and width). By implementing this method, different regions of the semiconductor structure can be made into GAAs with different performances. The present disclosure provides many different embodiments. A semiconductor structure and a method for manufacturing the same are disclosed herein. In an exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first transistor, the first transistor including a first gate structure, a first source / drain component, and a first semiconductor layer. The first gate structure surrounds a plurality of first nanostructures disposed above a substrate. The first source / drain component is electrically coupled to the topmost nanostructure of the first nanostructures and is separated from the bottommost nanostructure of the first nanostructures by a first dielectric layer. The first semiconductor layer is disposed between the substrate and the first source / drain component, wherein the first source / drain component is in direct contact with the top surface of the first semiconductor layer. In some embodiments, the first dielectric layer may extend along a sidewall surface of the first semiconductor layer. In some embodiments, the first transistor may further include a plurality of inner spacer components disposed between two adjacent nanostructures of the first nanostructures, wherein the first dielectric layer extends along a sidewall surface of the bottommost inner spacer component of the inner spacer components. In some embodiments, a portion of the first dielectric layer may be disposed above a top surface of the bottommost inner spacer component of the inner spacer components and is in direct contact with the top surface. In some embodiments, a sidewall surface of the first semiconductor layer may be in direct contact with the first dielectric layer and the bottommost inner spacer component of the inner spacer components. In some embodiments, the first source / drain component may be a p-type source / drain component. In some embodiments, the first source / drain component may be disposed adjacent to the first nanostructures along a first direction, and the bottommost nanostructure of the first nanostructures has a width along the first direction, and the width may be greater than widths of other nanostructures of the first nanostructures. In some embodiments, a top surface of the first dielectric layer may be above a top surface of the first semiconductor layer. In some embodiments, the semiconductor structure may further include a second transistor, the second transistor including a second gate structure, a second source / drain component, and a second semiconductor layer. The second gate structure surrounds a plurality of second nanostructures disposed above a substrate. The second source / drain component is electrically coupled to the topmost nanostructure of the second nanostructures and is separated from the bottommost nanostructure of the second nanostructures by a second dielectric layer. The second semiconductor layer is adjacent to the second dielectric layer and is separated from the second source / drain component by a third dielectric layer. In some embodiments, the first dielectric layer and the second dielectric layer may include the same composition and the same thickness. In some embodiments, the second source / drain component may be an n-type source / drain component. In some embodiments, the third dielectric layer may be in direct contact with the second source / drain component, the second dielectric layer, and the second semiconductor layer. In another exemplary aspect, the present disclosure relates to a transistor. The transistor includes a gate structure, an undoped semiconductor layer, a dielectric layer, and a source / drain component. The gate structure surrounds a plurality of nanostructures disposed above a substrate. The undoped semiconductor layer is located in and above the substrate, wherein a top surface of the undoped semiconductor layer is flush with or above a top surface of a bottommost nanostructure of the plurality of nanostructures. The dielectric layer is disposed between the undoped semiconductor layer and the bottommost nanostructure of the plurality of nanostructures. The source / drain component is adjacent to the nanostructures, wherein a bottom surface of the source / drain component is in direct contact with the top surface of the undoped semiconductor layer. In some embodiments, the undoped semiconductor layer may further include a first portion embedded in the substrate and a second portion on the substrate, and an entire sidewall surface of the second portion of the undoped semiconductor layer may be covered by the dielectric layer. In some embodiments, the transistor may further include a plurality of inner spacer components vertically disposed between two adjacent nanostructures of the plurality of nanostructures, wherein the dielectric layer is disposed between the undoped semiconductor layer and a bottommost inner spacer component of the plurality of inner spacer components. In some embodiments, the dielectric layer may be in direct contact with the source / drain component, the undoped semiconductor layer, and the bottommost inner spacer component of the plurality of inner spacer components. In yet another exemplary aspect, the present disclosure relates to a method of manufacturing a semiconductor structure. The method includes forming a first fin-shaped active region extending from a substrate and including a plurality of channel layers interleaved by a plurality of sacrificial layers, forming a first gate stack above a first channel region of the first fin-shaped active region, recessing a first source / drain region of the first fin-shaped active region to form a first source / drain opening, forming a first semiconductor layer in a bottom of the first source / drain opening, forming a first dielectric layer on the first semiconductor layer and extending along a sidewall surface of an intermediate portion of the first source / drain opening, wherein an entire sidewall surface of a bottommost channel layer of the plurality of channel layers is covered by the first dielectric layer, forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer, forming a first source / drain component on the second semiconductor layer, and replacing the first gate stack and the sacrificial layers with a gate structure. In some embodiments, the method may further include selectively etching a sacrificial layer to form a plurality of inner spacer recesses and forming a plurality of inner spacer members in the inner spacer recesses. In some embodiments, the first source / drain member is a p-type source / drain member and is in direct contact with the second semiconductor layer and the first dielectric layer. In some embodiments, forming the first dielectric layer may include conformally depositing an insulating layer over the substrate, the insulating layer including a vertical portion and a horizontal portion, the vertical portion extending along a sidewall surface of the first source / drain opening, the horizontal portion extending along a top surface of the first semiconductor layer, performing a first etching process to remove the horizontal portion of the insulating layer, and after forming the second semiconductor layer, performing a second etching process to remove a plurality of portions of the vertical portion of the insulating layer not covered by the second semiconductor layer. The foregoing outlines components of several embodiments so that those of ordinary skill in the art to which this disclosure pertains can more readily understand the aspects of the embodiments of the present disclosure. Those of ordinary skill in the art to which this disclosure pertains should understand that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art to which this disclosure pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure. 10: First region 20: Second region 100: Method 102 / 104 / 106 / 108 / 110 / 112 / 114 / 116 / 118 / 120 / 122 / 124 / 126 / 128: Box 200: Semiconductor structure 200N2: Second n-type device region 200N3: First n-type device region 200P2: Second p-type device region 200P3: First p-type device region 202: Substrate 202t: Top, mesa structure 204a / 204b: Fin-shaped active region 204C: Channel region 204SD: Source / drain region 205: Isolation component 206: Sacrificial layer 207: Vertical stack 208, 208b, 208m, 208t: Channel layer 210: dummy gate stack 210a: dummy gate dielectric layer 210b: dummy gate electrode layer 210c: Gate top hard mask layer 212: Gate spacer layer 212a: Gate spacer 212b: Fin sidewall spacer 214: Source / drain opening 216, 216b, 216m, 216t: Inner spacer component 218: First semiconductor layer 220: First dielectric layer 220a: Vertical portion 220al: Lower, sidewall dielectric layer 220au: Upper portion 220b: Horizontal portion 220t: Top 222: Patterned mask layer 222a: First opening 222b: Second opening 224: First etching process 226: Second semiconductor layer 226ts: Top surface 228: Second etching process 230: Patterned mask layer 232a / 232b: p-type source / drain component 234: Second dielectric layer 236a / 236b: n-type source / drain component 238: Contact etch stop layer 240: First interlayer dielectric layer 242: Metal gate structure 244: Etch stop layer 246: Second interlayer dielectric layer 250: Silicide layer 252: Source / drain contact 300: Method 310 / 320: Box 400, 400’: Semiconductor structure 400N2: Second n-type device region 400N3: First n-type device region 400P2: Second p-type device region 400P3: First p-type device region 410: Patterned mask layer 420: Etching process 430: Opening 500: Method 600, 600’: Semiconductor structure 600N2: Second n-type device region 600N3: First n-type device region 600P2: Second p-type device region 600P3: First p-type device region H1: Height T1: Deposition thickness T2 / T3: Thickness W1 / W2 / W3: Width Aspects of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, various components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the elements can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. FIG. 1 is a flowchart showing a method of forming a semiconductor structure according to one or more aspects of the present disclosure. FIG. 2 is a partial top view of an exemplary semiconductor structure at each manufacturing stage in the method of FIG. 1 according to various aspects of the present disclosure. FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, and 16A (FIGS. 3A to 16A) are partial cross-sectional views of the semiconductor structure at each manufacturing stage in the method of FIG. 1 taken along line A-A' in FIG. 2 according to one or more aspects of the present disclosure. FIGS. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, and 16B (FIGS. 3B to 16B) are partial cross-sectional views of the semiconductor structure at each manufacturing stage in the method of FIG. 1 taken along line B-B' in FIG. 2 according to one or more aspects of the present disclosure. FIGS. 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, and 16C (FIGS. 3C to 16C) are partial cross-sectional views of the semiconductor structure at each manufacturing stage in the method of FIG. 1 taken along line C-C' in FIG. 2 according to one or more aspects of the present disclosure. FIGS. 3D, 4D, 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, 14D, 15D, and 16D (FIGS. 3D to 16D) are partial cross-sectional views of the semiconductor structure at each manufacturing stage in the method of FIG. 1 taken along line D-D' in FIG. 2 according to one or more aspects of the present disclosure. FIGS. 3E, 4E, 11E, 14E, and 16E are partial cross-sectional views of the semiconductor structure at each manufacturing stage in the method of FIG. 1 taken along line E-E' in FIG. 2 according to one or more aspects of the present disclosure. FIGS. 3F, 4F, 11F, 14F, and 16F are partial cross-sectional views of the semiconductor structure at each manufacturing stage in the method of FIG. 1 taken along line F-F' in FIG. 2 according to one or more aspects of the present disclosure.Figures 3G, 4G, 11G, 14G, and 16G are partial cross-sectional views taken along line G-G' of the semiconductor structure at each manufacturing stage in the method of FIG. 1, in accordance with one or more aspects of the present disclosure. Figures 3H, 4H, 11H, 14H, and 16H are partial cross-sectional views taken along line H-H' of the semiconductor structure at each manufacturing stage in the method of FIG. 1, in accordance with one or more aspects of the present disclosure. FIG. 17 is a flowchart of a first alternative method for forming a semiconductor structure, in accordance with one or more aspects of the present disclosure. FIGS. 18A, 19A, 20A, 21A, and 22A (collectively FIGS. 18A-22A) are partial cross-sectional views taken along line A-A' of the semiconductor structure at each manufacturing stage in the first alternative method of FIG. 17, in accordance with one or more aspects of the present disclosure. FIGS. 18B, 19B, 20B, 21B, and 22B (collectively FIGS. 18B-22B) are partial cross-sectional views taken along line B-B' of the semiconductor structure at each manufacturing stage in the first alternative method of FIG. 17, in accordance with one or more aspects of the present disclosure. FIGS. 18C, 19C, 20C, 21C, and 22C (collectively FIGS. 18C-22C) are partial cross-sectional views taken along line C-C' of the semiconductor structure at each manufacturing stage in the first alternative method of FIG. 17, in accordance with one or more aspects of the present disclosure. FIGS. 18D, 19D, 20D, 21D, and 22D (collectively FIGS. 18D-22D) are partial cross-sectional views taken along line D-D' of the semiconductor structure at each manufacturing stage in the first alternative method of FIG. 17, in accordance with one or more aspects of the present disclosure. FIGS. 23A, 23B, 23C, and 23D are alternative partial cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of the semiconductor structure at each manufacturing stage in the first alternative method of FIG. 17, respectively, in accordance with one or more aspects of the present disclosure. FIGS. 24A, 24B, 24C, 24D, 24E, 24F, 24G, and 24H are alternative partial cross-sectional views taken along lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H' of the semiconductor structure at each manufacturing stage in the first alternative method of FIG. 17, respectively, in accordance with one or more aspects of the present disclosure. FIG. 25 is a flowchart of a second alternative method for forming a semiconductor structure, in accordance with one or more aspects of the present disclosure.FIG. 26A and FIG. 27A, FIG. 26B and FIG. 27B, FIG. 26C and FIG. 27C, and FIG. 26D and FIG. 27D are alternative partial cross-sectional views taken along lines A-A', B-B', C-C', and D-D' in FIG. 2 of the semiconductor structure at each manufacturing stage in the second alternative method of FIG. 25, respectively, according to one or more aspects of the present disclosure. FIG. 28A, FIG. 28B, FIG. 28C, and FIG. 28D are alternative partial cross-sectional views taken along lines A-A', B-B', C-C', and D-D' in FIG. 2 of the semiconductor structure at each manufacturing stage in the second alternative method of FIG. 25, respectively, according to one or more aspects of the present disclosure. FIG. 29A, FIG. 29B, FIG. 29C, FIG. 29D, FIG. 29E, FIG. 29F, FIG. 29G, and FIG. 29H are alternative partial cross-sectional views taken along lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H' in FIG. 2 of the semiconductor structure at each manufacturing stage in the second alternative method of FIG. 25, respectively, according to one or more aspects of the present disclosure. 200P2: Second p-Type Device Region 204C: Channel Region 204SD: Source / Drain Region 208b: Lowest Channel Layer 208m: Intermediate Channel Layer 208t: Topmost Channel Layer 216b: Lowest Inner Spacer Member 216m: Intermediate Inner Spacer Member 216t: Topmost Inner Spacer Member 218: First Semiconductor Layer 220al: Lower / Sidewall Dielectric Layer 226: Second Semiconductor Layer 232b: p-Type Source / Drain Member 234: Second Dielectric Layer 238: Contact Etch Stop Layer 240: First Interlayer Dielectric Layer 242: Metal Gate Structure 244: Etch Stop Layer 246: Second Interlayer Dielectric Layer 252: Source / Drain Contact

Claims

1. A semiconductor structure, comprising: A first transistor includes: a first gate structure surrounding a plurality of first nanostructures disposed above a substrate; a first source / drain component electrically coupled to a topmost nanostructure of the first nanostructures and separated from a bottommost nanostructure of the first nanostructures by a first dielectric layer; and a first semiconductor layer disposed between the substrate and the first source / drain component, wherein the first source / drain component is in direct contact with a top surface of the first semiconductor layer, wherein the first source / drain component is disposed adjacent to the first nanostructures along a first direction, and the first nanostructures have different widths along the first direction.

2. The semiconductor structure of claim 1, wherein the first dielectric layer extends along one sidewall surface of the first semiconductor layer.

3. The semiconductor structure of claim 1 or 2, wherein the first transistor further comprises: A plurality of inner spacer components are disposed between two adjacent nanostructures of the first nanostructures, wherein the first dielectric layer extends along one sidewall surface of the bottom inner spacer component of the inner spacer components.

4. The semiconductor structure of claim 3, wherein a portion of the first dielectric layer is disposed above and in direct contact with a top surface of the bottommost inner spacer member of the inner spacer members.

5. The semiconductor structure of claim 4, wherein one sidewall surface of the first semiconductor layer is in direct contact with the first dielectric layer and the bottommost inner spacer member of the inner spacer members.

6. The semiconductor structure of claim 1, wherein the bottommost nanostructure of the first nanostructures has a width along the first direction, the width being greater than the width of the other nanostructures of the first nanostructures.

7. The semiconductor structure of claim 1, wherein a top surface of the first dielectric layer is above the top surface of the first semiconductor layer.

8. The semiconductor structure of claim 1 further includes: A second transistor includes: a second gate structure surrounding a plurality of second nanostructures disposed above the substrate; a second source / drain component electrically coupled to a topmost nanostructure of the second nanostructures and separated from a bottommost nanostructure of the second nanostructures by a second dielectric layer; and a second semiconductor layer adjacent to the second dielectric layer and separated from the second source / drain component by a third dielectric layer.

9. The semiconductor structure of claim 8, wherein the third dielectric layer is in direct contact with the second source / drain component, the second dielectric layer, and the second semiconductor layer.

10. A transistor, comprising: A gate structure surrounds a plurality of nanostructures disposed above a substrate; An undoped semiconductor layer is disposed in and above the substrate, wherein a top surface of the undoped semiconductor layer is flush with or above a top surface of a bottommost nanostructure of the nanostructures; a dielectric layer is disposed between the undoped semiconductor layer and the bottommost nanostructure of the nanostructures; and a source / drain member is adjacent to the nanostructures, wherein a bottom surface of the source / drain member is in direct contact with the top surface of the undoped semiconductor layer, wherein the source / drain member is disposed adjacent to the nanostructures along a first direction, and the nanostructures have different widths along the first direction.

11. The transistor of claim 10, wherein the undoped semiconductor layer includes a first portion embedded in the substrate and a second portion on the substrate, wherein the entire sidewall surface of the second portion of the undoped semiconductor layer is covered by the dielectric layer.

12. A method for manufacturing a semiconductor structure, comprising: A first fin-shaped active region is formed, the first fin-shaped active region extending from a substrate and including a plurality of channel layers interleaved by a plurality of sacrificial layers; A first gate stack is formed above a first channel region of the first fin-shaped active region; a first source / drain region of the first fin-shaped active region is etched to form a first source / drain opening; a first semiconductor layer is formed in a bottom of the first source / drain opening; a first dielectric layer is formed on the first semiconductor layer and extends along a sidewall surface of a middle portion of the first source / drain opening, wherein the entire sidewall surface of the bottommost channel layer of the channel layers is covered by the first dielectric layer; a second semiconductor layer is formed on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer; a first source / drain component is formed on the second semiconductor layer; and the first gate stack and the sacrificial layers are replaced by a gate structure, wherein the gate structure surrounds the channel layers, the first source / drain component is adjacent to the channel layers along a first direction, and the channel layers have different widths along the first direction.

13. A method for manufacturing a semiconductor structure as claimed in claim 12, wherein the first source / drain component is a p-type source / drain component and is in direct contact with the second semiconductor layer and the first dielectric layer.

14. A method for manufacturing a semiconductor structure as claimed in claim 12, wherein forming the first dielectric layer comprises: An insulating layer is compliantly deposited over the substrate. The insulating layer includes a vertical portion and a horizontal portion. The vertical portion extends along a sidewall surface of the first source / drain opening, and the horizontal portion extends along a top surface of the first semiconductor layer. A first etching process is performed to remove the horizontal portion of the insulating layer. And after the second semiconductor layer is formed, a second etching process is performed to remove multiple portions of the vertical portion of the insulating layer that are not covered by the second semiconductor layer.

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