Method of manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device comprising: a semiconductor substrate; an interlayer insulating layer located on the semiconductor substrate; a first via structure passing through the semiconductor substrate and the interlayer insulating layer and having a first diameter; and a second via structure passing through the semiconductor substrate and the interlayer insulating layer, the second via structure having a second diameter greater than the first diameter at the same vertical level. The sidewall of the first via structure may include at least one undercut region projecting horizontally toward the center of the first via structure, and the outer sidewall of the second via structure may contact the semiconductor substrate or the interlayer insulating layer in a region above the undercut region.

Description

Technical Field

[0001] [Cross - reference to Related Applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2021 - 0175208, filed with the Korean Intellectual Property Office on December 8, 2021, the disclosure of which is incorporated herein by reference in its entirety.

[0003] The present inventive concept relates to a semiconductor device, a semiconductor package, and / or a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device, a semiconductor package, and / or a method of manufacturing a semiconductor device that processes data quickly and has low power consumption. Prior Art

[0004] As three - dimensional (3D) packaging in which multiple semiconductor chips are stacked in a semiconductor package has been actively developed, through - silicon - via (TSV) technology in which electrical connections are formed vertically through a substrate or a die has been significantly recognized. To enhance the performance of 3D packaging, data speed and power consumption must be improved. Summary of the Invention

[0005] The present inventive concept provides a semiconductor device that processes data quickly and has low power consumption.

[0006] The present inventive concept provides a semiconductor package that processes data quickly and has low power consumption.

[0007] According to an aspect of the present inventive concept, a semiconductor device includes: a semiconductor substrate; an interlayer insulating layer on the semiconductor substrate; a first via structure passing through the semiconductor substrate and the interlayer insulating layer, the first via structure having a first diameter; and a second via structure passing through the semiconductor substrate and the interlayer insulating layer, the second via structure having a second diameter that is greater than the first diameter at the same vertical level. The sidewall of the first via structure includes at least one undercut region that horizontally protrudes toward the center of the first via structure, and the outer sidewall of the second via structure contacts the semiconductor substrate or the interlayer insulating layer at a region above the undercut region.

[0008] According to another aspect of the inventive concept, a semiconductor device includes: a semiconductor substrate; an interlayer insulating layer on the semiconductor substrate; a signal via structure passing through the semiconductor substrate and the interlayer insulating layer; and a power via structure passing through the semiconductor substrate and the interlayer insulating layer. A sidewall of the signal via structure includes at least one undercut region horizontally protruding toward a horizontal center of the signal via structure. A height of the signal via structure is the same as a height of the power via structure. The signal via structure has a first diameter and the power via structure has a second diameter. The second diameter is greater than the first diameter at the same vertical level. An outer sidewall of the power via structure contacts the semiconductor substrate or the interlayer insulating layer at a region above the undercut region.

[0009] According to another aspect of the inventive concept, a semiconductor package includes: a first semiconductor device including a cell region and a peripheral region; and a second semiconductor device stacked on the first semiconductor device and electrically connected to the first semiconductor device. The first semiconductor device includes a semiconductor substrate and an interlayer insulating layer on the semiconductor substrate. The first semiconductor device further includes a first via structure and a second via structure disposed in the peripheral region. The first via structure passes through the semiconductor substrate and the interlayer insulating layer and has a first diameter in the peripheral region. The second via structure passes through the semiconductor substrate and the interlayer insulating layer and has a second diameter greater than the first diameter. A sidewall of the first via structure includes at least one undercut region horizontally protruding toward a center of the first via structure. A height of the first via structure is the same as a height of the second via structure. An outer sidewall of the second via structure contacts the semiconductor substrate or the interlayer insulating layer at a region above the undercut region.

[0010] According to another aspect of the inventive concept, a method of manufacturing a semiconductor device includes: forming an interlayer insulating layer on a semiconductor substrate; forming a mask material layer on the interlayer insulating layer; removing a portion of the mask material layer on an upper surface of the mask material layer at each of a first position for forming a first via hole structure having a first diameter and a second position for forming a second via hole structure having a second diameter; removing both a portion of the interlayer insulating layer and a portion of the semiconductor substrate at the first position to form a first primary groove; removing at least a portion of the interlayer insulating layer at the second position to form a second primary groove; etching a portion of the semiconductor substrate at positions of the first primary groove and the second primary groove simultaneously to form a first via hole and a second via hole; forming the first via hole structure and the second via hole structure in the first via hole and the second via hole, respectively; and forming external connection terminals electrically connected to the first via hole structure and the second via hole structure, wherein a depth of the first primary groove is greater than a depth of the second primary groove, a diameter of the first primary groove is smaller than a diameter of the second primary groove, and removing the portion of the mask material layer at the second position includes exposing the mask material layer by using a reticle including a scattering bar disposed on the upper surface of the mask material layer at the second position. Brief Description of the Drawings

[0011] Some example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a plan view for describing a semiconductor device according to an example embodiment. FIG. 2 is an enlarged view showing a first through-silicon via (TSV) cell region of FIG. 1. FIG. 3 is a side view showing a cross-sectional surface taken along line III-III' of FIG. 2 in a semiconductor device according to an example embodiment. FIGS. 4A and 4B are partial enlarged views showing in detail a region indicated by IV of FIG. 3. FIG. 5 is a side view showing a cross-sectional surface taken along line III-III' of FIG. 2 in a semiconductor device according to an example embodiment. FIG. 6 is a side view showing a cross-sectional surface of a semiconductor device according to an example embodiment. FIG. 7 is a flowchart showing a method of manufacturing a semiconductor device according to an example embodiment. FIGS. 8A to 8I are side cross-sectional views showing a method of manufacturing a semiconductor device. FIG. 9 is a flowchart showing in more detail an operation of forming a first primary groove and a second primary groove. FIG. 10 is a flowchart showing operations of forming the first via structure via holes and the second via structure via holes in more detail. FIGS. 11A to 11D are side cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment. FIG. 12 is a cross-sectional view showing a main configuration of a semiconductor package according to an exemplary embodiment. Embodiments

[0012] Hereinafter, some exemplary embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements, and redundant descriptions thereof are omitted.

[0013] Although the terms "same", "equal", or "identical" are used in the description of the exemplary embodiments, it should be understood that there may be some inaccuracies. Thus, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as another element within the manufacturing or operable tolerance range (e.g., ±10%).

[0014] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include the manufacturing or operating tolerance around the stated numerical value (e.g., ±10%). In addition, when the phrases "about" and "substantially" are used in conjunction with a geometric shape, it is intended that the geometric shape not require precision, but the tolerance of the shape is within the scope of this disclosure. Further, regardless of whether the numerical value or shape is modified with "about" or "substantially", it should be understood that these values and shapes should be interpreted as including the manufacturing or operating tolerance around the stated numerical value or shape (e.g., ±10%). FIG. 1 is a plan view for describing a semiconductor device 100 according to an exemplary embodiment.

[0015] Referring to FIG. 1, the semiconductor device 100 may include a plurality of cell regions 14. A plurality of memory cells may be disposed in the plurality of cell regions 14. A plurality of word lines, a plurality of bit lines, and sense amplifiers may be disposed in the plurality of cell regions 14 based on various schemes. A peripheral region may be provided near the plurality of cell regions 14, and the peripheral region may include a plurality of row decoders 16, a plurality of column decoders 18, and a through-silicon via (TSV) region 20. The plurality of row decoders 16 may receive an address and decode the address to select a row line of the cell region 14. The plurality of column decoders 18 may receive an address and decode the address to output a column address for selecting a column line of the cell region 14. The memory semiconductor chip 12 may include a write driver, an input / output (I / O) sense amplifier, and an I / O buffer.

[0016] The TSV region 20 can be disposed at an approximate central portion of the memory semiconductor chip 12. A plurality of TSV structures 30 can be configured in the TSV region 20. The number and shape of the TSV structures 30 shown in FIG. 1 can be only exemplary embodiments, and the inventive concept is not limited to the illustration of FIG. 1. For example, about hundreds or thousands of TSV structures 30 can be configured in the TSV region 20.

[0017] The I / O buffers included in the memory semiconductor chip 12 can receive signals from the outside via the TSV structures 30, or can transmit signals to the outside via the TSV structures 30.

[0018] The TSV region 20 can include a plurality of first TSV unit regions 22, second TSV unit regions 24, third TSV unit regions 26, and fourth TSV unit regions 28. The plurality of first TSV unit regions 22, second TSV unit regions 24, third TSV unit regions 26, and fourth TSV unit regions 28 can include one first TSV unit region 22, one second TSV unit region 24, one third TSV unit region 26, and one fourth TSV unit region 28. In FIG. 1, the TSV region 20 is shown as including four TSV regions (for example, the first TSV unit region 22, the second TSV unit region 24, the third TSV unit region 26, and the fourth TSV unit region 28), but the inventive concept is not limited to the illustration of FIG. 1. The TSV region 20 can include a different number of TSV unit regions.

[0019] FIG. 2 is an enlarged view showing the first TSV unit region 22 of FIG. 1. In FIG. 2, the first TSV unit region 22 is shown, but it can be understood that the second TSV unit region 24, the third TSV unit region 26, and the fourth TSV unit region 28 are also shown in the same way.

[0020] Referring to FIG. 2, a plurality of via structures 110 and via structures 120 can be disposed in the first TSV unit region 22. The via structures 110 and via structures 120 can include a first via structure 110 having a relatively small diameter and a second via structure 120 having a relatively large diameter. For example, the first via structure 110 can include a signal via structure, and the second via structure 120 can include a power via structure.

[0021] The second via structure 120 can have a relatively low resistance due to its relatively large diameter and can be a power transmission path for more effectively supplying power. The first via structure 110 can have a relatively low capacitance due to its relatively small diameter and can be a signal transmission path for providing a high data transmission speed.

[0022] In some example embodiments, a plurality of first via structures 110 each corresponding to a signal transmission path may be arranged in a lattice form, and a plurality of second via structures 120 each corresponding to a power transmission path may be arranged in a "one" shape (e.g., a line shape). However, the inventive concept is not limited to this configuration.

[0023] FIG. 3 is a side view showing a cross-sectional surface taken along line III-III' of FIG. 2 in the semiconductor device 100 according to an example embodiment.

[0024] Referring to FIG. 3, the semiconductor device 100 may include a semiconductor substrate 101, an interlayer insulating layer 134 formed on the semiconductor substrate 101, a first via structure 110 passing through the semiconductor substrate 101 and the interlayer insulating layer 134, and a second via structure 120 passing through the semiconductor substrate 101 and the interlayer insulating layer 134.

[0025] The semiconductor substrate 101 may include a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In at least one example embodiment, the semiconductor substrate 101 may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate 101 may include a buried oxide (BOX) layer. In some example embodiments, the semiconductor substrate 101 may include a conductive region (e.g., a doped well) or a doping structure. In addition, the semiconductor substrate 101 may include various isolation layers (not shown), such as a shallow trench isolation (STI) structure.

[0026] The interlayer insulating layer 134 can be configured as a single material layer or can be configured as a multi-material layer in which two or more than two material layers are stacked. In some exemplary embodiments, the interlayer insulating layer 134 can include a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, or an ultra low K (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK film can include, for example, a SiOC layer or a SiCOH layer. In some exemplary embodiments, the interlayer insulating layer 134 can include a layer containing silicon nitride (SiN) or silicon oxynitride (SiON).

[0027] A plurality of semiconductor devices 132 of various types can be disposed in the interlayer insulating layer 134 and the semiconductor substrate 101. The semiconductor device 132 can include a microelectronic device and can include, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) image sensor, a system large scale integration (LSI), or a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), a micro-electro-mechanical system (MEMS), active components, and / or passive components. The semiconductor device 132 can be electrically connected to a conductive region of the semiconductor substrate 101. The semiconductor device 132 and the interlayer insulating layer 134 formed before forming the multi-wiring structure can be referred to as a front-end-of-line (FEOL) structure 130. According to other exemplary embodiments, the semiconductor device 132 can be electrically disconnected from other adjacent semiconductor devices 132 by an isolation layer.

[0028] The isolation layer can be configured as a single material layer or can be configured as a multi-material layer in which two or more than two material layers are stacked. In some exemplary embodiments, the isolation layer can have a STI structure. In some exemplary embodiments, the upper surface of the isolation layer can be disposed in a plane substantially the same as the upper surface of the semiconductor substrate 101. In some exemplary embodiments, the isolation layer can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0029] A first via hole 110H can be formed to penetrate through the semiconductor substrate 101 and the interlayer insulating layer 134. The first via structure 110 can include a first via insulating layer 116 covering the sidewalls of the first via hole 110H, a first barrier layer 114 covering the sidewalls of the first via insulating layer 116, and a first via plug 112 filling the internal space defined by the first barrier layer 114.

[0030] In some exemplary embodiments, the first via insulating layer 116 can conformally cover the sidewalls of the first via hole 110H. For example, the first via insulating layer 116 can extend along the sidewalls of the first via hole 110H to have a substantially uniform thickness. The first via insulating layer 116 can include an oxide, a nitride, a carbide, a polymer, or a combination thereof. In some exemplary embodiments, the first via insulating layer 116 can be formed by a chemical vapor deposition (CVD) process. In some exemplary embodiments, the first via insulating layer 116 can have a thickness of about 500 angstroms to about 2,500 angstroms.

[0031] In addition, the sidewalls of the first via hole 110H can include at least one undercut region UC. The undercut region UC can refer to a portion of the sidewalls of the first via hole 110H that horizontally protrudes toward the center of the first via hole 110H. As described below, the first via hole 110H can be formed by a process such as a deep reactive ion etching process, and in this case, fine uneven portions can be formed in the sidewalls of the first via hole 110H, and the undercut region UC can protrude significantly compared to the fine uneven portions.

[0032] In addition, according to an exemplary embodiment, the height range of each of the first vias structure 110 and the second vias structure 120 may be from about 30 micrometers to about 150 micrometers. According to an exemplary embodiment, the distance Ha from the undercut region UC to the upper surface of the first vias structure 110 may be less than the distance Hb from the undercut region UC to the lower surface of the first vias structure 110. For example, the range of the distance Hb from the undercut region UC to the lower surface of the first vias structure 110 may be from about 200% to about 500% of the distance Ha from the undercut region UC to the upper surface of the first vias structure 110. In addition, the range of the distance Hc from the lower surface of the interlayer insulating layer 134 to the undercut region UC may be from about 5 micrometers to about 15 micrometers.

[0033] In FIG. 3, the first via 110H is shown as including one undercut region UC, but the inventive concept is not limited thereto. The first via 110H may also include more than one undercut region UC (e.g., two or more than two undercut regions UC).

[0034] In some exemplary embodiments, the first barrier layer 114 may extend along the sidewalls of the first via insulating layer 116 to have a substantially uniform thickness. The first barrier layer 114 may include a conductive layer having a relatively low wiring resistance. For example, the first barrier layer 114 may include a single layer or multiple layers, the single layer or multiple layers including at least one material selected from the following: tungsten (W), tungsten nitride (WN), tungsten carbide (WC), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and nickel boride (NiB). For example, the first barrier layer 114 may include multiple layers, the multiple layers including TaN / W, TiN / W, or WN / W. The first barrier layer 114 may have a thickness of from about 500 angstroms to about 1,000 angstroms. In some exemplary embodiments, the first barrier layer 114 may be formed by a physical vapor deposition (PVD) process, a CVD process, or an atomic layer deposition (ALD) process, but the inventive concept is not limited thereto.

[0035] The second vias structure 120 may include a second via insulating layer 126 covering the sidewalls of the second via 120H, a second barrier layer 124 covering the sidewalls of the second via insulating layer 126, and a second via plug 122 filling the internal space defined by the second barrier layer 124.

[0036] The second via insulating layer 126, the second barrier layer 124, and the second via plug 122 may be the same as or substantially similar to the first via insulating layer 116, the first barrier layer 114, and the first via plug 112, respectively. The first via insulating layer 116, the first barrier layer 114, and the first via plug 112 have been described above, and thus the detailed descriptions of the second via insulating layer 126, the second barrier layer 124, and the second via plug 122 are omitted.

[0037] In some example embodiments, the horizontal cross-sectional surface of each of the first via structure 110 and the second via structure 120 may have, for example, a flat circular shape, a polygonal shape, or an elliptical shape. However, the inventive concept is not limited thereto. The width of each of the first via structure 110 and the second via structure 120 in the interlayer insulating layer 134 may have a constant rate of change in the horizontal direction. In addition, the first via structure 110 and the second via structure 120 may have the same height. The height of the first via structure 110 or the second via structure 120 may refer to the vertical direction (Z direction) length.

[0038] The first via structure 110 may have a first diameter D1, and the second via structure 120 may have a second diameter D2 that is greater than the first diameter D1 at the same vertical level. Each of the first diameter D1 and the second diameter D2 may be a diameter measured on the outer diameter of the corresponding one in the first via insulating layer 116 and the second via insulating layer 126. For example, the range of the first diameter D1 may be from about 2 micrometers to about 4 micrometers, and the range of the second diameter D2 may be from about 3 micrometers to about 8 micrometers. In some example embodiments, the second diameter D2 may be about 1 micrometer to about 5 micrometers larger than the first diameter D1. For example, the ratio range of the second diameter D2 to the first diameter D1 may be from about 110% to about 200%.

[0039] The first barrier layer 114 of the first via structure 110 may have a first barrier width E1 limited by the outer diameter of the first barrier layer 114, and the second barrier layer 124 of the second via structure 120 may have a second barrier width E2 limited by the outer diameter of the second barrier layer 124. In some example embodiments, the second barrier width E2 may be greater than the first barrier width E1. In some example embodiments, the second barrier width E2 may be about 1 micrometer to about 4 micrometers larger than the first barrier width E1.

[0040] One end of each of the first vias structure 110 and the second vias structure 120 can be electrically connected to a multilayer wiring structure 146 including a plurality of metal wiring layers 142 and a plurality of contact plugs 144. In FIG. 3, the multilayer wiring structure 146 is shown in direct contact with the first vias structure 110 and the second vias structure 120, but another conductor can be disposed between the multilayer wiring structure 146 and the first vias structure 110 or the second vias structure 120 to electrically connect the multilayer wiring structure 146 to the first vias structure 110 or the second vias structure 120. In addition, the plurality of multilayer wiring structures 146 can be insulated from each other by an inter-metal dielectric layer 148.

[0041] In some example embodiments, an upper insulating layer 150 can be formed on the inter-metal dielectric layer 148. The upper insulating layer 150 can include silicon oxide, silicon nitride, a polymer, or a combination thereof. A hole 150H exposing a bonding pad 152 connected to the multilayer wiring structure 146 can be formed in the upper insulating layer 150. The bonding pad 152 can be connected to an upper connection terminal 154 via the hole 150H.

[0042] The other end of each of the first vias structure 110 and the second vias structure 120 can be covered by a conductive layer 172. A connection terminal 174 can be electrically connected to the first vias structure 110 and the second vias structure 120 via the conductive layer 172.

[0043] The upper connection terminal 154 and the connection terminal 174 are not limited to the shapes shown in FIG. 3. Each of the upper connection terminal 154 and the connection terminal 174 can be in the form of a conductive pad, a solder ball, a solder bump, or a redistribution conductive layer. In some example embodiments of the semiconductor device 100, the upper connection terminal 154 is omitted.

[0044] In addition, the semiconductor device 100 according to the exemplary embodiments may not include an etching delay layer. Thus, the outer sidewalls of each of the first via structure 110 and the second via structure 120 may contact the semiconductor substrate 101 or the interlayer insulating layer 134 at a region above the undercut region UC. For example, the outer sidewalls of each of the first via structure 110 and the second via structure 120 may contact the semiconductor substrate 101 or the interlayer insulating layer 134 at the same vertical level. For example, the outer sidewalls of each of the first via structure 110 and the second via structure 120 may contact only the semiconductor substrate 101 and the interlayer insulating layer 134 without contacting the etching delay layer. Regardless of the name of the etching delay layer, the etching delay layer may be disposed inward from the semiconductor substrate 101, inward from the interlayer insulating layer 134, or between the semiconductor substrate 101 and the interlayer insulating layer 134, and may refer to a material that forms an etching rate difference between the first via hole 110H and the second via hole 120H. That is, the etching delay layer may refer to a material layer having an etching selectivity with respect to the semiconductor substrate 101 or having an etching selectivity with respect to the interlayer insulating layer 134. For example, the etching delay layer may include at least one of an SiN-based material, an oxide-based material, an Si-based material (e.g., SiGe), a metal-based material, and a carbon-based material.

[0045] A general semiconductor device includes an etching delay layer inward from the semiconductor substrate or inward from the interlayer insulating layer to cause a diameter difference between a first via structure and a second via structure. In the case where the etching delay layer is provided, the etching delay layer may contact the outer wall of the first via structure or the second via structure after the first via structure and the second via structure are formed, and due to this, the reliability of the semiconductor device may be relatively low.

[0046] On the other hand, since the semiconductor device 100 according to the exemplary embodiments does not include an etching delay layer, contaminants may not be included in the semiconductor substrate 101 or the interlayer insulating layer 134 when the first via structure 110 and the second via structure 120 are formed. Thus, the reliability of the semiconductor device 100 may be relatively high.

[0047] FIGS. 4A and 4B are partial enlarged views showing in detail the region shown by IV of FIG. 3.

[0048] Referring to FIG. 4A, an undercut region UC protruding horizontally toward the center of the first via hole 110H may be disposed in the first via hole 110H. Based on the protruding shape of the undercut region UC, the first via insulating layer 116 and the first barrier layer 114 stacked thereon in sequence may have a protruding shape. Since the first via insulating layer 116 and the first barrier layer 114 are conformally formed to have a substantially constant thickness, the protruding shape of the undercut region UC of the first via hole 110H may be transmitted to the first via insulating layer 116 and the first barrier layer 114 in the same or similar manner.

[0049] Referring to FIG. 4B, a plurality of sectors SC and a protruding undercut region UC may be disposed in the first via hole 110H. The horizontal width of each of the sectors SC may be smaller than the horizontal width of the undercut region UC. The first via hole 110H may be formed by a Bosch process. For example, an inductive coupled plasma deep reactive ion etching (ICP DRIE) process using SF6 or O2 plasma and a sidewall passivation process using one of CFx-based materials (such as C4F8) may be repeated multiple times to form the first via hole 110H in the semiconductor substrate 101. Thus, as shown in FIG. 4B, the first via hole 110H including a plurality of sectors SC may be formed. According to another exemplary embodiment, the first via hole 110H may be formed by an ALD process or a CVD process.

[0050] Based on the protruding shapes of the undercut region UC and the sectors SC, the first via insulating layer 116 and the first barrier layer 114 stacked thereon in sequence may have shapes corresponding to the protruding shapes.

[0051] In the interface between the first via insulating layer 116 and the first barrier layer 114, the uneven portions of the sectors SC may be reduced compared to the sidewall of the first via hole 110H. In some exemplary embodiments, the interface between the first via insulating layer 116 and the first barrier layer 114 may include an interface that does not transmit the uneven portions of the sectors SC thereto.

[0052] FIG. 5 is a side view showing a cross-sectional surface taken along line III-III' of FIG. 2 in the semiconductor device 100a according to an exemplary embodiment. Comparing the exemplary embodiment of FIG. 5 with the exemplary embodiment of FIG. 3, there may be only the following differences: the first via structure 110 is different in the upper portion and the lower portion of the undercut region UC, and other features may be the same. Therefore, hereinafter, such differences will be mainly described.

[0053] Referring to FIG. 5, the first through-hole structure 110 may have a first width W1 in the upper portion of the undercut region UC and a second width W2 in the lower portion of the undercut region UC. The first width W1 may be different from the second width W2. In some exemplary embodiments, the first width W1 may be greater than the second width W2. In some exemplary embodiments, the first width W1 may be less than the second width W2. Each of the first width W1 and the second width W2 may be less than the diameter D2 of the second through-hole structure 120 (see FIG. 3).

[0054] FIG. 6 is a side view showing a cross-sectional surface of a semiconductor device 100b according to an exemplary embodiment. Comparing the exemplary embodiment of FIG. 6 with the exemplary embodiment of FIG. 3, there may be only the following differences: the semiconductor device 100b further includes a third through-hole structure 180 having a third diameter D3 greater than the second diameter D2, and other features may be the same. Therefore, hereinafter, such differences will be mainly described.

[0055] Referring to FIG. 6, the third through-hole structure 180 may have a third diameter D3 and may include a third through-hole plug 182, a third barrier layer 184 formed on the surface of the third through-hole plug 182 to have a substantially uniform thickness, and a third through-hole insulating layer 186 formed on the surface of the third barrier layer 184 to have a substantially uniform thickness.

[0056] Except for the dimensions, the third through-hole plug 182, the third barrier layer 184, and the third through-hole insulating layer 186 may be the same as or substantially similar to the first through-hole plug 112, the first barrier layer 114, and the first through-hole insulating layer 116, and thus their detailed descriptions are omitted.

[0057] The third through-hole structure 180 may have a third diameter D3, and the third diameter D3 may be greater than the second diameter D2 of the second through-hole structure 120. In some exemplary embodiments, the third diameter D3 may be about 1 micron to about 5 microns larger than the second diameter D2. The third diameter D3 may be the diameter measured on the outer diameter of the third through-hole insulating layer 186.

[0058] The third barrier layer 184 of the third through-hole structure 180 may have a third barrier width E3, and the third barrier width E3 may be greater than the second barrier width E2 of the second through-hole structure 120. The third barrier width E3 may be about 1 micron to about 4 microns larger than the second barrier width E2.

[0059] In this case, the first vias structure 110 may include two or more than two first undercut regions UC1 and first undercut region UC2. In addition, the second vias structure 120 may include one or more second undercut regions UC3. The second undercut region UC3 may refer to a part of the sidewall of the second interlayer via 120H that horizontally protrudes toward the center of the second interlayer via 120H. The first vias structure 110 may include more undercut regions UC than the second vias structure 120. In some exemplary embodiments, the first vias structure 110 may include two first undercut regions UC1 and first undercut region UC2, and the second vias structure 120 may include one second undercut region UC3.

[0060] In some exemplary embodiments, the vertical level of the second undercut region UC3 of the second vias structure 120 may be located between the vertical level of the first undercut region UC1 of the first vias structure 110 and the vertical level of the first undercut region UC2 of the first vias structure 110. In other words, relative to the lower surface 101B of the semiconductor substrate 101, the vertical level of the first lower undercut region UC2 of the first vias structure 110 may be the lowest, the vertical level of the first upper undercut region UC1 of the first vias structure 110 may be the highest, and the vertical level of the second undercut region UC3 of the second vias structure 120 may be between the vertical levels of the first lower undercut region and the first upper undercut region. In other exemplary embodiments, the vertical level of each of the first undercut regions UC1 and UC2 may be different from the vertical level of the second undercut region UC3.

[0061] In other exemplary embodiments, the isolation layer surrounding the third vias structure 180 in the horizontal direction may be disposed at a certain height to contact the side surface of the third vias structure 180.

[0062] FIG. 7 is a flowchart illustrating a method of manufacturing a semiconductor device 100 according to an exemplary embodiment. FIGS. 8A to 8I are side cross-sectional side views illustrating a method of manufacturing a semiconductor device 100.

[0063] Referring to FIGS. 7 and 8A, in operation S110, an interlayer insulating layer 134 may be formed on the semiconductor substrate 101. In some exemplary embodiments, a semiconductor device 132 may be formed on the semiconductor substrate 101 before forming the interlayer insulating layer 134. As described above, the semiconductor device 132 and the interlayer insulating layer 134 formed before forming the multilayer wiring structure may be referred to as a FEOL structure (130 in FIG. 3). Subsequently, a capping material layer 200 may be coated and formed on the interlayer insulating layer 134.

[0064] Referring to FIGS. 7, 8B, and 9, the capping material layer 200 on the upper surface of the interlayer insulating layer 134 can be etched at the position (hereinafter referred to as the first position) for forming the first via structure 110, and a portion of the capping material layer 200 on the upper surface of the interlayer insulating layer 134 can be removed at the position (hereinafter referred to as the second position) for forming the second via structure 120. Due to the removal of a portion of the capping material layer 200, a capping pattern 201 can be formed. The capping pattern 201 can be a photoresist pattern and can be formed by a coating process, an exposure process, and a development process performed on the capping material layer 200 respectively. FIG. 9 is a flowchart showing the operation S120 of forming the first primary groove PRCS1 and the second primary groove PRCS2 in more detail. A photomask SR including a scattering bar SB can be disposed on the upper surface at the second position, and thus, the capping material layer 200 on the upper surface at the second position can be exposed. For example, the scattering bar SB can be disposed on the upper surface at the second position, and the capping material layer 200 on the upper surface at the second position can be exposed. In addition, the open photomask SR can be disposed on the upper surface at the first position.

[0065] According to an exemplary embodiment, the scattering bar SB can include a line and space pattern, an island pattern, or a combination thereof. The exposure energy of the scattering bar SB passing through the photomask SR can be reduced. Therefore, the exposure energy reaching the capping material layer 200 on the upper surface at the second position corresponding to the scattering bar SB can be reduced. Referring to FIG. 9, in operation S121, the scattering bar SB of the photomask SR can be disposed on the upper surface at the second position. In this case, in operation S123, the amount of exposure energy reaching the upper surface at the second position can be adjusted by adjusting the density of the scattering bar SB corresponding to the upper surface at the second position. Therefore, in operation S125, a portion of the capping material layer 200 on the upper surface at each of the first position and the second position can be removed. In addition, the degree of removal of the capping material layer 200 on the upper surface at the first position can be greater than the degree of removal of the capping material layer 200 on the upper surface at the second position. The capping material layer 200 on the upper surface at each of the first position and the second position can be removed, and thus, the capping pattern 201 can be formed. Therefore, although described below, the depth of the first primary groove PRCS1 can be deeper than the depth of the second primary groove PRCS2.

[0066] Referring to FIGS. 7, 8C, and 9, in operation S125, a portion of the interlayer insulating layer 134 or the semiconductor substrate 101 at the first position and the second position can be etched by using the capping pattern 201 as an etching mask. Therefore, a portion of the first semiconductor substrate 101 at the first position can be exposed.

[0067] Referring to FIGS. 7, 8D, and 9, in operation S125, a first primary recess PRCS1 may be formed in the exposed semiconductor substrate 101. The first primary recess PRCS1 having a first depth H1 may be formed from the upper surface of the semiconductor substrate 101 at a first location. Subsequently, in operation S130, a second primary recess PRCS2 may be formed at a second location. The first primary recess PRCS1 may be formed by etching the semiconductor substrate 101 at the first location, and then, the second primary recess PRCS2 may be formed by etching a portion of the interlayer insulating layer 134 at the second location.

[0068] According to an exemplary embodiment, the second primary recess PRCS2 may be configured to include an opening portion, wherein the opening width of the opening portion is greater than the opening width of the opening portion of the first primary recess PRCS1. The first primary recess PRCS1 or the second primary recess PRCS2 may have, for example, a flat circular shape, a polygonal shape, or an elliptical shape. However, the inventive concept is not limited thereto.

[0069] In some exemplary embodiments, a deep reactive ion etching (DRIE) process may be performed to form the first primary recess PRCS1 or the second primary recess PRCS2 at the first location or the second location.

[0070] Since the semiconductor substrate 101 at the first location and the interlayer insulating layer 134 at the second location have an etching selectivity, the first primary recess PRCS1 at the first location may not be etched or may be etched relatively slightly, while the interlayer insulating layer 134 at the second location is etched and removed.

[0071] Referring to FIGS. 7, 8E, and 9, a first via structure via hole (referred to as a first via hole) 110H and a second via structure via hole (referred to as a second via hole) 120H each having a second depth H2 greater than the first depth H1 may be formed by simultaneously etching the first primary recess PRCS1 and the second primary recess PRCS2. FIG. 10 is a flowchart of operation S140 showing in more detail the formation of the first via structure via hole 110H and the second via structure via hole 120H of FIG. 7.

[0072] In operation S131, the deep reactive ion etching (DRIE) process described above can be performed to form the first via hole 110H and the second via hole 120H. The first via hole 110H may have a first diameter D1, and the second via hole 120H may have a second diameter D2. The second diameter D2 may be greater than the first diameter D1. Since the second diameter D2 is greater than the first diameter D1, the etching rate in the second via hole 120H may be greater than the etching rate in the first via hole 110H. Since the etching rate of the semiconductor substrate 101 in the first via hole 110H is slower than the etching rate of the semiconductor substrate 101 in the second via hole 120H, the depth of the first via hole 110H may be the same as the depth of the second via hole 120H at the end of etching.

[0073] In addition, after the first primary groove PRCS1 is formed by using the DRIE process in the first via hole 110H, an undercut region UC can be formed at the interface between the portions etched by another DRIE process (e.g., by further etching the semiconductor substrate 101 by using the DRIE process) for forming other portions of the first via hole 110H. In other words, the vertical level of the undercut region UC of the first via hole 110H can correspond to the vertical level of the lower surface of the first primary groove PRCS1.

[0074] In FIGS. 8B to 8E, the side surfaces of the respective patterns are shown as inclined surfaces instead of vertical surfaces, but the inventive concept is not limited thereto. Based on actual manufacturing conditions, the side surfaces of the respective patterns may be vertical surfaces instead of inclined surfaces.

[0075] Subsequently, the mask pattern 201 can be removed. In operation S135, the mask pattern 201 can be removed by a dissolution process using a solvent or an ashing process under an oxidizing atmosphere.

[0076] Referring to FIGS. 7 and 8F, the via insulating material layer 116m and the barrier material layer 114m can be sequentially formed on the sidewalls and lower surfaces of each of the first via hole 110H and the second via hole 120H and on the exposed surface of the interlayer insulating layer 134.

[0077] The via insulating material layer 116m and the barrier material layer 114m can be formed by a PVD process, a CVD process, or an ALD process and the materials obtainable therefrom described above with reference to FIG. 3, and thus their detailed descriptions are omitted.

[0078] In addition, a plug material layer 112m for filling the space may be formed on the barrier material layer 114m. The plug material layer 112m may be formed by, for example, an electroplating process. For example, a metal seed layer (not shown) may be formed on the surface of the barrier material layer 114, and then a metal layer may grow from the metal seed layer by an electroplating process, thereby forming the plug material layer 112m that fills the space on the barrier material layer 114m. The metal seed layer may include copper (Cu), a Cu alloy, Co, Ni, Ru, Co / Cu, or Ru / Cu. A PVD process may be used to form the metal seed layer. The main material of the plug material layer 112m may be Cu or W. In some example embodiments, the plug material layer 112m may include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuW, W, or a W alloy, but is not limited thereto. The electroplating process may be performed at a temperature of about 10°C to about 65°C. For example, the electroplating process may be performed at room temperature. After the plug material layer 112m is formed, the composite material forming the plug material layer 112m may be annealed at a temperature of about 150°C to about 450°C.

[0079] Referring to FIGS. 7 (operation S150) and 8G, the first via structure 110 and the second via structure 120 may be formed by partially removing the plug material layer 112, the barrier material layer 114m, and the via insulating material layer 116m.

[0080] The operation of partially removing the plug material layer 112, the barrier material layer 114m, and the via insulating material layer 116m may be performed by a process such as a chemical mechanical polishing (CMP) process or an etch-back process.

[0081] Referring to FIGS. 7 and 8H, a plurality of metal wiring layers 142, a plurality of contact plugs 144, and bonding pads 152 electrically connected to the first via plug 112 may be formed at a first position. In addition, a plurality of metal wiring layers 142, a plurality of contact plugs 144, and bonding pads 152 electrically connected to the second via plug 122 may be formed at a second position.

[0082] Subsequently, an upper insulating layer 150 that partially exposes the bonding pads 152 may be formed, and upper connection terminals 154 may be formed on the bonding pads 152.

[0083] Referring to FIGS. 7 and 8I, by removing a portion of the semiconductor substrate 101, the end portions of each of the first vias structure 110 and the second vias structure 120 can penetrate through the lower surface 101B of the semiconductor substrate 101 and can be exposed.

[0084] In some exemplary embodiments, the operation of removing a portion of the semiconductor substrate 101 can be performed by, for example, a CMP process.

[0085] In addition, a lower insulating layer 160 covering the lower surface 101B of the semiconductor substrate 101 can be formed. The lower insulating layer 160 can be formed to cover the first vias structure 110 and the second vias structure 120 that respectively protrude from the lower surface 101B of the semiconductor substrate 101. In some exemplary embodiments, the lower insulating layer 160 can be formed by a CVD process. In some exemplary embodiments, the lower insulating layer 160 can include silicon oxide, silicon nitride, or a polymer.

[0086] Subsequently, referring to FIG. 3, a polishing process can be performed from the exposed surface of the lower insulating layer 160 until a planarized surface is obtained at the lower surface 101B of the semiconductor substrate 101, and the lower surfaces of the first vias structure 110 and the second vias structure 120 planarized at the lower surface 101B of the semiconductor substrate 101 can be exposed.

[0087] Subsequently, a conductive layer 172 and connection terminals 174 connected to the first structure 110 and the second structure 120 can be formed.

[0088] The conductive layer 172 can configure an under bump metallization (UBM) layer and can include a layer having a composition of various materials based on the connection terminals 174. In some exemplary embodiments, the conductive layer 172 can include Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CrCu, or a combination thereof. For example, the conductive layer 172 can have a stacked structure of Cr / Cu / Au, a stacked structure of Cr / CrCu / Cu, a TiWCu compound, a stacked structure of TiWCu / Cu, a stacked structure of Ni / Cu, a stacked structure of NiV / Cu, a stacked structure of Ti / Ni, a stacked structure of Ti / NiP, a TiWNiV compound, a stacked structure of Al / Ni / Au, a stacked structure of Al / NiP / Au, a stacked structure of Ti / TiNi / CuNi compound, a stacked structure of Ti / Ni / Pd, a stacked structure of Ni / Pd / Au, or a stacked structure of NiP / Pd / Au.

[0089] The connection terminal 174 may include a conductive gasket, solder balls, solder bumps, or a redistribution conductive layer. The connection terminal 174 may be connected to the lower surfaces of the first via structure 110 and the second via structure 120 via the conductive layer 172. The connection terminal 174 may include Ni, Cu, Al, or a combination thereof, but is not limited thereto.

[0090] FIGS. 11A to 11D are side cross-sectional views showing a method of manufacturing the semiconductor device 100b according to an exemplary embodiment.

[0091] Referring to FIGS. 6 and 11A, the interlayer insulating layer 134 may be formed on the semiconductor substrate 101. In some exemplary embodiments, the semiconductor device 132 may be formed on the semiconductor substrate 101 before the interlayer insulating layer 134 is formed. Subsequently, the mask material layer 200 may be coated and formed on the interlayer insulating layer 134.

[0092] Subsequently, the first scattering bar SB1 and the second scattering bar SB2 of the photomask SR may be disposed on the upper surfaces at each of the second position and the position (hereinafter referred to as the third position) for forming the third via structure 180. In addition, the opened photomask SR may be disposed on the upper surface at the first position. The density of the first scattering bar SB1 disposed on the upper surface at the second position may be less than the density of the second scattering bar SB2 disposed on the upper surface at the third position. In addition, the removal depth of the mask material layer 200 on the upper surface at the third position may be less than the removal depth of the mask material layer 200 on the upper surface at the second position. Subsequently, an exposure process may be performed on the mask material layer 200 on the upper surfaces at each of the first to third positions.

[0093] Referring to FIGS. 6 and 11B, a portion of the interlayer insulating layer 134 or the semiconductor substrate 101 may be etched at each of the first to third positions. Accordingly, a portion of the first semiconductor substrate 101 at the first position may be exposed.

[0094] Referring to FIGS. 6 and 11C, a first primary recess PRCS1 having a first depth H1' from the semiconductor substrate 101 can be formed by etching the exposed semiconductor substrate 101. Thus, a second primary recess PRCS2 can be formed in the interlayer insulating layer 134 at a second position, while the first primary recess PRCS1 is formed by etching the semiconductor substrate 101 at a first position, and a third primary recess PRCS3 can be formed in the interlayer insulating layer 134 at a third position. According to an exemplary embodiment, the third primary recess PRCS3 can be configured to include an opening portion, wherein the opening width of the opening portion is greater than the opening width of the opening portions of each of the first primary recess PRCS1 and the second primary recess PRCS2. The first primary recess PRCS1 to the third primary recess PRCS3 can have, for example, a flat circular shape, a polygonal shape, or an elliptical shape. However, the inventive concept is not limited thereto.

[0095] Referring to FIGS. 6 and 11D, a fourth primary recess PRCS4 can be formed by etching the semiconductor substrate 101 at a first position, and a fifth primary recess PRCS5 can be formed by etching the semiconductor substrate 101 at a second position. The second depth H2' of the fourth primary recess PRCS4 from the semiconductor substrate 101 can be greater than the third depth H3' of the fifth primary recess PRCS5 from the semiconductor substrate 101. In addition, a portion of the semiconductor substrate 101 or the interlayer insulating layer 134 at the third position can be etched, and thus a sixth primary recess PRCS6 can be formed. The depth of the sixth primary recess PRCS6 can be less than the depth of each of the fourth primary recess PRCS4 and the fifth primary recess PRCS5. In addition, the upper surface of the semiconductor substrate 101 at the third position can be exposed by removing a portion of the interlayer insulating layer 134 at the third position.

[0096] Subsequently, after the first through hole 110H to the third through hole 130H are formed, the semiconductor device 100b in FIG. 6 can be manufactured by filling the first through hole 110H to the third through hole 130H.

[0097] FIG. 12 is a cross-sectional view showing a main configuration of a semiconductor package 600 according to an exemplary embodiment.

[0098] Referring to FIG. 12, the semiconductor package 600 may include a plurality of semiconductor wafers 620 stacked in sequence on a package substrate 610. The control wafer 630 may be connected to the plurality of semiconductor wafers 620. The stacked structure of the plurality of semiconductor wafers 620 and the control wafer 630 may be sealed by an encapsulant 640 (such as a thermosetting resin) on the package substrate 610. In FIG. 12, a structure in which six semiconductor wafers 620 are vertically stacked is shown, but the number and stacking direction of the semiconductor wafers 620 are not limited to those illustrated. Optionally, the number of semiconductor wafers 620 may be determined to be more than six or less than six. The plurality of semiconductor wafers 620 may be arranged on the package substrate 610 in a horizontal direction, or may be arranged in a connection structure in which a combination of vertical and horizontal mounting is provided. In some exemplary embodiments, the control wafer 630 may be omitted.

[0099] The package substrate 610 may include a flexible printed circuit board, a rigid printed circuit board, or a combination thereof. The package substrate 610 may include internal substrate wirings 612 and connection terminals 614. The connection terminals 614 may be formed on one surface of the package substrate 610. Solder balls 616 may be formed on the other surface of the package substrate 610. The connection terminals 614 may be electrically connected to the solder balls 616 via the internal substrate wirings 612. In some exemplary embodiments, the solder balls 616 may be replaced with conductive bumps or a lead grid array (LGA).

[0100] The semiconductor package 600 may include a via structure unit 622 and a via structure unit 632. The via structure unit 622 and the via structure unit 632 may be electrically connected to the connection terminals 614 of the package substrate 610 by connection components 650 such as bumps. In some exemplary embodiments, the via structure unit 632 may be omitted in the control wafer 630.

[0101] At least one of the plurality of semiconductor wafers 620 and the control wafer 630 may include at least one of the semiconductor devices 100 described above with reference to FIGS. 1 to 11D.

[0102] Each of the multiple semiconductor wafers 620 may include a system LSI, flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), magnetic random access memory (magnetic random access memory; MRAM), or resistance random access memory (RRAM). The control chip 630 may include, for example, logic circuits such as serializer / deserializer (SER / DES) circuits.

[0103] Although the inventive concept has been specifically illustrated and described with reference to some exemplary embodiments thereof, it is to be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

[0104] 12: Memory semiconductor wafer 14: Cell region 16: Row decoder 18: Column decoder 20: Through-silicon via region 22: First TSV cell region 24: Second TSV cell region 26: Third TSV cell region 28: Fourth TSV cell region 30: Through-silicon via structure 100, 100a, 100b, 132: Semiconductor device 101: Semiconductor substrate 101B: Lower surface 110: First via structure 110H: First via hole 112: First via plug 112m: Plug material layer 114: First barrier layer 114m: Barrier material layer 116: First via insulating layer 116m: Via insulating material layer 120: Second via structure 120H: Second via hole 122: Second via plug 124: Second barrier layer 126: Second via insulating layer 130: Front-end line structure 130H: Third via hole 134: Interlayer insulating layer 142: Metal wiring layer 144: Contact plug 146: Multilayer wiring structure 148: Metal interlayer insulating layer 150: Upper insulating layer 150H: Hole 152: Bonding pad 154: Upper connection terminal 160: Lower insulating layer 172: Conductive layer 174, 614: Connection terminal 180: Third via structure 182: Third via plug 184: Third barrier layer 186: Third via insulating layer 200: Capping material layer 201: Capping pattern 600: Semiconductor package 610: Package substrate 612: Internal wiring of substrate 616: Solder ball 620: Semiconductor wafer 622, 632: Via structure unit 630: Control chip 640: Encapsulant 650: Connection component III-III': Line D1: First diameter D2: Second diameter D3: Third diameter E1: First barrier width E2: Second barrier width E3: Third barrier width H1, H1': First depth H2, H2': Second depth H3': Third depth Ha, Hb, Hc: Distance PRCS1: First primary groove PRCS2: Second primary groove PRCS3: Third primary groove PRCS4: Fourth primary groove PRCS5: Fifth primary groove PRCS6: Sixth primary groove S110, S120, S121, S123, S125, S130, S131, S135, S140, S150: Operations SB: First scattering bar SB1: First scattering bar SB2: Second scattering bar SC: Sector SR: Reticle UC: Undercut region UC1: First upper undercut region UC2: First lower undercut region UC3: Second undercut region W1: First width W2: Second width Z: Direction

Claims

1. A method for manufacturing a semiconductor device, the method comprising: An interlayer insulating layer is formed on a semiconductor substrate; A cover material layer is formed on the interlayer insulation layer; A portion of the masking material layer on the upper surface of the interlayer insulating layer is removed at each of a first location for forming a first via structure with a first diameter and a second location for forming a second via structure with a second diameter; at the first location, both the interlayer insulating layer and a portion of the semiconductor substrate are removed to form a first primary groove; at the second location, at least a portion of the interlayer insulating layer is removed to form a second primary groove; portions of the semiconductor substrate are simultaneously etched at the locations of the first and second primary grooves to form a first via and a second via; the first via structure and the second via structure are formed in the first via and the second via, respectively; and external connection terminals electrically connected to the first via structure and the second via structure are formed, wherein the depth of the first primary groove is greater than the depth of the second primary groove to compensate for the difference in etching rate during the simultaneous etching of portions of the semiconductor substrate caused by the diameter difference between the first and second primary grooves. The diameter of the first primary groove is smaller than the diameter of the second primary groove, and removing the portion of the masking material layer at the second position includes exposing the masking material layer by using a photomask containing scattering strips disposed on the upper surface of the masking material layer at the second position, wherein during the removal of the portion of the masking material layer on the upper surface of the interlayer insulating layer, when at least the upper surface of the interlayer insulating layer is exposed, the thickness of the masking material layer at the first position is different from the thickness of the masking material layer at the second position.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the outer wall of the second via structure contacts the semiconductor substrate or the interlayer insulating layer at a vertical level above the lower surface of the first primary recess.

3. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the lower surface of the first primary recess is located at a vertical level below the upper surface of the semiconductor substrate, and the lower surface of the second primary recess is located on the same plane as the upper surface of the semiconductor substrate, or at a vertical level below the upper surface of the semiconductor substrate.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the sidewall of the first via structure includes at least one undercut region projecting horizontally toward the center of the first via structure, and at least one location of the undercut region is at the same location as the lower surface of the first primary recess.

Images