Multiplication-accumulation circuit used in a node of artificial neural network

Abstract

This invention proposes a multiply-accumulate circuit, including a switched capacitor module, a buffer, and a voltage-delay converter. The switched capacitor is controlled by an input signal to receive a ramp signal to generate a voltage signal. The buffer is configured to receive the voltage signal to generate a buffered signal. The voltage-delay converter is configured to convert the buffered signal into an output delayed signal with delay time information.

Description

Multiplication and Accumulation Circuit for Artificial Neural Network Nodes The present invention relates to the field of circuit technology, and particularly relates to a multiplication and accumulation circuit. An artificial neural network consists of multiple processing units called nodes, which are organized into layers and interconnected by weights. Each node receives input signals and processes the input signals using weights to generate output signals to the next node. Traditional neural network circuits may require a large number of fast Fourier transform (FFT) operations. However, FFT operations are not energy-efficient, and neural network circuits using FFT operations require analog-to-digital converters (ADCs) and some digital memories for node processing. In addition, the processing of nodes in traditional neural network circuits may be affected by inaccurate settling and interference problems, which will affect their accuracy. Therefore, the object of the present invention is to provide an analog multiplication and accumulation circuit to implement the nodes of a neural network circuit to solve the above problems. According to an embodiment of the present invention, a multiplication and accumulation circuit including a switched-capacitor module, a buffer, and a voltage-to-delay converter is disclosed. The switched-capacitor module is controlled by an input signal to receive a ramp signal to generate a voltage signal. The buffer is configured to receive the voltage signal to generate a buffered signal. The voltage-to-delay converter is configured to convert the buffered signal into an output delay signal with delay time information. After reading the following detailed description of the preferred embodiments shown in various figures, these and other objects of the present invention will undoubtedly become apparent to those of ordinary skill in the art. In the following description and claims, certain terms are used to refer to specific system components. As those of ordinary skill in the art will recognize, manufacturers may use different names to refer to components. This application does not intend to distinguish components with different names but the same function. In the following discussion and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". The term "coupled" is intended to mean an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, the coupling may be a direct electrical connection or an indirect electrical connection through other devices and connections. FIG. 1 is an artificial neural network according to an embodiment of the present invention. As shown in FIG. 1, the artificial neural network includes three types of layers, such as an input layer, one or more hidden layers, and an output layer. The input layer is configured to receive input signals and pass them to one or more hidden layers. The hidden layer is configured to process the signals from the input layer to generate processed signals. Regarding each node of the hidden layer, the node can perform a weighted average or other weighted calculations on the received signals to generate a processed signal. For example, if the node receives three signals x1, x2, and x3, and the three signals x1, x2, and x3 have weights W1, W2, and W3 respectively, the formula can be used for calculation to obtain the processed signal. The output layer is configured to receive the processed signals from the hidden layer to generate a final result. In this embodiment, the artificial neural network shown in FIG. 1 can be applied to any deep learning or recognition system, such as a speech recognition system. As described in the prior art of the present invention, traditional neural network circuits have ADCs and some digital memories for node processing, and the node processing may be affected by inaccurate convergence and interference problems. To solve these problems, the present invention designs an analog multiplication accumulation circuit to implement the nodes of the artificial neural network. This circuit has better accuracy and lower manufacturing cost, and can suppress the problems of inaccurate convergence and interference. It should be noted that the architectures and operations of the input layer, one or more hidden layers, and the output layer are known to those of ordinary skill in the art. The present invention focuses on the analog circuit design of the hidden layer nodes. Therefore, the following content only describes the circuit design of the nodes. FIG. 2 is a schematic diagram of a multiplication accumulation circuit 200 according to an embodiment of the present invention, where the multiplication accumulation circuit 200 is configured to receive one or more input signals from a previous node to generate an output signal to the next node. As shown in FIG. 2, the multiplication accumulation circuit 200 includes a switched-capacitor module, a buffer 210, and a voltage-to-delay converter 220. The switched-capacitor module includes a plurality of switches SW1–SWN and a plurality of capacitors C1 –CN. The switches SW1–SWN are respectively coupled to the lower plates of the capacitors C1–CN, and the switches SW1–SWN are used to selectively connect the ramp signal Vramp to the lower plates of the capacitors C1–CN. The upper plates of the capacitors C1–CN are coupled together. The buffer 210 is configured to receive the signal (voltage signal) at the upper plates of the capacitors C1–CN to generate a buffered signal, and the voltage-to-delay converter 220 converts the buffered signal into an output delay signal with delay time information to the next node. The switches SW1–SWN are controlled by one or more input signals x(t) and corresponding weights. In one embodiment, the weight corresponding to each input signal x(t) has one or more bits, and each bit of the weight is used together with the input signal x(t) to control a switch. For example, the weight corresponding to the input signal x(t) has four bits W[1], W[2], W[3], and W[4], and the switches SW1–SW4 are controlled by W[1], W[2], W[3], and W[4] together with the input signal x(t), respectively. That is, if the input signal x(t) has an enabling state and W[1] is equal to "1", the switch SW1 is enabled to connect the ramp signal Vramp to the capacitor C1; if the input signal x(t) has an enabling state and W[2] is equal to "1", the switch SW2 is enabled to connect the ramp signal Vramp to the capacitor C2; if the input signal x(t) has an enabling state and W[3] is equal to "1", the switch SW3 is enabled to connect the ramp signal Vramp to the capacitor C3; if the input signal x(t) has an enabling state and W[4] is equal to "1", the switch SW4 is enabled to connect the ramp signal Vramp to the capacitor C4. In addition, referring to FIG. 3, the input signal x(t) is a delayed signal with delay time information "t", where the input signal x(t) has a predetermined period "T", and T is the period during which the ramp signal Vramp has a ramp. In this embodiment, without limiting the present invention, a low voltage level of the input signal x(t) means that the input signal x(t) has an enabling state. In the operation of the multiply-accumulate circuit 200, referring to FIGS. 2 and 3 together, initially the multiply-accumulate circuit 200 operates in a first stage, and the input and output terminals of the buffer 210 are reset to have a reset voltage, such as 0V. In a second stage immediately following the first stage, the ramp signal Vramp starts to gradually increase its voltage level, and bit-wise multiplication is performed, that is, the switches SW1–SWN are controlled by the input signal and the corresponding weights to selectively connect the ramp signal Vramp. For example, if the input signal x(t) has an enabling state (e.g., a low voltage level) and W[1] is equal to "1", the switch SW1 is enabled to connect the ramp signal Vramp to the capacitor C1, and the voltage level at the lower plate of the capacitor C1 is gradually increased until the input signal x(t) no longer has an enabling state (e.g., the input signal x(t) is at a high voltage level). Referring to FIG. 3, the input signal x(t) has delay time information "t". When the input signal x(t) changes from a low voltage level to a high voltage level, the switch SW1 is disabled, and the lower plate of the capacitor C1 will maintain the previous voltage level ("Vx", which can be the Vramp voltage corresponding to the rising edge of x(t) in FIG. 3). In the third stage immediately following the second stage, the ramp signal Vramp returns to its original voltage level (e.g., 0V), and charge accumulation occurs at the upper plates of capacitors C1 – CN. For example, the charge accumulation at the upper plates of capacitors C1 – CN is similar to , where “x” is equal to “t / T”. Then, the buffer 210 receives the signal at the upper plates of capacitors C1–CN to generate a buffered signal, and the voltage-to-delay converter 220 converts the buffered signal into an output delayed signal y(t) with delay time information t’ and provides it to the next node, where the output delayed signal y(t) has a predetermined period “T”. In one embodiment, the voltage-to-delay converter 220 includes a rectified linear unit (ReLU) to convert the buffered signal into the output delayed signal. FIG. 4 is a schematic diagram of a multiply-accumulate circuit 400 according to an embodiment of the present invention, where the multiply-accumulate circuit 400 is configured to receive one or more input signals from a previous node to generate an output signal to a next node. As shown in FIG. 4, the multiply-accumulate circuit 400 includes a switched-capacitor module, a buffer 410, and a voltage-to-delay converter 420. The switched-capacitor module includes a plurality of switches and a plurality of capacitors with capacitances of 8C, 4C, 2C, and 1C respectively. In this embodiment, the switches corresponding to the capacitors with capacitances of 4C, 2C, or 1C include transistor M1 and transistor M2, where transistor M1 is controlled by a function of the input signal x(t) and the corresponding weight W[2:0], and transistor M2 is controlled by the corresponding weight. For each switch, transistor M1 is used to selectively connect the ramp signal Vramp to the lower plate of the capacitor, and transistor M2 is used to selectively connect the reference voltage Vref (e.g., 0V) to the lower plate of the capacitor. In addition, the switch corresponding to the capacitor with a capacitance of 8C includes transistor M3 and transistor M4, where transistor M3 is controlled by a function of the input signal x(t) and the corresponding weight W[3], and transistor M4 is controlled by the inverted signal of the reset signal RST. For the switch corresponding to the capacitor with a capacitance of 8C, transistor M3 is used to selectively connect the ramp signal Vramp to the upper plate of the capacitor, and the lower plate of the capacitor is coupled to the reference voltage Vref. The buffer 410 includes an amplifier 412, a capacitor C_amp, and two switches (the transistors M5 and M6 serve as these two switches). The positive input terminal of the amplifier 412 is connected to the reference voltage Vref. The capacitor C_amp is coupled between the negative input terminal and the output terminal of the amplifier 412. According to the reset signal RST, the transistor M5 is selectively connected to connect the negative input terminal to the output terminal of the amplifier 412. In addition, the transistor M6 is controlled by the inverted signal of the reset signal RST, and the transistor M6 is configured to selectively connect the output terminal of the amplifier 412 to the voltage-to-delay converter 420. The voltage-to-delay converter 420 includes a capacitor C_hold and a comparator 422. The comparator 422 receives the ramp signal Vramp' via the capacitor C_hold, and the comparator 422 compares the combined signal generated by combining the ramp signal Vramp' with the buffered signal generated by the amplifier 412 with the reference voltage Vref to generate an output delay signal with delay time information and provides it to the next node. In the operation of the multiply-accumulate circuit 400, referring to FIGS. 4 and 3, initially the multiply-accumulate circuit 400 operates in the first stage, and the reset signal RST is enabled (e.g., RST = 1), such that the transistor M5 is configured to connect the negative input terminal to the output terminal of the amplifier 412, such that the voltage levels at the negative input terminal and the output terminal of the amplifier 412 are equal to the reference voltage. At the same time, the reference voltage Vref is connected to the transistor M2 and the capacitor with a capacitance of 8C. In addition, the transistor M6 is disabled, such that the output terminal of the amplifier 412 is disconnected from the voltage-to-delay converter 420. In the second stage immediately following the first stage, the switched-capacitor module is disconnected from the reference voltage Vref, the ramp signal Vramp starts to gradually increase its voltage level, and bit-by-bit multiplication is performed, that is, the switches are controlled by the input signal and the corresponding weights to selectively connect the ramp signal Vramp. At this time, the reset signal RST is also enabled, so that the transistor M5 is enabled, while the transistors M4 and M6 are disabled. For example, if the input signal x(t) has an enabled state (e.g., a low voltage level) and W[2:0] is equal to "1", then the transistor M1 is enabled to connect the ramp signal Vramp to the corresponding capacitor, and the voltage level at the lower plate of the corresponding capacitor is gradually increased until the input signal x(t) no longer has an enabled state (e.g., a high voltage level). Referring to Figure 3, the input signal x(t) has the delay time information "t". When the input signal x(t) enters the high voltage level from the low voltage level, the transistor M1 is disabled, and the lower plate of the corresponding capacitor will maintain the previous voltage level (i.e., "Vx"). In addition, the switch with transistors M3, M4 and the capacitor with a capacitance of 8C is used to provide negative charge, that is, if the input signal x(t) has an enabled state and W[3] is equal to "1", then the transistor M3 is enabled to connect the ramp signal Vramp to the upper plate of the corresponding capacitor (the capacitor with a capacitance of 8C). In the third stage immediately following the second stage, the ramp signal Vramp returns to its original voltage level (e.g., 0V), and charge accumulation occurs at the upper plates of the multiple capacitors. In the third stage, the reset signal RST is disabled (e.g., RST = 0), so that the transistor M5 is disabled, while the transistors M4 and M6 are enabled. At this time, the capacitor with a capacitance of 8C is coupled to the upper plates of the other capacitors with capacitances of 4C, 2C and 1C through the transistor M4, resulting in the upper plates of the capacitors (i.e., the negative input terminal of the amplifier 412) being a charge conservation point. In addition, since the lower plates of the multiple capacitors are reconnected to the reference voltage Vref, the charge C*x*W on the capacitors will be accumulated at the charge conservation point and reflected to the output terminal of the amplifier 412 through the buffer 410. For example, the charge accumulation at the upper plates of the capacitors C1–CN is similar to , where "x" is equal to "t / T". Then, the amplifier 412 receives the signal at the upper plate of the capacitor to generate a buffer signal, and the voltage-to-delay converter 420 converts the buffer signal into an output delay signal with delay time information and provides it to the next node. In this embodiment, the buffer signal generated by the amplifier 412 is combined with the ramp signal Vramp' to generate a combined signal, and the comparator 422 compares the combined signal with the reference voltage Vref to generate an output delay signal. In one embodiment, since the buffer signal generated by amplifier 412 may have a gain loss due to the normalization of charge conservation (i.e., the voltage generated by charge accumulation is less than the ideal voltage), the slope of the ramp signal Vramp' received by voltage-to-delay converter 420 is less than the slope of the ramp signal Vramp received by the switched-capacitor module. For example, the slope of the ramp signal Vramp' can be half or a quarter of the slope of the ramp signal Vramp. By using the ramp signal Vramp' with a smaller slope, the delay time of the output delay signal will be increased to compensate for the aforementioned gain loss. Brief summary, in the multiply-accumulate circuit of the present invention, the input signal is a delay signal, and the multiply-accumulate circuit uses a switched-capacitor module and a ramp signal to convert the input signal into an output delay signal and provide it to the next node of the artificial neural network. Therefore, the multiply-accumulate circuit can have better accuracy and lower manufacturing cost, and can suppress stability and interference problems. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention. 210: Buffer 220: Voltage-to-delay converter 200: Multiply-accumulate circuit 410: Buffer 420: Voltage-to-delay converter 400: Multiply-accumulate circuit FIG. 1 is an artificial neural network according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a multiply-accumulate circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a ramp signal, an input signal, and an output delay signal according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a multiply-accumulate circuit according to an embodiment of the present invention. 210: Buffer 220: Voltage-to-delay converter 200: Multiply-accumulate circuit

Claims

1. A multiply-accumulate circuit, comprising: A switched capacitor module, wherein the switched capacitor module is controlled by an input signal to receive a ramp signal to generate a voltage signal; A buffer is configured to receive the voltage signal to generate a buffered signal; And a voltage-to-delay converter, configured to convert the buffered signal into an output delayed signal with delay time information.

2. The multiply-accumulate circuit as described in claim 1, wherein, The switched capacitor module includes a plurality of switches and a plurality of capacitors; and for at least a portion of the plurality of switches, each switch is configured to selectively connect the ramp signal to the lower plate of the corresponding capacitor according to the input signal.

3. The multiply-accumulate circuit as described in claim 2, wherein, The input signal is a delayed signal, and each switch is configured to selectively connect the ramp signal to the lower plate of the corresponding capacitor according to the input signal and the corresponding weight.

4. The multiply-accumulate circuit as described in claim 2, wherein, The buffer includes: an amplifier configured to receive the voltage signal and a reference voltage to generate the buffer signal; a first capacitor coupled between the input and output of the amplifier; and a first switch coupled between the input and output of the amplifier.

5. The multiply-accumulate circuit as claimed in claim 4, wherein when the multiply-accumulate circuit operates in a first stage, the first switch is enabled such that the voltage levels at the input and output of the amplifier are equal to a reference voltage; when the multiply-accumulate circuit operates in a second stage immediately following the first stage, the first switch is disabled, and each switch is configured to selectively connect the ramp signal to the lower plate of a corresponding capacitor according to the input signal; when the multiply-accumulate circuit operates in a third stage immediately following the second stage, charge accumulation occurs at the upper plates of the plurality of capacitors to generate a voltage signal for a buffer to generate the buffered signal, and the voltage-to-delay converter converts the buffered signal into the output delayed signal having delay time information.

6. The multiply-accumulate circuit as described in claim 1, wherein, The ramp signal received by the switched capacitor module is a first ramp signal; and the voltage-to-delay converter converts the buffer signal into the output delay signal with delay time information according to the second ramp signal.

7. The multiply-accumulate circuit as described in claim 6, wherein, The second ramp signal is different from the first ramp signal.

8. The multiply-accumulate circuit as described in claim 7, wherein, The slope of the second ramp signal is less than the slope of the first ramp signal.

9. The multiply-accumulate circuit as described in claim 6, wherein, The voltage-to-delay converter includes a comparator that compares a combined signal with a reference voltage to generate the output delayed signal, and the combined signal is generated by the second ramp signal and the buffer signal.

10. The multiply-accumulate circuit as described in claim 1, wherein, The multiply-accumulate circuit is used as a node in an artificial neural network.

Images