Semiconductor device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device includes forming a shielding region, a well region, and a source region in a drift layer, wherein the source region is on the well region, the top of the shielding region is lower than the bottom of the well region, and at least a portion of the shielding region does not overlap with the well region; forming a trench in the drift layer that exposes the shielding region; forming a gate dielectric layer on the sidewalls and bottom of the trench, wherein the thickness of the gate dielectric layer along the source region is greater than the thickness of the gate dielectric layer along the well region; and forming a gate in the trench.

Description

[Technical Field]

[0001] This disclosure and some embodiments relate to a semiconductor device and a method of manufacturing the same. [Previous Technology]

[0002] To increase the channel density of metal oxide semiconductor field effect transistors (MOSFETs), MOSFETs can have gate trench structures and vertical channels, and reduce the on-resistance of MOSFETs. However, many problems remain to be solved when manufacturing MOSFETs with gate trench structures. [Summary of the Invention]

[0003] This disclosure provides a method for manufacturing a semiconductor device, comprising forming a shielding region, a well region, and a source region in a drift layer, wherein the source region is on the well region, the top of the shielding region is lower than the bottom of the well region, and at least a portion of the shielding region does not overlap with the well region, forming a trench in the drift layer, the trench exposing the shielding region, forming a gate dielectric layer on the sidewalls and bottom of the trench, wherein the thickness of the gate dielectric layer along the source region is greater than the thickness of the gate dielectric layer along the well region, and forming a gate in the trench.

[0004] In some embodiments, prior to forming the gate dielectric layer, the method further includes performing a thermal oxidation process on the sidewalls and bottom of the trench to form a thermal oxide layer on the sidewalls and bottom of the trench, wherein the thickness of the thermal oxide layer along the source region is greater than the thickness of the thermal oxide layer along the well region, and removing the thermal oxide layer.

[0005] In some embodiments, the thickness of the thermal oxide layer along the shielding area is greater than the thickness of the thermal oxide layer along the well area.

[0006] In some embodiments, after the thermal oxide layer is removed, the top of the trench is wider than the bottom of the trench.

[0007] In some embodiments, a portion of the gate dielectric layer is formed by performing a thermal oxidation process, and the rate at which the top of the source region is oxidized in the thermal oxidation process is lower than the rate at which the sidewalls of the source region are oxidized.

[0008] Some embodiments of this disclosure provide a semiconductor device comprising a drift layer, a gate, a gate dielectric layer, a shielding region, a well region, and a source region. The gate is on the drift layer. The gate dielectric layer extends along the sidewalls and bottom of the gate. The shielding region is at the bottom of the gate dielectric layer. The well region is on one side of the gate dielectric layer. The source region is on this side of the gate dielectric layer and on the well region, wherein the thickness of the gate dielectric layer along the source region is greater than the thickness of the gate dielectric layer along the well region.

[0009] In some embodiments, the thickness of the gate dielectric layer along the shielded area is greater than the thickness of the gate dielectric layer along the well area.

[0010] In some embodiments, the doping concentration in the shielded area is higher than that in the well area.

[0011] In some embodiments, the top of the gate is wider than the bottom of the gate.

[0012] In some embodiments, the gate dielectric layer contacts the drift layer, and the thickness of the gate dielectric layer along the source region is greater than the thickness of the gate dielectric layer along the drift layer.

Implementation Method

[0014] Figures 1 through 6 illustrate cross-sectional views of the fabrication process of a semiconductor device according to some embodiments of the present disclosure. Referring to Figure 1, a shielding region 102, a well region 104, a source region 106, and a body contact region 108 are formed in a drift layer 100, wherein the source region 106 and the body contact region 108 are on the well region 104, the top of the shielding region 102 is lower than the bottom of the well region 104, and at least a portion of the shielding region 102 does not overlap with the well region 104. In some embodiments, the drift layer 100, the shielding region 102, the well region 104, the source region 106, and the body contact region 108 are made of silicon. The drift layer 100 and the source region 106 have a first conductor type, and the shielding region 102, the well region 104, and the body contact region 108 have a second conductor type, and the first conductor type is different from the second conductor type. The doping concentration of the source region 106 is higher than the doping concentration of the drift layer 100. The doping concentration of the shielding region 102 and the body contact region 108 is higher than that of the well region 104. The doping concentration of the source region 106 is higher than that of the well region 104. In some embodiments, the first conductor type is N-type and the second conductor type is P-type. In some embodiments, the drift layer 100 may be formed on the substrate in advance, the conductor type of the substrate may be the same as that of the drift layer 100, and the doping concentration of the substrate may be higher than that of the drift layer 100.

[0015] The formation order of the shielding region 102, well region 104, source region 106, and body contact region 108 can be interchanged. For example, a shielding region 102 having a second conductor type can be formed first in a drift layer 100 having a first conductor type, with a distance between the top of the shielding region 102 and the top of the drift layer 100. Next, well regions 104 having the second conductor type are formed on both sides of the shielding region 102. The bottom of the well region 104 is higher than the top of the shielding region 102 and does not contact the shielding region 102. Next, a source region 106 having the first conductor type is formed on the upper part of the well region 104. Next, a body contact region 108 having the second conductor type is formed on the upper part of the well region 104 and on one side of the source region 106. However, this disclosure is not limited to this formation order.

[0016] Referring to Figure 2, a trench T is formed in the drift layer 100, exposing the masking region 102. Specifically, a hard masking layer HM is first formed on the source region 106 and the body contact region 108, and the hard masking layer HM exposes the drift layer 100 on the masking region 102. Next, an etching process is performed to etch the drift layer 100 on the masking region 102 to form the trench T, and the bottom of the trench T exposes the masking region 102. After the trench T is formed, the sidewalls of the trench T also expose the source region 106, the well region 104, and the drift layer 100.

[0017] In this disclosure, the trench T is formed after the formation of the shielding region 102, which improves the doping concentration uniformity of the shielding region 102. Specifically, when the shielding region 102 is formed after the formation of the trench T, the ion implantation process used to form the shielding region 102 may easily damage the sidewalls of the trench T or affect the doping concentration on both sides of the trench T. Therefore, a protective layer is usually formed on the sidewalls of the trench T before the formation of the shielding region 102 to avoid the above situation. However, this protective layer easily increases the difficulty of the ion implantation process used to form the shielding region 102, resulting in lower doping concentration uniformity of the shielding region 102. When the shielding region 102 is formed before the formation of the trench T, the problem of lower doping concentration uniformity of the shielding region 102 due to the presence of the protective layer can be avoided.

[0018] Referring to Figure 3, after forming the trench T, the hard masking layer HM can be removed. Then, a thermal oxidation process is performed on the sidewalls and bottom of the trench T to form a thermal oxide layer 110 on the sidewalls and bottom of the trench T. The thickness of the thermal oxide layer 110 along the source region 106 is greater than the thickness of the thermal oxide layer 110 along the well region 104. Specifically, the thermal oxidation process in Figure 3 can be used to smooth the roughened surface of the trench T caused by the etching process in Figure 2. The thermal oxidation process has a higher oxidation rate for regions with higher doping concentrations, and the doping concentration of the source region 106 and the masking region 102 is higher than the doping concentration of the well region 104. Therefore, the thickness of the thermal oxide layer 110 along the source region 106 is greater than the thickness of the thermal oxide layer 110 along the well region 104, and the thickness of the thermal oxide layer 110 along the masking region 102 is greater than the thickness of the thermal oxide layer 110 along the well region 104. Furthermore, since the oxidation rate at the top of the source region 106 during the thermal oxidation process is lower than the oxidation rate at the sidewalls of the source region 106, the thermal oxide layer 110 along the source region 106 has arc-shaped sidewalls. In some embodiments, the thermal oxide layer 110 is a silicon oxide layer. In this disclosure, since the shielding region 102 is formed before the trench T is formed, the ion implantation process of the shielding region 102 is less likely to affect the doping concentration on both sides of the trench T. That is, the doping concentration of the source region 106 and the well region 104 on both sides of the trench T is not affected, so that during the thermal oxidation process, the thickness of the thermal oxide layer 110 along the source region 106 can be ensured to be greater than the thickness of the thermal oxide layer 110 along the well region 104. In some embodiments, the thermal oxide layer 110 is in closer contact with the drift layer 100, and because the doping concentration of the source region 106 is higher than that of the drift layer 100, the thickness of the thermal oxide layer 110 along the shielding region 102 is greater than that along the drift layer 100.

[0019] Referring to Figure 4, the thermal oxide layer 110 is removed, thereby smoothing the roughened surface of the trench T. Specifically, a wet etching process can be performed to remove the thermal oxide layer 110 from the surface of the trench T, leaving the drift layer 100, the masking region 102, the well region 104, and the source region 106 un-thermally oxidized portions. At this time, the top of the trench T is wider than the bottom of the trench T, and the trench T surrounded by the source region 106 is wider than the trench T surrounded by the well region 104. In other words, the bottom of the source region 106 is wider than the top of the source region 106. Furthermore, the trench T has arc-shaped sidewalls in the source region 106.

[0020] Referring to Figure 5, a dielectric layer 122 is formed on the sidewalls and bottom of the trench T, wherein the thickness of the dielectric layer 122 along the source region 106 is greater than the thickness of the dielectric layer 122 along the well region 104. Specifically, the dielectric layer 122 is formed by performing a thermal oxidation process, which has a higher oxidation rate for regions with higher doping concentrations, and the doping concentrations of the source region 106 and the shielding region 102 are higher than the doping concentration of the well region 104. Therefore, the thickness of the dielectric layer 122 along the source region 106 is greater than the thickness of the dielectric layer 122 along the well region 104, and the thickness of the dielectric layer 122 along the shielding region 102 is greater than the thickness of the dielectric layer 122 along the well region 104. Furthermore, since the rate of oxidation of the top of the source region 106 in the thermal oxidation process is lower than the rate of oxidation of the sidewalls of the source region 106, the dielectric layer 122 along the source region 106 has arc-shaped sidewalls. In some embodiments, dielectric layer 122 is a silicon oxide layer.

[0021] Referring to Figure 6, a dielectric layer 124 is formed in the trench T. The dielectric layer 124 is conformally oriented to the contour of the trench T, and therefore has a substantially uniform thickness. The thickness of the dielectric layer 124 is greater than the thickness of the dielectric layer 122, and after the dielectric layer 124 is formed, the top of the trench T is still wider than the bottom of the trench T. In some embodiments, the dielectric layer 124 is a silicon oxide layer. In this disclosure, the dielectric layer 122 and the dielectric layer 124 are collectively referred to as the gate dielectric layer 125. Since the thickness of the dielectric layer 122 along the source region 106 is greater than the thickness of the dielectric layer 122 along the well region 104, the thickness of the dielectric layer 122 along the shielding region 102 is greater than the thickness of the dielectric layer 122 along the well region 104, and the dielectric layer 124 has a substantially uniform thickness, the thickness of the gate dielectric layer 125 along the source region 106 is greater than the thickness of the gate dielectric layer 125 along the well region 104, and the thickness of the gate dielectric layer 125 along the shielding region 102 is greater than the thickness of the gate dielectric layer 125 along the well region 104.

[0022] Next, a gate 126 is formed in the trench T. Specifically, a conductive material can be filled into the trench T, and excess conductive material (e.g., conductive material on the source region 106 and the body contact region 108) can be removed using a planarization process to form the gate 126 in the trench T. Since the top of the trench T is wider than the bottom of the trench T, it is less likely to form pores when filling the conductive material, and the formed gate 126 is also wider than the bottom of the gate 126. The formed gate 126 can also have fewer pores. In some embodiments, the gate 126 can be made of polysilicon, metal, or a combination thereof. Since the bottom of the gate 126 is usually accompanied by a strong electric field, the shielding region 102 and the thicker gate dielectric layer 125 at the bottom of the gate 126 can be used to shield the strong electric field and prevent leakage.

[0023] After forming the gate 126, a dielectric layer 130 may be formed on the gate 126, a source electrode 140 may be formed on the source region 106 and the body contact region 108, and a drain electrode 150 may be formed under the drift layer 100. The resulting semiconductor device is shown in Figure 6. The semiconductor device includes a drift layer 100, a gate 126, a gate dielectric layer 125, a well region 104, a source region 106, a body contact region 108, a shielding region 102, a dielectric layer 130, a source electrode 140, and a drain electrode 150. The gate 126 is on the drift layer 100. The gate dielectric layer 125 extends along the sidewalls and bottom of the gate 126. The gate dielectric layer 125 contacts the source region 106 and the well region 104. The well region 104 is on one side of the gate dielectric layer 125. Source region 106 is located on this side of gate dielectric layer 125 and on well region 104, and shielding region 102 is located at the bottom of gate dielectric layer 125. Body contact region 108 is located on well region 104 and adjacent to source region 106, and source region 106 is located between body contact region 108 and gate dielectric layer 125. Dielectric layer 130 is located on gate 126 and source region 106. Source electrode 140 is located on dielectric layer 130, source region 106, and body contact region 108. Drain electrode 150 is located below drift layer 100.

[0024] The thickness of the gate dielectric layer 125 is related to the doping concentration of the region in contact with the gate dielectric layer 125. The higher the doping concentration of the region in contact, the greater the thickness of the gate dielectric layer 125. Since the doping concentration of the source region 106 is higher than that of the well region 104, and the doping concentration of the shielding region 102 is higher than that of the well region 104, the thickness of the gate dielectric layer 125 along the source region 106 is greater than that along the well region 104, and the thickness of the gate dielectric layer 125 along the shielding region 102 is greater than that along the well region 104. In some embodiments, the gate dielectric layer 125 is in closer contact with the drift layer 100, and the doping concentration of the source region 106 is higher than that of the drift layer 100. Therefore, the thickness of the gate dielectric layer 125 along the source region 106 is greater than the thickness of the gate dielectric layer 125 along the drift layer 100.

[0025] In summary, some embodiments disclosed herein can be used to improve the fabrication process of semiconductor devices with gate trench structures. For example, in this disclosure, the various doped regions of the semiconductor device can be formed first, and then the trench can be formed, thereby avoiding the complexity of ion implantation processes in the trench structure and ensuring that the doping concentration of each doped region is not easily affected. In this case, when the trench is thermally oxidized to smooth the surface of the trench, the top of the trench can become wider than the bottom of the trench. When the gate material is filled into the trench, the formed gate can also have fewer pores.

[0026] The above description is only a part of the embodiments disclosed herein, and not all of the embodiments. Any equivalent changes made by those skilled in the art to the technical solutions disclosed herein by reading the specification thereof shall be covered by the claims of this disclosure. [Simplified Explanation of the Diagram]

[0013] Figures 1 to 6 illustrate cross-sectional views of a semiconductor device formed in some embodiments of this disclosure. [Biomaterial Storage]

[0028] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a shielding region, a well region, and a source region in a drift layer, wherein the source region is on the well region, the top of the shielding region is lower than the bottom of the well region, and at least a portion of the shielding region does not overlap with the well region; after forming the shielding region, the well region, and the source region in the drift layer, forming a trench in the drift layer, the trench exposing the shielding region; performing a thermal oxidation process on a sidewall and a bottom of the trench to form a thermal oxide layer on the sidewall and the bottom of the trench, wherein a thickness of the thermal oxide layer along the source region is greater than a thickness of the thermal oxide layer along the well region; removing the thermal oxide layer; forming a gate dielectric layer on the sidewall and the bottom of the trench, wherein a thickness of the gate dielectric layer along the source region is greater than a thickness of the gate dielectric layer along the well region; and forming a gate in the trench.

2. The method as described in claim 1, wherein the thickness of the thermal oxide layer along the shielded area is greater than the thickness of the thermal oxide layer along the well area.

3. The method as described in claim 1, wherein after the thermal oxide layer is removed, a top of the trench is wider than the bottom of the trench.

4. The method as claimed in claim 1, wherein a portion of the gate dielectric layer is formed by performing the thermal oxidation process, and the rate at which the thermal oxidation process oxidizes a top of the source region is lower than the rate at which it oxidizes a sidewall of the source region.

5. A semiconductor device comprising: a drift layer; a gate on the drift layer; a gate dielectric layer along a sidewall and a bottom of the gate; a shielding region at the bottom of the gate dielectric layer and in contact with the bottom of the gate dielectric layer; a well region on a side of the gate dielectric layer, wherein a thickness of the gate dielectric layer along the shielding region is greater than the thickness of the gate dielectric layer along the well region; and a source region on the side of the gate dielectric layer and the well region, wherein a thickness of the gate dielectric layer along the source region is greater than the thickness of the gate dielectric layer along the well region, and the gate dielectric layer along the source region has an arcuate sidewall.

6. The semiconductor device as claimed in claim 5, wherein the doping concentration of the shielded region is higher than the doping concentration of the well region.

7. The semiconductor device as claimed in claim 5, wherein a top of the gate is wider than a bottom of the gate.

8. The semiconductor device as claimed in claim 5, wherein the gate dielectric layer contacts the drift layer, and the thickness of the gate dielectric layer along the source region is greater than the thickness of the gate dielectric layer along the drift layer.

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