Integrated circuit (IC) devICe, IC layout, and method of generating IC layout

Abstract

An integrated circuit device includes a plurality of columns made of semiconductor devices. The columns extend along a first axis and are arranged side-by-side along a second axis spanning the first axis. Each column includes: a first column having a first height along the second axis; and a second column having a second height along the second axis. The second height is less than the first height. Each of the columns includes: a first active region of a first conductivity type; and a second active region of a second conductivity type different from the first conductivity type. The second active region is spaced apart from the first active region along the second axis. Along the second axis, a first width of the first or second active region in the first column is greater than a second width of the first or second active region in the second column.

Description

Prior Art

[0001] An integrated circuit (IC) device includes one or more semiconductor devices represented in an IC layout (also referred to as an "IC design layout," "layout," "IC layout," or "layout"). The layout is hierarchical and includes modules that implement higher-level functions according to the semiconductor device's design specifications. A module is typically constructed from a combination of cells, each of which represents one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layouts (sometimes referred to as standard cells) are stored in a standard cell library (hereinafter referred to as a "library" or "cell library" for brevity) and can be accessed by various tools, such as electronic design automation (EDA) tools, to generate, optimize, and verify IC designs. Power, performance, and area (PPA) are design considerations for IC devices. Simple diagram description

[0002] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a block diagram of an IC device according to some embodiments. FIG. 1B is a perspective view of a portion of an IC device according to some embodiments. FIG. 1C is a cross-sectional view of the portion of the IC device shown in FIG. 1B , according to some embodiments. FIG. 2A is a schematic diagram of an IC layout of a circuit area of an IC device according to some embodiments. FIG. 2B is a simplified schematic diagram of the IC layout shown in FIG. 2A , according to some embodiments. FIG. 2C includes schematic diagrams of various cell column configurations in one or more IC layouts according to some embodiments. FIG. 3 includes a schematic diagram of various cells that may be placed in an IC layout according to some embodiments. FIG. 4A is a schematic diagram of an IC layout of a circuit area of an IC device according to some embodiments. 4B and 4C are diagrams illustrating various cell column configurations in one or more IC layouts according to some embodiments. FIG. 5A is a block diagram of an IC device according to some embodiments. 5B and 5C are schematic diagrams of IC layouts of various circuit regions of one or more IC devices according to some embodiments. FIG. 6 is a schematic diagram of an IC layout of a circuit area of an IC device according to some embodiments. 7A includes a schematic circuit diagram and a cross-sectional view of a circuit area of an IC device according to some embodiments. 7B and 7C are schematic diagrams of the IC layout at respective layers of the circuit area shown in FIG. 7A according to some embodiments. 7D includes a schematic circuit diagram and a cross-sectional view of a circuit area of an IC device according to some embodiments. 7E and 7F are schematic diagrams of the IC layout at various layers of the circuit area shown in FIG. 7D according to some embodiments. FIG. 8A is a schematic circuit diagram of a circuit area of an IC device according to some embodiments. FIG. 8B is a schematic diagram of an IC layout of the circuit area shown in FIG. 8A , according to some embodiments. 9A and 9B are schematic diagrams of IC layouts of various circuit regions of one or more IC devices according to some embodiments. FIG. 10 is a table illustrating routing characteristics of various cells that may be placed in an IC layout according to some embodiments. 11 and 12 are flowcharts of various methods according to some embodiments. FIG13 is a block diagram of an electronic design automation (EDA) system according to some embodiments. 14 is a block diagram of an IC device manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. Implementation Method

[0003] The following disclosure provides various embodiments or examples for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, or the like are contemplated. For example, the following description of a first feature being formed over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, thereby preventing the first and second features from being in direct contact. Furthermore, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of brevity and clarity and does not inherently indicate a relationship between the various embodiments and / or configurations discussed. Depending on the context, source / drain may refer to a source or drain individually or collectively.

[0004] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0005] In some embodiments, cells having different cell heights are read from one or more cell libraries and placed into an IC layout, for example, by an automated placement and routing (APR) tool or system. Cells having a cell height greater than the unit cell height of a unit cell are sometimes referred to as tall cells and are configured to improve (i.e., increase) performance or speed in one or more areas of an IC device fabricated according to the IC layout. Cells having a cell height less than the unit cell height are sometimes referred to as short cells and are configured to improve (i.e., reduce) power consumption and / or chip area (hereinafter referred to as "power and area") in one or more other areas of the fabricated IC device. In at least one embodiment, the IC layout further includes unit cells. In some embodiments, active regions of adjacent cells are merged to create a merged cell with improved performance or speed. In at least one embodiment, the active region width of one or more short cells, unit cells, and / or tall cells is reduced to improve power and area. Therefore, in one or more embodiments, the IC layout can be optimized and / or customized to improve speed in one or more areas while improving power and area in one or more other areas, depending on the purpose and / or application of the IC device fabricated based on the IC layout. This is an improvement over other approaches in which all cells in the IC layout have the same cell height. Other features and corresponding advantages according to various embodiments are also described herein.

[0006] FIG. 1A is a block diagram of an IC device 100A according to some embodiments.

[0007] In FIG1A , IC device 100A includes, among other components, macro 101. In some embodiments, macro 101 includes one or more of memory, a power grid, one or more cells, inverters, latches, buffers, and / or any other type of circuit arrangement that can be represented digitally in a cell library. In some embodiments, macro 101 is understood in the context of an architectural hierarchy analogous to modular programming, in which subroutines / procedures are called by a main program (or other subroutines) to perform a given computing function. In this context, IC device 100A uses macro 101 to implement one or more given functions. Thus, in this context and at the architectural level, IC device 100A is analogous to a main program, while macro 101 is analogous to a subroutine / procedure. In some embodiments, macro 101 is a soft macro. In some embodiments, macro 101 is a hard macro. In some embodiments, macro 101 is a soft macro described digitally using register-transfer level (RTL) code. In some embodiments, macro 101 has not yet been synthesized, placed, and routed, thereby allowing the soft macro to be synthesized, placed, and routed for various process nodes. In some embodiments, macro 101 is a hard macro described digitally using a binary file format (e.g., a Graphics Database System II (GDSII) stream format) that hierarchically represents the planar geometry of one or more layouts of macro 101, context labels, other information, and the like. In some embodiments, macro 101 has already been synthesized, placed, and routed, thereby making the hard macro specific to a particular process node.

[0008] Macro 101 includes region 103, which includes cells having different cell heights as described herein. In some embodiments, region 103 includes a substrate having circuitry formed thereon during front-end-of-line (FEOL) fabrication. Furthermore, above and / or below the substrate, region 103 includes various metal layers stacked above and / or below insulating layers during back-end-of-line (BEOL) fabrication. The BEOL provides routing for the circuitry of IC device 100A, which includes macro 101 and region 103.

[0009] 1B is a perspective view of a portion of an IC device 100B according to some embodiments. In at least one embodiment, IC device 100B corresponds to IC device 100A.

[0010] IC device 100B includes a substrate 110 with a plurality of semiconductor devices formed thereon. FIG. 1B shows two semiconductor devices 111 and 121 of IC device 100B. In the exemplary configuration of FIG. 1B , semiconductor devices 111 and 121 comprise nanosheet field-effect transistors (FETs), sometimes referred to as nanosheet devices. Nanosheet devices are examples of gate-all-around (GAA) devices. Other GAA configurations, such as nanowire FETs (sometimes referred to as nanowire devices), are also within the scope of various embodiments.

[0011] Substrate 110 includes a substrate portion 112 corresponding to semiconductor device 111, a substrate portion 122 corresponding to semiconductor device 121, and an isolation region 114 located between and around substrate portions 112 and 122. Substrate portions 112 and 122 extend or elongate along the X-axis. In some embodiments, substrate portions 112 and 122 are portions of the same wafer (not shown). During the fabrication of IC device 100B, the wafer is partially removed, leaving substrate portions 112 and 122. In some embodiments, the wafer is a doped (e.g., with P-type dopants or N-type dopants) or undoped semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Generally, an SOI substrate includes a semiconductor material layer formed on an insulator layer. Example materials for the insulator layer include, but are not limited to, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a silicon substrate, a glass substrate, a multilayer substrate, or a gradient substrate. In some embodiments, substrate portions 112 and 122 comprise semiconductor materials, including, but not limited to: elemental semiconductors, including silicon or germanium in crystalline, polycrystalline, or amorphous structures; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. An isolation region 114 is formed in a trench between substrate portions 112 and 122. Isolation region 114 has an upper surface flush with the upper surfaces of substrate portions 112 and 122. Example materials for isolation region 114 include, but are not limited to, insulating materials, such as dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like).

[0012] IC device 100B further includes gate electrodes 116, 118 and nanosheet stacks 124, 134. Gate electrode 116 and nanosheet stack 124 constitute semiconductor device 111. Gate electrode 116 and nanosheet stack 134 constitute semiconductor device 121. Gate electrodes 116, 118 are formed on substrate portions 112, 122 and isolation region 114. Gate electrodes 116, 118 extend along a Y-axis that transverses the X-axis. In at least one embodiment, the Y-axis is perpendicular to the X-axis. In some embodiments, gate electrodes 116, 118 include one or more layers formed of a conductive material, including but not limited to doped polysilicon, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, or the like. In some embodiments, the gate electrodes 116 and 118 further include other work function adjustment metals, diffusion barrier materials, glue layers, or similar materials.

[0013] Each of the nanosheet stacks 124 and 134 comprises a plurality of separate nanosheets stacked on the respective substrate portions 112 and 122 along the Z-axis, which is the thickness direction of the substrate 110. The nanosheet stacks 124 and 134 extend along the X-axis, while the substrate portions 112 and 122 extend along the X-axis. In other words, the nanosheet stacks 124 and 134 extend laterally relative to the gate electrodes 116 and 118. A portion of each nanosheet in the nanosheet stacks 124 and 134 is surrounded by at least one of the gate electrodes 116 and 118. In some embodiments, the nanosheets in the nanosheet stacks 124 and 134 are generally two-dimensional semiconductor slabs having a length (along the X-axis) or a width (along the Y-axis) greater than approximately 110 nanometers and a thickness (along the Z-axis) less than approximately 20 nanometers. Other nanosheet or nanowire configurations are also within the scope of various embodiments. 1B , each of the nanosheet stacks 124, 134 includes four nanosheets. Other numbers of nanosheets in a nanosheet stack are also within the scope of various embodiments.

[0014] In some embodiments, nanosheet stacks 124, 134 and base portions 112, 122 are formed from the same wafer by performing photolithography and etching operations on the wafer. In at least one embodiment, nanosheet stack 124 or nanosheet stack 134 is doped with N-type impurities (e.g., arsenic, phosphorus, or similar impurities) to form an N-type nanosheet FET, or with P-type impurities (e.g., boron or similar impurities) to form a P-type nanosheet FET. For example, nanosheet stack 124 is configured as an N-type nanosheet, which configures semiconductor device 111 as an N-type semiconductor device (e.g., an N-type transistor), while nanosheet stack 134 is configured as a P-type nanosheet, which configures semiconductor device 121 as a P-type semiconductor device (e.g., a P-type transistor). N-type is an example of one of the first conductivity type and the second conductivity type, and P-type is an example of the other of the first conductivity type and the second conductivity type.

[0015] The stacked nanosheets of the same nanosheet stack 124 or 134 are configured to form a combined channel region and / or a combined source / drain region of a corresponding semiconductor device. For example, the portion of each nanosheet in nanosheet stack 124 that overlaps with gate electrode 116 is configured as the combined channel region of semiconductor device 111, while the remaining portion of each nanosheet in nanosheet stack 124 located on the opposite side of the channel region is configured as the source / drain region of semiconductor device 111. Similarly, the portion of each nanosheet in nanosheet stack 134 that overlaps with gate electrode 116 is configured as the combined channel region of semiconductor device 121, while the remaining portion of each nanosheet in nanosheet stack 134 located on the opposite side of the channel region is configured as the source / drain region of semiconductor device 121.

[0016] 1C is a cross-sectional view of the portion of the IC device 100B according to some embodiments. The cross-sectional view in FIG1C is taken along line CC that cuts through the gate electrode 116 in FIG1B .

[0017] As shown in FIG. 1C , the semiconductor devices 111 , 121 further include corresponding gate dielectric layers 126 , 136 located between the gate electrode 116 and each nanosheet of the corresponding nanosheet stack 124 , 134 . In some embodiments, the gate dielectric layers 126 and 136 include one or more dielectric materials, including but not limited to oxides, nitrides, oxynitrides, high-k dielectric materials, such as Al2O3, HfO2, ZrO2, HfOxNy, ZrOxNy, HfSixOy, ZrSixOy, HfSixOyNz, ZrSixOyNz, TiO2, Ta2O5, La2O3, CeO2, Bi4Si2O12, WO3, Y2O3, LaAlO3, Ba1-xSrxTiO3, PbTiO3, BaTiO3 (BTO), SrTiO3 (STO), BaSrTiO3 (BST), PbZrO 3. lead-strontium-titanate (PST), lead-zinc-niobate (PZN), lead-zirconate-titanate (PZT), lead-magnesium-niobium (PMN), yttria-stabilized zirconia (YSZ), ZnO / Ag / ZnO (ZAZ), combinations thereof, or similar materials. In some embodiments, IC device 100B further includes a work function regulating layer (not shown) between gate electrode 116 and each of gate dielectric layers 126 and 136. In the exemplary configuration of FIG1C , the nanosheets in each of nanosheet stacks 124 and 134 have substantially the same width w along the Y-axis. Other configurations are also within the scope of various embodiments.

[0018] FIG2A is a schematic diagram of an IC layout 200 of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A and 100B. In some embodiments, IC layout 200, as well as the IC layouts described herein for various embodiments, is generated by an EDA system (e.g., an APR system) and / or stored in a non-transitory computer-readable storage medium.

[0019] IC layout 200 includes a plurality of columns 210, 220, and 230 comprised of semiconductor devices. Columns 210, 220, and 230 extend along an X-axis and are arranged side-by-side along a Y-axis. The X-axis is an example of a first axis, and the Y-axis is an example of a second axis that transverses the first axis. In at least one embodiment, the semiconductor devices in columns 210, 220, and 230 correspond to semiconductor devices 111 and 121 and / or include GAA devices.

[0020] Each of rows 210, 220, and 230 has a pair of boundary lines spaced apart from each other along the Y-axis by a distance corresponding to the row's height. For example, row 210 has a pair of boundary lines 201 and 202 and a corresponding height HT between them, row 220 has a pair of boundary lines 202 and 203 and a corresponding height HS between them, and row 230 has a pair of boundary lines 203 and 204 and a corresponding height HS between them. Row 210 is an example of a first row, and HT is an example of a first height of the first row along the Y-axis. Row 220 is an example of a second row, and HS is an example of a second height of the second row along the Y-axis. As described herein, HS is less than HT to achieve one or more advantages in one or more embodiments. Row 230 is an example of a third row, and HS is an example of a third height of the third row along the Y-axis. In some embodiments, at least one of the boundary lines 201 - 204 corresponds to a centerline of a power rail, as described herein.

[0021] In the example configuration of FIG2A , rows 210 , 220 , and 230 touch each other and share a common boundary line. For example, rows 210 , 220 touch each other at common boundary line 202 and share common boundary line 202 , and rows 220 , 230 touch each other at common boundary line 203 and share common boundary line 203 . Other configurations are also within the scope of various embodiments. For example, in at least one embodiment (not shown), two adjacent rows do not share a common boundary line and are separated from each other along the Y-axis by an empty space that does not contain semiconductor devices. Such two rows are sometimes referred to as immediately adjacent non-touching rows. In some embodiments, two rows are considered adjacent to each other when they share a common boundary line (e.g., rows 210 , 220 ) or when they are immediately adjacent non-touching rows.

[0022] Each of the columns 210, 220, and 230 includes a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type, wherein the second active region is spaced apart from the first active region. For example, column 210 includes a first active region 251 including portions 231 and 237 having different active region widths as described herein, and a second active region 252 including portions 232 and 238 having different active region widths as described herein. One of the active regions 251 and 252 is an N-type active region, and the other of the active regions 251 and 252 is a P-type active region. For example, active region 251 is a P-type active region, and active region 252 is an N-type active region. In some embodiments, the N-type active region corresponds to the nanosheet stack 124, and the P-type active region corresponds to the nanosheet stack 134.

[0023] Active regions 251 and 252 of row 210 are spaced apart from each other along the Y-axis by at least spacing S. For example, portions 231 and 232 of active regions 251 and 252 are spaced apart from each other along the Y-axis by spacing S, while portions 237 and 238 of active regions 251 and 252 are spaced apart from each other along the Y-axis by a spacing greater than spacing S. In some embodiments, spacing S is a predetermined minimum active region spacing along the Y-axis between immediately adjacent active regions. Two active regions are directly adjacent when no other active regions exist between them. Spacing S is a design rule that must be met to ensure manufacturability and / or operability of an IC device corresponding to IC layout 200.

[0024] Each of the active regions 251 and 252 is arranged in a region of a corresponding conductivity type (e.g., a base region, a doped region, or a well region). For example, active region 251 is a P-type active region and is arranged in an N-type well region 221, and active region 252 is an N-type active region and is arranged in a P-type base region having portions 222 and 226. For simplicity, reference numeral 222 herein denotes the P-type base region containing active region 252. P-type base region 222 extends continuously across boundary line 202 into row 220. In some embodiments, N-type well region 221 extends continuously across boundary line 201 (upward in FIG. 2A ) into another row (not shown) of semiconductor devices.

[0025] Column 220 includes a first active region 254 including portions 234 and 240 and a second active region 253 including portions 233 and 239. The active regions 253 and 254 of column 220 are spaced at least a distance S from each other along the Y-axis. For example, portions 233 and 234 of active regions 253 and 254 are spaced a distance S from each other along the Y-axis, while portions 239 and 240 of active regions 253 and 254 are spaced a distance greater than the distance S from each other along the Y-axis. In the exemplary configuration of FIG. 2A , active region 253 is an N-type active region disposed within a P-type base region 222, and active region 254 is a P-type active region disposed within an N-type well region having portions 223 and 227. For simplicity, reference numeral 223 herein denotes the N-type well region containing active region 254. N-type well region 223 extends continuously across boundary line 203 into column 230.

[0026] Row 230 includes a first active region 255 including portions 235 and 241, and a second active region 256 including portions 236 and 242. Active regions 255 and 256 of row 230 are spaced apart from each other along the Y-axis by at least a spacing S. For example, portions 235 and 236 of active regions 255 and 256 are spaced apart from each other along the Y-axis by a spacing S, while portions 241 and 242 of active regions 255 and 256 are spaced apart from each other along the Y-axis by a spacing greater than spacing S. Portions 231 and 242 are sometimes referred to as active regions 231 and 242.

[0027] In the exemplary configuration of FIG2A , active region 255 is a P-type active region disposed in N-type well region 223, and active region 256 is an N-type active region disposed in a P-type body region having portions 224 and 228. For simplicity, reference numeral 224 herein denotes the P-type body region containing active region 256. In some embodiments, P-type body region 224 extends continuously across boundary line 204 (downward in FIG2A ) into another row (not shown) of semiconductor devices. Active region 240 and active region 241 are continuous with each other and merge into a merged active region (sometimes referred to as 240 / 241).

[0028] Active regions 231-242 are functional active regions that, along with functional gate regions as described herein, form a plurality of semiconductor devices in rows 210, 220, and 230. IC layout 200 further includes non-functional or dummy active regions 245, 246, and 247 that are not configured to form semiconductor devices, and / or one or more semiconductor devices formed by the dummy active regions are not electrically coupled to other circuitry in the IC device corresponding to IC layout 200. In some embodiments, the dummy active regions have the same configuration as the functional active regions and / or are fabricated using the same process as the functional active regions. In the exemplary configuration of FIG2A , dummy active region 245 is arranged in P-type base region 222 and is contiguous with active regions 233 and 239 ; dummy active region 246 is arranged in N-type well region 223 and is contiguous with active regions 234 , 235 , 240 , and 241 ; and dummy active region 247 is arranged in P-type base region 224 and is contiguous with active regions 236 and 242 . In some embodiments, the dummy active regions are configured to isolate and interface active regions with different active region widths in the same well region, base region, or doped region. For example, in the same N-type well region 223 , dummy active region 246 is configured to isolate and interface active regions 234 and 235 on one side with merged active regions 240 and 241 on the other side. In some embodiments, one or more of the dummy active regions are omitted.

[0029] IC layout 200 further includes gate regions 211 to 217 extending along the Y-axis across active regions 231 to 242. Each of gate regions 211 to 212 and gate regions 214 to 216 extends across all columns 210, 220, and 230. Gate region 213 extends across column 210 and is aligned along the Y-axis with gate region 217, which extends across columns 220 and 230. For simplicity, the widths of gate regions 211 to 217 are not shown in FIG. 2A. In the exemplary configuration of FIG. 2A, gate regions 212, 213, and 215 are functional gate regions that, together with active regions 231 to 242, form a plurality of semiconductor devices. For example, gate regions 212, 213 and active regions 231 and 232 form a number of semiconductor devices corresponding to the semiconductor devices described with respect to FIG. 1B to FIG. 1C. Gate regions 212 and 215, together with corresponding active regions 233 to 236 and 237 to 242, further constitute other semiconductor devices. IC layout 200 includes several cut-gate-region marks (sometimes referred to as "CPOs"), generally designated by reference numeral 250, to indicate locations where the gate region is divided into multiple segments. For example, gate region 212 is cut into three segments by four cut-gate-region marks 250. In at least one embodiment, the centerlines of the cut-gate-region marks 250 coincide with the boundary lines 201 to 204 that overlap with the cut-gate-region marks 250.

[0030] Gate regions 211, 214, and 217 are non-functional gate regions or dummy gate regions. The dummy gate regions are not configured to form a semiconductor device with the underlying active region, and / or the one or more semiconductor devices formed by the dummy gate regions and the underlying active region are not electrically coupled to other circuitry in an IC device corresponding to IC layout 200. In at least one embodiment, in the fabricated IC device, the non-functional gate regions or dummy gate regions comprise a dielectric material. Other configurations are also within the scope of the various embodiments. In some embodiments, as described with respect to FIG. 2B , the dummy gate regions define the boundaries of a cell.

[0031] FIG. 2B is a simplified schematic diagram of an IC layout 200 in accordance with some embodiments.

[0032] FIG2B illustrates the cell boundaries of various cells C1 through C5 included in IC layout 200. Each of cells C1 through C5 includes a semiconductor device configured with at least one corresponding gate region and at least one corresponding active region, as described with respect to FIG2A. The gate region and active region are omitted in FIG2B. Cell C1 is located in row 210 and has a cell boundary defined by boundary lines 201 and 202 and the centerline of dummy gate regions 211 and 214. Cell C2 is located in row 210 and has a cell boundary defined by boundary lines 201 and 202 and the centerline of dummy gate regions 214 and 216. Cell C3 is located in row 220 and has a cell boundary defined by boundary lines 202 and 203 and the centerline of dummy gate regions 211 and 217. Cell C4 is located in row 230 and has a cell boundary defined by boundary lines 203, 204 and the centerline of dummy gate regions 211, 217. Cell C5 is arranged across rows 220, 230 and has a cell boundary defined by boundary lines 202, 204 and the centerline of dummy gate regions 214, 216. During a place and route operation, such as that performed by an APR system, cells are positioned in an IC layout so that they touch each other at their respective cell boundaries. For example, along the X-axis, cell C1 is positioned so that it touches cell C2 along a common cell boundary defined by dummy gate region 214. Along the Y-axis, cell C1 is positioned so that it touches cell C3 along a common cell boundary defined by boundary line 202. In one or more embodiments, boundary line 202 is defined by a power rail as described herein. The cell arrangements described are examples. Other cell arrangements are within the scope of the various embodiments. Examples of cells C1 to C5 include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), multiplexers (MUX), flip-flops, buffers (BUFF), latches, delays, clocks, memories such as static random-access memory (SRAM), decoupling capacitors, analog amplifiers, logic drivers, digital drivers, or similar circuits.

[0033] As can be seen in FIG2B , the heights of columns 210, 220, and 230 correspond to the cell heights of the corresponding cells in the columns along the Y-axis. The Y-axis is sometimes referred to as the cell height direction. For example, cells C1 and C2 have a cell height HT corresponding to the height of column 210, cells C3 and C4 have a cell height HS corresponding to the heights of columns 220 and 230, and cell C5 has a cell height 2HS corresponding to the sum of the cell heights of the columns 220 and 230 spanned by cell C5.

[0034] A row (or cell) whose height (or cell height) is greater than the unit height (or unit cell height) H of a unit row is sometimes referred to as a tall row (or tall cell). A row (or cell) whose height (or cell height) is less than the unit height (or unit cell height) H is sometimes referred to as a short row (or short cell). In the example configuration of FIG2B , HT>H, and the corresponding row 210 and cells C1 and C2 are sometimes referred to as tall rows and tall cells, respectively. On the other hand, H>HS, and the corresponding rows 220 and 230 and cells C3 and C4 are sometimes referred to as short rows and short cells, respectively. As described herein, cell C5 is sometimes referred to as a merged cell. Examples of unit rows and unit cells contained therein are described with respect to FIG3 and FIG4A .

[0035] Returning to FIG. 2A , cells C1 to C5 are represented by the active regions included therein. For example, cell C1 includes active regions 231 and 232 and is represented by active regions 231 and 232. Cell C2 includes active regions 237 and 238 and is represented by active regions 237 and 238. Cell C3 includes active regions 233 and 234 and is represented by active regions 233 and 234. Cell C4 includes active regions 235 and 236 and is represented by active regions 235 and 236. Cell C5 includes active regions 239 and 242 and the merged active regions 240 and 241 and is represented by active regions 239 and 242 and the merged active regions 240 and 241. Merged active regions 240 / 241 are arranged between active regions 239 and 242 and have a different conductivity type (e.g., P-type) than the conductivity type (e.g., N-type) of active regions 239 and 242. Cell C5 is an example of a merged cell that extends along the Y-axis across two rows of semiconductor devices and includes a merged active region. In the example configuration of Figures 2A-2B, cell C5 is a merged cell that spans two short rows 220 and 230. Other merged cell configurations are also within the scope of various embodiments. For example, in one or more embodiments, the merged cell extends across any two touching rows (e.g., two short rows, two tall rows, two single-row rows, one short row and one tall row, one short row and one single-row row, one tall row and one single-row row).

[0036] Each active region 231-242 has a width along the Y-axis (sometimes referred to as an "active region width"). For example, active regions 231 and 232 in row 210 or cell C1 have an active region width WT. In some embodiments, active region width WT is predetermined and depends on the corresponding cell height (or row height) HT and one or more design rules. As described herein, one example design rule is the spacing S between active regions in the same row. Another example design rule is a predetermined minimum spacing Sx between active regions and the nearest boundary line along the Y-axis. For example, as shown in FIG2A , the spacing between active region 231 and the nearest boundary line 201 is at least Sx. In some embodiments, S = 2Sx. Other design rules are also within the scope of various embodiments. In some embodiments, given the cell height HT, WT is the maximum active region width of active regions 231 and 232 when all design rules are met. In some embodiments, the corresponding values of WT and HT are predetermined, for example, for a set of design rules, materials, manufacturing processes, or the like, and are stored in or associated with a cell library, for example.

[0037] Active regions 233-236 in rows 220, 230 or cells C3, C4 have an active region width WS. In some embodiments, active region width WS is predetermined and depends on the corresponding cell height (or row height) HS and one or more design rules. In at least one embodiment, the same set of design rules that apply to cell C1 or row 210 also apply to cells C3, C4, and rows 220, 230. In some embodiments, given cell height HS, WS is the maximum active region width of active regions 233-236 when all design rules are met. In some embodiments, the corresponding values of WS and HS are predetermined, for example, for a set of design rules, materials, manufacturing processes, or the like, and are stored, for example, in or associated with a cell library.

[0038] As described herein, HS < H < HT, where H is the unit cell height of the unit cell. As described with respect to Figures 3 and 4A, the active region in the unit cell has a unit active region width W. In some embodiments, WS < W < WT. In some embodiments, the unit active region width W is predetermined and depends on the corresponding unit cell height H and one or more design rules. In at least one embodiment, the same set of design rules that apply to the tall cell C1, short cells C3 and C4, and columns 210, 220, and 230 also apply to the unit cells. In some embodiments, given a unit cell height H, W is the maximum active region width of the active region in the unit cell when all design rules are met. In some embodiments, the corresponding values of W and H are predetermined, for example, for a set of design rules, materials, manufacturing processes, or the like, and are stored, for example, in or associated with a cell library.

[0039] The active region width WT of the tall row 210 or tall cell C1 is greater than the active region width WS of the short row 220, 230 or short cells C3, C4. Therefore, the semiconductor devices in the tall cell C1 are configured to provide higher performance or faster speed than the semiconductor devices in the short cells C3, C4. When WT > W, the semiconductor devices in the tall cell C1 are configured to also provide higher performance than the semiconductor devices in the unit cell. In other words, the tall cell C1 is configured for performance-oriented improvements. On the other hand, the semiconductor devices in the short cells C3, C4 occupy a smaller chip area due to their smaller size (e.g., smaller cell height and / or smaller active region width) and are configured to consume less power during operation than the semiconductor devices in the tall cell C1. When WS < W, the semiconductor devices in the short cells C3, C4 also occupy a smaller chip area and are configured to consume less power during operation than the semiconductor devices in the unit cell. In other words, short cells C3 and C4 are configured for power and area-oriented improvements. The arrangement of rows of semiconductor devices with varying cell heights and / or active region widths in an IC layout is an example of a mixed row height configuration (also referred to herein as a "mixed row configuration"). In at least one embodiment, an IC layout with a mixed row configuration makes it possible to provide improvements in all PPA aspects, such as those described for tall cell C1 and short cells C3 and C4.

[0040] In contrast, other approaches to IC layouts that include rows of semiconductor devices with similar cell heights and active region widths have difficulty achieving improvements across all PPA profiles. For example, to improve (i.e., increase) performance according to other approaches, the cell height of all cells is increased, which can negatively impact power and area (i.e., increase power and area). For another example, to improve (i.e., reduce) power and area according to other approaches, the cell height of all cells is decreased, which can negatively impact performance (i.e., reduce performance). Hybrid row configurations according to some embodiments overcome these difficulties experienced by other approaches and provide optimizability and / or customization for different IC layouts and / or different circuit regions of an IC layout to suit one or more specific applications and / or functions.

[0041] In some embodiments, the tall cell C1 (or the tall row 210 ) and / or the short cell C3 or C4 (or the short row 220 or 230 ) satisfies one or more or all of the following relations (1) to (5):

[0042] 1.2H ≤ HT≤ 1.6H (1)

[0043] 0.6H ≤ HS≤ 0.8H (2)

[0044] 1.2W ≤ WT≤ 2W (3)

[0045] 0.3W ≤ WS≤ 0.8W (4)

[0046] 1.5 ≤ WT / WS ≤ 2 (5)

[0047] In some cases, when one of relations (1) to (5) is not satisfied, the expected or desired improvement in one of performance, power, and area may not be achieved.

[0048] In some embodiments, all tall cells in a tall row have the same active region width (e.g., WT). However, in at least one embodiment, at least one tall cell in a tall row has an active region width less than WT. For example, in FIG2A , the active regions 237 and 238 of tall cell C2 have a reduced active region width W SM . Active regions 237 and 238 with reduced active region widths are sometimes referred to as "small ODs." In some embodiments, tall cells with small ODs (e.g., cell C2) are configured to consume less power than conventional tall cells (e.g., cell C1) and are placed in locations in the tall row where performance improvement is not needed. Therefore, according to some embodiments, along the tall row, performance improvement can be achieved by placing tall cells (e.g., tall cell C1) where needed, while power consumption can be reduced by placing tall cells with small ODs (e.g., cell C2) where performance improvement is not needed. In at least one embodiment, this arrangement further enhances the optimizability and / or customizability of the IC layout or its circuit areas.

[0049] In some embodiments, different tall cells with small OD have different reduced active area widths (i.e., different WSM values). In at least one embodiment, this arrangement further enhances the optimizability and / or customizability of an IC layout or its circuit regions, by selecting and placing tall cells with small OD values at appropriate WSM values along the tall rows to achieve a balance between performance and power consumption at those locations. In some embodiments, for a given HT, the various WSM values for tall cells with small OD are predetermined and stored, for example, in a cell library or associated with the cell library.

[0050] In some embodiments, a tall cell with a small OD (e.g., cell C2) satisfies the following relationship (6):

[0051] 0.3W ≤ W SM ≤ 0.8W (6)

[0052] In some cases, when tall cells with small OD do not satisfy relationship (6), the expected or desired improvement in one of performance, power, and area may not be achieved.

[0053] In some embodiments, the described small OD configuration is applicable to short cells or unit cells. For example, a short cell with a small OD has a reduced active region width W SM, where W SM < WS. In some embodiments, a short cell with a small OD satisfies the relationship (6). In some embodiments, for a given HS, various W SM values for short cells with a small OD are predetermined and stored, for example, in a cell library or associated with the cell library. In the exemplary configuration of FIG2A , in one or more embodiments, at least one of the short cells C3, C4 may be a short cell with a small OD. In at least one embodiment, both cells C3 and C4 are short cells with a small OD, wherein the W SM value of cell C3 is different from the W SM value of cell C4.

[0054] The unit cell with small OD has a reduced active region width W SM, where W SM < W. In some embodiments, the unit cell with small OD satisfies the relationship (6). In some embodiments, for a given H, various W SM values for the unit cell with small OD are predetermined and stored, for example, in a cell library or associated with the cell library. In at least one embodiment, one or more advantages described herein for tall cells with small OD can be achieved by short cells with small OD and / or by unit cells with small OD. Examples and further details of short cells with small OD and unit cells with small OD are described with respect to FIG. 3 and FIG. 4A.

[0055] In at least one embodiment, the tall cells (or tall columns) can be optimized / customized independently of the short cells (or short columns) and / or independently of the unit cells (or unit columns), for example, by appropriate WSM values for the tall cells with small OD, the short cells with small OD, the unit cells with small OD, and / or by the number and / or position of the tall cells with small OD, the short cells with small OD, the unit cells with small OD in the corresponding tall columns, short columns, and unit columns.

[0056] As described herein, merged cell C5 includes a merged active region 240 / 241 of one conductivity type disposed between active regions 239 and 242 of different conductivity types. In some embodiments, the active region width W M1 of active region 239 is the same as the active region width of active region 240, and the active region width W M2 of active region 242 is the same as the active region width of active region 241. Therefore, the active region width W M of the merged active region 240 / 241 is the sum of W M1 and W M2. In at least one embodiment, W M1 = W M2, and W M = 2W M1 = 2W M2.

[0057] In at least one embodiment, by merging active regions 240 and 241 into a merged active region 240 / 241, the merged active region 240 / 241 has a larger active region width WM than the cells originally included in the constituent cells before / after the merging (i.e., the first cell having active regions 239 and 240 and the second cell having active regions 241 and 242). In one or more embodiments, the increased active region width WM improves the performance of the merged cell C5. The merged cell configuration described in some embodiments can provide performance improvements (i.e., increased speed) even in regions with limited active region widths, such as those with short and / or single-digit rows. The described performance improvements can also be achieved in regions with tall cells because, as described herein, in one or more embodiments, any two cells or rows (including two tall cells or two tall rows) can be merged to form a merged cell.

[0058] In some embodiments, the merged cell (e.g., cell C5) satisfies the following relationship (7):

[0059] 1W ≤ WM ≤ 4W (7)

[0060] As can be seen from relations (3) and (7), in some embodiments, the WM of the merged active region is greater than the maximum active region width WT of the tall cell (2W). In other words, in one or more embodiments, the merged cell can provide a greater speed improvement than the tall cell. In some cases, when the merged cell does not satisfy relation (7), the expected or desired improvement in one of performance, power, and area may not be achieved.

[0061] FIG. 2C includes schematic diagrams of various cell column configurations 261 - 265 in one or more IC layouts according to some embodiments.

[0062] Each of cell column configurations 261 to 265 includes a set of columns comprising at least one tall cell and at least one short cell. In at least one embodiment, the set of columns is repeated multiple times along the Y-axis to cover the floor plan or area of the IC layout. Thus, the IC layout includes a repeating pattern comprised of the set of columns. This repeating pattern comprised of a set of columns is sometimes referred to as a cell array. A cell array in which all columns have the same height is sometimes referred to as a single-height (SH) cell array with a single-row height configuration (or a single-row height cell array). In some embodiments, all columns in a single-height cell array are unit columns, and the single-height cell array is a unit cell array. A cell array comprising columns with different heights (e.g., a cell array based on any of cell column configurations 261 to 265) is sometimes referred to as a mixed row cell array. An example cell array having a repeating pattern comprised of a set of columns is described with reference to Figures 4B and 4C.

[0063] In the example configuration of FIG2C , cell column configuration 261 includes a set of columns comprising three tall columns 271, 272, and 273 and one short column 274. Cell column configuration 262 includes a set of columns comprising two tall columns and one short column. Cell column configuration 263 includes a set of columns comprising one tall column and one short column. Cell column configuration 264 includes a set of columns comprising one tall column and two short columns. Cell column configuration 265 includes a set of columns comprising one tall column 275 and three short columns 276, 277, and 278. Other cell column configurations having other numbers of tall columns and / or short columns are also within the scope of various embodiments. In at least one embodiment, each of the tall columns (e.g., 271, 272, 273, and 275) corresponds to the tall column 210, and / or each of the short columns 274, 276, 277, and 278 corresponds to the short columns 220 or 230. Specific examples of cell column configuration 264 are described with reference to Figures 2A and 2B. In the exemplary configuration of Figure 2C, all tall columns have the same height HT and all short columns have the same height HS. Other configurations are also within the scope of various embodiments. For example, in one or more embodiments, two tall columns in the same cell column configuration (e.g., tall columns 271 and 272 in cell column configuration 261) can have different heights greater than H, and / or two short columns in the same cell column configuration (e.g., short columns 276 and 277 in cell column configuration 265) can have different heights less than H.

[0064] As described herein, tall rows containing tall cells are configured for performance, while short rows containing short cells are configured for power and area. The number of tall rows, the number of short rows, and the corresponding heights HT and HS in each of the cell row configurations 261-265 determine the suitability of the cell row configuration for improving performance or improving power and area. In some embodiments, this suitability is represented by the equivalent cell height HE of the cell row configuration. In at least one embodiment, HE is determined by the mixed row ratio Rmix as follows:

[0065] R mix=high number of columns / number of short columns (8)

[0066] HE= (HT× R mix+ HS) / (R mix+ 1) (9)

[0067] In one example, for cell column configuration 261, R mix = 3, and HE = (3H T + HS) / 4. In another example, for cell column configuration 265, R mix = 1 / 3, and HE = (H T + 3H S) / 4. As shown in FIG2C , HE and R mix increase toward cell column configuration 261 and decrease toward cell column configuration 265. Cell column configuration 263 has R mix = 1. In at least one embodiment, H T + HS = 2H, such that cell column configuration 263 has HE = H. HE = H indicates that a cell array including a repeating pattern of cell column configuration 263 is comparable in performance, power, and area to a single-height cell array including unit columns having a height of H.

[0068] HE > H (e.g., for cell column configurations 261 and 262) indicates that cell column configurations 261 and 262 are configured to provide performance improvements compared to a single-height cell array and are suitable for speed-oriented applications or circuit areas. Of cell column configurations 261 and 262, cell column configuration 262 is configured to provide less performance improvement than cell column configuration 261, but has better power and area parameters than cell column configuration 261. In at least one embodiment, cell column configuration 261 is suitable or preferred for applications or circuit areas where speed is the highest priority, while cell column configuration 262 is suitable or preferred for applications or circuit areas where speed is less critical and power and area are design considerations.

[0069] HE < H (e.g., for cell column configurations 264 and 265) indicates that cell column configurations 264 and 265 are configured to provide power and area improvements compared to a single-height cell array and are suitable for applications or circuit areas where power and area are the primary considerations. Of cell column configurations 264 and 265, cell column configuration 264 is configured to provide less power and area improvements than cell column configuration 265, but has better performance (i.e., higher speed) than cell column configuration 265. In at least one embodiment, cell column configuration 265 is suitable or preferred for applications or circuit areas where low power and low area are top priorities, while cell column configuration 264 is suitable or preferred for applications or circuit areas where low power and low area are less critical and speed is a design consideration.

[0070] In some embodiments, the cell column configurations 261 to 265 satisfy the following relationship (10):

[0071] 0.8H ≤ HE≤ 1.2H (10)

[0072] In at least one embodiment, H < HE ≤ 1.2H indicates performance improvement, while 0.8H ≤ HE < H indicates power and area improvement. In some cases, when a cell row configuration does not satisfy relation (10), the expected or desired improvement in one of performance, power, and area of the cell row configuration may not be achieved.

[0073] In some embodiments, multiple applications and / or circuit regions are pre-associated with different HE values, such as in a lookup table. For example, high-speed applications are associated with high HE values, while low-power applications are associated with low HE values. In at least one embodiment, for a given H value, different HE values are pre-associated with corresponding different cell column configurations, such as described with respect to FIG. 2C , for example, in the same or different lookup tables. In some embodiments, different H values (e.g., for different manufacturing processes, sets of design rules, materials, or the like) result in different cell column configurations being associated with HE values.

[0074] In at least one embodiment, when developing an IC layout or circuit area thereof for an application, a lookup table is consulted to determine the corresponding HE, and then a corresponding cell row configuration is determined. A mixed row cell array is generated as a repeating pattern of the determined cell row configuration. Tall cells and short cells are read from one or more cell libraries and placed in corresponding tall and short rows in the mixed row cell array according to the circuitry of the circuit area. Routing is performed to couple the placed cells together and / or to other circuitry. Thus, an IC layout or circuit area thereof is generated for the application in which the desired improvement in one or more PPA aspects is applicable to the application. In at least one embodiment, one or more advantages described herein can be achieved by the method and / or cell row configuration.

[0075] FIG3 includes a schematic diagram of various cells 310 through 360 that can be placed in an IC layout according to some embodiments. In some embodiments, cells 310 through 360 are stored in a non-transitory computer-readable storage medium as part of one or more cell libraries (e.g., cell library 300 shown in FIG3 ). In at least one embodiment, cells 310 through 360 all meet and / or are configured for the same set of design rules and / or manufacturing processes and / or materials, such that all cells 310 through 360 can be included in the same manufacturable IC layout.

[0076] As described herein, cell 310 is an example of a unit cell having a cell height H and an active area width W. Unit cells are sometimes referred to as default cells. Cell 310 can be placed in a unit row having a unit height H. An example unit row is described with respect to FIG. 4A . Due to the spacing S between active areas, cell 310 has an optimal active area density (sometimes referred to as "OD density") among cells having a cell height H. In at least one embodiment, the OD density of a cell is determined as the ratio between the sum of the active area widths in the cell and the cell height. The cell height of cell 310 is H = 2W + 2S (where 2Sx = S). The OD density of cell 310 is 2W / (2W + 2S) or W / (W+S).

[0077] As described herein, cell 320 is an example of a unit cell with a small OD. Cell 320 has a cell height H and a reduced active region width W SM , where W SM < W. In at least one embodiment, the W SM of cell 320 satisfies relation (6). In at least one embodiment, cell library 300 includes variants of cell 320 (i.e., multiple unit cells with a small OD similar to cell 320 ), configured for the same function / operation (e.g., a variant of an NAND gate cell is an NAND gate cell), but with different W SM values. Cell 320 can be placed in a unit column. In some embodiments, all cells in a unit column are unit cells similar to cell 310 . In at least one embodiment, all cells in a unit column are unit cells with a small OD similar to cell 320 , having the same W SM or having different W SM values. In some embodiments, the cells in a unit column include one or more unit cells similar to cell 310 and one or more unit cells with a small OD similar to cell 320 . In at least one embodiment, as described herein, cells in a unit column include a portion of a merged cell.

[0078] As described herein, cell 330 is an example of a short cell having a cell height HS (where HS < H) and an active region width WS (where WS < W). In at least one embodiment, cell library 300 includes variations of cell 330 (i.e., multiple short cells similar to cell 330) configured for the same function / operation, but with different HS and WS values. In some embodiments, cell 330 corresponds to short cell C3 or C4. Cell 330 can be placed in a short column having a corresponding height HS. An example short column is described with respect to FIG. 2A . Due to the spacing S between active regions, cell 330 has the best OD density among cells having a cell height HS. In at least one embodiment, the OD density of cell 330 is WS / (WS + S), which is less than the OD density of cell 310.

[0079] As described herein, cell 340 is an example of a short cell with a small OD. Cell 340 has a cell height HS and a reduced active region width W SM , where W SM < WS. In at least one embodiment, the W SM of cell 340 satisfies relation (6). In at least one embodiment, cell library 300 includes variants of cell 340 (i.e., multiple short cells with a small OD similar to cell 340 ), configured for the same function / operation, but with different W SM values. Cell 340 can be placed in short columns. In some embodiments, all cells in a short column are short cells similar to cell 330 . In at least one embodiment, all cells in a short column are short cells with a small OD similar to cell 340 , with the same W SM or with different W SM values. In some embodiments, the cells in a short column include one or more short cells similar to cell 330 and one or more short cells with a small OD similar to cell 340 . In at least one embodiment, the cells in the short column include a portion of the merged cells, as described herein.

[0080] As described herein, cell 350 is an example of a tall cell having a cell height HT (where HT > H) and an active region width WT (where WT > W). In at least one embodiment, cell library 300 includes variations of cell 350 (i.e., multiple tall cells similar to cell 350) configured for the same function / operation but with different HT and WT values. In some embodiments, cell 350 corresponds to tall cell C1. Cell 350 can be placed in a tall column having a corresponding height HT. An example tall column is described with respect to FIG. Due to the spacing S between active regions, cell 350 has the best OD density among cells having a cell height HT. In at least one embodiment, the OD density of cell 350 is WT / (WT + S) and is greater than the OD density of cell 310. The higher OD density of cell 350 indicates that cell 350 has better performance (e.g., higher speed) than cell 310.

[0081] As described herein, cell 360 is an example of a tall cell with a small OD. Cell 360 has a cell height HT and a reduced active region width W SM , where W SM < WT. In at least one embodiment, the W SM of cell 360 satisfies relationship (6). In at least one embodiment, cell library 300 includes variants of cell 360 (i.e., multiple tall cells with a small OD similar to cell 360 ), configured for the same function / operation, but with different W SM values. Cell 360 can be placed in tall columns. In some embodiments, all cells in a tall column are tall cells similar to cell 350 . In at least one embodiment, all cells in a tall column are tall cells with a small OD similar to cell 360 , with the same W SM or different W SM values. In some embodiments, the cells in a tall column include one or more tall cells similar to cell 350 and one or more tall cells with a small OD similar to cell 360 . In at least one embodiment, the cells in a tall column include a portion of a merged cell, as described herein.

[0082] In some embodiments, in addition to cells 310 through 360 and their corresponding variants, cell library 300 further includes one or more merged cells. In at least one embodiment, a merged cell is obtained by merging the active regions of any two cells selected from cells 310 through 360 and their corresponding variants. In some embodiments, the merged cell is not pre-stored in the cell library, but is generated by an EDA system by merging two cells read from a cell library (e.g., cell library 300).

[0083] In some embodiments, cells read from the cell library 300 are placed in rows of corresponding heights in the generated cell array, such as described with respect to FIG. 2C , FIG. 4B , and FIG. In at least one embodiment, by selecting cells from the cell library to be placed in the IC layout based not only on the function / operation the cell is configured to perform, but also on other considerations (e.g., cell height, active area width, whether the cell will be placed in a circuit area optimized or improved for one or more of performance, power, and area), one or more advantages described herein, including but not limited to improved PPA, enhanced layout optimizability and / or customizability, or the like, can be achieved.

[0084] 4A is a schematic diagram of an IC layout 400A of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B.

[0085] Compared to IC layout 200, which includes tall and short columns, IC layout 400A includes tall, short, and unit columns. For example, in the circuit area shown in FIG4A, IC layout 400A includes a first subset 401 consisting of two unit columns 403 and 405, and a second subset 402 consisting of a tall column 404 and a short column 406. In FIG4A, unit columns 403 and 405 are labeled "SH" (single height). The side-by-side arrangement of subset 401 and subset 402 is for illustrative purposes and indicates that in the exemplary configuration of FIG4A, HS + HT = 2H. In at least one embodiment, subset 401 and subset 402 are not aligned along the X-axis; instead, one of subsets 401 and 402 is arranged above or below the other along the Y-axis, as described with respect to FIG4B and FIG4C.

[0086] Unit cell 410, including active regions 411 and 412, is placed in unit row 403. In at least one embodiment, unit cell 410 corresponds to cell 310. Unit cell 420, including active regions 421 and 422, is placed in unit row 405. In at least one embodiment, unit cell 420 is a unit cell with a small OD and corresponds to cell 320. Merged cell 470, including active regions 471 and 473 on opposite sides of merged active region 472, is placed across unit rows 403 and 405. Active regions 471, 472, 473 of merged cell 470 are isolated from active regions 411, 412, 421, 422 of cells 410 and 420 by dummy active regions 475, 476, 477 in a manner similar to that described for dummy active regions 245, 246, 247. Short cell 440, including active regions 441 and 442, is placed in short column 406. In at least one embodiment, cell 440 is a short cell with a small OD and corresponds to cell 340. Tall cell 450, including active regions 451 and 452, is placed in tall column 404. In at least one embodiment, tall cell 450 corresponds to cell 350.

[0087] When HS + HT = 2H and the number of tall and short columns is the same, IC layout 400A has Rmix = 1 and HE = H, meaning that IC layout 400A is generally comparable to a single-height cell array in which all columns are unit columns. However, the arrangement of tall and short columns in IC layout 400A allows for at least local optimization of one or more PPA aspects. For example, in at least one embodiment, cells implementing functions or operations where speed is the highest priority are placed in tall columns or configured as merged cells. Other cells with roughly the same considerations regarding speed, on the one hand, and power and area, on the other, are placed in unit columns. The remaining cells, whose functions or operations favor power and / or area over speed, are placed in short columns or configured with reduced active area widths. The described local PPA optimization / improvement is one example.

[0088] 4B and 4C illustrate various cell column configurations 400B and 400C in one or more IC layouts according to some embodiments.

[0089] In FIG4B , cell column configuration 400B includes a repeating pattern of subgroups 401 and subgroups 402, where subgroups 401 and 402 are arranged alternately along the Y-axis. In FIG4C , cell column configuration 400C includes a repeating pattern of subgroups 401 in a portion (e.g., the upper portion shown in FIG4C ) and a repeating pattern of subgroups 402 in another portion (e.g., the lower portion shown in FIG4C ). Other cell column configurations including subgroups 401 and 402 are also within the scope of various embodiments. The cell arrays described with respect to FIG4B and FIG4C , including tall columns, short columns, and unit columns, are sometimes referred to as integrated cell arrays.

[0090] The described integrated cell arrays are examples. Other configurations are also within the scope of various embodiments. For example, in one or more embodiments, the relationship HS + HT = 2H and / or the relationship of two unit columns per tall column and one short column need not necessarily be satisfied. In some embodiments, the integrated cell array includes other numbers of unit columns and / or tall columns and / or short columns. In at least one embodiment, the integrated cell array is obtained by including one or more unit columns in a cell column configuration of a mixed column cell array. In some embodiments, the columns in subgroup 401 or subgroup 402 are adjacent and do not necessarily touch each other. In some embodiments, one or more advantages described herein can be achieved by using an IC layout using an integrated cell array (e.g., an integrated cell array based on cell column configuration 400B or 400C) and / or an IC device manufactured according to such an IC layout.

[0091] 5A is a block diagram of an IC device 500A according to some embodiments. In at least one embodiment, IC device 500A corresponds to IC device 100A.

[0092] IC device 500A includes multiple circuit areas 501 to 504. In at least one embodiment, circuit areas 501 to 504 meet the same set of design rules and / or are configured using the same manufacturing process and / or materials, so that all circuit areas 501 to 504 can be manufactured simultaneously.

[0093] In the example configuration of FIG5A , circuit region 501 includes a mixed column cell array comprising tall cells and short cells arranged in corresponding tall and short columns arranged, for example, in the cell column configuration described with respect to FIG2C . Circuit region 501 has an equivalent cell height HE1 and a mixed column ratio Rmix1 determined as described herein.

[0094] Circuit area 502 includes another mixed column cell array, comprising tall cells and short cells arranged in corresponding tall and short columns, such as the cell column configuration described with respect to FIG. 2C . Circuit area 502 has an equivalent cell height HE2 and a mixed column ratio Rmix2. In some embodiments, circuit area 501 differs from circuit area 502 in one or more of the number of tall columns, the number of short columns, the cell height of tall cells, the cell height of short cells, or the like. In some embodiments, circuit areas 501 and 502 have the same HT, HS, WT, and WS based on the same H and W, and circuit areas 501 and 502 differ from each other in the number of tall columns and / or the number of short columns. Due to one or more of these differences, the equivalent cell height HE1 and the equivalent cell height HE2 differ from each other, and / or the mixed column ratio Rmix1 and the mixed column ratio Rmix2 differ from each other. For example, HE1>HE2, and the circuit area 501 with higher HE1 is configured for high-speed applications, while the circuit area 502 with lower HE2 is configured for low-power applications.

[0095] Circuit area 503 includes an integrated cell array comprising tall cells, short cells, and unit cells arranged in corresponding tall columns, short columns, and unit columns, such as those described with respect to FIG. 4B and FIG. 4C . Circuit area 503 has an equivalent cell height HE3 and a mixed column ratio Rmix3. In some embodiments, circuit area 503 differs from circuit area 501 and / or circuit area 502 in one or more of the number of tall columns, the number of short columns, the cell height of tall cells, the cell height of short cells, or the like. In some embodiments, circuit areas 501, 502, and 503 have the same HT, HS, WT, and WS based on the same H and W, and circuit area 503 differs from circuit area 501 and / or circuit area 502 in the number of tall columns and / or the number of short columns. In at least one embodiment, circuit area 503 has the same HT, HS, WT, WS, H, W, tall row count, and short row count as circuit area 501 and / or circuit area 502, but differs from circuit area 501 and / or circuit area 502 by additionally including one or more unit rows. Due to one or more of these differences, the equivalent cell height HE3 differs from at least one of HE1 or HE2, and / or the mixed row ratio R mix3 differs from at least one of R mix1 or R mix2. In at least one embodiment, HE3 and R mix3 are determined as described herein based on the application to be implemented in circuit area 503 to implement the application while achieving one or more desired PPA improvements.

[0096] Circuit area 504 is a single-height cell array in which all cells and all rows have the same cell height. In other words, all rows in circuit area 504 are unit rows. In some embodiments, the unit cells in circuit area 504 have the same H and W, which form the basis for determining the HT, HS, WT, and WS of one or more circuit areas 501 through 503. In at least one embodiment, circuit area 504 includes unit cells, unit cells with small OD, and merged cells, enabling one or more localized PPA improvements, as described for subgroup 401 in FIG. 4A . In some embodiments, one or more of circuit areas 501 through 504 are omitted. One or more of the advantages described herein can be achieved with IC device 500A.

[0097] FIG5B is a schematic diagram of an IC layout 500B of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or region 504, or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, or 500A.

[0098] IC layout 500B includes a single-height cell array having various unit columns 505-510 arranged along the Y-axis. Each of unit columns 505-510 has a height H. IC layout 500B includes multiple power rails configured to supply different power supply voltages (e.g., VDD and VSS). A power rail configured to supply VDD is sometimes referred to as a VDD rail. A power rail configured to carry VSS is sometimes referred to as a VSS rail. In the example configuration shown in FIG5B , the VDD and VSS rails are arranged alternately in IC layout 500B. The centerline of each power rail coincides with the boundary between two contact columns. For simplicity, the width of the power rails is not shown in FIG5B . The illustrated power rail arrangement is an example. Other power rail arrangements are also within the scope of various embodiments.

[0099] IC layout 500B includes three types of cells: unit cells, unit cells with small ODs, and merged cells. For example, each of regions 511 through 516 includes one or more unit cells corresponding to, for example, cell 310. Each of regions 521 through 522 includes one or more unit cells with small ODs corresponding to, for example, cell 320. Each of regions 531 through 535 includes one or more merged cells, each extending across two unit columns. For example, each merged cell in region 531 extends across two unit columns 509 and 510 and corresponds to, for example, merged cell 470. In at least one embodiment, IC layout 500B enables one or more PPA improvements to be achieved, at least locally. For example, the merged cells in regions 531-535 provide speed improvements, the unit cells with small OD in regions 521, 522 provide power and / or area improvements, and the unit cells in regions 511-516 provide a balance between various performance, power, and area considerations.

[0100] FIG5C is a schematic diagram of an IC layout 500C of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103, 501, or 502, or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, or 500A. In at least one embodiment, IC layout 500B and IC layout 500C correspond to different circuit regions of the same IC device.

[0101] IC layout 500C includes a hybrid column cell array having columns 594 through 599 of varying heights arranged along the Y-axis. Columns 594, 595, 598, and 599 are short columns having a height HS, while columns 596 and 597 are tall columns having a height HT. IC layout 500C includes multiple power rails including alternating VDD and VSS rails as described with respect to FIG.

[0102] IC layout 500C includes five types of cells: tall cells, tall cells with small OD, short cells, short cells with small OD, and merged cells. For example, each of regions 541 to 544 includes one or more short cells corresponding to, for example, cell 330. Each of regions 551 to 552 includes one or more short cells with small OD corresponding to, for example, cell 340. Each of regions 561 to 563 includes one or more tall cells corresponding to, for example, cell 350. Each of regions 571 to 572 includes one or more tall cells with small OD corresponding to, for example, cell 360. Each of regions 581 to 585 includes one or more merged cells, each of which extends across two reach columns. For example, each merged cell in region 581, region 584, or region 585 extends across two short columns 594, 595 and corresponds to, for example, merged cell C5. Each merged cell in region 582 or region 583 extends across one short column 595 or short column 598 and one tall column 596 or tall column 597.

[0103] In some embodiments, depending on the equivalent cell height HE of IC layout 500C, one or more overall PPA improvements can be achieved across IC layout 500C, such as described with respect to FIG. 2C . In at least one embodiment, IC layout 500C further enables one or more local PPA improvements to be achieved. For example, merged cells in region 581 provide speed improvements even in areas with short rows targeted for power and area. Short cells with small OD in regions 551 and 552 enhance the power and area improvements already provided by short rows 595 and 599. Tall cells with small OD in regions 571 and 572 provide power and area improvements even in areas with tall rows targeted for speed. In some embodiments, one or more of the advantages described herein can be achieved by IC layout 500C and / or IC devices fabricated according to IC layout 500C.

[0104] 6 is a schematic diagram of an IC layout 600 of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B.

[0105] IC layout 600 includes a subgroup 601 consisting of two unit columns and a subgroup 602 consisting of tall columns and short columns. In at least one embodiment, subgroup 601 corresponds to subgroup 401 and / or subgroup 602 corresponds to subgroup 402. IC layout 600 further includes multiple conductive patterns in the M0 layer. In some embodiments, the M0 layer is the metal layer closest to the active region in the IC layout or IC device, while the metal layer M1 directly above the M0 layer is the metal layer second closest to the active region. More details about the M0 and M1 layers are provided with reference to Figures 7A, 7C, 7D, and 7F. Conductive patterns in the M0 layer or M1 layer are sometimes referred to as M0 conductive patterns or M1 conductive patterns, respectively. In Figure 6, a first group of M0 conductive patterns 611-623 is used for the unit columns in subgroup 601, while a second group of M0 conductive patterns 630-641 is used for the tall and short columns in subgroup 602. For illustrative purposes, the M0 conductive patterns are shown on one side of the corresponding columns and cells. In an actual IC layout, the M0 conductive pattern extends along the X-axis over the rows and cells, as described with respect to Figures 7C and 7F. As described herein, the two sets of M0 conductive patterns in subgroups 601 and 602 are different from each other to achieve one or more PPA improvements.

[0106] The first set of M0 conductive patterns 611 to 623 for the unit columns in subgroup 601 includes wider M0 conductive patterns 611, 617, and 623 configured as power rails and having centerlines coinciding with the unit column boundaries, as described with respect to FIG. 5B and FIG. 5C . The remaining M0 conductive patterns in the first set are configured for data or signals and are sometimes referred to as signal M0 conductive patterns. The signal M0 conductive patterns have a uniform width M (sometimes referred to as "M0 metal width" or "metal width") along the Y-axis. The metal width M is smaller than the width of the power rails 611, 617, and 623 along the Y-axis. In at least one embodiment, the first set of M0 conductive patterns 611 to 623 includes two subgroups, each corresponding to and manufactured using a separate mask. The M0 conductive patterns of the two subgroups are arranged alternately along the Y-axis. For example, the first subgroup includes M0 conductive patterns 611, 613, 615, 617, 619, 621, and 623, while the second subgroup includes M0 conductive patterns 612, 614, 616, 618, 620, and 622. The same number (e.g., five) of signal M0 conductive patterns are arranged on each unit row.

[0107] The second group of M0 conductive patterns 630-641 for the columns in subgroup 602 includes wider power rails 630, 636, and 641. The remaining M0 conductive patterns in the second group are signal M0 conductive patterns and are narrower than power rails 630, 636, and 641. In at least one embodiment, the second group of M0 conductive patterns 630-641 includes two subgroups, each corresponding to and manufactured using a separate mask. The M0 conductive patterns of the two subgroups are arranged alternately along the Y-axis. For example, the first subgroup includes M0 conductive patterns 631, 633, 635, 637, 639, and 641, while the second subgroup includes M0 conductive patterns 630, 632, 634, 636, 638, and 640. In some embodiments, the M0 conductive patterns 611, 613, 615, 617, 619, 621, 623 and 631, 633, 635, 637, 639, 641 correspond to the first mask and are manufactured by the first mask, while the M0 conductive patterns 612, 614, 616, 618, 620, 622 and 630, 632, 634, 636, 638, 640 correspond to the second mask and are manufactured by the second mask.

[0108] The signal M0 conductive patterns 631-635 located above the tall columns in subgroup 602 have a metal width MT, where MT>M. This is because the tall cells in the tall columns have a larger active region width WT, which is configured to handle higher currents (to improve speed) than the unit cells with smaller active region widths W. The larger MT of the signal M0 conductive patterns located above the tall columns reduces the voltage drop (IR drop) associated with the higher currents handled by the tall cells. In at least one embodiment, for similar reasons, the vias coupled to the signal M0 conductive patterns 631-635 located above the tall columns also have a larger size than the vias coupled to the signal M0 conductive patterns 612-616 located above the unit columns.

[0109] Signal M0 conductive patterns 637-640 located on the short rows in subgroup 602 have a metal width MS, where MS < M. This is because the short cells in the short rows are not designed for speed improvement and have smaller active area widths WS or WSM, which are configured to handle smaller currents than unit cells with larger active area widths W. In one or more embodiments, the smaller metal width MS of the signal M0 conductive patterns located on the short rows contributes to area reduction, i.e., improved chip area. In the exemplary configuration of FIG6 , the number of signal M0 conductive patterns 637-640 located on the short rows (e.g., four) is smaller than the number of signal M0 conductive patterns 631-635 located on the tall rows (e.g., five), further improving area. In at least one embodiment, to achieve the desired area improvement, it is sufficient to reduce the number of signal M0 conductive patterns located on the short row compared to the unit row or tall row, or to reduce the metal width of the signal M0 conductive patterns located on the short row compared to the unit row or tall row.

[0110] 7A includes a schematic circuit diagram and a cross-sectional view of a circuit area of an IC device 700A according to some embodiments. In some embodiments, IC device 700A corresponds to one or more of IC devices 100A, 100B, and 500A.

[0111] In the exemplary configuration of FIG7A , the circuit region includes an inverter INV. As can be seen from the schematic circuit diagram in FIG7A , the inverter INV includes a P-type device MP and an N-type device MN. The gate of device MP and the gate of device MN are coupled to input IN. A first source / drain of device MP is coupled to a first source / drain of device MN and to output ZN. A second source / drain of device MP is coupled to VDD, and a second source / drain of device MN is coupled to VSS.

[0112] 7A , IC device 700A includes a first structure 701 and a second structure 702. Structure 701 is formed by FEOL fabrication and is sometimes referred to as FEOL structure 701. Structure 702 is formed on FEOL structure 701 by BEOL fabrication and is sometimes referred to as BEOL structure 702.

[0113] FEOL structure 701 includes a substrate (unnumbered), which in one or more embodiments corresponds to substrate 110. Active regions 761 and 762 (schematically indicated by the label "OD") are located above the substrate and constitute the source / drain of device MP and the source / drain of device MN, respectively. In at least one embodiment, active regions 761 and 762 correspond to nanosheet stacks 134 and 124 and / or various active regions described herein. Isolation region 704 is located between active regions 761 and 762 and, in one or more embodiments, corresponds to isolation region 114. The gates of device MP and device MN are not shown in FIG7A . In some embodiments, the gates of device MP and device MN are continuous and correspond to gate electrode 116 or gate electrode 118. Source / drain contacts 763 and 764 (schematically indicated by the label "MD") are located above and electrically contact the active regions 761 and 762, respectively. Isolation region 704 is also located between source / drain contacts 763 and 764. Dielectric layer 703 is located above source / drain contacts 763 and 764. Via-to-device (VD) vias 765 and 766 are located above and electrically contact source / drain contacts 763 and 764, respectively. Via-to-gate (VG) vias (not shown in FIG. 7A ) are located above and electrically contact the gates of device MP and device MN. VD vias 765 and 766 and VG vias are embedded in dielectric layer 703. The upper surface of dielectric layer 703, VD vias 765 and 766, and VG vias correspond to the upper surface of FEOL structure 701, on which BEOL structure 702 is formed.

[0114] The BEOL structure 702 is sometimes referred to as a redistribution structure. The redistribution structure includes multiple metal layers and via layers sequentially and alternately arranged above the VD and VG vias. The redistribution structure further includes various interlayer dielectric (ILD) layers (generally represented by 705) embedded therein, with the metal layers and via layers. The metal layers and via layers of the redistribution structure are configured to electrically couple the various components or circuits of the IC device 700A to each other and to external circuitry. In the redistribution structure, the lowest metal layer directly above and in electrical contact with the VD and VG vias is the M0 (metal zero) layer. The next metal layer directly above the M0 layer is the M1 layer, the next metal layer directly above the M1 layer is the M2 layer, and so on. A via layer Vn is arranged between the Mn and Mn+1 layers to electrically couple the Mn and Mn+1 layers, where n is an integer of zero or greater. For example, the via-zero (V0) layer is the lowest via layer disposed between the M0 layer and the M1 layer and electrically couples the M0 layer and the M1 layer. Other via layers are V1, V2, or similar via layers. Vias in the V0 layer are referred to as V0 vias, vias in the V1 layer are referred to as V1 vias, and so on. For the sake of simplicity, FIG. 7A does not fully illustrate the metal layers and via layers in the redistribution structure.

[0115] In the exemplary configuration of FIG7A , M0 conductive patterns 730 through 735 are provided above FEOL structure 701. M0 conductive patterns 731 and 735 are located above and electrically contact VD vias 765 and 766, respectively, and M0 conductive pattern 733 is located above and electrically contacting a VG via. V0 vias 741 and 742 are located above and electrically contacting M0 conductive patterns 731 and 735, respectively. Another V0 via (not shown in FIG7A ) is located above and electrically contacting M0 conductive pattern 733 to provide electrical connections to the gates of device MP and device MN. M1 conductive pattern 740 is located above and electrically contacts V0 vias 741 and 742, electrically coupling the source / drain of device MP in active region 761 with the source / drain of device MN in active region 762. M1 conductive pattern 740 constitutes output ZN. Another M1 conductive pattern (not shown in FIG. 7A ) is located above and electrically contacts the V0 vias coupled to the gates of device MP and MN, constituting input IN.

[0116] FIG7B and FIG7C are schematic diagrams of various layers of an IC layout 700B in the circuit area shown in FIG7A , according to some embodiments. FIG7A corresponds to a cross-sectional view taken along line AA in FIG7B and FIG7C . FIG7B illustrates a portion of the IC layout 700B corresponding to the FEOL structure 701. FIG7C illustrates another portion of the IC layout 700B corresponding to the BEOL structure 702. For simplicity, corresponding components in FIG7A through FIG7C are denoted by the same reference numerals.

[0117] Portions of IC layout 700B in FIG7B are similar to the short cell or unit cell layout described herein. IC layout 700B includes gate G1 of device MP and gate G2 of device MN. Gates G1 and G2 are continuous with each other, and VG vias are located above gates G1 and G2. IC layout 700B includes cut-MD masks CMD1 and CMD2, which indicate where the source / drain contacts are segmented. Mask CMD2 corresponds to isolation region 704 separating source / drain contacts 763 and 764 in FIG7A . Mask CMD1 separates additional source / drain contacts 767 and 768 located above and in electrical contact with other source / drain electrodes of devices MP and MN, respectively, located in active regions 761 and 762. The extended VD vias VDR1 and VDR2 are correspondingly located above the source / drain contacts 767 and 768 and electrically contact the source / drain contacts 767 and 768 to electrically couple the source / drain contacts 767 and 768 to the M0 conductive patterns 730 and 736 (which are the VDD rail and the VSS rail, respectively).

[0118] The portion of IC layout 700B in FIG7C includes M0 conductive patterns 730-736, V0 vias 741-743, and M1 conductive patterns 740 and 744. V0 via 743 electrically couples M0 conductive pattern 733 to M1 conductive pattern 744, which constitutes input IN. In some embodiments, M0 conductive patterns 731-735 correspond to signal M0 conductive patterns located above a unit cell or short cell, as described with respect to FIG6 .

[0119] As shown in Figures 7A and 7C , the source / drain of device MP and the source / drain of device MN are electrically coupled via M1 conductive pattern 740. In one or more embodiments, this arrangement is suitable for cells with a relatively low OD density (e.g., unit cells, short cells, or cells with a small OD). In one or more embodiments, for cells with a high OD density (e.g., tall cells), additional conductors are provided parallel to M1 conductive pattern 740, as described with respect to Figures 7D to 7F .

[0120] FIG7D includes a schematic circuit diagram and a cross-sectional view of a circuit area of an IC device 700D according to some embodiments. In some embodiments, IC device 700D corresponds to one or more of IC devices 100A, 100B, 500A, and 700A. For simplicity, corresponding components in FIG7A and FIG7D are denoted by the same reference numerals.

[0121] IC device 700D in FIG7D is similar to IC device 700A in FIG7A , with the differences described herein. IC device 700D includes a FEOL structure 771 and a BEOL structure 702 . FEOL structure 771 differs from FEOL structure 701 of IC device 700A in that it includes extended source / drain contacts 773 in place of the source / drain contacts 763 and 764 of IC device 700A. Extended source / drain contacts 773 extend continuously along the Y-axis between active regions 761 and 762 . Thus, active regions 761 and 762 are electrically coupled to each other via a pair of parallel-coupled conductors (i.e., extended source / drain contacts 773 and M1 conductive pattern 740 ) to reduce resistance (sometimes referred to as "drain-side resistance"). In the exemplary configuration of FIG7D , extended source / drain contacts 773 further include a section 774 extending downward along the Z-axis. In some embodiments, the segment 774 of the extended source / drain contact 773 further contacts the active regions 761 and 762 along the Y-axis to further reduce resistance. In at least one embodiment, the segment 774 is omitted.

[0122] FIG7E and FIG7F are schematic diagrams of various layers of the IC layout 700E of the circuit area shown in FIG7D , according to some embodiments. FIG7D corresponds to a cross-sectional view taken along line AA in FIG7E and FIG7F . FIG7E illustrates a portion of the IC layout 700E corresponding to the FEOL structure 771. FIG7F illustrates another portion of the IC layout 700E corresponding to the BEOL structure 702. For simplicity, corresponding components in FIG7A through FIG7F are denoted by the same reference numerals.

[0123] The portion of layout 700E in FIG7F is identical to the portion of IC layout 700B in FIG7C . The portion of layout 700E in FIG7E is similar to the portion of layout 700B in FIG7B , except that IC layout 700E does not include mask CMD2 of IC layout 700B. Therefore, the extended source / drain contact 773 in IC layout 700E is not separated into source / drain contacts 763 and 764 as shown in IC layout 700B. Instead, the extended source / drain contact 773 in IC layout 700E extends continuously between active regions 761 and 762 to form a pair of parallel-coupled conductors together with M1 conductive pattern 740, as described herein.

[0124] In at least one embodiment, the parallel coupling arrangement described with respect to Figures 7D-7F is suitable for cells with high OD density (e.g., tall cells). In one or more embodiments, this arrangement reduces the resistance between the source / drain (e.g., drain) of device MP and the source / drain (e.g., drain) of device MN, thereby increasing current flow and providing speed improvements. The extended source / drain contacts 773 may create additional parasitic capacitance with adjacent conductive structures (e.g., gate electrodes). However, in at least one embodiment, the increased current outweighs any adverse effects associated with the potential additional parasitic capacitance, and the speed improvements achieved by the extended source / drain contacts 773 are further improved.

[0125] FIG8A is a schematic circuit diagram of a circuit region 800A of an IC device according to some embodiments. In some embodiments, circuit region 800A corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, 500A, 700A, and 700D.

[0126] Circuit area 800A includes a multi-stage circuit, such as a buffer, an AND gate, an OR gate, or the like. In the exemplary configuration of FIG8A , the multi-stage circuit includes two stages, each of which is an inverter. Specifically, the first stage includes inverter INV1, and the second stage includes inverter INV2. In at least one embodiment, inverters INV1 and INV2 correspond to the inverter INV described with respect to FIG7A through FIG7F . Other numbers of stages are also within the scope of various embodiments. Other circuit configurations for each stage are also within the scope of various embodiments.

[0127] Inverter INV1 has an input IN1 and an output ZN1. Inverter INV2 has an input IN2 and an output ZN2. Input IN2 of inverter INV2 is coupled to output ZN1 of inverter INV1. Inverter INV1 is configured to receive input signal 821 at input IN1. Inverter INV1 is configured to output an intermediate signal 822 at output ZN1 based on input signal 821. Intermediate signal 822 is input to inverter INV2 via input IN2, and inverter INV2 is configured to output an output signal 823 at output ZN2 based on intermediate signal 822. In some embodiments, to achieve one or more PPA improvements in a multi-stage circuit, inverter INV1, as the first stage, is configured to reduce input impedance and / or capacitance, while inverter INV2, as the second stage, is configured to provide a higher drive current than inverter INV1. Therefore, in one or more embodiments, an improved stage ratio and performance of a multi-stage circuit can be achieved. An exemplary layout of the multi-stage circuit is described with respect to FIG. 8B .

[0128] FIG. 8B is a schematic diagram of an IC layout 800B of the circuit area 800A in FIG. 8A , according to some embodiments.

[0129] IC layout 800B includes a short cell 831 having a cell height HS and a tall cell 832 having a cell height HT. In one or more embodiments, cells 831 and 832 are arranged along the Y-axis in configuration 802, which corresponds to the configuration of subgroup 402 or subgroup 602. Cell 831 includes an active region 851 constituting an N-type device N1 and an active region 852 constituting a P-type device P1. Although not shown in FIG8B , cell 831 further includes various conductive structures, vias, and patterns corresponding to those described with respect to one or more of FIG7B , FIG7C , FIG7E , and FIG7F . These various conductive structures, vias, and patterns couple the P-type device P1 and the N-type device N1 to an inverter corresponding to inverter INV1.

[0130] Cell 832 includes an active region 861 that constitutes a P-type device P2 and an active region 862 that constitutes an N-type device N2. Although not shown in FIG8B , cell 832 further includes various conductive structures, vias, and patterns corresponding to the conductive structures, vias, and patterns described with respect to one or more of FIG7B , FIG7C , FIG7E , and FIG7F . These various conductive structures, vias, and patterns couple the P-type device P2 and the N-type device N2 to an inverter corresponding to inverter INV2.

[0131] As described with respect to FIG8A , the output of inverter INV1 in cell 831 is coupled to the input of inverter INV2 in cell 832. In this example, cell 832 has the layout shown in FIG7C , while cell 831 has the layout shown in FIG7C but is horizontally flipped across the Y-axis. A single M1 conductive pattern extends continuously from cell 831 into cell 832 and constitutes both the output of cell 831 and the input of cell 832. Therefore, the output of inverter INV1 in cell 831 is coupled to the input of inverter INV2 in cell 832, forming a multi-stage circuit, as described with respect to FIG8A .

[0132] In IC layout 800B, cell 831 is a short cell with a small OD, such as described for cell 340. In at least one embodiment, cell 831 is a short cell, such as described for cell 330. Due to the reduced size of cell 831 (e.g., cell height and / or active region width), the requirements for reduced input impedance and / or lower capacitance of the first stage formed by cell 831 can be met. On the other hand, cell 832 is a tall cell, such as described for cell 350. As described herein, such tall cells have a higher current capacity than shorter cells. Therefore, the requirements for high drive current of the second stage formed by cell 832 can be met. In some embodiments, one or more PPA improvements described herein can be achieved by configuring the first stage of a multi-stage circuit in a short cell and the second stage in a tall cell.

[0133] FIG9A is a schematic diagram of an IC layout 900A of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, 500A, 700A, and 700D.

[0134] IC layout 900A includes a hybrid column cell array having columns 901 through 912 of varying heights arranged along the Y-axis. Columns 901 through 902, 905 through 906, and 909 through 910 are tall columns having a height HT (not shown in FIG. 9A ), while columns 903 through 904, 907 through 908, and 911 through 912 are short columns having a height HS (not shown in FIG. 9A ). In some embodiments, IC layout 900A includes multiple power rails including alternating VDD and VSS rails along the boundaries between the columns, as described with respect to FIG. 5B .

[0135] During the design phase, critical paths 950 are identified in IC layout 900A. A critical path is a timing-sensitive path along which a signal propagates during operation. In one example, a critical path is a path with a time delay that does not meet (i.e., exceeds) timing requirements. In another example, a critical path is a path with a long delay (in some cases, the longest time delay) within a circuit region of an IC device or within the entire IC device. A long delay is a delay that may meet timing requirements but is still greater than a predetermined threshold. During the design phase, the time delays of various paths in the IC design of the IC device are estimated by one or more simulations, for example, performed before or after an APR operation. Based on the results of such simulations, one or more critical paths are identified. In some embodiments, reducing the time delay of a critical path is necessary to meet timing requirements or desirable to improve the performance of the IC device.

[0136] In the example configuration of FIG. 9A , once a critical path (e.g., critical path 950) is identified, IC design or IC layout 900A is modified to reduce the time delay of critical path 950. To reduce the time delay of critical path 950 in IC layout 900A, in one or more embodiments, one or more cells in IC layout 900A are rerouted and / or reconfigured to route critical path 950 through cells configured for speed or performance (e.g., through tall cells and / or merged cells). For example, FIG. 9A illustrates critical path 950 after IC layout 900A has been modified, with critical path 950 being routed through tall cells 921, 922, 924, 925, 927 and merged cells 923, 926, and 928. In some embodiments, cells in short columns are reconfigured (e.g., merged) into one or more merged cells to provide merged cells 923, 926, and 928. In at least one embodiment, as described herein, merged cells can be configured to provide improved performance (e.g., higher speed, lower latency) compared to higher-speed cells. Merged cells 923, 926, and 928 enable high performance and reduced latency even when critical path 950 passes through short columns that are typically not configured for high speed. In at least one embodiment, the use of one or more merged cells further shortens critical path 950, thereby reducing the latency of the critical path and / or reducing the dragging effect observed when the critical path is too long and passes through unnecessary columns. In some embodiments, after making improvements, one or more simulations are re-run to confirm that path 950 is no longer a critical path. In at least one embodiment, when generating an IC layout from an IC design (IC schematic), the routing and / or merged cell placement to reduce the path's latency is performed during the first APR run, rather than as an improvement to an existing IC layout.

[0137] FIG9B is a schematic diagram of an IC layout 900B of a circuit region of an IC device according to some embodiments. In some embodiments, the circuit region corresponds to region 103 or a portion thereof. In at least one embodiment, the IC device corresponds to one or more of IC devices 100A, 100B, 500A, 700A, and 700D. In at least one embodiment, IC layout 900A and IC layout 900B are part of the same IC layout of the same IC device. For simplicity, corresponding components in FIG9A and FIG9B are represented by the same reference numerals.

[0138] Compared to IC layout 900A, which illustrates examples of cells along the critical path (sometimes referred to as "critical cells"), IC layout 900B illustrates examples of cells outside the critical path (sometimes referred to as "non-critical cells"). In some embodiments, non-critical cells do not need to provide high current or high speed and are configured with a small active region width to improve (e.g., reduce) power and / or area. In the example configuration of FIG9B , non-critical cells are configured as tall cells with a small OD, short cells, or short cells with a small OD. FIG9B shows two example tall cells with a small OD 941 and 942 and two short cells 943 and 944. In at least one embodiment, at least one of cells 943 and 944 is a short cell with a small OD. In some embodiments, the tall cells with a small OD, the short cells, and the short cells with a small OD in IC layout 900B correspond to cells 360, 330, and 340. In at least one embodiment, using tall cells with small OD for non-critical cells improves at least power consumption, while using short cells and / or short cells with small OD for non-critical cells improves both power and area.

[0139] FIG10 is a table 1000 illustrating routing features of various cells that may be placed in an IC layout according to some embodiments. Example IC layouts are described with respect to one or more of FIG2A-2C, FIG3, FIG4A-4C, FIG5A-5B, FIG6, FIG7B-7C, FIG7E-7F, FIG8B, FIG9A, and FIG9B.

[0140] In some embodiments, routing features include BEOL features (e.g., metal layers, via layers, or similar features), as described with respect to Figures 6, 7A, and 7D. In the example of Figure 10, routing features include M0 tracks, M2 tracks, M0 PG widths, M2 structures, via 0 (VIA0), and via 1 (VIA1), corresponding to columns 1001 through 1005 of table 1000. The M0 track includes the width and layout of the M0 conductive pattern, for example, as described with respect to Figure 6. The M2 track includes the width and layout of the M2 conductive pattern. The M0 PG (power-ground) width represents the width of the M0 conductive pattern configured as a VDD rail (power) and a VSS rail (ground). The M2 structure includes further details of the M2 track. Via 0 includes the dimensions of the V0 via. Via 1 includes the dimensions of the V1 via. Other routing features are also within the scope of various embodiments.

[0141] FIG10 illustrates the wiring characteristics of three example cells: the unit cell in row 1010, the short cell in row 1030, and the tall cell in row 1050 of table 1000. The unit cell shown in row 1010 can be placed in a single-height cell array with a single-column height configuration, such as described with respect to FIG5A-5B. Correspondingly, the short cell and tall cell shown in rows 1030 and 1050 can be placed in a mixed-column cell array with a mixed-column height configuration of two short cells and two tall cells, such as described with respect to FIG9A-9B. In some embodiments, the unit cell, short cell, and tall cell shown in table 1000 can be placed in an integrated cell array, such as described with respect to FIG4A-4C, FIG5A, and FIG6. In at least one embodiment, the short cell and tall cell shown in table 1000 can be placed in other mixed-column configurations, such as described with respect to FIG2A-2C and FIG8B. In some embodiments, the routing features for unit cells shown in FIG10 are also applicable to unit cells with small ODs and a portion of merged cells located above a unit column. The routing features for short cells shown in FIG10 are also applicable to short cells with small ODs and a portion of merged cells located above a short column. The routing features for tall cells shown in FIG10 are also applicable to tall cells with small ODs and a portion of merged cells located above a tall column.

[0142] For the unit cell in row 1010 of table 1000, the M0 rail corresponds to the rail described for the unit cell in Figure 6 . Five signal M0 conductive patterns with width W1 (corresponding to width M in Figure 6 ) are arranged along the Y-axis between two M0 conductive patterns, respectively configured as the VDD and VSS rails. The VDD and VSS rails have the same width PG1, where PG1 > W1. For the M2 rail, seven M2 conductive patterns are arranged above the cell, and all seven M2 conductive patterns have the same width W2, where W2 > W1. The V0 and V1 vias have the same dimensions D1 × D1.

[0143] For the short cell in row 1030 of table 1000, the M0 rail is similar to the rail in row 1010, except that the VDD rail has a width PG3 that is greater than the width PG1 of the VSS rail. For the M2 rail, four M2 conductive patterns with a width of W2 are arranged between the VDD and VSS rails, without overlapping them. One M2 conductive pattern overlaps the VSS rail and has a width of W5. Another M2 conductive pattern overlaps the VDD rail and has a width of W4, where W4 > W5 > W2. The V0 via has the same dimensions D1 × D1 as the V0 via in the unit cell, while the V1 via has a larger dimension of D2 × D2, where D2 > D1.

[0144] For the tall cells in row 1050 of table 1000, the VDD rail has the same width PG3 as the short cells in row 1030. The VSS rail has a larger width PG4, where PG4 > PG3. The two signal M0 conductive patterns 1052 and 1054 have a width W2. The signal M0 conductive pattern 1053 between these two patterns has a width W3, where W3 > W2. The two signal M0 conductive patterns 1051 and 1055 adjacent to the VDD and VSS rails, respectively, have a width W4, where W4 > W3. In some embodiments, the M0 conductive patterns 1051, 1053, and 1055 correspond to one M0 mask, while the VDD and VSS rails and the M0 conductive patterns 1052 and 1054 correspond to another M0 mask. For the M2 rail, two M2 conductive patterns overlap the VDD and VSS rails, respectively, and four M2 conductive patterns are arranged between the VDD and VSS rails without overlapping them. All six M2 conductive patterns have the same width, W4. The V0 vias include a first V0 via with dimensions D2 × D2 and a second V0 via with larger dimensions, D3 × D3, where D3 > D2 > D1. The first V0 via with smaller dimensions, D2 × D2, couples with M0 conductive patterns 1052 and 1054, which have a smaller width, W2. The second V0 via with larger dimensions, D3 × D3, couples with M0 conductive patterns 1051, 1053, and 1055, which have larger widths, W4 or W3. The V1 via has dimensions D2 × D2.

[0145] In the example configuration of FIG10 , the tall cells in row 1050 have wider M0 and M2 conductive patterns and similarly larger V0 vias compared to the unit cells in row 1010 and the short cells in row 1030, achieving lower resistance and higher speed. The narrower signal M0 and M2 conductive patterns of the unit cells in row 1010 and the short cells in row 1030 are configured to improve power and / or area. In some embodiments, a hybrid column cell array with short and tall cells and the corresponding routing features shown in rows 1030 and 1050 provide performance improvements compared to a single-height cell array with the unit cells in row 1010. In at least one embodiment, the performance improvement includes an approximately 4.5% speed increase at the cell array's maximum operating frequency.

[0146] FIG11 is a flow chart of a method 1100 for designing and / or manufacturing an IC device, according to some embodiments. In some embodiments, method 1100 may be used to design and / or manufacture one or more IC devices described herein. According to some embodiments, method 1100 may be implemented, for example, using an EDA system and / or a manufacturing system as discussed below.

[0147] At operation 1102, a layout diagram is generated that includes one or more of the layouts of the various circuits disclosed herein or similar layouts, etc. According to some embodiments, operation 1102 may be implemented, for example, using an EDA system discussed below. Examples of the layout diagram obtained at operation 1102 include one or more of the layout diagrams described herein.

[0148] At operation 1104, based on the layout, at least one of (A) one or more photolithographic exposures is performed, (B) one or more semiconductor masks are fabricated, or (C) one or more components in a layer of an IC device are fabricated. According to some embodiments, operation 1104 can be implemented, for example, using a manufacturing system discussed below. Examples of the IC device obtained at operation 1104 include one or more IC devices described herein. In some embodiments, operation 1104 is omitted.

[0149] 12 is a flow chart of a method 1200 for generating an IC layout for a circuit region of an IC device, according to some embodiments. In some embodiments, method 1200 is an example of at least a portion of operation 1102. In at least one embodiment, method 1200 may be implemented, at least in part, using a processor in an EDA system, such as discussed below.

[0150] At operation 1205, a circuit area for which an IC layout is to be generated is received. In some embodiments, the circuit area includes all circuitry of the IC device. In at least one embodiment, the circuit area includes circuitry of a portion of the IC device and corresponds to, for example, one or more of the circuit areas described with respect to FIG. 5A . In some embodiments, the circuit area is received in the form of an IC schematic (i.e., an electrical diagram) for the circuit area. In some embodiments, the schematic is generated or provided in the form of a schematic netlist (e.g., a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist). Other data formats for describing the design, such as Verilog, are also available in some embodiments.

[0151] In some embodiments, various cell groups of different cell heights are obtained. For simplicity, a first cell having a first cell height and a second cell having a second cell height are obtained. In an example, the first cell is a tall cell and the second cell is a short cell. In some embodiments, as described with respect to FIG. 3 , one or more tall cells having different values of one or more of HT, WT, and W SM and / or one or more short cells having different values of one or more of HS, WS, and W SM are obtained from a cell library. In at least one embodiment, at least one tall cell or short cell is derived from a preset unit cell by an EDA system. For example, as described herein, the H and W of the preset unit cell are used in combination with one or more of relations (1) to (6) and a set of predetermined design rules to generate tall cells and / or short cells that satisfy the set of design rules and can be used to achieve one or more PPA improvements. In some embodiments, all or part of operation 1205 is omitted.

[0152] At operation 1210, an equivalent cell height (e.g., HE) of the resulting IC layout is determined based on the application to be implemented by the circuit area. For example, a pre-prepared lookup table is accessed, as described herein. The lookup table associates different HE values with various applications and / or circuit areas. For example, high-speed applications are associated with high HE values, while low-power applications are associated with low HE values. The application of the circuit area is input into the lookup table, which returns the HE value that matches or is closest to the input application.

[0153] At operation 1215, based on the determined equivalent cell height, the cell column configuration includes at least one first column having a first height and at least one second column having a second height different from the first height. An exemplary cell column configuration is described with respect to FIG. 2C. In at least one embodiment, various cell column configurations are pre-developed and associated with corresponding HE values, for example in the same lookup table or another lookup table, the determined HE is input into the lookup table, and the lookup table returns the corresponding cell column configuration. In some embodiments, the determined HE is used together with the HT and HS of the tall cells and short cells obtained at operation 1205 to calculate R mix based on relationship (9). Based on the calculated R mix and relationship (8), the number of tall columns and the number of short columns in the cell column configuration to be used can be determined. For example, when the calculated R mix is 3, the cell column configuration 261 in FIG. 2C is used to generate the IC layout.

[0154] At operation 1220, a cell array is generated based on the determined cell column configuration. For example, assuming that at operation 1215 it was determined that a cell column configuration comprising two short columns and two tall columns (2 short, 2 tall) would be used, the determined cell column configuration is repeated multiple times along the Y-axis to cover the floor plan of the IC layout. The resulting cell array includes a repeating pattern of 2 short columns, 2 tall columns, 2 short columns, 2 tall columns, and so on along the Y-axis, as shown, for example, in FIG5C . In at least one embodiment, at this stage, no cells have yet been placed in the generated cell array.

[0155] At operation 1225, one or more routing characteristics are determined for the cells to be placed in the generated cell array. An example of the routing characteristics to be determined is described with respect to FIG. 10 . In at least one embodiment, routing characteristics are determined for each cell based on cell height, active area width, and / or various design rules. As described with respect to FIG. 10 , routing characteristics for short and tall cells vary in various states to optimize one or more of the PPAs. In some embodiments, operation 1225 is omitted, and the routing characteristics are determined by an APR tool when performing an APR operation as described herein.

[0156] At operation 1230, a place and route operation is performed to generate an IC layout for the circuit area. During the place and route operation, one or more first cells having a first height are placed in one or more first columns having the first height in the generated cell array, and one or more second cells having a second height are placed in one or more second columns having the second height in the generated cell array. In at least one embodiment, the place and route operation includes an APR operation performed by an APR tool or system. For example, based on an IC schematic for the circuit area, the APR tool places cells corresponding to various functions of the IC schematic in the generated cell array. When cells having a specific function (e.g., an AND gate) are placed in tall columns in the cell array, tall cells having the specific function (e.g., an AND gate) are placed. Similarly, when cells having a specific function are placed in short columns in the cell array, short cells having the specific function are placed.

[0157] After the placement operation is completed, a routing operation is performed to couple the placed cells according to the IC schematic. In some embodiments, the routing operation is performed based on the routing characteristics determined at operation 1225. In at least one embodiment, the routing operation is performed based on other routing characteristics and / or design rules.

[0158] According to some embodiments, during the APR operation, one or more of operations 1235 to 1238 are performed to achieve further PPA improvement. In some embodiments, one or more of operations 1235 to 1238 are omitted.

[0159] At operation 1235, to configure a multi-stage circuit in the circuit region, one or more short cells are placed and routed to form an earlier stage or input stage, while tall cells are placed and routed to form a later stage or output stage, as described with respect to FIG8A-8B. Thus, in one or more embodiments, low input impedance / capacitance and high drive current can be achieved.

[0160] At operation 1236, for cells with high OD density (e.g., tall cells), where the source / drain of a P-type device is coupled to the source / drain of an N-type device via an M1 conductive pattern, extended source / drain contacts (MD) are used to form parallel conductors with the M1 conductive pattern, as described with respect to Figures 7D-7F. Consequently, in one or more embodiments, resistance can be reduced and speed can be increased. In some embodiments, the changes required to create the extended MD in the existing cell layout are as simple as removing the mask that cuts the MD.

[0161] At operations 1237 and 1238, when a critical path is identified in the IC layout, in one or more embodiments, at least one of critical cells along the critical path or non-critical cells outside the critical path may be optimized. In at least one embodiment, to optimize critical cells along the critical path, cells configured for speed (e.g., merged cells, tall cells) are placed or created along the path to reduce the time delay and / or length of the path, as described with respect to FIG. 9A . In some embodiments, to optimize non-critical cells outside the critical path, cells configured for power and / or area (e.g., short cells, cells with small OD) are placed to improve power and / or area, as described with respect to FIG. 9B .

[0162] After the placement and routing operations, the generated IC layout is subjected to one or more verifications and / or simulations and / or modifications prior to fabrication. In at least one embodiment, one or more advantages described herein can be achieved by one or more IC layouts generated by method 1200 and / or IC devices fabricated based on such IC layouts.

[0163] The methods described include example operations, which do not necessarily need to be performed in the order shown. Operations may be added, replaced, changed in order, and / or eliminated as appropriate, consistent with the spirit and scope of the disclosed embodiments. Combinations of different features and / or different embodiments are also within the scope of the disclosed embodiments and will be readily apparent to those skilled in the art upon reading this disclosure.

[0164] In some embodiments, at least one or more of the methods discussed above are implemented in whole or in part by at least one EDA system. In some embodiments, the EDA system can be used as part of a design house of an IC manufacturing system discussed below.

[0165] FIG13 is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0166] In some embodiments, the EDA system 1300 includes an automatic placement and routing (APR) system. According to some embodiments, the method of designing a layout diagram representing a wire routing arrangement according to one or more embodiments described herein may be implemented, for example, using the EDA system 1300.

[0167] In some embodiments, EDA system 1300 is a general-purpose computing device that includes a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. Storage medium 1304 is encoded with (i.e., stores) computer program code 1306 (i.e., a set of executable instructions), among other elements. Execution of instructions 1306 by hardware processor 1302 represents an EDA tool that (at least partially) implements a portion or all of the methods described herein (hereinafter, the proposed processes and / or methods) according to one or more embodiments.

[0168] The processor 1302 is electrically coupled to the computer-readable storage medium 1304 via a bus 1308. The processor 1302 is also electrically coupled to an input / output (I / O) interface 1310 via the bus 1308. A network interface 1312 is also electrically connected to the processor 1302 via the bus 1308. The network interface 1312 is connected to a network 1314, enabling the processor 1302 and the computer-readable storage medium 1304 to connect to external components via the network 1314. The processor 1302 is configured to execute computer program code 1306 encoded on the computer-readable storage medium 1304 to enable the system 1300 to perform part or all of the processes and / or methods described herein. In one or more embodiments, the processor 1302 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0169] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1304 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0170] In one or more embodiments, storage medium 1304 stores computer program code 1306 configured to enable system 1300 (where such execution represents (at least in part) an EDA tool) to implement part or all of the proposed process and / or method. In one or more embodiments, storage medium 1304 also stores information that facilitates implementation of part or all of the proposed process and / or method. In one or more embodiments, storage medium 1304 stores a standard cell library 1307 including standard cells such as those disclosed herein.

[0171] EDA system 1300 includes an I / O interface 1310. I / O interface 1310 is coupled to external circuitry. In one or more embodiments, I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor keys for communicating information and commands to processor 1302.

[0172] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 enables system 1300 to communicate with a network 1314, which is connected to one or more other computer systems. Network interface 1312 includes a wireless network interface, such as Bluetooth, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA), or a wired network interface, such as Ethernet, universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In one or more embodiments, part or all of the proposed process and / or method is implemented in two or more systems 1300 .

[0173] System 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of instructions, data, design rules, a standard cell library, and / or other parameters to be processed by processor 1302. This information is transmitted to processor 1302 via bus 1308. EDA system 1300 is also configured to receive information related to a user interface (UI) via I / O interface 1310. This information is stored as UI 1342 in computer-readable storage medium 1304.

[0174] In some embodiments, part or all of the proposed process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the proposed process and / or method is implemented as a software application that is part of an add-on software application. In some embodiments, part or all of the proposed process and / or method is implemented as a plug-in to the software application. In some embodiments, at least one of the proposed process and / or method is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the proposed process and / or method is implemented as a software application used by EDA system 1300. In some embodiments, a layout diagram including standard cells is generated using a tool (e.g., VIRTUOSO® available from Cadence Design Systems, Inc. or another suitable layout generation tool).

[0175] In some embodiments, the process is implemented in the form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more of an optical disc (e.g., a DVD), a magnetic disc (e.g., a hard disk), a semiconductor memory (e.g., ROM, RAM), a memory card, and the like.

[0176] 14 is a block diagram of an integrated circuit (IC) fabrication system 1400 and an IC fabrication process associated with IC fabrication system 1400, according to some embodiments. In some embodiments, fabrication system 1400 is used to fabricate, based on a layout, at least one of: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0177] In FIG14 , IC manufacturing system 1400 includes entities such as a design organization 1420, a mask house 1430, and an IC manufacturer / fab 1450. These entities interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 1460. The entities in system 1400 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and / or receives services from one or more of the other entities. In some embodiments, a single, larger company owns two or more of design organization 1420, mask house 1430, and IC fab 1450. In some embodiments, two or more of the design facility 1420, the mask facility 1430, and the IC foundry 1450 are co-located in a common facility and utilize common resources.

[0178] Design organization (or design team) 1420 generates an IC design layout 1422. IC design layout 1422 includes various geometric patterns designed for IC device 1460. These geometric patterns correspond to the patterns of metal layers, oxide layers, or semiconductor layers that comprise the various components of IC device 1460 to be fabricated. These layers combine to form various IC features. For example, a portion of IC design layout 1422 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) (e.g., active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads), as well as various material layers disposed on the semiconductor substrate. Design organization 1420 implements an appropriate design process to generate IC design layout 1422. The design process includes one or more of logical design, physical design, or place and route operations. IC design layout 1422 is presented in the form of one or more data files containing information about the geometric patterns. For example, IC design layout 1422 can be expressed in a GDSII file format or a DFII file format.

[0179] Mask mechanism 1430 includes data preparation 1432 and mask fabrication 1444. Mask mechanism 1430 uses IC design layout 1422 to create one or more masks 1445 based on IC design layout 1422 for use in fabricating various layers of IC device 1460. Mask mechanism 1430 performs mask data preparation 1432, translating IC design layout 1422 into a representative data file (RDF). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) 1445 or a semiconductor wafer 1453). Mask data preparation 1432 manipulates design layout 1422 to conform to the specific characteristics of the mask writer and / or the requirements of IC foundry 1450. 14, mask data preparation 1432 and mask production 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask production 1444 may be collectively referred to as mask data preparation.

[0180] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, crosstalk, other process effects, and the like). OPC adjusts IC design layout 1422. In some embodiments, mask data preparation 1432 further includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0181] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that checks the IC design layout 1422, which has undergone the OPC process, against a set of mask generation rules containing certain geometric constraints and / or connectivity constraints to ensure that sufficient margins are in place to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for constraints during mask fabrication 1444, which may undo some of the modifications performed by the OPC to satisfy the mask generation rules.

[0182] In some embodiments, mask data preparation 1432 includes lithography process checking (LPC), which simulates the process to be performed by IC foundry 1450 to fabricate IC device 1460. LPC simulates this process based on IC design layout 1422 to generate a simulated manufactured device, such as IC device 1460. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC may take into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated manufactured device is generated by LPC, if the simulated device's shape is not sufficiently close to meet design rules, OPC and / or MRC are repeated to further refine IC design layout 1422.

[0183] It should be understood that the above description of mask data preparation 1432 has been simplified for the sake of clarity. In some embodiments, data preparation 1432 includes additional features, such as modifying logic operations (LOPs) of IC design layout 1422 based on manufacturing rules. Furthermore, the processes applied to IC design layout 1422 during data preparation 1432 can be performed in a variety of different orders.

[0184] After mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 are fabricated based on the modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more lithographic exposures based on the IC design layout 1422. In some embodiments, an electron beam (e-beam) or a mechanism comprising multiple electron beams is used to form a pattern on a mask (photomask or reticle) 1445 based on the modified IC design layout 1422. Mask 1445 can be formed using various techniques. In some embodiments, mask 1445 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1445 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1445, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1444 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in semiconductor wafer 1453, in an etching process to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0185] IC foundry 1450 is an IC fabrication company that includes one or more fabrication facilities for producing a variety of different IC products. In some embodiments, IC foundry 1450 is a semiconductor foundry. For example, one fabrication facility may be used for front-end fabrication (front-end of line (FEOL) fabrication) of multiple IC products, while a second fabrication facility may provide back-end of line (BEOL) fabrication for interconnects and packaging of IC products. A third fabrication facility may provide other services for the foundry.

[0186] IC foundry 1450 includes fabrication tools 1452 configured to perform various fabrication operations on semiconductor wafers 1453, thereby fabricating IC devices 1460 based on masks (e.g., mask 1445). In various embodiments, fabrication tools 1452 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0187] IC foundry 1450 uses mask 1445 produced by mask mechanism 1430 to fabricate IC device 1460. Thus, IC foundry 1450 at least indirectly uses IC design layout 1422 to fabricate IC device 1460. In some embodiments, IC foundry 1450 uses mask 1445 to fabricate semiconductor wafer 1453 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1453 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent fabrication steps).

[0188] In some embodiments, an integrated circuit (IC) device includes multiple columns comprised of semiconductor devices. The columns extend along a first axis and are arranged side by side along a second axis transverse to the first axis. The columns include: a first column having a first height along the second axis; and a second column having a second height along the second axis. The second height is less than the first height. Each of the columns includes: a first active region of a first conductivity type; and a second active region of a second conductivity type different from the first conductivity type. The second active region is spaced apart from the first active region along the second axis. Along the second axis, the first width of the first active region or the second active region in the first column is greater than the second width of the first active region or the second active region in the second column.

[0189] In some embodiments, an integrated circuit (IC) layout is stored on a non-transitory computer-readable storage medium. The IC layout includes a first circuit area and a second circuit area. Each of the first circuit area and the second circuit area includes: a first cell having a first cell height along a cell height direction; a second cell having a second cell height along the cell height direction, the second cell height being smaller than the first cell height; and an equivalent cell height corresponding to the first cell height, the second cell height, the number of rows of the first cell, and the number of rows of the second cell. The equivalent cell height of the first circuit area is different from the equivalent cell height of the second circuit area.

[0190] In some embodiments, a method for generating an integrated circuit (IC) layout for a circuit region is performed, at least in part, by a processor. The method includes determining an equivalent cell height based on an application to be performed by the circuit region. The method further includes determining a cell column configuration based on the determined equivalent cell height, the cell column configuration including at least one first column having a first height and at least one second column having a second height different from the first height. The method further includes generating a cell array based on the determined cell column configuration. The method further includes performing a place and route operation to generate the IC layout for the circuit region. The place and route operation includes, based on the circuit region, placing one or more first cells having a first height in one or more first columns having the first height in the generated cell array; and placing one or more second cells having a second height in one or more second columns having the second height in the generated cell array.

[0191] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

[0192] 100A, 100B, 500A, 700A, 700D, 1460: IC devices 101: Macro 103, 511, 512, 513, 514, 515, 516, 521, 522, 531, 532, 533, 534, 535, 541, 542, 543, 544, 551, 552, 561, 562, 563, 571, 572, 581, 582, 583, 584, 585: District 110: Base 111, 121: Semiconductor devices 112, 122: base part 114, 704: Isolation Area 116, 118: Gate electrode 124, 134: Nanosheet stacking 126, 136: Gate dielectric layer 200, 400A, 500B, 500C, 600, 800B, 900A, 900B: IC layout 201, 202, 203, 204: Boundary lines 210, 596, 597: column / high column 211, 214, 216, 217: Gate region / dummy gate region 212, 213, 215: Gate region 220, 230, 594, 595, 598, 599: column / short column 221: N-type well region 222, 224: Partial / P-type base region 223: Partial / N-type well region 226, 227, 228: Part 231, 232, 233, 234, 235, 236, 237, 238, 239, 242: Active area / part 240, 241: Active area / partial / merged active area 245, 246, 247, 475, 476, 477: Virtual active zone 250: Cutting gate area mark 251, 254, 255: Active area / first active area 252, 253, 256: Active area / second active area 261, 262, 263, 264, 265, 400B, 400C: Cell column configuration 271, 272, 273, 275, 404: High 274, 276, 277, 278, 406: short column 300: Cell library 310, 320, 330, 340, 350, 360: cells 401: Subgroup / First Subgroup 402: Subgroup / Second Subgroup 403, 405: Unit column 410, 420: cell / unit cell 411, 412, 421, 422, 441, 442, 451, 452, 471, 473, 761, 762, 851, 852, 861, 862: Active area 440, 831, 943, 944, C3, C4: Cell / Short Cell 450, 921, 922, 924, 925, 927, 941, 942: high cells 470, 923, 926, 928: Merged cells 472: Active area / Merged active area 501, 502, 504: Area / Circuit Area 503, 800A: Circuit area 505, 506, 507, 508, 509, 510: Unit columns 601, 602: Subgroup 611, 617, 623, 630, 636, 641: M0 conductive pattern / power rail 612, 613, 614, 615, 616, 631, 632, 633, 634, 635, 637, 638, 639, 640, 1051, 1052, 1053, 1054, 1055: M0 conductive pattern / signal M0 conductive pattern 618, 619, 620, 621, 622, 730, 731, 732, 733, 734, 735, 736: M0 conductive pattern 700B, 700E: Layout / IC Layout 701:Structure / FEOL structure / First structure 702:Structure / BEOL Structure / Second Structure 703: dielectric layer 705: Interlayer dielectric (ILD) layer 740, 744: M1 conductive pattern 741, 742, 743: V0 through-hole 763, 764, 767, 768, MD: Source / Drain Contacts 765, 766: through-hole to device (VD) through-hole 771:FEOL structure 773: Extended source / drain contacts 774: Segment 802: Configuration 821: Input signal 822: Middle signal 823: Output signal 832, C1, C2: Cell / High Cell 901, 902, 903, 904, 905, 906, 907, 908, 909, 910, 911, 912, 1001, 1002, 1003, 1004, 1005: Column 950: Critical Path / Path 1000:Table 1010, 1030, 1050: OK 1100, 1102, 1104, 1205, 1210, 1215, 1220, 1225, 1230, 1235, 1236, 1237, 1238: Operation 1200: Method 1300: Electronic Design Automation (EDA) Systems / Systems 1302: Processor / Hardware Processor 1304: Storage media / computer readable storage media 1306: Computer code / instructions 1307: Standard Cell Library 1308: Bus 1310: Input / Output (I / O) Interface 1312: Network Interface 1314: Internet 1342: User Interface (UI) 1400: Integrated Circuit (IC) Manufacturing System / Manufacturing System / System 1420:Design Agency 1422:IC Design Layout / Design Layout 1430: screen mechanism 1432:Mask Data Preparation / Data Preparation 1444:Mask Production 1445: veil 1450: IC foundry / IC manufacturer / fabricator 1452:Making Tools 1453:Semiconductor Wafer AA, CC: line C5: Cell / Merged Cell CMD1, CMD2: mask CPO: Cutting gate area mark D1, D2, D3: Dimensions G1, G2: Gate H: height / cell height / unit cell height / unit height HE, HE1, HE2, HE3: Equivalent cell height HS, HT: cell height / height IN, IN1, IN2: input INV, INV1, INV2: inverters M: Width / Active Area Width M0 PG, PG1, PG3, PG4, w, W1, W2, W3, W4, W5: Width MN:N type device / device MP:P type device / device MS: Metal Width / Minimum Metal Width MT: Metal width / active area width N1, N2: N-type device P1, P2: P-type device Rmix, Rmix1, Rmix2, Rmix3: Mixed column ratios S: Spacing SH: Single Height Sx: Predetermined minimum spacing VDD, VSS: rail VDR1, VDR2: Extended VD through hole W: Active area width / unit active area width WM, WM1, WM2, WT: Active area width WS: Active area width / minimum active area width WSM: Reduced active area width / smaller active area width ZN, ZN1, ZN2: output

Claims

1. An integrated circuit device, comprising: A plurality of columns comprising semiconductor devices, the plurality of columns extending along a first axis and arranged side-by-side along a second axis spanning the first axis, wherein the plurality of columns include: a first column having a first height along the second axis; a second column having a second height along the second axis, the second height being less than the first height; and a third column, each of the plurality of columns including: a first active region of a first conductivity type; and a second active region of a second conductivity type different from the first conductivity type, the second active region being spaced apart from the first active region along the second axis, and along the second axis, a first width of the first active region or the second active region in the first column being greater than a second width of the first active region or the second active region in the second column; the first active region of the third column being merged with the first active region of one of the first column and the second column to form a merged first active region, and the merged first active region being arranged along the second axis between the second active region of the third column and the second active region of one of the first column and the second column.

2. The integrated circuit device as claimed in claim 1, wherein the plurality of columns comprises a repeating pattern of a set of columns along the second axis, and the set of columns comprises the first column and the second column.

3. The integrated circuit device as claimed in claim 2, wherein the set of columns comprises at least one of: a first sub-group of columns, each having the first height along the second axis, the first sub-group of columns comprising the first column; or a second sub-group of columns, each having the second height along the second axis, the second sub-group of columns comprising the second column.

4. The integrated circuit device as claimed in claim 1, wherein the plurality of columns further includes a third column having a third height along the second axis, the third height being less than the first height and greater than the second height, and in the third column, the first active region or the second active region having a third width along the second axis, the third width being less than the first width and greater than the second width.

5. The integrated circuit device as claimed in claim 1, satisfying at least one of the following: In the first column, the first active region or the second active region includes: The first active region or the second active region includes: a portion having the first width, and another portion having a reduced first width, which is less than the first width, or in the second column, the first active region includes: a portion having the second width, and another portion having a reduced second width, which is less than the second width.

6. The integrated circuit arrangement as claimed in claim 1, wherein the third column has the same height along the second axis as one of the first column and the second column.

7. An integrated circuit (IC) layout stored on a non-transitory computer-readable storage medium, the integrated circuit layout comprising: First circuit region; The first circuit region and the second circuit region each include: a plurality of first cells having a first cell height along the cell height direction; a plurality of second cells having a second cell height along the cell height direction, the second cell height being less than the first cell height; and an equivalent cell height corresponding to the first cell height, the second cell height, the number of columns of the plurality of first cells, and the number of columns of the plurality of second cells, wherein the equivalent cell height of the first circuit region is different from the equivalent cell height of the second circuit region; one of the plurality of first cells includes: a first active region and a second active region having different conductivity types and being spaced apart from each other along the cell height direction. The extended source / drain contacts extend along the cell height direction over the first and second active regions and are electrically coupled to the first and second active regions, and the conductive pattern extends along the cell height direction over the extended source / drain contacts and is electrically coupled to the extended source / drain contacts in parallel with the extended source / drain contacts in a second metal layer of the plurality of metal layers in the integrated circuit layout, which is close to the first and second active regions.

8. The integrated circuit layout as described in claim 7, further comprising: A plurality of third cells having a third cell height along the cell height direction, the third cell height being less than the first cell height and greater than the second cell height, wherein the plurality of third cells includes at least one of the following: the first circuit region, the second circuit region, or the third circuit region of the integrated circuit layout, wherein all cells in the third circuit region are the plurality of third cells.

9. The integrated circuit layout as claimed in claim 8 further includes a merged cell, wherein the merged cell comprises two cells, each of the two cells being one of the plurality of first cells, one of the plurality of second cells, or one of the plurality of third cells, the active regions of the two cells being merged into a merged active region of the merged cell, and the cell height of the merged cell along the cell height direction is the sum of the cell heights of the two cells along the cell height direction.

10. A method for generating an integrated circuit layout of a circuit region, the method being at least partially executed by a processor and comprising: The equivalent cell height is determined based on the application to be implemented by the circuit region; a cell column configuration is determined based on the determined equivalent cell height, the cell column configuration including at least one first column having a first height, at least one second column having a second height different from the first height, and a third column, the first column, the second column, and the third column extending along a first axis and arranged side by side along a second axis spanning the first axis, wherein the first active area of ​​the third column is merged with the first active area of ​​one of the first column and the second column to form a merged first active area, and the merged first active area is arranged along the second axis between the second active area of ​​the third column and the second active area of ​​one of the first column and the second column; a cell array is generated according to the determined cell column configuration; and placement and routing operations are performed to generate the integrated circuit layout of the circuit region, the placement and routing operations including performing the following operations based on the circuit region: placing one or more first cells having the first height in one or more first columns having the first height in the generated cell array, and placing one or more second cells having the second height in one or more second columns having the second height in the generated cell array.

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